WO2023168570A1 - 形成电介质隔离的方法、器件的制备方法、器件及设备 - Google Patents

形成电介质隔离的方法、器件的制备方法、器件及设备 Download PDF

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Publication number
WO2023168570A1
WO2023168570A1 PCT/CN2022/079600 CN2022079600W WO2023168570A1 WO 2023168570 A1 WO2023168570 A1 WO 2023168570A1 CN 2022079600 W CN2022079600 W CN 2022079600W WO 2023168570 A1 WO2023168570 A1 WO 2023168570A1
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layer
substrate
source
etching
fin structure
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English (en)
French (fr)
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汪大伟
刘桃
孙新
徐敏
张卫
陈鲲
杨静雯
吴春蕾
王晨
徐赛生
尹睿
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • the present invention relates to the field of semiconductor devices, and in particular, to a method of forming dielectric isolation, a device preparation method, devices and equipment.
  • GAA Gate-all-around
  • GAA devices will choose wider nanosheets (Nanosheet, NS) as the channel region.
  • the width of the parasitic channel in the lower part of NS is larger (the same as the width of the upper NS). Due to the weak gate control capability of this parasitic channel, under the condition of short channel length, the parasitic channel will It will lead to a large leakage current between the source and drain, increase the energy consumption of the device, and limit the further reduction of the channel length; at the same time, it will lead to the sub-threshold characteristics of the device such as sub-threshold swing (SS) and drain potential. Deterioration of Drain-induced Barrier Lowering (DIBL) leads to device performance degradation.
  • DIBL Drain-induced Barrier Lowering
  • the present invention provides a method for forming dielectric isolation, a device preparation method, devices and equipment to solve the problem of large leakage current between source/drain regions of vertically stacked gate-all-around (GAA) devices. .
  • GAA gate-all-around
  • a method for vertically stacking gate-all-around devices to locally form body dielectric isolation includes:
  • the fin structure includes part of the substrate, and a sacrificial layer and a channel layer stacked at intervals on part of the substrate;
  • the height of the first electrical isolation layer is no higher than the top of the first sacrificial layer on the substrate and no lower than the bottom of the first sacrificial layer; wherein the first sacrificial layer is The sacrificial layer is in direct contact with the substrate.
  • forming the fin structure on the substrate specifically includes:
  • first stack Forming a first stack on the substrate, the first stack including a sacrificial layer and a channel layer stacked at intervals;
  • the first stack and the top layer of the substrate are etched to form a fin structure.
  • the thickness of the first sacrificial layer along the stacking direction of the first stack is greater than the thickness of the other sacrificial layers.
  • the dielectric material fills the etching gap, the source/drain cavity, and the substrate concave layer, and the dielectric material is formed along the first
  • the height of a stack in the stacking direction is not lower than the fin structure.
  • the dielectric material is deposited using isotropic deposition combined with chemical mechanical polishing or fluid chemical vapor deposition.
  • forming the first electrical isolation layer further includes: forming a source/drain region on the first electrical isolation layer, wherein the source/drain region is formed in the source/drain cavity.
  • a method for manufacturing a semiconductor device including:
  • a semiconductor device is provided, which is prepared by using the method for manufacturing a semiconductor device described in the second aspect of the present invention.
  • an electronic device including the semiconductor device according to the third aspect of the present invention.
  • the invention provides a method for locally forming bulk dielectric isolation for vertically stacked ring-gate devices. After the etching of the source/drain cavity is completed and before the source/drain region is formed, the surface layer of the substrate at the bottom of the source/drain cavity is embedded. The first electrical isolation layer extends out of the source/drain cavity, thereby isolating the surface layer of the substrate at the bottom of the fin structure and the source/drain layer to avoid source/drain regions and parasitic trenches formed in subsequent processes. The channels are in contact with each other, thereby reducing the leakage current between the source/drain regions, achieving the effect of reducing device energy consumption and avoiding device performance degradation.
  • Figure 1 is a flow chart of etching steps for a method for locally forming bulk dielectric isolation in a vertically stacked gate-all-around device according to the present invention
  • Figure 2 is a schematic diagram of different etching stages in a specific embodiment of the present invention.
  • Figure 3 is a schematic diagram 2 of different etching stages in a specific embodiment of the present invention.
  • Figure 4 is a schematic diagram three of different etching stages in a specific embodiment of the present invention.
  • Figure 5 is a schematic diagram 4 of different etching stages in a specific embodiment of the present invention.
  • Figure 6 is a schematic diagram 5 of different etching stages in a specific embodiment of the present invention.
  • GAA devices Vertically stacked gate-all-around (GAA) devices have become the mainstream device structure at 5nm and below nodes due to their superior channel control capabilities; in order to obtain stronger current driving capabilities per unit area, GAA devices will choose more A wide nanosheet (NS) serves as the channel region.
  • NS nanosheet
  • the width of the parasitic channel in the lower part of NS is larger (or consistent with the width of the upper NS). Due to the weak gate control capability of this parasitic channel, under the condition of short channel length, It will lead to a large leakage current between the source/drain layer, increase the energy consumption of the device, and limit the further reduction of the channel length; at the same time, it will lead to the sub-threshold characteristics of the device such as sub-threshold swing (SS) and Deterioration of Drain induced Barrier Lowering (DIBL) leads to reduced device performance.
  • SS sub-threshold swing
  • DIBL Deterioration of Drain induced Barrier Lowering
  • the width of the parasitic channel when the width of the parasitic channel is equal to the width of the upper nanosheet, the bottom end of the source/drain layer will contact the parasitic channel; therefore, the arrangement of the GAA FET structure in the prior art is relatively small. Under the condition of short channel length, it will lead to a large leakage current between the source/drain layer; the parasitic channel refers to the substrate surface layer at the bottom of the stacked channel layer and the sacrificial layer.
  • the present invention creatively proposes: after the etching of the source/drain cavity is completed and before the epitaxy of the source/drain layer, a first electrical isolation is embedded in the surface layer of the substrate at the bottom of the source/drain cavity. layer, and allows the first electrical isolation layer to extend out of the source/drain cavity, thereby isolating the parasitic channel and the source/drain layer, thereby preventing the source/drain layer formed in the subsequent process from contacting the parasitic channel, thereby reducing the source/drain layer.
  • the leakage current between drain layers achieves the effect of reducing device energy consumption and avoiding device performance degradation.
  • a method for locally forming body dielectric isolation for vertically stacked gate-all-around devices includes:
  • S11 Provide a substrate 101, and form a fin structure on the substrate 101.
  • the fin structure includes part of the substrate, and a sacrificial layer 102 and a channel layer 103 stacked at intervals on part of the substrate;
  • forming the fin structure on the substrate 101 specifically includes:
  • first stack Forming a first stack on the substrate 101, the first stack including a sacrificial layer 102 and a channel layer 103 stacked at intervals;
  • the first stack may be formed by alternating epitaxial deposition
  • the specific number of layers of the sacrificial layer 102 and the channel layer 103 is determined by the needs of the actual device. This article specifically takes four layers of sacrificial layers and three layers of channel layers as an example.
  • the first stack and the top layer of the substrate are etched by photolithography
  • a portion of the substrate is formed, as well as a sacrificial layer and a channel layer stacked at intervals on the portion of the substrate, that is, the fin structure.
  • the number of the fin structures depends on actual needs.
  • the shallow trench isolation structure is located between the fin structures (not shown in the figure);
  • S13 Form a surrounding stack 104 on the fin structure, and the surrounding stack 104 spans the fin structure along the first direction;
  • the number of surrounding stacks 104 depends on the actual situation.
  • S14 Etch the fin structures on both sides of the surrounding stack 104 along the second direction to form a source/drain cavity; and etch away the fin structure at the bottom of the source/drain cavity.
  • the surface layer of the substrate 101 forms a substrate concave layer, as shown in FIG. 3 .
  • This step requires excessive etching.
  • a part of the substrate 101 Si Fin
  • a part of the substrate 101 Si Fin
  • the first direction is also the arrangement direction of the fin structures.
  • the second direction is also the arrangement direction of the surrounding stacks 104 .
  • the surrounding stack 104 spans the fin structure along the first direction, and generally the angle between the fin structure and the surrounding stack 104 is 90°, so the first direction is perpendicular to The second direction; the second direction is the direction of the arrow shown in Figure 2; the first direction is perpendicular to the second direction on the plane of the substrate 101.
  • the surrounding stack 104 includes: a dummy gate structure 1042 and a first isolation layer 1041.
  • the first isolation layer 1041 is formed on a pair of sidewalls of the dummy gate structure 1042 along the second direction.
  • S15 Etch the sacrificial layer 102 at the end of the fin structure along the second direction to form an etching gap, as shown in FIG. 4 .
  • the dielectric material is etched using isotropic etching to form the etching gap
  • the width of the etching gap along the second direction is adapted to the width of the first isolation layer 1041, where adaptation to means: and the width of the etching gap is according to the The width of the first isolation layer 1041 is adjusted so that the width of the etching gap along the second direction is the same as the width of the first isolation layer 1041 . In other embodiments, the width of the etching gap along the second direction and the width of the first isolation layer 1041 may also be different.
  • the dielectric material 105 fills the etching gap, the source/drain cavity, and the substrate concave layer. , and the height of the dielectric material 105 along the stacking direction of the first stack is not lower than the fin structure.
  • S17 Etch the dielectric material 105 to form a first electrical isolation layer 107 on the substrate concave layer to isolate the source/drain cavity and the surface layer of the substrate 101 under the fin structure; and An inner spacer layer 106 is formed in the etching gap, as shown in FIG. 6 .
  • the method of etching the dielectric material to form the first electrical isolation layer is anisotropic quantitative etching; the etching direction is perpendicular to the substrate;
  • the width of the etching gap along the second direction when the width of the etching gap along the second direction is adapted to the width of the first isolation layer 1041; therefore, the width of the inner spacer layer 106 along the second direction is also adapted to matched to the width of the first isolation layer 1041. In another embodiment, when the width of the etching gap along the second direction is different from the width of the first isolation layer 1041, the width of the inner spacer layer 106 along the second direction is also different. to the width of the first isolation layer 1041;
  • the first electrical isolation layer 107 is filled in the substrate concave layer and extends out of the substrate concave layer to fill part of the source/drain cavity, so that the source/drain cavity and the fin structure
  • the underlying parasitic channel layer is isolated.
  • the parasitic channel layer is located on the surface layer of the substrate 101 under the fin structure.
  • the etching gap exists between the channel layers 103. After etching the dielectric material 105 to form the inner spacer layer 106, the side surfaces of the channel layer 103 are exposed.
  • the source/drain cavity is used to generate a source/drain region, wherein the source/drain material of the source/drain region contacts all exposed side surfaces of the channel layer 103, and due to the first electrical isolation Layer 107 is present without contacting the parasitic channel layer.
  • This step can simultaneously form the required inner spacer and bottom dielectric isolation (BDI); the inner spacer is the inner spacer layer 106; the bottom dielectric isolation is the first electrical isolation layer 107.
  • BDI bottom dielectric isolation
  • the large leakage current between the source/drain regions is reduced, thereby reducing the energy consumption of the device and improving the performance of the device.
  • the material constituting the inner spacer layer 106 is a dielectric material 105.
  • the height of the first electrical isolation layer 107 is no higher than the top of the first sacrificial layer 102 on the substrate 101 and no lower than the bottom of the first sacrificial layer 102; wherein, The first sacrificial layer 102 is the sacrificial layer 102 that directly contacts the substrate 101 .
  • the material constituting the first sacrificial layer 102 is SiGe.
  • the first electrical isolation layer 107 is formed by vertical selective etching of the dielectric material 105.
  • the amount of etching needs to be controlled to ensure contact with the first sacrificial layer 102.
  • the side of the channel layer 103 along the second direction is completely exposed, and at the same time, it cannot be over-etched, causing the source/drain region to contact the parasitic channel layer; therefore, the height of the first electrical isolation layer 107 needs to be It is controlled above the bottom layer of the first sacrificial layer 102 and below the bottom layer of the channel layer 103 closest to the first sacrificial layer 102, that is, as described above: the height of the first electrical isolation layer 107 is not higher than the The top of the first sacrificial layer 102 is not lower than the bottom of the first sacrificial layer 102 .
  • the thickness of the first sacrificial layer 102 may be considered to increase the thickness of the first sacrificial layer 102 to reduce the difficulty of controlling the etching process; therefore, preferably: in one embodiment, The thickness of the first sacrificial layer 102 along the stacking direction of the first stack is greater than the thickness of the other sacrificial layers 102; thus, the etching height of the first electrical isolation layer 107 is more controllable.
  • the dielectric material 105 is deposited using isotropic deposition combined with chemical mechanical polishing or fluid chemical vapor deposition.
  • the first electrical isolation layer 107 is formed by deposition and etching.
  • the method of depositing the dielectric material is: isotropic deposition combined with chemical mechanical polishing;
  • Specific steps include: depositing the dielectric material 105 on the substrate 101 by isotropic deposition. Therefore, the dielectric material 105 usually deposited in the step will cover the surface surrounding the top of the stack 104, so it is necessary to pass Chemical Mechanical Polishing (CMP) is used to achieve uniformity of the height of the dielectric material 105 and the surrounding stack 104 on the substrate 101, and on this basis, the dielectric material 105 is etched, and finally The first electrical isolation layer 107 is obtained.
  • CMP Chemical Mechanical Polishing
  • the filling of the dielectric material 105 is completed directly through Flowable Chemical Vapor Deposition (FCVD), so that the dielectric material 105 reaches a specified height, and then the dielectric material 105 is The material 105 is etched to obtain the first electrical isolation layer 107 .
  • FCVD Flowable Chemical Vapor Deposition
  • the specified height usually refers to: after the above process is completed, the dielectric material 105 is filled to the same height as the surrounding stack 104, or the same height as the height of the fin structure. Other heights are also possible. Since etching requires At the same time, an inner spacer layer 106 is formed in the etching gap, so that the specified height is not lower than the height of the fin structure.
  • forming the first electrical isolation layer 107 further includes: forming a source/drain region on the first electrical isolation layer 107, wherein the source/drain region is formed on the source/drain region. inside the cavity.
  • a source/drain region is formed on the first electrical isolation layer 107. Since the first electrical isolation layer 107 exists under the source/drain region, the source/drain region is effectively isolated from the parasitic channel layer. Reduce leakage current.
  • a source/drain layer Within the source/drain region is a source/drain layer.
  • An interlayer dielectric layer is formed on the source/drain layer and the shallow trench isolation structure.
  • the interlayer dielectric layer is formed in the source/drain cavity, and the interlayer dielectric layer covers the top and sidewalls of each source/drain layer.
  • Forming the interlayer dielectric layer on the source/drain layer and the shallow trench isolation structure specifically includes: depositing dielectric materials on the source/drain layer and the shallow trench isolation structure, and using CMP to The dielectric material is etched to a specific height, and the dielectric material is etched to form the interlayer dielectric layer.
  • the dummy gate structure 1042 is made of polysilicon material.
  • a dummy gate cavity is formed.
  • the selective etching method is dry etching.
  • the method further includes: filling the dummy gate cavity with a high dielectric constant material; the metal gate material covering the high dielectric constant material; the high dielectric constant material.
  • the constant material and metal gate (MG) complete the complete wrapping of the channel layer 103.
  • the high dielectric constant material (High-k, HK) is a high-K material; the metal gate material is a widely used material in the prior art.
  • the metal gate material and the high dielectric constant material are subjected to a CMP process to remove the metal gate material and the high dielectric constant material on the top of the interlayer dielectric layer, so that the metal gate material and the high dielectric constant material are removed.
  • the electrical constant material reaches a specified height after etching, and the specified height is the same as the height of the interlayer dielectric layer.
  • etching barrier layer (Nitride) on the outer surface of the structure formed in the above steps, perform patterned photolithography on the etching barrier layer, use the etching barrier layer as a mask, and etch the source/ Part of the interlayer dielectric layer on the top and side walls of the drain layer forms contact holes, and metal materials are deposited in the contact holes to form device contact structures.
  • the device contact structure wraps the source/drain layer to form a wrap around contact (WAC), which reduces Contact resistance;
  • the metal material may be W, TiN, etc.
  • a method for manufacturing a semiconductor device including:
  • a semiconductor device is provided, which is prepared by using the method for manufacturing a semiconductor device described in the previous embodiment of the present invention.
  • an electronic device including the semiconductor device described in the previous embodiment of the present invention.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种垂直堆叠环栅器件局部形成体电介质隔离的方法，包括：提供一衬底（101），在衬底（101）上形成鳍结构以及环绕堆叠件（104），环绕堆叠件（104）横跨鳍结构，鳍结构包括部分衬底（101）以及在部分衬底（101）上间隔堆叠的牺牲层（102）和沟道层（103）；对环绕堆叠件（104）沿第二方向的两侧的鳍结构进行刻蚀，以形成源/漏空腔；并刻蚀掉源/漏空腔底部的衬底（101）的表层，形成衬底凹层；对鳍结构沿第二方向的端部的牺牲层（102）进行刻蚀，形成刻蚀空隙；在衬底凹层上形成第一电隔离层（107），以隔离源/漏空腔和鳍结构下方的衬底（101）的表层；并在刻蚀空隙内形成内间隔层（106）；使得鳍结构底端的衬底（101）的表层和源/漏层隔离。还公开了一种半导体器件的制备方法、半导体器件、电子设备。

Description

形成电介质隔离的方法、器件的制备方法、器件及设备 技术领域
本发明涉及半导体器件领域，尤其涉及一种形成电介质隔离的方法、器件的制备方法、器件及设备。
背景技术
垂直堆叠环栅(Gate-all-around,GAA)器件由于其优越的沟道控制能力，从而成为5nm及以下节点的主流器件结构。
为了获得更强的单位面积电流驱动能力，GAA器件会选择较为宽的纳米薄片(Nanosheet,NS)作为沟道区域。
由Fin FET转向GAA FET结构，NS下部的寄生沟道的宽度较大(与上层NS的宽度一致)，该寄生沟道由于有着较弱的栅控能力，在较短沟道长度条件下，将会导致源漏之间较大的漏电流，增加器件的能耗，限制沟道长度的进一步缩小；同时导致器件的亚阈值特性如亚阈值摆幅(Sub-threshold swing,SS)与漏致势垒降低(Drain induced Barrier Lowering,DIBL)的劣化，导致器件性能下降。
因此，源漏之间存在较大的漏电流问题，成为本行业亟待要解决的技术重点。
发明内容
本发明提供一种形成电介质隔离的方法、器件的制备方法、器件及设备，以解决垂直堆叠环栅(Gate-all-around,GAA)器件的源/漏区之间的较大漏电流的问题。
根据本发明的第一方面，提供了一种垂直堆叠环栅器件局部形成体电介质隔离的方法，该方法包括：
提供一衬底，在所述衬底上形成鳍结构，所述鳍结构包括部分所 述衬底，以及在部分所述衬底上间隔堆叠的牺牲层和沟道层；
在所述衬底上形成浅沟槽隔离结构；
在所述鳍结构上形成环绕堆叠件，所述环绕堆叠件沿第一方向横跨所述鳍结构；
对所述环绕堆叠件沿第二方向的两侧的所述鳍结构进行刻蚀，以形成源/漏空腔；并刻蚀掉所述源/漏空腔底部的所述衬底的表层，形成衬底凹层；
对所述鳍结构沿第二方向的端部的所述牺牲层进行刻蚀，形成刻蚀空隙；
在所述衬底上沉积电介质材料；
对所述电介质材料进行刻蚀，从而在所述衬底凹层上形成第一电隔离层，以隔离源/漏空腔和所述鳍结构下方的衬底的表层；并在所述刻蚀空隙内形成内间隔层。
可选的，所述第一电隔离层的高度不高于所述衬底上的第一牺牲层的顶部且不低于所述第一牺牲层的底部；其中，所述第一牺牲层为直接接触所述衬底的所述牺牲层。
可选的，在所述衬底上形成鳍结构具体包括：
在所述衬底上形成第一堆叠件，所述第一堆叠件包括间隔堆叠的牺牲层与沟道层；
对所述第一堆叠件以及所述衬底顶层进行刻蚀，形成鳍结构。
可选的，所述第一牺牲层沿所述第一堆叠件的堆叠方向的厚度大于其他所述牺牲层的厚度。
可选的，在所述衬底上沉积电介质材料之后，所述电介质材料填充所述刻蚀空隙、所述源/漏空腔、所述衬底凹层，且所述电介质材料沿所述第一堆叠件堆叠方向的高度不低于所述鳍结构。
可选的，沉淀所述电介质材料采用各向同性淀积结合化学机械抛光的方式或流动性化学气相淀积的方式。
可选的，形成所述第一电隔离层之后还包括：在所述第一电隔离层上形成源/漏区，其中，所述源/漏区形成于所述源/漏空腔内。
根据本发明的第二方面，提供了一种半导体器件的制备方法，包 括：
本发明第一方面任一项所述的垂直堆叠环栅器件局部形成体电介质隔离的方法。
根据本发明的第三方面，提供了一种半导体器件，利用本发明第二方面所述的半导体器件的制备方法制备而成。
根据本发明的第四方面，提供了一种电子设备，包括本发明第三方面所述的半导体器件。
本发明提供的一种垂直堆叠环栅器件局部形成体电介质隔离的方法，在源/漏空腔刻蚀完成后，源/漏区形成之前，在源/漏空腔底端的衬底的表层嵌入第一电隔离层，并且使得第一电隔离层延伸出源/漏空腔，从而隔离鳍结构底端的衬底的表层和源/漏层，以避免后续工艺形成的源/漏区与寄生沟道相接触，从而减小源/漏区之间的漏电流，实现减小器件能耗，避免器件性能下降的效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明垂直堆叠环栅器件局部形成体电介质隔离的方法的刻蚀步骤流程图；
图2是本发明一具体实施例中不同刻蚀阶段的示意图一；
图3是本发明一具体实施例中不同刻蚀阶段的示意图二；
图4是本发明一具体实施例中不同刻蚀阶段的示意图三；
图5是本发明一具体实施例中不同刻蚀阶段的示意图四；
图6是本发明一具体实施例中不同刻蚀阶段的示意图五；
附图标记说明：
101-衬底；
102-牺牲层；
103-沟道层；
104-环绕堆叠件；
1041-第一隔离层；
1042-假栅结构；
105-电介质材料；
106-内间隔层；
107-第一电隔离层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
垂直堆叠环栅(Gate-all-around,GAA)器件由于其优越的沟道控制能力，从而成为5nm及以下节点的主流器件结构；为了获得更强的单位面积电流驱动能力，GAA器件会选择较为宽的纳米薄片(Nanosheet,NS)作为沟道区域。
由Fin FET转向GAA FET结构，NS下部的寄生沟道的宽度 较大(或者与上层NS的宽度一致)，该寄生沟道由于有着较弱的栅控能力，在较短沟道长度条件下，将会导致源/漏层之间较大的漏电流,增加器件的能耗，限制沟道长度的进一步缩小；同时导致器件的亚阈值特性如亚阈值摆幅(Sub-threshold swing,SS)与漏致势垒降低(Drain induced Barrier Lowering,DIBL)的劣化，导致器件性能下降。
具体的，现有技术中当寄生沟道的宽度等于其上层的纳米薄片的宽度时，源/漏层底端会接触到寄生沟道；因而，现有技术中GAA FET结构的设置，在较短沟道长度条件下，将会导致源/漏层之间较大的漏电流；寄生沟道是指间隔堆叠的沟道层和牺牲层底端的衬底表层。
针对上述技术手段所产生的技术问题，本发明创造性的提出：在源/漏空腔刻蚀完成后，源/漏层外延之前，在源/漏空腔底端的衬底表层嵌入第一电隔离层，并且使得第一电隔离层延伸出源/漏空腔，从而隔离寄生沟道和源/漏层，从而避免后续工艺形成的源/漏层与寄生沟道相接触，以减小源/漏层之间的漏电流，实现减小器件能耗，避免器件性能下降的效果。
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
请参考图1-图6，图中仅以一个鳍结构为例说明本发明的内容，然而本发明并不将鳍结构的数量作任何限制，只要包含类似结构，均在本发明保护范围内，根据本发明一实施例提供的一种垂直堆叠环栅器件局部形成体电介质隔离的方法，该方法包括：
S11：提供一衬底101，在所述衬底101上形成鳍结构，所述鳍结构包括部分所述衬底，以及在部分所述衬底上间隔堆叠的牺牲层102和沟道层103；
一种实施例中，在所述衬底101上形成鳍结构具体包括：
在所述衬底101上形成第一堆叠件，所述第一堆叠件包括间隔堆叠的牺牲层102与沟道层103；
对所述第一堆叠件和所述衬底顶层进行刻蚀，形成鳍结构；
所述第一堆叠件可以选择交替外延淀积的方式形成；
牺牲层102与沟道层103具体的层数由实际器件的需要而决定，本文具体以4层牺牲层与3层沟道层为例。
对所述第一堆叠件和所述衬底顶层进行刻蚀的方式采用光刻刻蚀的方式；
对所述第一堆叠件以及衬底顶层进行刻蚀之后，形成部分所述衬底，以及在部分所述衬底上间隔堆叠的牺牲层和沟道层，即所述鳍结构。
所述鳍结构的数量视实际需要而定。
S12：在所述衬底101上形成浅沟槽隔离结构；
所述浅沟槽隔离结构位于所述鳍结构之间(图中未示出)；
S13：在所述鳍结构上形成环绕堆叠件104，所述环绕堆叠件104沿第一方向横跨所述鳍结构；
所述环绕堆叠件104的数量视实际情况而定。
执行S11-S13之后的器件结构如图2所示；
S14：对所述环绕堆叠件104沿所述第二方向的两侧的所述鳍结构进行刻蚀，以形成源/漏空腔；并刻蚀掉所述源/漏空腔底部的所述衬底101的表层，形成衬底凹层，如图3所示。
该步骤需要过量刻蚀，除了需要刻蚀所述鳍结构的叠层，需要把所述衬底101(Si Fin)刻蚀掉一部分，从而形成所述源/漏空腔和所述衬底凹层。
所述第一方向同时也是所述鳍结构的排列方向。
所述第二方向同时也是所述环绕堆叠件104的排列方向。
而所述环绕堆叠件104沿所述第一方向横跨所述鳍结构，且通常所述鳍结构和所述环绕堆叠件104之间的夹角为90°，因此所述第一方向垂直于所述第二方向；所述第二方向如图2所示的箭头方向；所述第一方向在所述衬底101平面上垂直于所述第二方向。
所述环绕堆叠件104包括：假栅结构1042以及第一隔离层1041，第一隔离层1041形成于沿所述第二方向上的假栅结构1042的一对侧 壁上。
S15：对所述鳍结构沿第二方向的端部的所述牺牲层102进行刻蚀，形成刻蚀空隙，如图4所示。
一种实施方式中，采用各向同性刻蚀的方式刻蚀所述电介质材料形成所述刻蚀空隙；
一种实施方式中，所述刻蚀空隙沿所述第二方向上的宽度适配于第一隔离层1041的宽度，此处的适配于指：并且所述刻蚀空隙的宽度根据所述第一隔离层1041的宽度调整，使得所述刻蚀空隙沿所述第二方向上的宽度与第一隔离层1041的宽度相同。其他实施方式中，所述刻蚀空隙沿所述第二方向上的宽度同第一隔离层1041的宽度也可以不同。
S16：在所述衬底101上沉积电介质材料105，如图5所示。
请参考图5，一种实施例中，在所述衬底101上沉积电介质材料105之后，所述电介质材料105填充所述刻蚀空隙、所述源/漏空腔、所述衬底凹层，且所述电介质材料105沿所述第一堆叠件堆叠方向的高度不低于所述鳍结构。
S17：对所述电介质材料105进行刻蚀，从而在所述衬底凹层上形成第一电隔离层107，以隔离源/漏空腔和所述鳍结构下方的衬底101的表层；并在所述刻蚀空隙内形成内间隔层106，如图6所示。
一种实施方式中，刻蚀所述电介质材料形成所述第一电隔离层的方式为各向异性定量刻蚀；刻蚀方向垂直于所述衬底；
一种实施方式中，当所述刻蚀空隙沿所述第二方向上的宽度适配于第一隔离层1041的宽度；因而所述内间隔层106沿所述第二方向上的宽度也适配于所述第一隔离层1041的宽度。另一种实施方式中，当所述刻蚀空隙沿所述第二方向上的宽度同第一隔离层1041的宽度不同时，所述内间隔层106沿所述第二方向上的宽度也不同于所述第一隔离层1041的宽度；
所述第一电隔离层107填充于所述衬底凹层并延伸出所述衬底凹层而填充到部分源/漏空腔内，从而使得所述源/漏空腔和所述鳍结构下方的寄生沟道层隔离。
所述寄生沟道层位于所述鳍结构下方的衬底101的表层。
所述刻蚀空隙存在所述沟道层103之间，刻蚀所述电介质材料105形成内间隔层106后，暴露出所述沟道层103的侧面。
所述源/漏空腔用于生成源/漏区，其中，所述源/漏区的源/漏材料接触全部暴露出来的所述沟道层103的侧面，且由于所述第一电隔离层107的存在，不接触所述寄生沟道层。
该步骤可以同时形成所需的Inner spacer和Bottom dielectric isolation(BDI)；Inner spacer即为所述内间隔层106；Bottom dielectric isolation即为所述第一电隔离层107。
因而减少了源/漏区之间较大的漏电流，从而减少了器件的能耗，同时实现了器件性能的提升。
构成所述内间隔层106(inner spacer)的材料是电介质材料105。
一种实施例中，所述第一电隔离层107的高度不高于所述衬底101上的第一牺牲层102的顶部且不低于所述第一牺牲层102的底部；其中，所述第一牺牲层102为直接接触所述衬底101的所述牺牲层102。
一种实施方式中，构成所述第一牺牲层102的材料为SiGe。
所述第一电隔离层107是通过垂直的选择性刻蚀所述电介质材料105而形成的，刻蚀所述电介质材料105时：需要控制刻蚀的量，保证接触所述第一牺牲层102的沟道层103的沿所述第二方向的侧面完全露出，同时不能过量刻蚀，导致源/漏区与寄生沟道层相接触；因而，需要将所述第一电隔离层107的高度控制在所述第一牺牲层102底层之上，最接近所述第一牺牲层102的沟道层103底层之下，即上述描述的：所述第一电隔离层107的高度不高于所述第一牺牲层102的顶部且不低于所述第一牺牲层102的底部。
实际操作中，为了避免该步骤出现过量或者不足刻蚀的情况，可以考虑将所述第一牺牲层102厚度增加，从而减小刻蚀工艺控制难度；因而，优选的：一种实施例中，所述第一牺牲层102沿所述第一堆叠件的堆叠方向的厚度大于其他所述牺牲层102的厚度；从而所述第一电隔离层107的刻蚀高度更可控。
一种实施例中，沉淀所述电介质材料105采用各向同性淀积结合化学机械抛光的方式或流动性化学气相淀积的方式。
一种实施方式中，所述第一电隔离层107的形成方式为淀积加刻蚀，
一种实施方式中，沉淀所述电介质材料的方式为：各向同性淀积结合化学机械抛光的方式；
具体步骤包括：在所述衬底101上通过各向同性沉淀的方式沉淀所述电介质材料105，因此步骤通常沉淀的所述电介质材料105会覆盖所述环绕堆叠件104顶部的表面，因而需要通过化学机械抛光(Chemical Mechanical Polishing，CMP)的方式实现所述电介质材料105和所述衬底101上环绕堆叠件104的高度的统一，从而在此基础上对所述电介质材料105进行刻蚀，最终得到所述第一电隔离层107。
另一种实施方式中，直接通过可流动性化学气相淀积(Flowable Chemical Vapor Deposition,FCVD)来完成所述电介质材料105的填充，从而使得所述电介质材料105达到指定高度，再对所述电介质材料105进行刻蚀得到所述第一电隔离层107。
其中指定高度通常指：以上工艺完成后，所述电介质材料105填充至与所述环绕堆叠件104相同高度，或与所述鳍结构的高度相同的高度，其他高度同样可以,由于刻蚀后需同时在所述刻蚀空隙内形成内间隔层106，因而所述致指定高度不低于于所述鳍结构的高度。
一种实施例中，形成所述第一电隔离层107之后还包括：在所述第一电隔离层107上形成源/漏区，其中，所述源/漏区形成于所述源/漏空腔内。
在所述第一电隔离层107上形成源/漏区，由于所述源/漏区下存在所述第一电隔离层107，使得所述源/漏区与寄生沟道层相隔离从而有效降低漏电流。
所述源/漏区内是源/漏层。
在所述源/漏层和所述浅槽隔离结构上形成层间介质层。
所述层间介质层形成于所述源/漏空腔中，所述层间介质层覆盖于所述每个所述源/漏层顶部和侧壁。
在所述源/漏层和所述浅槽隔离结构上形成所述层间介质层具体包括：在所述源/漏层和所述浅槽隔离结构上沉淀介质材料，采用CMP的方式将所述介质材料刻蚀到特定高度，刻蚀所述介质材料形成所述层间介质层。
形成所述层间介质层之后包括以下步骤：
1)去除所述假栅结构1042。
一种实施方式中，所述假栅结构1042是由多晶硅材料制成的。
2)选择性刻蚀所述牺牲层102，从而释放Si沟道层103。
假栅结构1042去除后以及所述牺牲层102释放后形成假栅空腔。
一种实施方式中，所述选择性刻蚀的方法是干法刻蚀。
其他实施方式中，也可以采用其他方法选择性刻蚀所述牺牲层102。
3)在所述假栅空腔内填充金属栅材料形成所述金属栅。
在所述假栅空腔内填充金属栅材料之前还包括：在所述假栅空腔中填充高介电常数材料；所述金属栅材料覆盖所述高介电常数材料；所述高介电常数材料与金属栅(Metal gate,MG)完成对沟道层103的全包裹。
一种实施方式中，所述高介电常数材料(High-k,HK)即高K材料；所述金属栅材料为现有技术中应用广泛的材料。
对上述金属栅材料和所述高介电常数材料进行CMP处理，从而去除所述层间电介质层顶部的金属栅材料和所述高介电常数材料，使得所述金属栅材料和所述高介电常数材料刻蚀后达到指定高度，所述指定高度为同所述层间电介质层的高度相同的高度。
4)在上述步骤形成的结构外表面沉淀刻蚀阻挡层(Nitride)，在所述刻蚀阻挡层上做图形化光刻，以所述刻蚀阻挡层为掩膜，刻蚀所述源/漏层顶端和侧壁的部分层间电介质层，形成接触孔，在接触孔中沉淀金属材料形成器件接触结构。
此时不仅仅能够在源漏顶部形成接触，其侧面与底面也同样可以被金属材料包裹，所述器件接触结构将的源/漏层包裹，形成环绕式接触(wrap around contact,WAC)，降低接触电阻；
所述金属材料可以是W，TiN等。
根据本发明一实施例，提供了一种半导体器件的制备方法，包括：
本发明前述实施例任一项所述的垂直堆叠环栅器件局部形成体电介质隔离的方法。
根据本发明一实施例，提供了一种半导体器件，利用本发明前述实施例所述的半导体器件的制备方法制备而成。
根据本发明一实施例，提供了一种电子设备，包括本发明前述实施例所述的半导体器件。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种垂直堆叠环栅器件局部形成体电介质隔离的方法，其特征在于，该方法包括：
    提供一衬底，在所述衬底上形成鳍结构，所述鳍结构包括部分所述衬底，以及在部分所述衬底上间隔堆叠的牺牲层和沟道层；
    在所述衬底上形成浅沟槽隔离结构；
    在所述鳍结构上形成环绕堆叠件，所述环绕堆叠件沿第一方向横跨所述鳍结构；
    对所述环绕堆叠件沿第二方向的两侧的所述鳍结构进行刻蚀，以形成源/漏空腔；并刻蚀掉所述源/漏空腔底部的所述衬底的表层，形成衬底凹层；
    对所述鳍结构沿第二方向的端部的所述牺牲层进行刻蚀，形成刻蚀空隙；
    在所述衬底上沉积电介质材料；
    对所述电介质材料进行刻蚀，从而在所述衬底凹层上形成第一电隔离层，以隔离源/漏空腔和所述鳍结构下方的衬底的表层；并在所述刻蚀空隙内形成内间隔层。
  2. 根据权利要求1所述的垂直堆叠环栅器件局部形成体电介质隔离的方法，其特征在于，所述第一电隔离层的高度不高于所述衬底上的第一牺牲层的顶部且不低于所述第一牺牲层的底部；其中，所述第一牺牲层为直接接触所述衬底的所述牺牲层。
  3. 根据权利要求1所述的垂直堆叠环栅器件局部形成体电介质隔离的方法，其特征在于，
    形成鳍结构具体包括：
    在所述衬底上形成第一堆叠件，所述第一堆叠件包括间隔堆叠的牺牲层与沟道层；
    对所述第一堆叠件以及衬底顶层进行刻蚀，形成鳍结构。
  4. 根据权利要求3所述的垂直堆叠环栅器件局部形成电介质隔离的方法，其特征在于，所述第一牺牲层沿所述第一堆叠件的堆叠方向的厚度大于其他所述牺牲层的厚度。
  5. 根据权利要求1所述的垂直堆叠环栅器件局部形成体电介质隔离的方法，其特征在于，在所述衬底上沉积电介质材料之后，所述电介质材料填充所述刻蚀空隙、所述源/漏空腔、所述衬底凹层，且所述电介质材料沿所述第一堆叠件堆叠方向的高度不低于所述鳍结构。
  6. 根据权利要求1所述的垂直堆叠环栅器件局部形成体电介质隔离的方法，其特征在于，
    沉淀所述电介质材料采用各向同性淀积结合化学机械抛光的方式或流动性化学气相淀积的方式。
  7. 根据权利要求1-6任意一项所述的垂直堆叠环栅器件局部形成体电介质隔离的方法，其特征在于，形成所述第一电隔离层之后还包括：在所述第一电隔离层上形成源/漏区，其中，所述源/漏区形成于所述源/漏空腔内。
  8. 一种半导体器件的制备方法，其特征在于，包括：
    权利要求1至7任一项所述的垂直堆叠环栅器件局部形成体电介质隔离的方法。
  9. 一种半导体器件，其特征在于，利用权利要求8所述的半导体器件的制备方法制备而成。
  10. 一种电子设备，包括权利要求9所述的半导体器件。
PCT/CN2022/079600 2022-03-07 2022-03-07 形成电介质隔离的方法、器件的制备方法、器件及设备 Ceased WO2023168570A1 (zh)

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CN109599335A (zh) * 2018-12-27 2019-04-09 中国科学院微电子研究所 环栅纳米线晶体管及其制备方法
CN111223778A (zh) * 2018-11-23 2020-06-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20210305420A1 (en) * 2020-03-24 2021-09-30 International Business Machines Corporation Enhanced bottom dielectric isolation in gate-all-around devices
CN113903666A (zh) * 2020-07-06 2022-01-07 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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CN111223778A (zh) * 2018-11-23 2020-06-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109599335A (zh) * 2018-12-27 2019-04-09 中国科学院微电子研究所 环栅纳米线晶体管及其制备方法
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