WO2023165442A1 - 感光组件及其电导通方法和制备方法、摄像模组 - Google Patents

感光组件及其电导通方法和制备方法、摄像模组 Download PDF

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Publication number
WO2023165442A1
WO2023165442A1 PCT/CN2023/078446 CN2023078446W WO2023165442A1 WO 2023165442 A1 WO2023165442 A1 WO 2023165442A1 CN 2023078446 W CN2023078446 W CN 2023078446W WO 2023165442 A1 WO2023165442 A1 WO 2023165442A1
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WO
WIPO (PCT)
Prior art keywords
photosensitive
circuit board
electrical connection
electrical
molding unit
Prior art date
Application number
PCT/CN2023/078446
Other languages
English (en)
French (fr)
Inventor
俞杰
许晨祥
易峰亮
陆锡松
Original Assignee
宁波舜宇光电信息有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202210197949.XA external-priority patent/CN116744534A/zh
Priority claimed from CN202210196821.1A external-priority patent/CN116744095A/zh
Priority claimed from CN202210198030.2A external-priority patent/CN116744097A/zh
Priority claimed from CN202210197984.1A external-priority patent/CN116744096A/zh
Priority claimed from CN202210196826.4A external-priority patent/CN116744080A/zh
Priority claimed from CN202210198022.8A external-priority patent/CN116744082A/zh
Priority claimed from CN202210196851.2A external-priority patent/CN116744081A/zh
Application filed by 宁波舜宇光电信息有限公司 filed Critical 宁波舜宇光电信息有限公司
Publication of WO2023165442A1 publication Critical patent/WO2023165442A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details

Definitions

  • the application relates to the field of module assembly, in particular to a photosensitive component and its electrical conduction method and preparation method, a circuit board component and its preparation method, and a camera module.
  • the market has put forward higher and higher demands on the image quality of camera modules, how to obtain higher image quality with smaller camera module volume has become a compact camera module (such as for mobile phones) camera module) field, especially on the premise of technological development trends such as high pixels, large aperture, and large chips in the mobile phone industry;
  • the internal space that can be used for the front camera module is getting smaller and smaller;
  • the number of rear camera modules is increasing, and the occupied area is also increasing, resulting in a corresponding reduction in other phone configurations such as battery size and motherboard size.
  • the market hopes that the size of the rear camera module can be reduced, that is, to achieve small-size packaging; third, with the popularity of high-pixel chips and the gradual improvement of video shooting and other functions, chip energy consumption and heat dissipation have become important issues. It needs to be solved in the process of module design and manufacture.
  • the above-mentioned market demand is the bottleneck in the development of the camera module packaging industry, and the analysis of the reasons for the unresolved problems of the above-mentioned demand is mainly as follows:
  • the chip when the chip is attached, since the suction nozzle picks up the chip from the upper part, the chip will also be imaged in a curved shape whose periphery is lower than the center.
  • the coefficient of thermal expansion (CTE) index of the product is different between the chip, the glue, and the circuit board.
  • the different CTE coefficients of materials will lead to chip bending problems, and the current rigid-flex boards commonly used in the industry use a lamination process, which has serious warping, which will also aggravate the chip bending problem.
  • the above-mentioned chip bending problem will cause the chip field curvature problem in the final module imaging, and ultimately affect the imaging quality.
  • the camera module tends to adopt an optical solution with a large aperture.
  • the aperture of the optical lens in the optical lens is much larger, which will cause the maximum outer diameter of the optical lens to be larger than the length of the long side of the photosensitive chip, resulting in a larger cross-sectional size of the optical lens than the photosensitive chip. situation.
  • An advantage of the present application is to provide a photosensitive component and its electrical conduction method, wherein the photosensitive component includes a circuit board and a photosensitive chip mounted on the lower surface of the circuit board in a flip-chip manner, and the photosensitive chip and the circuit board are electrically connected to each other through an integrated electrical conduction structure, wherein the integrated electrical conduction structure can not only ensure the electrical connection between the photosensitive chip and the circuit board, but also ensure that the The stability of the physical connection between the photosensitive chip and the circuit board.
  • An advantage of the present application is to provide a photosensitive component and a camera module, wherein the camera module The group integrates a part of the optical lens into the photosensitive component so that the camera module has a relatively better optical design and size design.
  • An advantage of the present application is to provide a photosensitive component and its preparation method, wherein the photosensitive component includes a circuit board and a photosensitive chip, wherein the photosensitive chip is electrically connected to the circuit board through a plurality of integrated electrical conduction structures
  • the lower surface and the through hole of the circuit board correspond to the photosensitive area of the photosensitive chip; and the molded body includes a first molding unit integrally combined with the upper surface of the circuit board and a The second molding unit of the lower surface of the circuit board.
  • An advantage of the present application is to provide a camera module, wherein the camera module has a special parameter configuration through a special structural configuration and manufacturing process, specifically, the maximum outer diameter of the optical lens and the photosensitive The ratio between the lengths of the long sides of the chip is 0.85 to 1.7.
  • An advantage of the present application is to provide a camera module, wherein the camera module includes a photosensitive component, an optical lens held on the photosensitive path of the photosensitive component, and is used to drive the photosensitive component relative to the The chip drive assembly for moving the optical lens.
  • the photosensitive component adopts the circuit board manufactured by the additive method or the semi-additive method as the mounting substrate, and the advantages and compensations of the circuit board are fully utilized through a special process and structural design. its disadvantages.
  • An advantage of the present application is to provide a circuit board assembly and its preparation method, wherein the circuit board assembly includes a circuit board made by an additive method or a semi-additive method, wherein the circuit board has an upper and a through hole formed between the upper surface and the lower surface, the lower surface of the circuit board has an electrical conduction area adjacent to the through hole and an electrical conduction area located in the electrical conduction area.
  • the circuit board includes a plurality of first electrical connection terminals formed in the electrical conduction area.
  • the wiring board assembly further includes a first molding unit integrally bonded to an upper surface of the wiring board and a second molding unit integrally bonded to a peripheral area of a lower surface of the wiring board to pass through the The first molding unit and the second molding unit are used to strengthen the structural strength of the circuit board and optimize the flatness of the circuit board assembly.
  • a photosensitive component which includes:
  • a wiring board having opposing upper and lower surfaces, and penetratingly formed on the upper surface and the through hole between the lower surface, wherein the circuit board includes a plurality of first electrical connection terminals formed on the lower surface;
  • a photosensitive chip having opposing upper and lower surfaces, the upper surface having a photosensitive area and a non-photosensitive area located around the photosensitive area, wherein the photosensitive chip includes a non-photosensitive area formed on the upper surface of the photosensitive chip a plurality of second electrical connection terminals of the region, the plurality of second electrical connection terminals respectively corresponding to the plurality of first electrical connection terminals;
  • a plurality of integrated electrical conduction structures wherein the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the plurality of electrical connection terminals located on the lower surface of the circuit board through the plurality of integrated electrical conduction structures.
  • a first electrical connection end, and each pair of the first electrical connection end and the second electrical connection end electrically connected to each other is insulated by the plurality of integral electrical conduction structures;
  • each of the integral electrical conduction structures includes a first electrical coupling part electrically connected to the first electrical connection end and a second electrical coupling part electrically connected to the second electrical connection end, and the first electrical coupling part Eutectic bonding with the second electrical bonding member, wherein each of the integrated electrical conduction structures further includes insulation covering the first electrical bonding member and the second electrical bonding member that are eutectically bonded. a medium, so that each pair of the first electrical connection end and the second electrical connection end electrically connected to each other is insulated from each other through the insulating medium;
  • the through hole of the circuit board corresponds to the photosensitive area of the photosensitive chip.
  • the glass transition temperature of the insulating medium is lower than the melting points of the first electrical coupling member and the second electrical coupling member.
  • the first electrical coupling part and the second electrical coupling part are made of the same metal material, and the first electrical coupling part and the second electrical coupling part have the same melting point.
  • the difference between the melting point temperature of the first electrical coupling member and the second electrical coupling member and the glass transition temperature of the insulating medium is greater than or equal to 30° and less than or equal to 80°
  • the glass transition temperature of the insulating medium is 180°, and the melting points of the first electrical coupling member and the second electrical coupling member are 250°.
  • the first electrical coupling part and the second electrical coupling part are made of solder balls, and the insulating medium is implemented as NCP flux.
  • the first electrical coupling part is electrically connected to the first electrical connection end through reflow soldering
  • the second electrical coupling part is electrically connected to the second electrical connection end through reflow soldering. Electrically connected, the first electrical joint and the second electrical joint achieve eutectic crystallization through a hot-pressing process combine.
  • the first electrical connection end has a predetermined cross-sectional size to allow at least five solder balls to be stacked on the first electrical connection end at the same time
  • the second electrical connection end has The cross-sectional size is preset to allow at least five solder balls to be stacked on the second electrical connection end at the same time.
  • the diameters of the first electrical connection end and the second electrical connection end are 70um, and the diameters of the solder balls are 5um-15um.
  • the wiring board is prepared by an additive method or a semi-additive method.
  • the circuit board further includes an ink layer laid on the periphery of the plurality of first electrical connection terminals on the lower surface, wherein, between the plurality of first electrical connection terminals The ink layer is not provided.
  • the plurality of first electrical connection terminals are uniformly and equidistantly distributed on the lower surface of the circuit board.
  • the application also provides a photosensitive assembly, which includes:
  • circuit board having opposite upper and lower surfaces, and a through hole penetratingly formed between the upper surface and the lower surface, wherein the circuit board includes a plurality of first an electrical connection terminal;
  • a photosensitive chip having opposing upper and lower surfaces, the upper surface having a photosensitive area and a non-photosensitive area located around the photosensitive area, wherein the photosensitive chip includes a non-photosensitive area formed on the upper surface of the photosensitive chip a plurality of second electrical connections of the region;
  • the lower surface of the circuit board is superimposed on the upper surface of the photosensitive chip and the plurality of first electrical connection terminals are respectively corresponding to and electrically connected to the plurality of second electrical connection terminals.
  • the photosensitive chip is electrically connected to the lower surface of the circuit board and the through hole of the circuit board corresponds to the photosensitive area of the photosensitive chip;
  • a molded body comprising a first molding unit integrally combined with the upper surface of the wiring board and a second molding unit integrally combined with the lower surface of the wiring board, wherein the first molding unit The first projection area on the upper surface of the circuit board along the height direction set by the photosensitive component and the second projection area of the second molding unit on the lower surface of the circuit board along the height direction Common central axis setup.
  • the first projected area and the second projected area have the same shape and size.
  • the first projected area and the second projected area have the same shape and different sizes.
  • the inner periphery of the first projection area is aligned with the inner periphery of the second projection area
  • the outer periphery of the first projection area is aligned with the outer periphery of the second projection area .
  • the outer periphery of the first projection area is aligned with the outer periphery of the second projection area, and the circuit board has an inner periphery forming the through hole, wherein the first The inner periphery of the projection area is closer to the inner periphery of the circuit board than the inner periphery of the second projection area.
  • the inner periphery of the first projection area is aligned with the inner periphery of the second projection area
  • the circuit board has an outer periphery, wherein the outer periphery of the second projection area is aligned with It is closer to the outer periphery of the circuit board than the outer periphery of the first projected area.
  • the photosensitive component further includes at least one electronic component disposed on the upper surface of the circuit board and covered by the first molding unit.
  • the height dimension of the first molding unit is 0.35 mm to 0.5 mm.
  • the circuit board is prepared by an additive method or a semi-additive method, and the thickness of the circuit board is 0.05mm-0.35mm.
  • the first molding unit has a top surface, and the flatness RZ of the top surface is 5 um.
  • a height dimension of the first molding unit is greater than a height dimension of the second molding unit.
  • the height dimension of the second molding unit is 0.2mm-0.3mm.
  • the second molding unit is formed surrounding the photosensitive chip.
  • the height dimension of the second molding unit is larger than the thickness dimension of the photosensitive chip.
  • the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the plurality of second electrical connection terminals located on the lower surface of the circuit board through the plurality of integrated electrical conduction structures.
  • the first electrical connection terminal, and each pair of the first electrical connection terminal and the first electrical connection terminal electrically connected to each other The two electrical connection ends are insulated by the plurality of integral electrical conduction structures.
  • each of the integrated electrical conduction structures includes a first electrical coupling member electrically connected to the first electrical connection end and a second electrical coupling member electrically connected to the second electrical connection end,
  • the first electrical bonding element is eutectically bonded to the second electrical bonding element, wherein each of the integrated electrical conduction structures further includes the first electrical bonding element and the second electrical bonding element covered in the eutectic bonding.
  • an insulating medium around the electrical coupling so that each pair of the first electrical connection end and the second electrical connection end electrically connected to each other is insulated from each other through the insulating medium;
  • the glass transition temperature of the insulating medium is lower than the melting points of the first electrical coupling member and the second electrical coupling member.
  • the application also provides a photosensitive assembly, which includes:
  • circuit board having opposite upper and lower surfaces, and a through hole penetratingly formed between the upper surface and the lower surface, wherein the circuit board includes a plurality of first an electrical connection terminal;
  • a photosensitive chip having opposing upper and lower surfaces, the upper surface having a photosensitive area and a non-photosensitive area located around the photosensitive area, wherein the photosensitive chip includes a non-photosensitive area formed on the upper surface of the photosensitive chip A plurality of second electrical connection ends of the region, the plurality of second electrical connection ends respectively corresponding to the plurality of first electrical connection ends;
  • a plurality of integrated electrical conduction structures wherein the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the plurality of electrical connection terminals located on the lower surface of the circuit board through the plurality of integrated electrical conduction structures.
  • the first electrical connection terminal in such a way that the photosensitive chip is electrically connected to the lower surface of the circuit board and the through hole of the circuit board corresponds to the photosensitive area of the photosensitive chip;
  • the molded body includes a first molding unit integrally combined with the upper surface of the circuit board and a second molding unit integrally combined with the lower surface of the circuit board.
  • the junction of the photosensitive chip and the circuit board on the lower surface of the circuit board corresponding to the position on the upper surface of the circuit board is covered by the first molding unit cover.
  • the circuit board has an inner periphery and an outer periphery, the inner periphery of the circuit board forms the through hole, and the photosensitive chip has an outer periphery, wherein the first molding unit It has an inner peripheral edge and an outer peripheral edge, and the inner peripheral edge of the first molding unit is located at the junction of the photosensitive chip and the circuit board on the lower surface of the circuit board corresponding to the upper surface of the circuit board and between the inner peripheral edges of the circuit board.
  • an inner peripheral edge of the first molding unit is aligned with an inner peripheral edge of the wiring board.
  • the second molding unit has an inner edge and an outer edge, and the inner peripheral edge of the first molding unit is closer to the inner peripheral edge of the second molding unit than the inner peripheral edge of the second molding unit.
  • the inner periphery of the circuit board is closer to the inner peripheral edge of the second molding unit than the inner peripheral edge of the second molding unit.
  • the outer peripheral edge of the first molding unit is adjacent to or flush with the outer peripheral edge of the circuit board.
  • an outer peripheral edge of the first molding unit is aligned with an outer peripheral edge of the second molding unit in the height direction.
  • the outer peripheral edge of the first molding unit is adjacent to or flush with the outer peripheral edge of the circuit board.
  • the photosensitive component further includes at least one electronic component disposed on the upper surface of the circuit board and covered by the first molding unit.
  • the height dimension of the first molding unit is 0.35 mm to 0.5 mm.
  • the first molding unit has a top surface, and the flatness RZ of the top surface is 5 um.
  • the second molding unit is formed surrounding the photosensitive chip.
  • a bottom surface of the second molding unit is lower than a lower surface of the photosensitive chip.
  • the height dimension of the second molding unit is 0.2mm-0.3mm.
  • the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the plurality of second electrical connection terminals located on the lower surface of the circuit board through the plurality of integrated electrical conduction structures.
  • the first electrical connection end, and each pair of the first electrical connection end and the second electrical connection end electrically connected to each other is insulated by the plurality of integral electrical conduction structures.
  • each of the integrated electrical conduction structures includes a first electrical coupling member electrically connected to the first electrical connection end and a second electrical coupling member electrically connected to the second electrical connection end,
  • the first electrical bonding element is eutectically bonded to the second electrical bonding element, wherein each of the integrated electrical conduction structures further includes the first electrical bonding element and the second electrical bonding element covered in the eutectic bonding.
  • the glass transition temperature of the insulating medium is lower than the melting points of the first electrical coupling member and the second electrical coupling member.
  • the application also provides a method for preparing a photosensitive component, which includes:
  • a circuit board and a photosensitive chip are provided, wherein the circuit board has opposite upper and lower surfaces, and a through hole is formed penetratingly between the upper surface and the lower surface, and the circuit board includes A plurality of first electrical connection terminals formed on the lower surface, wherein the photosensitive chip has opposite upper and lower surfaces, the upper surface has a photosensitive area and a non-photosensitive area around the photosensitive area, so The photosensitive chip includes a plurality of second electrical connection terminals formed on the non-photosensitive area of the upper surface of the photosensitive chip;
  • a first molding unit is formed on the upper surface of the wiring board and a second molding unit is formed on the lower surface of the wiring board by a molding process, so that by the first molding unit and the second molding The unit strengthens the structure of the circuit board;
  • a layer of insulating medium is respectively laid on the first electrical coupling part and/or the second electrical coupling part, wherein the glass transition temperature of the insulating medium is lower than that of the first electrical coupling part and the second electrical coupling part.
  • the eutectic bonding between the plurality of first electrical bonding parts and the plurality of second electrical bonding parts is realized through a hot-pressing process, and the insulating medium is respectively coated on the eutectic first electrical bonding parts and the surroundings of the second electrical coupling member, in such a way that the photosensitive chip is electrically connected to the lower surface of the circuit board, and the photosensitive area of the photosensitive chip corresponds to the through hole.
  • the application also provides a method for preparing a photosensitive component, which includes:
  • a circuit board and a photosensitive chip are provided, wherein the circuit board has opposite upper and lower surfaces, and a through hole is formed penetratingly between the upper surface and the lower surface, and the circuit board includes A plurality of first electrical connection terminals formed on the lower surface, wherein the photosensitive chip has opposite upper and lower surfaces, the upper surface has a photosensitive area and a non-photosensitive area around the photosensitive area, so The photosensitive chip includes a plurality of second electrical connection terminals formed on the non-photosensitive area of the upper surface of the photosensitive chip;
  • a first molding unit is formed on the upper surface of the wiring board and a second molding unit is formed on the lower surface of the wiring board by a molding process, so that by the first molding unit and the second molding The unit strengthens the structure of the circuit board;
  • a layer of insulating medium is respectively laid on the first electrical coupling part and/or the second electrical coupling part, wherein the glass transition temperature of the insulating medium is lower than that of the first electrical coupling part and the second electrical coupling part.
  • the eutectic bonding between the plurality of first electrical bonding parts and the plurality of second electrical bonding parts is realized through a hot-pressing process, and the insulating medium is respectively coated on the eutectic first electrical bonding parts and the surroundings of the second electrical coupling member, in such a way that the photosensitive chip is electrically connected to the lower surface of the circuit board, and the photosensitive area of the photosensitive chip corresponds to the through hole.
  • an electrical conduction method for a photosensitive component which includes:
  • a circuit board and a photosensitive chip are provided, wherein the circuit board has opposite upper and lower surfaces, and a through hole is formed penetratingly between the upper surface and the lower surface, and the circuit board includes A plurality of first electrical connection terminals formed on the lower surface, wherein the photosensitive chip has opposite upper and lower surfaces, the upper surface has a photosensitive area and a non-photosensitive area around the photosensitive area, so The photosensitive chip includes a plurality of second electrical connection terminals formed on the non-photosensitive area of the upper surface of the photosensitive chip;
  • a layer of insulating medium is respectively laid on the first electrical coupling part and/or the second electrical coupling part, wherein the glass transition temperature of the insulating medium is lower than that of the first electrical coupling part and the second electrical coupling part.
  • the eutectic bonding between the plurality of first electrical bonding parts and the plurality of second electrical bonding parts is realized through a hot-pressing process, and the insulating medium is respectively coated on the eutectic first electrical bonding parts and the surroundings of the second electrical coupling member, in such a way that the photosensitive chip is electrically connected to the lower surface of the circuit board, and the photosensitive area of the photosensitive chip corresponds to the through hole.
  • the A plurality of first electrical joints are formed on the first electrical connection ends of the circuit board and a plurality of second electrical joints are formed on the second electrical connection ends of the photosensitive chip, including:
  • the steel mesh has a plurality of circular openings corresponding to the plurality of first electrical connection ends;
  • the circuit board covered with the solder paste is processed by reflow soldering, wherein the solder paste processed by reflow soldering forms the plurality of first electrical bonding elements.
  • the diameter of the circular opening is configured such that at least five solder balls in the solder paste can be accommodated in the circular opening at the same time.
  • the diameter of the circular opening is 70um, and the diameter of the solder ball is 5um-15um.
  • the eutectic bonding between the plurality of first electrical coupling parts and the plurality of second electrical coupling parts is realized through a hot-pressing process, and the insulating medium respectively wraps Surrounding the eutectically bonded first electrical bonding element and the second electrical bonding element, including:
  • said insulating medium is transformed from a solid state to a glass state upon heating to the glass transition temperature of said insulating medium;
  • the first electrical bonding part and the second electrical bonding part break through the insulating medium in the glass state and eutectically bond with each other, and the glass state
  • the insulating medium is extruded around the eutectically bonded first and second electrical bonds.
  • the circuit board further includes an ink layer laid on the periphery of the plurality of first electrical connection ends on the lower surface, wherein the plurality of first electrical connections The ink layer is not provided between the connecting ends.
  • circuit board assembly which includes:
  • the wiring board having opposing upper and lower surfaces, and a through hole formed penetratingly between the upper and lower surfaces, the lower surface of the wiring board having an electrical connection adjacent to the through hole area and a surrounding area located at the periphery of the electrical conduction area; wherein the wiring board includes a plurality of first electrical connection terminals formed in the electrical conduction area;
  • the molded body includes a first molding unit integrally bonded to the upper surface of the wiring board and a second molding unit integrally bonded to a peripheral area of the lower surface of the wiring board.
  • the circuit board further includes an ink layer laid on the surrounding area, and the ink layer is not provided between the plurality of first electrical connection terminals.
  • the plurality of first electrical connection terminals are evenly and equidistantly distributed in the electrical conduction area.
  • the thickness of the circuit board is 0.2 mm.
  • the first electrical connection end has a predetermined diameter so that at least five solder balls with a diameter of 5um-15um can be stacked above the first electrical connection end.
  • the laying position of the plurality of first electrical connection terminals on the lower surface of the circuit board corresponds to the position of the upper surface of the circuit board by the first mold Covered by plastic unit.
  • the first molding unit and the second molding unit are aligned with each other in a height direction set by the circuit board assembly.
  • the circuit board has an inner periphery and an outer periphery, and the inner periphery of the circuit board forms the through hole, wherein the first molding unit has an inner periphery and an outer periphery.
  • the outer peripheral edge, the second molding unit has an inner edge and an outer edge, and the inner peripheral edge of the first molding unit is closer to the inner peripheral edge of the circuit board than the inner peripheral edge of the second molding unit.
  • the circuit board has an inner periphery and an outer periphery, and the inner periphery of the circuit board forms the through hole, wherein the first molding unit has an inner periphery and an outer periphery.
  • the outer peripheral edge, the second molding unit has an inner edge and an outer edge, the inner peripheral edge of the first molding unit is aligned with the inner peripheral edge of the second molding unit in the height direction, the first The outer periphery of the molding unit is aligned with the outer periphery of the second molding unit in the height direction.
  • the circuit board assembly further includes at least one electronic component disposed on the upper surface of the circuit board and covered by the first molding unit.
  • the height dimension of the first molding unit is 0.35 mm to 0.5 mm.
  • the first molding unit has a top surface, and the flatness RZ of the top surface is 5um.
  • the second molding unit is formed around the photosensitive chip in a surrounding manner.
  • the bottom surface of the second molding unit is lower than the lower surface of the photosensitive chip.
  • the height dimension of the second molding unit is 0.2mm-0.3mm.
  • a method for preparing a circuit board assembly which includes:
  • a circuit board and a photosensitive chip are provided, wherein the circuit board has opposite upper and lower surfaces, and a through hole is formed penetratingly between the upper surface and the lower surface, and the circuit board includes A plurality of first electrical connection terminals formed on the lower surface, wherein the photosensitive chip has opposite upper and lower surfaces, the upper surface has a photosensitive area and a non-photosensitive area around the photosensitive area, so The photosensitive chip includes a plurality of second electrical connection terminals formed on the non-photosensitive area of the upper surface of the photosensitive chip; and
  • a first molding unit is formed on the upper surface of the wiring board and a second molding unit is formed on the lower surface of the wiring board by a molding process, so that by the first molding unit and the second molding The unit strengthens the structure of the circuit board.
  • a camera module which includes:
  • the photosensitive component includes:
  • a wiring board having opposing upper and lower surfaces, and a through hole formed penetratingly between the upper and lower surfaces;
  • a photosensitive chip has opposite upper and lower surfaces, the upper surface has a photosensitive area and a non-photosensitive area around the photosensitive area, wherein the upper surface of the photosensitive chip is electrically connected to the lower surface of the circuit board , and the photosensitive area of the photosensitive chip corresponds to the through hole;
  • a molded body including a first molding unit integrally bonded to the upper surface of the wiring board and a second molding unit integrally bonded to the lower surface of the wiring board;
  • the ratio between the maximum outer diameter of the optical lens and the length of the long side of the photosensitive chip is 0.85 to 1.7.
  • the camera module further includes a camera module mounted on the top surface of the first molding unit and used to drive at least a part of the optical lens relative to the photosensitive chip.
  • the flatness RZ of the top surface of the first molding unit is 5um.
  • the optical lens includes at least a first lens unit of a first optical lens and a second optical lens, and the second optical lens is installed on the first module.
  • a molding unit, the second optical lens cooperates with the first molding unit to form a second lens unit.
  • the back focus size of the camera module is 0.41mm-0.72mm, and the back focus size of the camera module is the distance between the second optical lens and the photosensitive chip. the distance between.
  • the ratio between the back focus size of the camera module and the total optical length of the camera module is 0.05-0.2.
  • the ratio between the back focus size of the camera module and the total optical length of the camera module is 0.05-0.1.
  • the maximum outer diameter of the second optical lens is less than or equal to 1.2 times the long side dimension of the photosensitive chip.
  • the second optical lens has a first cut side and a second cut side corresponding to the two long sides of the photosensitive chip, and, corresponding to the photosensitive chip The third and fourth trimmings of the two short sides of the
  • the second optical lens has four light-transmitting areas protrudingly formed in four corner areas thereof.
  • the thickness of the circuit board is 0.05mm-0.4mm
  • the height of the first molding unit is 0.2mm-0.5mm
  • the second molding unit The height dimension of the unit is 0.2mm-0.3mm.
  • the bottom surface of the second molding unit is lower than the lower surface of the photosensitive chip.
  • the photosensitive component further includes a filter element attached to the upper surface of the photosensitive chip.
  • the photosensitive component further includes a filter element attached to the second optical lens.
  • the circuit board includes A plurality of first electrical connection ends on the surface
  • the photosensitive chip includes a plurality of second electrical connection ends formed in the non-photosensitive area of the upper surface of the photosensitive chip, and the plurality of second electrical connection ends are respectively connected to the Corresponding to a plurality of first electrical connection ends;
  • the photosensitive assembly further includes a plurality of integrated electrical conduction structures, wherein the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the A plurality of first electrical connection terminals on the lower surface of the circuit board, in such a way that the photosensitive chip is electrically connected to the lower surface of the circuit board and the through hole of the circuit board corresponds to the photosensitive area of the photosensitive chip .
  • the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the lower part of the circuit board through the plurality of integrated electrical conduction structures.
  • a plurality of first electrical connection terminals on the surface, and each pair of the first electrical connection terminals and the second electrical connection terminals that are electrically connected to each other are insulated by the plurality of integrated electrical conduction structures, wherein each The integrated electrical conduction structure includes a first electrical coupling that is electrically connected to the first electrical connection end and a second electrical coupling that is electrically connected to the second electrical connection. The first electrical coupling is connected to the second electrical connection.
  • each of the integrated electrical conduction structures further includes an insulating medium covering the surroundings of the eutecticly bonded first electrical coupling parts and the second electrical coupling parts, so as to pass through the electrical coupling parts.
  • the insulating medium insulates each pair of the first electrical connection end and the second electrical connection end electrically connected to each other.
  • the application also provides a camera module, which includes:
  • a chip driving component for driving the photosensitive component to move relative to the optical lens
  • the photosensitive component includes:
  • a wiring board having opposing upper and lower surfaces, and a through hole formed penetratingly between the upper and lower surfaces;
  • a photosensitive chip has opposite upper and lower surfaces, the upper surface has a photosensitive area and a non-photosensitive area around the photosensitive area, wherein the upper surface of the photosensitive chip is electrically connected to the lower surface of the circuit board , and the photosensitive area of the photosensitive chip corresponds to the through hole;
  • a molded body including a first molding unit integrally bonded to the upper surface of the wiring board and a second molding unit integrally bonded to the lower surface of the wiring board;
  • the chip drive assembly includes: a drive unit, a lead frame, an anti-shake bracket and an anti-shake Shake housing, wherein the photosensitive component is accommodated in the anti-shake housing, the anti-shake bracket is fixed in the anti-shake housing and is located outside the photosensitive component, and the lead frame extends from the Between the photosensitive component and the anti-shake bracket, the photosensitive component is movable relative to the anti-shake bracket through the lead frame, and the driving unit is suitable for driving the photosensitive component to move relative to the anti-shake bracket for optical image stabilization.
  • the lead frame includes a fixed plate arranged on the anti-shake bracket, a moving plate arranged on the circuit board, and a connecting plate connecting the moving plate and the fixed plate.
  • Elastic connection straps for boards are used.
  • the moving board is fixed on and electrically connected to the upper surface of the circuit board.
  • the moving plate is fixed on and electrically connected to the lower surface of the circuit board.
  • the driving unit includes a driving coil and a driving magnet corresponding to the driving coil, wherein the driving coil is arranged on the upper surface of the circuit board and located on the The outer side of the first molding unit described above.
  • the first molding unit has an outer peripheral edge and an inner peripheral edge, the outer peripheral edge of the first molding unit is adjacent to the driving coil, and the first molding unit The inner peripheral edge of the unit is adjacent to the inner peripheral edge of the circuit board forming the through hole.
  • the position corresponding to the upper surface of the circuit board at the junction of the photosensitive chip and the circuit board on the lower surface of the circuit board is captured by the first module Covered by plastic unit.
  • the second molding unit has an outer peripheral edge and an inner peripheral edge, and the inner peripheral edge of the first molding unit is closer to the inner peripheral edge of the second molding unit. Adjacent to the inner periphery of the circuit board.
  • the area of the first projected area of the first molding unit on the upper surface of the circuit board along the height direction set by the camera module is smaller than the area of the first molding unit.
  • the circuit board has an outer peripheral edge, and the outer peripheral edge of the second molding unit is closer to the outer peripheral edge of the first molding unit than the outer peripheral edge of the first molding unit. The outer periphery of the circuit board.
  • the driving unit includes four driving coils, and the four driving coils are located at four corners of the first molding unit.
  • the moving board includes a main body of the moving board and at least one conductive protrusion extending inward from the inner frame of the main body of the moving board, and the at least one conductive protrusion electrically connected to the upper surface of the circuit board.
  • the at least one conductive protrusion includes four conductive protrusions, and the four conductive protrusions respectively correspond to the outer periphery of the first molding unit. The middle of the four sides.
  • the photosensitive component further includes at least one electronic component electrically connected to the upper surface of the circuit board, at least a part of the at least one electronic component is covered with
  • the height dimension of the first molding unit is 0.2mm-0.5mm
  • the second molding unit is formed around the photosensitive chip
  • the second molding unit The bottom surface of the unit is lower than the lower surface of the photosensitive chip, and the height dimension of the second molding unit is 0.2mm-0.3mm.
  • the circuit board includes a plurality of first electrical connection terminals formed on the lower surface, and the photosensitive chip includes a non-photosensitive terminal formed on the upper surface of the photosensitive chip.
  • the photosensitive assembly further includes a plurality of integrated electrical conduction structures, wherein the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the A plurality of first electrical connection terminals on the lower surface of the circuit board, in such a way that the photosensitive chip is electrically connected to the lower surface of the circuit board and the through hole of the circuit board corresponds to the photosensitive area of the photosensitive chip .
  • the plurality of second electrical connection terminals located on the upper surface of the photosensitive chip are electrically connected to the lower part of the circuit board through the plurality of integrated electrical conduction structures.
  • a plurality of first electrical connection terminals on the surface, and each pair of the first electrical connection terminals and the second electrical connection terminals that are electrically connected to each other are insulated by the plurality of integrated electrical conduction structures, wherein each The integrated electrical conduction structure includes a first electrical coupling that is electrically connected to the first electrical connection end and a second electrical coupling that is electrically connected to the second electrical connection. The first electrical coupling is connected to the second electrical connection.
  • each of the integrated electrical conduction structures also includes a coating on the eutectic bonding
  • the ends are insulated from each other.
  • the photosensitive component further includes a second optical lens disposed on the first molding unit.
  • the back focus size of the camera module is 0.41mm-0.72mm
  • the back focus size of the camera module is the distance between the second optical lens and the photosensitive chip. The distance between them, the ratio between the back focus size of the camera module and the total optical length of the camera module is 0.05-0.2.
  • FIG. 1A illustrates a schematic diagram of a conventional camera module.
  • FIG. 1B illustrates a schematic diagram of another conventional camera module.
  • FIG. 1C illustrates a schematic diagram of the process of the conventional subtractive method for circuit boards.
  • FIG. 1D illustrates a schematic diagram of the process of the conventional semi-additive method/additive method for circuit boards.
  • FIG. 2 illustrates a schematic diagram of a camera module according to an embodiment of the present application.
  • FIG. 3 illustrates a schematic diagram of a photosensitive component of the camera module according to an embodiment of the present application.
  • Fig. 4 illustrates a schematic diagram of a circuit board of the photosensitive component according to an embodiment of the present application.
  • FIG. 5 illustrates a partial schematic diagram of the integrated electrical conduction structure of the photosensitive component according to an embodiment of the present application.
  • 6A to 6C illustrate schematic diagrams of the conduction process of the photosensitive element according to the embodiment of the present application.
  • FIG. 6D illustrates a schematic view of the lower surface of the circuit board according to an embodiment of the present application.
  • FIG. 7A to 7C illustrate schematic diagrams of the manufacturing process of the circuit board assembly of the photosensitive assembly according to an embodiment of the present application.
  • FIG. 8A illustrates a schematic diagram of a modified implementation of the photosensitive assembly according to an embodiment of the present application.
  • FIG. 8B illustrates a schematic diagram of another modified implementation of the photosensitive component according to the embodiment of the present application.
  • Fig. 9 illustrates a schematic diagram of a modified implementation of the camera module according to an embodiment of the present application.
  • FIG. 10 is a schematic top view of the photosensitive component of the camera module shown in FIG. 9 .
  • FIG. 11 is a schematic top view of yet another modified implementation of the photosensitive component of the camera module according to the embodiment of the present application.
  • Fig. 12 shows a schematic diagram of another modified implementation of the camera module according to the embodiment of the present application.
  • Fig. 13 shows a schematic diagram of yet another modified implementation of the camera module according to the embodiment of the present application.
  • FIG. 14 illustrates a partial schematic diagram of a photosensitive component of the camera module according to an embodiment of the present application.
  • Fig. 15 shows a schematic diagram of yet another modified implementation of the camera module according to the embodiment of the present application.
  • the photosensitive chip is mounted on the circuit board and is used to drive the optical lens.
  • the motor can be mounted directly on the circuit board or on a mirror mount mounted on the circuit board. That is to say, in the camera module, the circuit board is the mounting substrate of other parts in the camera module, therefore, in order to reduce the overall size of the camera module (including the size of the X-axis direction, the size of the Y-axis direction and the size of the Z-axis direction) , where the dimension in the X-axis direction and the dimension in the Y-axis direction are the cross-sectional dimensions of the camera module, and the dimension in the Z-axis direction is the height dimension of the camera module), providing a circuit board with a smaller cross-sectional size and a relatively flatter.
  • the camera module can reduce the space required for vertical stacking of the components of the camera module from the bottom layer, and finally realize the technical requirements of high pixels, large chips, small size and large aperture.
  • Fig. 1A and Fig. 1B illustrate the structure diagram of two kinds of commonly used existing camera modules, wherein, the camera module shown in Fig. 1A is the camera module prepared by COB process and the camera module shown in Fig. 1B It is a camera module prepared by FC process.
  • the COB process refers to the Chip on Board process, that is, the photosensitive chip 1P is mounted on the upper surface of the circuit board 2P through an adhesive, and then the photosensitive chip 1P is laid between the photosensitive chip 1P and the circuit board 2P by means of gold wires.
  • the FC process refers to the Flip chip process (that is, the flip-chip process), that is, the photosensitive chip 1P is electrically connected to the lower surface of the circuit board 2P through a welding process, and at the same time, it is also passed through the SMT process (Surface mounting technology, surface mount technology) Process) Mount electronic components 4P (for example, capacitors, inductors, resistors, etc.) on the upper surface of the circuit board 2P.
  • the camera module when mounting the lens base 5P on the upper surface of the circuit board 2P, it is necessary to consider the avoidance problem between the lens base 5P and the electronic component 4P, that is, in A gap of 0.1mm-0.2mm is reserved in the Z-axis direction (for example, g as shown in FIG. 1A ) to prevent the mirror holder 5P from interfering with the electronic component 4P.
  • a gap of 0.1mm-0.2mm is reserved in the Z-axis direction (for example, g as shown in FIG. 1A ) to prevent the mirror holder 5P from interfering with the electronic component 4P.
  • the existing circuit boards used in the FC process are ceramic substrates.
  • ceramic substrates Compared with PCB boards or FPCB boards, ceramic substrates The substrate has advantages in hardness and flatness, but considering the characteristics of china clay, its internal circuit cannot be designed too complicated or it will be difficult to realize; secondly, the ceramic substrate has a relatively large thickness compared to the PCB board or FPCB board, which is for The camera module reduces its height direction The above dimensions are unfavorable.
  • the thickness dimension of the circuit board prepared by the subtractive method is larger (here, the thickness dimension of the circuit board prepared by the subtractive method is smaller than the thickness dimension of the ceramic substrate), and because the circuit laying density of the subtractive method is low, so , when forming a circuit of the same complexity, the cross-sectional size of the circuit board required is also larger.
  • the inventors of the present application tried to use the additive method or the semi-additive method to prepare the circuit board required by the present application.
  • the semiadditive process involves the following steps:
  • Step 1 The substrate is coated with copper, and a thinner copper layer is plated on the circuit board substrate.
  • Step 2 Exposure and development, coating photoresist (D/F) on the surface of the copper layer that has been plated with a thin copper layer to cover the copper layer, and then exposing through the ultraviolet exposure device, that is, the copper layer that needs to be turned on position is exposed. That is, the ultraviolet exposure device irradiates the area to be exposed, and the photoresist in the irradiated area is denatured to be soluble in a developer, and the photoresist in the area to be exposed is washed away by the developer.
  • D/F photoresist
  • Step 3 Increase the copper thickness of the exposed area to a required thickness through an electroplating process, that is, the exposed area is a conductive circuit part of the circuit board, and form a final usable conductive circuit by electroplating.
  • Step 4 flash etching, after removing the photoresist, the excess copper layer under the original photoresist is removed by flash etching to form the required circuit.
  • the semi-additive method/additive method is generally used to selectively form conductive patterns on an insulating substrate by means of silk screen printing, electroplating or pasting, thereby preparing a circuit board, it can be seen that the semi-additive method/ The method of additive method is to form the conductive circuit, and the method of subtractive method is to corrode the conductive circuit on the whole surface of the conductive circuit.
  • the circuit board prepared by the semi-additive method or the additive method has several characteristics such as high density, small aperture, thin line and ultra-thin shape.
  • the electrical connection between the layers of the circuit board prepared by the semi-additive method or the additive method is mainly done through metallized through holes, blind holes and buried holes (metallization is mainly realized by electroplating copper), and by
  • the circuit board made by the subtractive method mainly realizes the electrical connection between layers through through holes and conductive columns.
  • the circuit board prepared by the additive method can complete the connection of any layer and area through the through hole, blind hole and buried hole (that is, the circuit board prepared by the semi-additive method or the additive method has the effect of arbitrary interconnection), so that Under the premise of meeting the same circuit complexity requirements, the size of the circuit board in the X-axis direction and the Y-axis direction can be reduced, and the number of stacked layers can also be reduced, that is, the size of the circuit board in the Z-axis direction can also be reduced.
  • circuit board prepared by the additive method or the semi-additive method can have a relatively small cross-sectional size and height on the premise of meeting the requirements of the circuit board circuit.
  • circuit boards prepared by additive or semi-additive processes generally have the following parameters: 1. Conductive line width/line spacing ⁇ 50um/50um; 2. Wiring density ⁇ 50cm/1cm 2 ; 3. Lead wire The aperture diameter of through holes (including blind holes and buried holes) is ⁇ 100um, and the ring diameter is ⁇ 100um; and, 4. The hole density of via holes is ⁇ 1 million holes/square meter.
  • circuit board prepared by an additive method or a semi-additive method to replace the existing circuit board prepared by a subtractive method is conducive to realizing high pixel, large chip, small size and large aperture of the camera module.
  • circuit boards using the additive method or the semi-additive method participate in the assembly of the camera module.
  • the circuit board prepared by the additive method or the semi-additive method has a relatively thin thickness dimension, that is, the circuit board prepared by the additive method or the semi-additive method has relatively small hardness and strength, that is, , when the photosensitive chip is attached to the circuit board, the circuit board is more likely to bend, resulting in bending and deformation of the photosensitive chip.
  • the large photosensitive chip itself has the characteristics of easy deformation, so special attention should be paid to the processing technology of the chip.
  • the shape of the chip may be deformed and the chip may be bent, which will affect the imaging quality of the final camera module.
  • the size of the pads formed on the surface of the circuit board is relatively small, and the laying density between the pads is relatively high (that is, the pads and pads are relatively small).
  • the gap between the pads is small), so when applying an insulating layer such as an ink layer, an insulating medium such as ink cannot be applied between the pad and the pad, which will affect the subsequent circuit board and photosensitive chip.
  • a camera module according to an embodiment of the present application is illustrated, which includes a photosensitive component 20 and an optical lens 10 held on a photosensitive path of the photosensitive component 20 .
  • the camera module further includes a drive component for adjusting the relative positional relationship between the optical lens 10 and the photosensitive component 20, so as to realize the The adjustment of the optical performance of the camera module, for example, in some embodiments, the camera module also includes a device for driving the optical lens 10 to change the relative position between the optical lens 10 and the photosensitive component 20 Relational lens drive assembly 30, as another example, in some embodiments, the camera module also includes a camera module for driving the photosensitive assembly 20 to change the relative positional relationship between the optical lens 10 and the photosensitive assembly 20
  • the chip driver assembly 40 is not limited by this application.
  • the optical lens 10 includes at least one optical lens for collecting imaging light from the object to be photographed and transmitting the imaging light to the photosensitive component 20 .
  • the photosensitive assembly 20 includes a circuit board 21, a photosensitive chip 22 electrically connected to the circuit board 21, and a filter element 26 held on the photosensitive path of the photosensitive chip 22 and electrically connected to the circuit board. 21 of at least one electronic component 25 .
  • the circuit board prepared by additive method or semi-additive method is used to replace the existing Circuit boards prepared by the subtractive method.
  • the semi-additive process or additive process of the circuit board 21 includes at least the following steps: Step 1: Copper coating on the substrate, that is, plating a thin copper layer on the substrate; Step 2 : Exposure and development, that is, coating a photoresist on the surface of the copper layer that has been plated with a thin copper layer to cover the copper layer, and then exposing it through an ultraviolet exposure device. In this way, the position that needs to be turned on exposed.
  • the ultraviolet exposure device irradiates the area to be exposed, and the photoresist in the irradiated area is denatured and soluble in the developing solution, and is cleaned by the developing solution.
  • Remove the photoresist in the area to be exposed step 3: through the electroplating process, that is, increase the copper thickness of the exposed area to the required thickness, that is, the exposed area is the conductive circuit part of the circuit board 21 , to form a final usable conduction circuit by electroplating; and, step 4: flash etching, that is, after removing the photoresist, remove the excess copper layer under the original photoresist by flash etching to form the required circuit.
  • the circuit board 21 is generally prepared by selectively forming conductive patterns on an insulating substrate by silk screen printing, electroplating or pasting. Therefore, it can be seen that the method of semi-additive method/additive method is to form conductive lines. Moreover, compared with the circuit board prepared by the subtractive method, the circuit board 21 prepared by the semi-additive method or the additive method has several major characteristics such as high density, small aperture, thin line and ultra-thin shape. More specifically, the electrical connection between the layers of the circuit board 21 prepared by the semi-additive method or the additive method is mainly through metallized through holes, blind holes and buried holes (metallization is mainly done by electroplating copper).
  • the circuit board made by the subtractive method mainly realizes the electrical connection between layers through through holes and conductive columns. That is to say, the wiring board 21 prepared by the semi-additive method or the additive method can complete the connection of any layer and region through through holes, blind holes and buried holes (that is, by the semi-additive method or the additive method
  • the prepared circuit board has the effect of arbitrary interconnection), so that the size of the circuit board 21 in the X-axis direction and the Y-axis direction can be reduced under the premise of meeting the same circuit complexity requirements, and the number of stacked layers can also be reduced (ie , the size of the circuit board 21 in the Z-axis direction is also reduced).
  • the circuit board 21 prepared by the additive method or the semi-additive method can have relatively small cross-sectional dimensions (ie, length and width dimensions) and height dimensions on the premise of meeting circuit board circuit requirements.
  • the circuit board 21 prepared by additive or semi-additive process generally has the following parameters: 1. Width/spacing of conductive lines ⁇ 50um/50um; 2. Wiring density ⁇ 50cm/1cm 2 ; 3. The diameter of the via hole (including blind via and buried via) is ⁇ 100um, and the ring diameter is ⁇ 100um; and, 4. The hole density of the via hole is ⁇ 1 million holes/square meter.
  • the thickness of the circuit board 21 produced by the additive method or the semi-additive method is 0.2 mm.
  • the circuit board 21 is implemented as a rectangular thin plate with a rectangular opening in the central area, that is to say, the circuit board 21 has a
  • the through hole 210 therein has a rectangular shape. It should be understood that, in other examples of the present application, the through hole 210 can be formed through other positions of the circuit board 21 , that is, the location of the through hole 210 is not strictly limited to the circuit board 21 middle area area.
  • the circuit board 21 has an outer peripheral edge 2102 and an inner peripheral edge 2101, wherein the inner peripheral edge 2101 forms the through hole 210, that is, the edge of the through hole 210 is the edge of the circuit board 21.
  • the circuit board 21 also has an opposite upper surface 211 and a lower surface 212, wherein the upper surface 211 of the circuit board 21 is arranged towards the direction of the optical device, and the lower surface 212 of the circuit board 21 is connected to the lower surface 212 of the circuit board 21.
  • the upper surface 211 is opposite.
  • the photosensitive chip 22 has a set of opposite upper surface 221 and lower surface 222, wherein the upper surface 221 has a photosensitive area 2211 and a non-photosensitive area surrounding the photosensitive area 2211 2212.
  • the photosensitive area 2211 is located in the central area of the upper surface 221 of the photosensitive area 2211
  • the non-photosensitive area 2212 is arranged around the photosensitive area 2211 and has a zigzag structure.
  • the photosensitive area 2211 of the photosensitive chip 22 corresponds to the through hole 210 , and preferably the photosensitive area 2211 of the photosensitive chip 22 is completely exposed through the through hole 210 . That is, preferably, when the photosensitive chip 22 is mounted and electrically connected to the circuit board 21, the inner edge of the circuit board 21 corresponds to the non-photosensitive area 2212 of the photosensitive chip 22, and the photosensitive The photosensitive area 2211 of the chip 22 is not blocked by the circuit board 21 at all.
  • the photosensitive chip 22 is mounted on the lower surface 212 of the circuit board 21 in a flip-chip manner, that is, the upper surface 221 of the photosensitive chip 22 is stacked on the The lower surface 212 of the circuit board 21 , or in other words, the upper surface 221 of the photosensitive chip 22 is disposed opposite to the lower surface 212 of the circuit board 21 .
  • the circuit board 21 includes a plurality of first electrical connection terminals 21210 formed on its lower surface 212, such as gold fingers, wherein, in a specific example of the application, the plurality of A first electrical connection end 21210 is disposed close to the inner periphery 2101 of the circuit board 21 and surrounds the inner periphery 2101 of the circuit board 21 .
  • the photosensitive chip 22 includes a plurality of second electrical connection terminals 22121 formed in its non-photosensitive region 2212, such as aluminum pads, wherein, in a specific example of the present application, the A plurality of second electrical connection terminals 22121 of the photosensitive chip 22 are arranged around the photosensitive area 2211 .
  • the photosensitive chip 22 and the circuit board 21 are electrically connected through a plurality of integrated electrical conduction structures 23, that is, the plurality of first electrical connection ends of the circuit board 21 21210 and the plurality of second electrical connection ends 22121 of the photosensitive chip 22 are electrically connected through the plurality of integrated electrical conduction structures 23 .
  • each of the integrated electrical conduction structures 23 includes a first electrical coupling member 231 electrically connected to the first electrical connection end 21210 and an electrical connection In the second electrical connection part 232 of the second electrical connection end 22121, the first electrical connection part 231 and the second electrical connection part 232 are eutectically bonded, wherein each of the integrated electrical conduction structures 23 is also Including an insulating medium 233 coated around the first electrical joint 231 and the second electrical joint 232 that are eutectically bonded, so that each pair of the first electrical joints that are electrically connected to each other can pass through the insulating medium 233
  • the first electrical connection end 21210 and the second electrical connection end 22121 are insulated from each other.
  • the first electrical coupling part 231 and/or the second electrical coupling part 232 can be a structure such as a solder ball, a gold ball, a copper column, etc., which are made of metal materials, such as a sphere or a cylinder.
  • the first electrical coupling part 231 The bonding process with the first electrical connection end 21210 and the bonding process between the second electrical connection part 232 and the second electrical connection end 22121 may be processes such as pressure welding, reflow soldering, and ultrasonic welding.
  • the plurality of second electrical connection ends 22121 of the photosensitive chip 22 must at least partially overlap with the plurality of first electrical connection ends 21210 of the circuit board 21 in the direction of the X-axis and the direction of the Y-axis.
  • the avoidance distance originally reserved for the gold wire is canceled, so that the size of the entire photosensitive assembly 20 in the X-axis direction and the Y-axis direction can be reduced, that is, the lateral size of the photosensitive assembly 20 (or Said, section size) can be reduced.
  • the photosensitive chip 22 is flipped, so that the image plane of the camera module sinks, which can reduce the total optical length of the camera module, that is, make the Z-axis of the camera module The dimension of the direction is reduced (ie, the height dimension of the camera module is reduced).
  • the circuit board prepared by the subtractive method in order to protect and insulate the components and parts located on the surface of the circuit board, further on the surface of the circuit board (including the lower surface of the circuit board, The upper surface and the side surface) are provided with an insulating layer, usually an ink layer 2123 . That is to say, in the circuit board prepared by the subtractive method, the circuit board 21 further includes an ink layer 2123 disposed on the lower surface 212 thereof so as to make a plurality of first electrical connections through the ink layer 2123 .
  • the terminals 21210 are insulated from each other.
  • the circuit board 21 is made by an additive method or a semi-additive method, the distance between the plurality of first electrical connection terminals 21210 is too small, which makes the ink layer 2123 cannot be filled between the first electrical connection ends 21210, that is, in the circuit board according to the present application, the ink layer 2123 is not provided between the plurality of first electrical connection ends 21210, which makes The design and layout of the electrical connection structure between the photosensitive chip 22 and the circuit board 21 becomes complicated and difficult.
  • the lower surface 212 of the circuit board 21 has an electrical conduction area 2121 and a surrounding area 2122 located around the electrical conduction area 2121 , wherein the circuit The board 21 includes the plurality of first electrical connection terminals 21210 formed in the electrical conduction area 2121 and the electrical conduction lines laid in the circuit board 21 .
  • the circuit board 21 further includes an ink layer 2123 disposed on the surrounding area 2122 of the lower surface 212 thereof, and the ink layer 2123 is not provided between the first electrical connection terminals 21210 .
  • the tinning operation is realized through stencil printing, that is, the tinning operation is completed through an SMT process.
  • the stencil is provided with a plurality of circular openings with a diameter of 70um, and the circular openings are tin holes, and the plurality of first electrical connections with the circuit board 21
  • the connection end 21210 is aligned with the position of the lower tin hole, and then the solder paste is applied by the scraper, and the solder paste is forced to pass through the lower tin hole and fall on the plurality of first electrical connection ends 21210 of the circuit board 21 to Complete the tinning operation.
  • the diameter of the circular opening of the stencil is set to 70um, and the setting of the hole diameter matches the minimum particle size of the solder ball 230 in the solder paste. More specifically, the size of the circular hole opening allows at least five solder balls 230 to be stacked above the first electrical connection end 21210 . Quantitatively, in this specific example, the particle diameter of the solder ball 230 in the solder paste is 5-15um (the diameter is the selected diameter, of course, it can also be other diameters), so as to meet at least the requirements in the production process. The principle of five balls, that is, at least five solder paste particles can be accommodated at the same solder position.
  • each of the first electrical connection ends 21210 needs at least Five solder balls 230 need to be stacked so that the solder balls 230 fused into one body can meet the production requirements, so setting the opening of the stencil to 70um can basically meet the requirements.
  • the diameter of the circular opening corresponds to the cross-sectional size of the first electrical connection end 21210. Therefore, in the embodiment of the present application, the first electrical connection end 21210 has The preset cross-sectional size allows at least five solder balls 230 to be stacked on the first electrical connection end 21210 at the same time. In terms of quantification, the diameter of the first electrical connection end 21210 is 70um, and the diameter of the solder ball 230 is 5um-15um.
  • the openings of the stencil are configured as circular openings. It should be noted that during the tinning process of the circuit board 21, no matter what the relative angle between the scraper and the circular opening is, the force on the circular opening is the same in all directions, so that it will not affect the solder paste along the With the falling of the circular opening, tin connection can be greatly avoided. Moreover, the circular opening also needs to be deburred and polished to remove the burrs around the circular opening, so as to prevent the burrs from affecting the scraper and solder paste falling along the circular opening. In some embodiments, the inner wall of the circular opening may also be polished to prevent solder paste from clogging or adhering to the inner wall, resulting in insufficient amount of solder.
  • tinning can also be improved.
  • ultra-fine pitch is used for solder paste printing, that is, the gap between the stencil and the circuit board 21 is controlled to be extremely small, so that the solder paste can pass through the stencil during the printing process. It is directly pressed onto the first electrical connection end 21210 of the circuit board 21, that is to say, there is no extra stroke during the falling process of the solder paste to cause the solder paste to move to other directions subsequent to the printing hole, so as to avoid connecting the solder generation.
  • the circuit board 21 after the tinning process is used to process the circuit board 21, so that the The solder paste on the first electrical connection ends 21210 is melted at high temperature and solidified again to form the plurality of first electrical joints 231 electrically connected to the plurality of first electrical connection ends 21210 .
  • one second electrical coupling member 232 can be formed on each second electrical connection end 22121 through the same ball planting process.
  • the plurality of second electrical couplings 232 can also be formed on the plurality of second electrical connection ends 22121 of the photosensitive chip 22 through other processes, for example, through a channel mask plating process , tinning and reflow soldering, etc., which are not limited by this application.
  • a thermal pressing head is arranged on the lower surface 222 of the photosensitive chip 22, and then the side of the photosensitive chip 22 on which the plurality of second electrical connection terminals 22121 are arranged (that is, The upper surface 221) of the photosensitive chip 22 faces the side of the circuit board 21 on which the plurality of first electrical connection terminals 21210 are arranged (that is, the lower surface 212 of the circuit board 21 ), and then the photosensitive chip 22 and the circuit board 21 are physically fixed and electrically connected to each other under the action of certain pressure and preset temperature changes.
  • the first electrical connection part 231 formed on the first electrical connection end 21210 of the circuit board or the second electrical connection end 22121 formed on the photosensitive chip 22 may be A specific insulating medium 233 is laid and coated on the second electrical coupling part 232 on the upper part, which is used to prevent the conduction structure formed between the first electrical coupling part 231 and the second electrical coupling part 232 from occurring to each other. short circuit, wherein the insulating medium 233 may be under fill glue or NCP flux.
  • the insulating medium 233 may be applied on the surface of the plurality of first electrical coupling parts 231, for example, NCP auxiliary coating may be applied on the surface of the plurality of first electrical coupling parts 231.
  • the NCP flux covers the plurality of first electrical joints 231, since the glass transition point of the NCP flux is 180°C, and the first electrical joints 231
  • the melting point of the second electrical coupling member 232 is about 250°C, so that during the heating process of thermocompression bonding, as the temperature gradually increases and preferably reaches 180°C, at this time, the NCP flux begins to soften, And the first electrical coupling part 231 and the second electrical coupling part 232 have not softened (that is, the hardness of the first electrical coupling part 231 and the second electrical coupling part 232 is greater than that of the NCP flux) , so that in the process of pressing down, the first electrical coupling part 231 and the second electrical coupling part 232 press the NCP solder resist
  • the outer sides of the two electrical coupling parts 232 are extruded, the first electrical coupling part 231 and the second electrical coupling part 232 break through the NCP flux and contact each other, and at the same time, the NCP solder resist is squeezed to the
  • the gaps and surroundings of the first coupling part and the second coupling part are used to prevent short circuit between each pair of the first electrical coupling part 231 and the second electrical coupling part 232 that are electrically connected to each other.
  • the glass state of the insulating medium 233 means that the material changes from a solid state to a glass state.
  • the glass state is not a state of matter, but its structure. Solid matter is divided into crystal and amorphous, and the atoms ( Or ions or molecules) have a certain spatial structure, crystals have a certain crystal Solid shape and fixed melting point, and glassy state is a kind of non-crystal, non-crystal is a solid except crystal in solid, it has no fixed shape and fixed melting point, has isotropy, it will gradually change with the increase of temperature Soft and melted at the end.
  • the NCP flux can realize the soldering function, improve the bonding force between the circuit board 21 and the photosensitive chip 22, and prevent short circuit at the same time.
  • the first electrical coupling part 231 and the second electrical coupling part 232 are in contact with each other and as the temperature further increases to 300°C for a certain period of time, the The temperature of the first electrical coupling part 231 of the circuit board 21 and the second electrical coupling part 232 of the photosensitive chip 22 is lowered after being bonded to each other.
  • the direct conduction between the circuit board 21 and the photosensitive chip 22 is achieved by using the thermocompression bonding process, compared with the photosensitive chip and the circuit board assembled by the COB process components, which can effectively reduce the size of the photosensitive component 20 in the cross-sectional direction.
  • the materials of the first electrical coupling part 231 and the second electrical coupling part 232 include but are not limited to gold, tin, nickel, palladium, etc. or two of them Or a variety of alloys, as shown in Figure 5.
  • each of the integrated electrical conduction structures 23 also includes insulation covering the surroundings of the eutectically bonded first electrical joint 231 and the second electrical joint 232 . medium 233, so that each pair of the first electrical connection end 21210 and the second electrical connection end 22121 electrically connected to each other are insulated from each other through the insulating medium 233.
  • the ink layer 2123 is not laid between the plurality of first electrical connection terminals 21210 formed on the lower surface 212 of the circuit board 21, resulting in the The multiple first electrical connection ends 21210 cannot be insulated from each other.
  • an insulating medium 233 (for example, NCP flux) on the surface of the first electrical coupling 231 and/or the second electrical coupling 232, thermal After the press-bonding process, an insulating medium 233 is refilled between the plurality of first electrical connection terminals 21210 to ensure the accuracy and stability of the electrical connection between the circuit board 21 and the photosensitive chip 22 .
  • the physical bonding strength between the circuit board 21 and the photosensitive chip 22 only depends on the plurality of first electrical couplings 231 and the plurality of second electrical couplings.
  • the laying of the insulating medium 233 takes into account the particularity of the circuit laying and structure of the circuit board prepared by the additive method or the semi-additive method, and plays the role of insulation and isolation.
  • the insulating medium 233 is preferably made of a viscous material to enhance the physical bonding strength between the circuit board 21 and the photosensitive chip 22 . Therefore, the insulating medium 233 can play the function of the electrical level and the function of the physical level.
  • the insulating medium 233 can also be laid only on the surface of the second electrical coupling part 232, or can be laid on the first electrical coupling part 231 and the surface of the second electrical coupling part 232 at the same time.
  • the surface of the second electrical coupling member 232 is mentioned above, but this application is not limited thereto.
  • the glass transition temperature of the insulating medium 233 is 180°
  • the melting point temperature of the first electrical coupling member 231 and the second electrical coupling member 232 is 250°
  • the melting point temperature of the first electrical coupling member 231 and the second electrical coupling member 232, and the glass transition temperature of the insulating medium 233 The specific value of is not limited by the present application, and it only needs to satisfy: 1.
  • the melting point temperature of the first electrical coupling part 231 and the second electrical coupling part 232 is greater than the glass transition temperature of the insulating medium 233; 2.
  • the difference between the melting point temperature of the first electrical coupling part 231 and the second electrical coupling part 232 and the glass transition temperature of the insulating medium 233 is within a preset range.
  • the difference between the melting point temperature of the first electrical coupling member 231 and the second electrical coupling member 232 and the glass transition temperature of the insulating medium 233 is within a preset range, it should be understood that when the melting point temperature and the glass transition temperature When the temperature difference is too large, there is a large interval between the vitrification of the insulating medium 233 and the eutectic bonding between the first electrical coupling part 231 and the second electrical coupling part 232, which wastes It saves energy and is not conducive to improving production efficiency; and when the temperature difference between the two is small, the vitrification of the insulating medium 233 and the relationship between the first electrical coupling 231 and the second electrical coupling 232 The eutectic bonding occurs at similar times, which makes process control more difficult.
  • first electrical bonding member 231 of the circuit board 21 and the second electrical bonding member 232 of the photosensitive chip 22 are formed through a ball planting process, the ball planting materials (solder balls 230, gold There is a certain difference between the diameters of balls, etc., therefore, if the first electrical coupling member 231 or the second electrical coupling member 232 is formed by single-layer ball planting, due to the single-layer ball planting height will exist Certain differences lead to differences in the corresponding heights of the balls during thermocompression bonding. Further, when there is a large difference in the height of the bumps at the corresponding positions between the circuit board 21 and the photosensitive chip 22 , it is easy to have false soldering or non-soldering.
  • the single-layer ball planting process can be adjusted to a multi-layer ball planting process, for example, the ball planting can be adjusted to a double-layer structure, so as to make up for the influence of the height difference through double-layer ball planting.
  • the flatness of attaching the circuit board 21 and the photosensitive chip 22 can be improved by utilizing the complementarity between the diameter differences between the balls by means of double-layer ball planting.
  • the number of ball planting layers can also be other layers.
  • the circuit board 21 is prepared by an additive method or a semi-additive method, therefore, the circuit board 21 has a relatively thin thickness.
  • the circuit board 21 is more easily The deformation and bending cause the photosensitive chip 22 to bend, which in turn causes the camera module to produce defective imaging phenomena such as field curvature.
  • the photosensitive component 20 further includes a molded body 24 integrally formed on the surface of the circuit board 21 through a molding process.
  • the molded body 24 includes a first molding unit 241 integrally integrated with the upper surface 211 of the circuit board 21 through a molding process and integrally integrated with the upper surface 211 of the circuit board 21 through a molding process.
  • the second molding unit 242 of the lower surface 212 of the circuit board 21 is shown in FIGS. 2 to 5 .
  • the photosensitive component 20 also includes at least one electronic component 25 (including but not limited to resistors, capacitors, inductors, etc.) electrically connected to the surface of the circuit board 21, wherein, At least a part of the at least one electronic component 25 is covered by the first molding unit 241 or the second molding unit 242 .
  • the at least one electronic component 25 is arranged on the upper surface 211 of the circuit board 21, and the at least one electronic component 25 is also formed on the upper surface 211 of the circuit board 21.
  • the upper surface 211 is covered by the first molding unit 241 .
  • the molding process of the circuit board 21 is performed after the ball planting process of the circuit board 21, that is, after the ball planting process
  • the circuit board 21 is subjected to a molding process. More preferably, in the embodiment of this application, adopt The circuit board 21 is molded in a similar way of molding up and down at the same time, that is, during molding, the circuit board 21 is clamped and fixed by a molding jig, and the circuit board 21 acts as the molding tool. A component of the fixture.
  • the general molding process is one-sided molding (that is, molding on one side of the circuit board), and it is necessary to set a molded cover on the top of the circuit board 21 and a A molded carrier is arranged below the circuit board 21, wherein the molded carrier carries and fixes the circuit board 21, and the molded cover presses down and is tightly pressed with the molded carrier to form a molding cavity , the circuit board 21 is located at the bottom of the molding cavity, the molding material is poured into the molding cavity, and a molded structure is formed on the surface of the circuit board 21 after curing and demoulding.
  • the circuit board 21 is directly clamped by pressing molds located on its upper and lower sides, and no additional carrying mold is needed to carry the circuit board 21 .
  • the contours of the two contact surfaces of the upper and lower pressing molds and the circuit board 21 can be set to be substantially the same, so that the upper and lower pressing molds
  • the pressure applied to the circuit board 21 is basically coincident in the direction perpendicular to the circuit board 21. In this way, the obvious misalignment of the upper pressing mold and the lower pressing mold is prevented, which will cause the wiring board Bend up or down.
  • the first molding unit 241 formed on the upper surface 211 of the circuit board 21 and the second molding unit 242 formed on the lower surface 212 of the circuit board 21 have a relatively consistent shape and size.
  • the size and shape of the first molding unit 241 and the second molding unit 242 may also have errors. It should be understood that when the first molding unit 241 When there is a difference in size from the second molding unit 242, it is preferable to set a molding unit with a large area under the circuit board 21 during molding (at this time, the circuit board 21 can needs to be turned over), so that the large pressing mold of the large molding layer is used as the bottom support, and the small pressing mold is pressed downwards, and the large molding mold can completely bear the pressure of the main and small pressing mold.
  • the circuit board 21 is turned upside down so that the relatively large first molding unit 241 is formed under the circuit board 21 .
  • the first molding unit 241 and the second molding unit 242 formed on the upper surface 211 and the lower surface 212 of the circuit board 21 can adjust the circuit board 21 to a certain extent. flatness, so that the molded circuit board 21 has relatively higher flatness than the unmolded circuit board. Furthermore, based on the line with relatively higher flatness On the basis of the photosensitive chip 22 and the circuit board 21, performing a thermocompression bonding process on the photosensitive chip 22 and the circuit board 21 can improve the thermocompression bonding quality between the photosensitive chip 22 and the circuit board 21, especially flatness In terms of degree.
  • a preparation process of the photosensitive assembly 20 is as follows: first, a circuit board 21 and a photosensitive chip 22 are provided, wherein the circuit The board 21 has an upper surface 211 and a lower surface 212 opposite to each other, and a through hole 210 formed between the upper surface 211 and the lower surface 212, and the circuit board 21 includes a hole 210 formed on the lower surface 212.
  • a plurality of first electrical connection terminals 21210 wherein the photosensitive chip 22 has an opposite upper surface 221 and a lower surface 222, the upper surface 221 has a photosensitive area 2211 and a non-photosensitive area 2212 located around the photosensitive area 2211
  • the photosensitive chip 22 includes a plurality of second electrical connection terminals 22121 formed on the non-photosensitive region 2212 of the upper surface 221 of the photosensitive chip 22 .
  • a plurality of first electrical joints 231 are formed on the plurality of first electrical connection ends 21210 of the circuit board 21 and a plurality of second electrical connection ends 22121 of the photosensitive chip 22 are respectively formed by a ball planting process.
  • a plurality of second electrical coupling elements 232 are examples of second electrical coupling elements 232 .
  • a first molding unit 241 is formed on the upper surface 211 of the circuit board 21 and a second molding unit 242 is formed on the lower surface 212 of the circuit board 21 through a molding process, so that by the first molding The unit 241 and the second molding unit 242 strengthen the structure of the circuit board 21 .
  • a layer of insulating medium 233 is respectively laid on the first electrical coupling part 231 and/or the second electrical coupling part 232, wherein the glass transition temperature of the insulating medium 233 is lower than that of the first electrical coupling part 232.
  • the junction of the photosensitive chip 22 and the circuit board 21 on the lower surface 212 of the circuit board 21 corresponds to the upper surface of the circuit board 21 .
  • the position of the surface 211 is covered by the first molding unit 241 .
  • the joint between the photosensitive chip 22 and the circuit board 21 at the lower surface 212 of the circuit board 21 is the first electrical coupling member 231 and the second electrical joint.
  • the photosensitive chip 22 is electrically connected to connected to the lower surface 212 of the circuit board 21, therefore, the upper surface 211 of the circuit board 21 is the bearing surface in the thermocompression bonding process, therefore, when the first molding unit 241 is on the circuit board
  • the bonding area of the upper surface 211 of the board 21 covers the position corresponding to the upper surface 211 of the circuit board 21 at the junction of the photosensitive chip 22 and the circuit board 21 on the lower surface 212 of the circuit board 21, the The first molding unit 241 can strengthen the circuit board 21 in the thermocompression bonding process to prevent the circuit board 21 from bending upwards during thermocompression bonding.
  • the circuit board 21 has an inner peripheral edge 2101 and an outer peripheral edge 2102, the inner peripheral edge 2101 of the circuit board 21 forms the through hole 210, and the photosensitive chip 22 has an outer peripheral edge 2102, wherein the The first molding unit 241 has an inner peripheral edge 2411 and an outer peripheral edge 2412 .
  • the inner peripheral edge 2411 of the first molding unit 241 is located at the junction of the photosensitive chip 22 and the circuit board 21 on the lower surface 212 of the circuit board 21 corresponding to the circuit between the position of the upper surface 211 of the board 21 and the inner peripheral edge 2101 of the circuit board 21, so that the junction of the photosensitive chip 22 and the circuit board 21 at the lower surface 212 of the circuit board 21 corresponds to the The position of the upper surface 211 of the circuit board 21 is covered by the first molding unit 241 .
  • the inner peripheral edge 2411 of the first molding unit 241 is aligned with the inner peripheral edge 2101 of the circuit board 21, and the second molding unit 242 has an inner edge 2421 and The outer edge 2422 , the inner peripheral edge 2411 of the first molding unit 241 is closer to the inner peripheral edge 2101 of the circuit board 21 than the inner peripheral edge 2421 of the second molding unit 242 .
  • the outer peripheral edge 2412 of the first molding unit 241 is adjacent to or flush with the outer peripheral edge 2102 of the circuit board 21
  • the peripheral edge 2422 is adjacent to or flush with the outer peripheral edge 2102 of the circuit board 21.
  • the outer peripheral edge 2412 of the first molding unit 241 is in the same height direction as the outer side of the second molding unit 242.
  • the perimeter 2422 is aligned.
  • the joint position of the first molding unit 241 and the second molding unit 242 on the upper surface 211 and the lower surface 212 of the circuit board 21, and, the The geometric parameter configurations of the first molding unit 241 and the second molding unit 242 are not limited by this application.
  • the first projection area of the first molding unit 241 on the upper surface 211 of the circuit board 21 along the height direction set by the photosensitive component 20 and the The second molding unit 242 is arranged on the central axis of the second projected area of the lower surface 212 of the circuit board 21 along the height direction, that is to say, the first The bonding area between a molding unit 241 and the upper surface 211 of the circuit board 21 and the bonding area between the second molding unit 242 and the lower surface 212 of the circuit board 21 are simultaneously aligned with the central axis of the circuit board 21 is the axis, in this way, the distribution of the force formed by the first molding unit 241 on the upper surface 211 of the circuit board 21 is the same as that of the second molding unit 242 on the lower surface of the circuit board 21
  • the force distribution formed by the surface 212 is similar or consistent, so as to improve the flatness of the circuit board 21 through the first molding unit 241 and the second molding unit 242 .
  • the first projection area and the second projection area have the same shape and size, that is, the first molding unit 241 and The bonding area of the upper surface 211 of the circuit board 21 and the bonding area of the second molding unit 242 and the lower surface 212 of the circuit board 21 are completely symmetrical on the upper and lower sides of the circuit board 21, through such way, so that the distribution of the force formed by the first molding unit 241 on the upper surface 211 of the circuit board 21 is the same as that formed by the second molding unit 242 on the lower surface 212 of the circuit board 21 The force distribution is consistent. More specifically, in some embodiments of the present application, as shown in FIG. 2 , the inner periphery of the first projection area is aligned with the inner periphery of the second projection area, and the outer periphery of the first projection area is aligned with the outer periphery of the second projected area.
  • the first projection area and the second projection area have the same shape but different sizes.
  • the outer periphery of the first projection area is aligned with the outer periphery of the second projection area, and the inner periphery of the first projection area is larger than the inner periphery of the second projection area.
  • the peripheral edge is closer to the inner peripheral edge 2101 of the circuit board 21 .
  • the inner periphery of the first projection area is aligned with the inner periphery of the second projection area, and the outer periphery of the second projection area is The outer periphery of the first projected area is closer to the outer periphery 2102 of the circuit board 21 . In this regard, it is not limited by this application.
  • the at least one electronic component 25 is covered by the first molding unit 241 or the second molding unit 242 . More specifically, in some embodiments of the present application, the at least one electronic component 25 is formed on the upper surface 211 of the circuit board 21 .
  • the bottom surface of the first molding unit 241 (the first molding unit 241 The bottom surface of the first molding unit 241 is combined with the upper surface 211 of the circuit board 21) has a back-shaped structure, wherein the bottom surface of the first molding unit 241 has the inner peripheral edge 2411 and the outer peripheral edge 2412, wherein the inner peripheral edge 2411 of the first molding unit 241 is located between the electronic component 25 and the inner peripheral edge 2101 of the circuit board 21; the first molding unit 241
  • the outer peripheral edge 2412 is located between the electronic component 25 and the outer peripheral edge 2102 of the circuit board 21 , preferably, is flush with the outer peripheral edge 2102 of the circuit board 21 .
  • the distance between the top surface of the first molding unit 241 and the upper surface 211 of the circuit board 21 is greater than the height of the electronic components 25, so that the first molding unit 241 completely covers the electronic components 25 after molding, which protects the electronic components and prevents the electronic components from falling off due to external force. damaged etc.
  • the height of the first molding unit 241 is 0.35 mm to 0.5 mm, preferably greater than or equal to 0.4 mm.
  • the first molding unit 241 can further replace the mirror holder in the existing COB camera module, and provide an installation carrier for the lens driving assembly 30 or the optical lens 10 .
  • the lens driving assembly 30 or the optical lens 10 is installed in the first molding unit 241, compared with the COB camera module, the originally reserved space between the lens holder and the electronic components 25 The horizontal avoidance distance and longitudinal avoidance distance are cancelled, therefore, the cross-sectional size of the camera module and its photosensitive assembly 20 can be further reduced, and the height dimension of the camera module and its photosensitive assembly 20 can also be further reduced decrease. Due to the technical characteristics of the molding process itself, the surface of the molded structure has a very high flatness.
  • the second molding unit 242 is integrally combined with the lower surface 212 of the circuit board 21 .
  • the surface where the second molding unit 242 is in contact with the lower surface 212 of the circuit board 21 is defined as the top surface of the second molding unit 242, and the second molding unit 242 is far away from
  • the lower surface 212 of the circuit board 21 and the surface parallel thereto are defined as the bottom surface of the second molding unit 242 .
  • the top surface of the second molding unit 242 has a back-shaped structure, which has the inner peripheral edge 2411 and the outer peripheral edge 2412 .
  • the second molding unit 242 The inner peripheral edge 2411 of the second molding unit 242 is located between the outer peripheral edge 2102 of the photosensitive chip 22 and the outer peripheral edge 2102 of the circuit board 21.
  • the inner peripheral edge 2411 of the second molding unit 242 is in line with the first The inner periphery 2411 of a molding unit 241 is flush, and the outer periphery 2412 of the second molding unit 242 is flush with the outer periphery 2412 of the first molding unit 241 in the projection direction, so that the second The molding unit 242 can balance the warpage of the circuit board caused by the stress generated by the first molding unit 241 on the circuit board 21 to the greatest extent.
  • the projection areas of the molding unit 242 on the circuit board 21 may also not overlap, and have different area sizes.
  • the second molding unit 242 further compensates for the The assembly accuracy error caused by the unevenness of the circuit board 21 itself, and the uncontrollable influencing factors brought about by the unavoidable unevenness and warpage of the circuit board 21 during manufacturing on the imaging quality can be controlled , and then in the subsequent assembly process, active calibration and algorithms are used to compensate the impact of the controllable influencing factors on imaging, such as field curvature.
  • the first molding unit 241 and the second molding unit 242 jointly exert force on the circuit board 21 to improve the overall flatness of the circuit board, thereby After subsequent thermal compression bonding of the photosensitive chip 22 and the photosensitive chip 22 , attachment of the optical lens 10 or the lens driving assembly 30 and other processes, the accumulated error value can be effectively reduced to the minimum.
  • the height of the second molding unit 242 is slightly greater than or equal to the distance between the lower surface 222 of the photosensitive chip 22 and the lower surface 212 of the circuit board 21, that is, the second The bottom surface of the molding unit 242 is slightly lower than the lower surface 222 of the photosensitive chip 22 , so that the second molding unit 242 surrounds the photosensitive chip 22 to protect the photosensitive chip 22 .
  • the height dimension of the second molding unit 242 is preferably 0.2-0.3 mm.
  • the photosensitive assembly 20 further includes an adhesive layer disposed between the photosensitive chip 22 and the second molding unit 242, so as to form an adhesive layer for protecting the photosensitive chip after the adhesive layer is cured.
  • the sealed protective structure is used to isolate dust and prevent contamination of the photosensitive chip.
  • the circuit board 21 is first subjected to a molding process to form the molded body 24 on the surface of the circuit board 21, and then through the thermocompression bonding process
  • the reason for combining the photosensitive chip 22 and the circuit board 21 is: if the photosensitive chip 22 and the circuit board are combined together through a thermocompression bonding process before performing the molding process, The contact position where the molding indenter presses on the surface of the circuit board 21 is very close to the electrical connection structure between the photosensitive chip 22 and the circuit board 21, and the pressure caused by the molding indenter on the circuit board 21 It may destroy the electrical connection structure between the photosensitive chip 22 and the circuit board 21; secondly, when the molding fluid is poured into the mold, it will cause a relatively large impact on the circuit board 21, and may also damage the photosensitive chip 22. An electrical connection structure between the chip 22 and the circuit board 21 .
  • the large-sized photosensitive chip itself has the characteristics of easy deformation, so special attention should be paid to the processing technology of the photosensitive chip, for example, in the process of molding and packaging the photosensitive chip, the attachment of the photosensitive chip In the process of circuit boards, the photosensitive chip may be deformed and the photosensitive chip bent during the process of baking the glue after the photosensitive chip is mounted, which will affect the imaging quality of the final camera module.
  • the photosensitive chip 22 is mounted on the lower surface 212 of the circuit board 21 through a flip-chip process.
  • the first electrical coupling 231 and the second electrical coupling 232 are generally made of metal materials such as copper or tin, the thermal expansion coefficient of which is close to that of the photosensitive chip 22, therefore, when heated Due to the relative consistency of the CTE, the stress generated by the thermal deformation between the layers after thermal expansion will be reduced, and the effect of protecting the photosensitive chip 22 from warping and deformation will be better than that of the COB process photosensitive chip.
  • the first molding unit 241 and the second molding unit 242 are arranged on the upper surface 211 and the lower surface 212 of the circuit board 21, the first molding unit 241 and the second molding unit The molding unit 242 applies different stresses and stresses of different widths to the circuit board 21 during the respective molding processes. These stresses of different degrees can improve the upper and lower molding after proper design and process adjustment.
  • the flatness of the circuit board 21 has an effect similar to that of an electric iron.
  • the photosensitive component 20 also includes a heat dissipation layer disposed on the lower surface 212 of the photosensitive chip 22, wherein the heat dissipation layer can be a passive heat dissipation element 271, such as graphene
  • the coating can uniformize the heat along the cross-sectional direction of the photosensitive chip 22 in a short time.
  • the heat dissipation layer can also be laid on other positions, for example, it can be coated on the lower surface 222 of the photosensitive chip 22 and the lower surface of the second molding unit 242 at the same time, In this regard, it is not limited by this application.
  • the heat generated by the photosensitive chip 22 is conducted along the Z-axis direction set by the photosensitive element 20 .
  • the heat sink and the The heat dissipating layers are connected together, and are used to conduct the heat transferred in the cross-sectional direction of the photosensitive chip 22 out of the camera module from the Z-axis direction.
  • the thickness of the heat sink is not greater than the height of the second molding unit 242, that is, the bottom surface of the heat sink is lower than the bottom surface of the second molding unit 242, wherein the There is an escape space between the outer edge of the second molding unit 242 and the outer peripheral edge 2102 of the circuit board 21 , and the heat sink is disposed in the escape space.
  • the photosensitive component 20 further includes an optical element mounted on the first molding unit 241, wherein the optical element may be an optical lens (for convenience of description) Defined as the second optical lens 121) or the filter element 26.
  • the optical element may be an optical lens (for convenience of description) Defined as the second optical lens 121) or the filter element 26.
  • the second optical lens 121 cooperates with the first molding unit 241 to form the second lens unit 12 of the optical lens 10 .
  • the optical lens 10 is a split lens, which includes at least two lens units, for example, a first lens unit 11 and a second lens unit 12, wherein the first The molding unit 241 has an installation cavity 2410 for installing the second optical lens 121 , and the first molding unit 241 and the second optical lens 121 form the second lens unit 12 .
  • the optical element when the optical element is mounted on the first molding unit 241, the optical element, the photosensitive chip 22 and the circuit board 21 are surrounded by each other to form a seal between the three. cavity, so that the photosensitive area 2211 of the photosensitive chip 22 will not be polluted due to the entry of external dust through the sealed cavity.
  • the first molding unit 241 is integrally formed on the upper surface 211 of the circuit board 21 through a molding process, therefore, no bonding medium such as glue is needed Filling between devices, so that the height dimension of the camera module and its photosensitive assembly 20 can be reduced from the stacking direction.
  • the top surface of the first molding unit 241 has a relatively high flatness, It is beneficial to ensure the installation accuracy of other components on the first molding unit 241 .
  • the mirror base/motor base is used as a structural part, it is always necessary to avoid contact with electronic components 25 (requires Z-axis direction, X-axis and Y-axis directions), therefore, compared with the integral molding of the molded body 24, it is difficult to improve the dimensions in the three directions of the XYZ axes in the prior art.
  • the first molding unit 241 is formed by a molding process, the height of the molded integral molding is based on the maximum height dimension of the electronic components 25, so as long as the electronic components 25 can be protected That is, there is no need to reserve a gap of 0.1mm-0.2mm in the Z-axis direction. And for the horizontal space, because there is no need It is necessary to consider the attachment deviation of the electronic components 25, the dimensional changes caused by the glue baking, etc. Therefore, there is no need to reserve a space of about 0.2mm-0.4mm in the cross-sectional direction.
  • the photosensitive chip 22 is attached and electrically connected to the lower surface 212 of the circuit board 21 by flip-chip, that is, the circuit board 21 is located on the bottom surface of the photosensitive chip 22.
  • the circuit board 21 is located in the back focus area between the optical element (when the optical element is implemented as the second optical lens 121 ) and the photosensitive chip 22 .
  • circuit board 21 may not be provided on the back side of the photosensitive chip 22, it can reduce the 0.2mm-0.3mm from the bottom of the photosensitive chip 22 when the circuit board 21 is arranged on the lower side
  • the size of the stack in the Z-axis direction caused by the thickness of the circuit board 21 itself, and the space of 1mm-1.5mm in the back focus area is generally enough to accommodate the circuit board 21.
  • the second optical lens 121 cooperates with the first molding unit 241 to form the second lens unit 12, At this time, the first molding unit 241 is equivalent to the second lens barrel 122 of the second lens unit 12 .
  • the first lens unit 11 of the optical lens 10 includes a first lens barrel 112 and at least one first optical lens 111 accommodated in the first lens barrel 112 .
  • the lowest lens of the optical lens 10 is the second optical lens 121 installed on the first molding unit 241, therefore, the camera module
  • the back focus size of the group is the distance between the second optical lens 121 and the photosensitive chip 22 .
  • the distance between the second optical lens 121 and the photosensitive chip 22 only includes the height dimension of the circuit board 21, the height dimension of the integrated electrical conduction structure 23, the The avoidance gap between the second optical lens 121 and the photosensitive chip 22, and the attachment gap of the second optical lens 121, compared with the existing camera module assembled by the COB process, according to the embodiment of the present application
  • the size of the back focus of the camera module can be greatly reduced, so that the total optical length (Total Track Length, TTL) of the camera module can also be reduced.
  • the camera module according to the embodiment of the present application is compared with the traditional camera module assembled by the COB process, and its back focus size is reduced by the height dimension of the filter element 26 (0.1mm-0.2mm), The attachment gap (0.02mm-0.04mm) of the filter element 26 and the minimum avoidance space (0.5mm-1mm) between the last lens of the optical lens 10 and the filter element 26.
  • the back focus size of the camera module according to the embodiment of the present application is 0.41mm-0.72mm
  • the back focus size of the traditional camera module is 0.62mm-1.24mm, that is, compared to the traditional COB process Assembled camera module, according to the camera module of the present application, the reduction of the back focus space of 40-80% is realized.
  • the ratio between the back focus size of the camera module and its total optical length is 0.05-0.20.
  • the filter element 26 can be disposed on the upper surface 221 of the photosensitive chip 22, for example, the filter element 26 is implemented to be coated on the In this way, the filter film on the upper surface 221 of the photosensitive chip 22 can make full use of the back focus space of the camera module to compress the overall height of the camera module and its photosensitive component 20 .
  • the large aperture camera is especially suitable for use in portrait mode shooting.
  • the aperture of the camera module used as the main camera is required to be above F2.0, and some apertures are even required to be F1.4.
  • the effective focal length of 9mm it can be drawn that the light exit apertures of the last eyeglass of the required optical lens 10 are respectively 4.5mm (corresponding to the aperture being F2.0), 5mm, 6.4mm, and 9mm ( Corresponding to the aperture of F1.0).
  • the field of view diaphragm of the optical lens corresponding to the photosensitive chip 22 will also become larger, so the field of view light where the optical lens is often located
  • the original aperture of the diaphragm can be calculated according to the field of view angle of 90°.
  • the maximum outer diameter of the optical lens is generally 3 times the light exit aperture, so the maximum outer diameter of the last optical lens is 13.5mm, 15mm, 19.2mm, 27mm.
  • the ratio of the maximum outer diameter of the last optical lens to the long side dimension of the photosensitive chip 22 is 0.85, 0.94, 1.2, 1.6875.
  • the lens closest to the photosensitive chip 22 in the optical lens 10 is the second optical lens 121, therefore, in the embodiment of the application, the second optical lens
  • the ratio between the maximum outer diameter of 121 and the long side of the photosensitive chip 22 is 0.85-1.7.
  • the peripheral dimension will be increased by 2mm-3mm, so the belt
  • the maximum outer diameter of the camera module of the lens driving assembly 30 is 15.5mm, 17mm, 21.2mm, 29mm.
  • the ratio between the maximum outer diameter size of the camera module with the lens drive assembly 30 and the long side size of the photosensitive chip 22 is between 0.97-1.82, and these parameters can explain that due to The circuit board 21 can be made small, so relatively speaking, the size of the photosensitive chip 22 can be increased appropriately.
  • the optical lens closest to the photosensitive chip 22 in the optical lens 10 is the second optical lens 121 mounted on the first molding unit 241, and, the The second optical lens 121 at the bottom of the optical lens 10 has a relatively largest outer diameter. It should be understood that by increasing the size of the last optical lens in the optical lens 10 , the overall light throughput of the optical lens 10 can be increased. Moreover, the maximum outer diameter of the second optical lens 121 determines the maximum outer diameter of the optical lens 10 .
  • the ratio between the maximum outer diameter dimension of the second optical lens 121 and the long side dimension of the photosensitive chip 22 is 1.2-1.7, preferably, the second optical lens
  • the maximum outer diameter of 121 is less than or equal to 1.2 times the long side of the photosensitive chip 22 . It should be understood that, since the maximum outer diameter of the second optical lens 121 is close to the length of the long side of the photosensitive chip 22, in the design of the optical lens 10, the photosensitive chip 22 can The long side dimension serves as the design basis of the minimum size, and benefits from the size miniaturization of the circuit board 21 and its photosensitive assembly 20 of the present application, therefore, the size of the optical lens 10 and the lens driving assembly 30 can be further reduction.
  • the size of the back focus of the camera module can be reduced.
  • the aperture of the optical lens is too large, it will bring a larger diffusion area, so that the light will cause vignetting and the like when passing through the molded body 24. That is to say, in the embodiment of the present application, The size of the second optical lens 121 does not need to be too large.
  • the D-cut optical approach is used to effectively compress the outer space of the effective aperture of the second optical lens 121, thereby reducing the size of the second optical lens 121. size.
  • the second optical lens 121 has two cut sides respectively corresponding to the two short sides of the photosensitive chip 22, wherein the two cut sides are opposite to each other. Based on the symmetrical distribution of the central axis set by the optical lens, cutting the invalid area of the second optical lens 121 can not only reduce the size of the second optical lens 121, but also facilitate the operation of the second optical lens. 121 for injection molding.
  • the second optical lens 121 has a first cut side 1211 and a second cut side 1212 corresponding to the two long sides of the photosensitive chip 22, and , corresponding to the third cut edge 1213 and the fourth cut edge 1214 of the two short sides of the photosensitive chip 22 . Moreover, structural regions for bonding are provided on the four corner regions of the second optical lens 121 .
  • the second optical lens 121 has protrudingly formed
  • the four light-transmitting regions 1215 in each corner region are used to transmit light. It should be understood that the distances between the four corners of the second optical lens 121 relative to the set centers thereof are the largest, so if a The problem of eccentricity may easily cause dark corners to appear in the corresponding four corners of the photosensitive chip 22 . Therefore, in the embodiment of the present application, four light-transmitting regions 1215 are configured in four corner regions of the second optical lens 121 .
  • the four corners of the optical zone of the second optical lens 121 are provided with corresponding free-form surface extension sides to form the four light-transmitting regions 1215, wherein the four light-transmitting regions 1215 are located at the second
  • the free-form surface extension sides of the four corner regions of the optical lens 121 have an optical curvature consistent with the optical zone, which is equivalent to increasing the optical zone of the second optical lens 121 in disguise, thereby increasing the second optical zone.
  • the total light transmission area of the lens 121 is equivalent to increasing the optical zone of the second optical lens 121 in disguise, thereby increasing the second optical zone.
  • four structural areas can be set at the four corners of the second optical lens 121, and corresponding The optical curved surfaces at the four corners of the lens 121 can also increase the light transmission area of the effective optical region of the second optical lens 121 .
  • the camera module has an optical anti-shake function to improve the user's shooting experience.
  • the optical lens 10 may be driven to move in a plane perpendicular to the optical axis by the lens driving assembly 30 for optical anti-shake.
  • the anti-shake driving object is set as the photosensitive component 20, and the lens driving The component 30 is used to drive the first lens unit 11 of the optical lens 10 to move along the direction set by the optical axis for optical focusing.
  • the camera module further includes a chip drive component for driving the photosensitive component 20 to move in a plane perpendicular to the optical axis to achieve optical image stabilization.
  • the chip driver assembly 40 includes: a driver unit 41 , a lead frame 42 , an anti-shake bracket 43 and an anti-shake housing 44 .
  • the photosensitive assembly 20 is accommodated in the anti-shake housing 44 , the anti-shake bracket 43 is fixed in the anti-shake housing 44 and is located on the side of the photosensitive assembly 20 Outside, the lead frame 42 extends over the Between the photosensitive assembly 20 and the anti-shake support 43 and the photosensitive assembly 20 is movable relative to the anti-shake support 43 through the lead frame 42, the driving unit 41 is suitable for driving the photosensitive assembly 20 relative to the The anti-shake bracket 43 is moved for optical anti-shake.
  • the type of the lens driving assembly 30 is not limited by the present application, and includes but not limited to: electromagnetic motors, memory alloy actuators, piezoelectric actuators, and the like.
  • the lens drive assembly 30 is implemented as an electromagnetic motor, which includes: a first carrier 31 for carrying the first lens unit 11 , for driving the first The carrier 31 is used to drive the focusing coil 32 and the focusing magnet 33 of the first lens unit 11, the first elastic piece 34 and the second elastic piece 35 for limiting the movement of the first carrier 31, and for accommodating The first carrier 31 , the focus coil 32 and the focus magnet 33 , the first elastic piece 34 and the focus casing 36 of the second elastic piece 35 .
  • the chip driving assembly 40 is also implemented as an electromagnetic motor, wherein the driving unit 41 includes a driving coil 411 and a driving coil corresponding to the driving coil 411 magnet 412.
  • the driving magnet 412 of the chip driving assembly 40 and the focusing magnet 33 of the lens driving assembly 30 are the same magnet. More specifically, the driving coil 411 is disposed on the upper surface 211 of the circuit board 21 and outside the first molding unit 241 .
  • the lead frame 42 includes a fixed plate 421 arranged on the anti-shake bracket 43 , a movable plate 423 arranged on the circuit board 21 , and an elastic connecting band 422 connecting the movable plate 423 and the fixed plate 421 , wherein, on the one hand, the elastic element can provide a relatively stable initial state for the movable moving plate 423, and on the other hand, it can also play a role of circuit conduction.
  • the moving plate 423 has a light hole in its middle area, and the light hole corresponds to the photosensitive area 2211 of the photosensitive chip 22, so that the camera module light can pass through the light hole reach the photosensitive area 2211 of the photosensitive chip 22 .
  • the moving plate 423 of the lead frame 42 is fixedly connected with the circuit board 21 and is electrically connected, and the two can be fixed by welding.
  • the fixing plate 421 of the lead frame 42 is fixedly connected to the anti-shake bracket 43 , wherein the anti-shake bracket 43 is fixed in the anti-shake housing.
  • the anti-shake bracket 43 is a fixed object, and the photosensitive component 20 is suspended in the anti-shake housing through the lead frame 42 and can move relative to the anti-shake bracket 43 .
  • the lead frame 42 When the driving magnet 412 and the driving coil 411 generate electromagnetic induction, the lead frame 42 provides a certain restoring force, further making the lead frame 42 can still return to its original position after being driven and deformed; when the lead frame 42 is driven and deformed, it drives the circuit board 21 connected to it to move and then drives the entire photosensitive assembly 20 to move perpendicular to the light The movement is carried out in the plane of the axis, so that the photosensitive chip 22 realizes optical anti-shake in the direction of the X axis or the direction of the Y axis.
  • the inner end of the anti-shake bracket 43 has a heat sink, and the heat sink includes an active heat sink 272 and a passive heat sink 271.
  • the active heat sink 272 is set The fixed portion of the lead frame 42 or the upper surface of the anti-shake bracket 43 has the function of active heat dissipation, and the active heat dissipation element 272 has a high heat conduction efficiency, which reduces the heat generated by the photosensitive chip 22 ;
  • the passive heat sink 271 is disposed on the bottom of the photosensitive chip 22 .
  • the passive heat dissipation element 271 is a graphene coating, and the graphene coating can extend outward to the active heat dissipation element 272. Its lateral thermal conductivity is very strong, and it can cooperate with the active heat dissipation element 272 to dissipate heat. higher efficiency.
  • the driving unit 41 includes four driving coils 411, wherein the four driving coils 411 are arranged on four of the upper surface 211 of the circuit board 21. at the corner and outside of the first molding unit 241 .
  • the circuit board 21 further includes a plurality of third electrical connection terminals 2111 formed on the upper surface 211 thereof and located between every two driving coils 411 . More specifically, in the embodiment of the present application, the plurality of third electrical connection terminals 2111 are located in the middle of four sides of the upper surface 211 of the circuit board 21 .
  • the coverage area of the first molding unit 241 is: remove the through hole 210 formed in the middle area of the circuit board 21, remove the four driving parts located in the four corner areas.
  • the coil 411 is the remaining part except the plurality of third electrical connection ends 2111 located in the middle area of the four sides. It is worth mentioning that, compared with the second molding unit 242, since the first molding unit 241 needs to set more avoidance space, in some embodiments of the present application, the first molding unit The covering area of the molding unit 241 on the upper surface 211 of the circuit board 21 is greater than the covering area of the second molding unit 242 on the lower surface 212 of the circuit board 21 .
  • the moving board 423 includes a moving board main body 4231 and at least one conductive protrusion 4232 extending inward from the inner frame of the moving board main body 4231 , the at least one The conductive protrusion 4232 is electrically connected to the upper surface 211 of the circuit board 21 . More specifically, in the embodiment of the present application, the at least one conductive protrusion 4232 includes four conductive protrusions 4232, and the four conductive protrusions 4232 respectively correspond to the first molding The middle parts of the four sides of the outer peripheral edge 2412 of the unit 241 are respectively electrically connected to the plurality of third electrical connection terminals 2111 located in the middle regions of the four sides.
  • the lead frame 42 in the photosensitive assembly 20 can also be arranged on the lower surface 212 of the circuit board 21 , at this time, the movement of the lead frame 42
  • the board 423 is fixedly connected and electrically connected to the lower surface 212 of the circuit board 21 , and the two are fixed by welding.
  • the heat dissipation element includes an active heat dissipation element 272 and a passive heat dissipation element 271, and the active heat dissipation element 272 is arranged on the fixed part of the lead frame 42 or the upper surface of the anti-shake bracket 43, It has the function of active heat dissipation, and the active heat dissipation element 272 has high heat conduction efficiency, which reduces the heat generated by the photosensitive chip 22.
  • the passive heat dissipation element 271 is arranged at the bottom of the photosensitive chip 22.
  • the The passive heat sink 271 is a graphene coating, and the graphene coating can extend outward to the moving plate 423 of the lead frame 42, and the moving plate 423 is then connected to the active heat sink 272 through a line, and its lateral direction
  • the thermal conductivity is very strong, and it can work with the active heat dissipation element 272, so that the heat dissipation efficiency is higher.

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Abstract

公开了一种感光组件及其电导通方法和制备方法、摄像模组，其中，所述感光组件包括线路板和以倒装的方式贴装于所述线路板的下表面的感光芯片。特别地，所述感光芯片和所述线路板之间通过一体电导通结构实现相互之间的电连接，其中，所述一体电导通结构既能够确保所述感光芯片和所述线路板之间的电连接，又能够确保所述感光芯片和所述线路板的物理连接的稳定性。

Description

感光组件及其电导通方法和制备方法、摄像模组 技术领域
本申请涉及模组组装领域，尤其涉及感光组件及其电导通方法和制备方法、线路板组件及其制备方法、摄像模组。
背景技术
随着移动电子设备的普及，被应用于移动电子设备的用于帮助使用者获取影像的摄像模组的相关技术得到了迅猛的发展和进步，摄像模组已经普遍安装在诸如平板电脑、笔记本电脑以及智能手机等移动电子设备中。
为了满足越来越广泛的市场需求，高像素、大芯片、小尺寸、大光圈是现有摄像模组不可逆转的发展趋势。然而，要在同一摄像模组实现高像素、大芯片、小尺寸、大光圈四个方面的需求是有很大难度的。例如，第一，市场对摄像模组的成像质量提出了越来越高的需求，如何以较小的摄像模组体积获得更高的成像质量已成为紧凑型摄像模组(例如用于手机的摄像模组)领域的一大难题，尤其是建立在手机行业高像素、大光圈、大芯片等技术发展趋势的前提下；第二，手机的紧凑型发展和手机屏占比的增加，让手机内部能够用于前置摄像模组的空间越来越小；后置摄像模组的数量越来越多，占据的面积也越来越大，导致手机其他配置诸如电池尺寸、主板尺寸相应缩小，为了避免其他配置的牺牲，市场希望后置摄像模组体积能缩小，即实现小尺寸封装；第三，随着高像素芯片普及和视频拍摄等功能逐步提升，芯片能耗和散热成为重要问题，需要在模组设计制造过程中加以解决。
上述市场需求是摄像模组封装行业的发展瓶颈，造成上述需求迟迟未得到解决的问题原因分析主要如下：
(1)高像素、大芯片尺寸：由于其芯片尺寸逐步提升，比如现阶段比较常见的4800万像素以上芯片，其尺寸1/2英寸，未来1/1.7英寸芯片乃至更大尺寸芯片普及，导致芯片尺寸快速增大，但是由于感光芯片相对一般芯片要薄，只有0.15mm左右厚度，所以大芯片更容易产生场曲问题。同时，由于芯片和线路板之间一般通过胶水连接，胶水涂布一般呈现四周低中间高 的形态，比如米字型画胶，导致芯片中部会微微隆起。再者，芯片贴附时，由于吸嘴从上部吸取芯片，导致芯片也会成像四周低于中央的弯曲形态。还有，芯片、胶水、线路板之间产品热膨胀系数(CTE)指数不同，比如芯片CTE是6ppm/C，而PCB是14ppm/C，模组组装工艺中一般都有烘烤工艺，基于各种材质CTE系数不同会导致芯片弯曲问题，而目前业内常规采用的软硬结合板由于采用层压工艺，自带翘曲较为严重，也会加剧芯片弯曲问题。而上述芯片弯曲问题会在最终的模组成像上造成芯片场曲问题，并最终影响成像品质。
(2)小型化/小尺寸：随着感光芯片朝着高像素和大尺寸的方向发展，与感光芯片适配的摄像模组内的其他光学部件的尺寸也将增大。例如，对于摄像模组的截面尺寸而言(即，X轴和Y轴方向上的尺寸)，由于感光芯片的像面变大，导致光学镜头的尺寸变大，而光学镜头的尺寸增加又会导致用于驱动光学镜头移动的马达的尺寸变大，进而导致模组整体截面尺寸的增加。应可以理解，由于光学镜头的尺寸增大，对用于驱动光学镜头进行移动的马达的驱动力要求需提高，相应地，马达中的回复器件,例如弹片，的尺寸需增加，驱动所需的线圈和磁石也会因为相对行程的变化，尺寸也需增加。
(3)大光圈
为了提高摄像模组的进光量以提高成像质量，摄像模组倾向于采用大光圈的光学方案。在大光圈的方案中，光学镜头中光学透镜的孔径要大得多，这会导致光学镜头的最大外径尺寸大于感光芯片的长边长度，造成光学镜头的截面尺寸比感光芯片的截面尺寸大的局面。
因此，需要一种满足高像素、大芯片、小尺寸和大光圈的模组设计方案和制备方案。
发明内容
本申请的一优势在于提供一种感光组件及其电导通方法，其中，所述感光组件包括线路板和以倒装的方式贴装于所述线路板的下表面的感光芯片，所述感光芯片和所述线路板之间通过一体电导通结构实现相互之间的电连接，其中，所述一体电导通结构既能够确保所述感光芯片和所述线路板之间的电连接，又能够确保所述感光芯片和所述线路板的物理连接的稳定性。
本申请的一优势在于提供一种感光组件和摄像模组，其中，所述摄像模 组将所述光学镜头的一部分集成于所述感光组件以使得所述摄像模组具有相对更优的光学设计和尺寸设计。
本申请的一优势在于提供一种感光组件及其制备方法，其中，所述感光组件包括线路板、感光芯片，其中，通过多个一体电导通结构所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域；以及，模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元。这样，通过模塑工艺和电导通工艺来优化所述感光芯片倒装于所述线路板的组装精度和电连接的稳定性。
本申请的一优势在于提供一种摄像模组，其中，通过特殊的结构配置和制备工艺所述摄像模组具有特殊的参数配置，具体地，所述光学镜头的最大外径尺寸与所述感光芯片的长边长度之间的比值为0.85至1.7。
本申请的一优势在于提供一种摄像模组，其中，所述摄像模组包括感光组件、被保持于所述感光组件的感光路径上的光学镜头，以及，用于驱动所述感光组件相对于所述光学镜头进行移动的芯片驱动组件。特别地，在本申请实施例中，所述感光组件采用由加成法或半加成法制得的线路板作为安装基板并通过特殊的工艺和结构设计来充分发挥所述线路板的优势和弥补其劣势。
本申请的一优势在于提供一种线路板组件及其制备方法，其中，所述线路板组件包括由加成法或者半加成法制成的线路板，其中，所述线路板具有相对的上表面和下表面以及贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板的下表面具有邻近于所述通孔的电导通区域和位于所述电导通区域的外围的周围区域，所述线路板包括形成于所述电导通区域的多个第一电连接端。所述线路板组件还包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的周围区域的第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元来加强所述线路板的结构强度和优化所述线路板组件的平整度。
通过下面的描述，本申请的其它优势和特征将会变得显而易见，并可以通过权利要求书中特别指出的手段和组合得到实现。
为实现上述至少一优势，本申请提供一种感光组件，其包括：
线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面 和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；以及
多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘；
其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘；
其中，所述线路板的通孔对应于所述感光芯片的感光区域。
在根据本申请的感光组件中，所述绝缘介质的玻璃化温度小于所述第一电结合件和所述第二电结合件的熔点。
在根据本申请的感光组件中，所述第一电结合件和所述第二电结合件由相同的金属材料制成，所述第一电结合件和所述第二电结合件具有相同的熔点。
在根据本申请的感光组件中，所述第一电结合件和所述第二电结合件的熔点温度与所述绝缘介质的玻璃化温度之差大于等于30°小于等于80°
在根据本申请的感光组件中，所述绝缘介质的玻璃化温度为180°，所述第一电结合件和所述第二电结合件的熔点为250°。
在根据本申请的感光组件中，所述第一电结合件和所述第二电结合件由锡球制成，所述绝缘介质被实施为NCP助焊剂。
在根据本申请的感光组件中，所述第一电结合件通过回流焊与所述第一电连接端进行电连接，所述第二电结合件通过回流焊与所述第二电连接端进行电连接，所述第一电结合件和所述第二电结合件通过热压工艺实现共晶结 合。
在根据本申请的感光组件中，所述第一电连接端具有预设截面尺寸以允许至少五颗所述锡球同时堆叠于所述第一电连接端上，所述第二电连接端具有预设截面尺寸以允许至少五颗所述锡球同时堆叠于所述第二电连接端上。
在根据本申请的感光组件中，所述第一电连接端和所述第二电连接端的直径为70um，所述锡球的直径为5um-15um。
在根据本申请的感光组件中，所述线路板由加成法或半加成法制备而成。
在根据本申请的感光组件中，所述线路板还包括铺设于所述下表面的所述多个第一电连接端的外围的油墨层，其中，在所述多个第一电连接端之间不设有所述油墨层。
在根据本申请的感光组件中，所述多个第一电连接端均匀地且等间距的分布于所述线路板的下表面。
本申请还提供一种感光组件，其包括：
线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
其中，所述线路板的下表面叠置于所述感光芯片的上表面且所述多个第一电连接端分别对应并电连接于所述多个第二电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域；以及
模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元，其中，所述第一模塑单元沿所述感光组件设定的高度方向上在所述线路板的上表面的第一投影区域与所述第二模塑单元沿所述高度方向在所述线路板的下表面的第二投影区域共中心轴设置。
在根据本申请的感光组件中，所述第一投影区域和所述第二投影区域具有相同的形状和尺寸。
在根据本申请的感光组件中，所述第一投影区域和所述第二投影区域具有相同的形状和不同的尺寸。
在根据本申请的感光组件中，所述第一投影区域的内周缘对齐于所述第二投影区域的内周缘，所述第一投影区域的外周缘对齐于所述第二投影区域的外周缘。
在根据本申请的感光组件中，所述第一投影区域的外周缘与所述第二投影区域的外周缘对齐，所述线路板具有形成所述通孔的内周缘，其中，所述第一投影区域的内周缘相较于所述第二投影区域的内周缘更邻近于所述线路板的内周缘。
在根据本申请的感光组件中，所述第一投影区域的内周缘与所述第二投影区域的内周缘对齐，所述线路板具有外周缘，其中，所述第二投影区域的外周缘相较于所述第一投影区域的外周缘更邻近于所述线路板的外周缘。
在根据本申请的感光组件中，所述感光组件还包括被设置于所述线路板的上表面且被所述第一模塑单元包覆的至少一电子元器件。
在根据本申请的感光组件中，所述第一模塑单元的高度尺寸为0.35mm至0.5mm。
在根据本申请的感光组件中，所述线路板由加成法或半加成法制备而成，所述线路板的厚度尺寸为0.05mm-0.35mm。
在根据本申请的感光组件中，所述第一模塑单元具有顶表面，所述顶表面的平整度RZ为5um。
在根据本申请的感光组件中，所述第一模塑单元的高度尺寸大于所述第二模塑单元的高度尺寸。
在根据本申请的感光组件中，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
在根据本申请的感光组件中，所述第二模塑单元包绕地形成于所述感光芯片的周围。
在根据本申请的感光组件中，所述第二模塑单元的高度尺寸大于所述感光芯片的厚度尺寸。
在根据本申请的感光组件中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第 二电连接端通过所述多个一体电导通结构进行绝缘。
在根据本申请的感光组件中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘；
在根据本申请的感光组件中，所述绝缘介质的玻璃化温度小于所述第一电结合件和所述第二电结合件的熔点。
本申请还提供一种感光组件，其包括：
线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；
多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域；以及
模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元。
在根据本申请的感光组件中，所述感光芯片与所述线路板在所述线路板的下表面的结合处对应于所述线路板的上表面的位置被所述第一模塑单元所包覆。
在根据本申请的感光组件中，所述线路板具有内周缘和外周缘，所述线路板的内周缘形成所述通孔，所述感光芯片具有外周缘，其中，所述第一模塑单元具有内侧周缘和外侧周缘，所述第一模塑单元的内侧周缘位于所述感光芯片与所述线路板在所述线路板的下表面的结合处对应于所述线路板的上表面的位置和所述线路板的内周缘之间。
在根据本申请的感光组件中，所述第一模塑单元的内侧周缘与所述线路板的内周缘对齐。
在根据本申请的感光组件中，所述第二模塑单元具有内侧边缘和外侧边缘，所述第一模塑单元的内周缘相对于所述第二模塑单元的内周缘更邻近于所述线路板的内周缘。
在根据本申请的感光组件中，所述第一模塑单元的外侧周缘邻近于或者齐平于所述线路板的外周缘。
在根据本申请的感光组件中，所述第一模塑单元的外侧周缘在所述高度方向上与所述第二模塑单元的外侧周缘对齐。
在根据本申请的感光组件中，所述第一模塑单元的外侧周缘邻近于或者齐平于所述线路板的外周缘。
在根据本申请的感光组件中，所述感光组件还包括被设置于所述线路板的上表面且被所述第一模塑单元包覆的至少一电子元件。
在根据本申请的感光组件中，所述第一模塑单元的高度尺寸为0.35mm至0.5mm。
在根据本申请的感光组件中，所述第一模塑单元具有顶表面，所述顶表面的平整度RZ为5um。
在根据本申请的感光组件中，所述第二模塑单元包绕地形成于所述感光芯片的周围。
在根据本申请的感光组件中，所述第二模塑单元的底表面低于所述感光芯片的下表面。
在根据本申请的感光组件中，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
在根据本申请的感光组件中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘。
在根据本申请的感光组件中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电 结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘；
在根据本申请的感光组件中，所述绝缘介质的玻璃化温度小于所述第一电结合件和所述第二电结合件的熔点。
本申请还提供一种感光组件的制备方法，其包括：
提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件；
通过模塑工艺在所述线路板的上表面形成第一模塑单元以及在所述线路板的下表面形成第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元对所述线路板进行结构加强；
分别在所述第一电结合件和/或所述第二电结合件上铺设一层绝缘介质，其中，所述绝缘介质的玻璃化温度低于所述第一电结合件和所述第二电结合件的熔点温度；以及
通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，通过这样的方式，将所述感光芯片电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔。
本申请还提供了一种感光组件的制备方法，其包括：
提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件；
通过模塑工艺在所述线路板的上表面形成第一模塑单元以及在所述线路板的下表面形成第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元对所述线路板进行结构加强；
分别在所述第一电结合件和/或所述第二电结合件上铺设一层绝缘介质，其中，所述绝缘介质的玻璃化温度低于所述第一电结合件和所述第二电结合件的熔点温度；以及
通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，通过这样的方式，将所述感光芯片电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔。
根据本申请的另一方面，还提供了一种感光组件的电导通方法，其包括：
提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件；
分别在所述第一电结合件和/或所述第二电结合件上铺设一层绝缘介质，其中，所述绝缘介质的玻璃化温度低于所述第一电结合件和所述第二电结合件的熔点温度；以及
通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，通过这样的方式，将所述感光芯片电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔。
在根据本申请的感光组件的电导通方法中，通过植球工艺分别在所述线 路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件，包括：
在所述线路板的下表面上叠置钢网，所述钢网具有多个对应于所述多个第一电连接端的圆形开孔；
将锡膏铺设于所述钢网上并通过刮刀刮图所述锡膏以使得所述锡膏分别落于所述多个第一电连接端上；以及
通过回流焊对铺设有所述锡膏的所述线路板进行处理，其中，经回流焊处理后的所述锡膏形成所述多个第一电结合件。
在根据本申请的感光组件的电导通方法中，所述圆形开孔的直径配置使得至少所述锡膏中至少五颗锡球可同时被收容于所述圆形开孔内。
在根据本申请的感光组件的电导通方法中，所述圆形开孔的直径为70um，所述锡球的直径为5um-15um。
在根据本申请的感光组件的电导通方法中，通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，包括：
在加热到所述绝缘介质的玻璃化温度时，所述绝缘介质由固态被转化为玻璃态；以及
继续加热并压合所述线路板和所述感光芯片，其中，所述第一电结合件和所述第二电结合件破开玻璃态的所述绝缘介质并相互共晶结合，玻璃态的所述绝缘介质被挤压至共晶结合的所述第一电结合件和所述第二电结合件的周围。
在根据本申请的感光组件的电导通方法中，所述线路板还包括铺设于所述下表面的所述多个第一电连接端的外围的油墨层，其中，在所述多个第一电连接端之间不设有所述油墨层。
根据本申请的又一方面，还提供了一种线路板组件，其包括：
线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板的下表面具有邻近于所述通孔的电导通区域和位于所述电导通区域的外围的周围区域；其中，所述线路板包括形成于所述电导通区域的多个第一电连接端；以及
模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的周围区域的第二模塑单元。
在根据本申请的感光组件的线路板组件中，所述线路板还包括铺设于所述周围区域的油墨层，且所述多个第一电连接端之间不设有所述油墨层。
在根据本申请的感光组件的线路板组件中，所述多个第一电连接端均匀地且等间距的分布于所述电导通区域。
在根据本申请的感光组件的线路板组件中，所述线路板的厚度尺寸为0.2mm。
在根据本申请的感光组件的线路板组件中，所述第一电连接端具有预设直径尺寸使得在所述第一电连接端的上方能够叠置至少五颗直径为5um-15um的锡球。
在根据本申请的感光组件的线路板组件中，所述多个第一电连接端在所述线路板的下表面的铺设位置对应于所述线路板的上表面的位置被所述第一模塑单元所包覆。
在根据本申请的感光组件的线路板组件中，所述第一模塑单元与所述第二模塑单元在所述线路板组件所设定的高度方向上相互对齐。
在根据本申请的感光组件的线路板组件中，所述线路板具有内周缘和外周缘，所述线路板的内周缘形成所述通孔，其中，所述第一模塑单元具有内侧周缘和外侧周缘，所述第二模塑单元具有内侧边缘和外侧边缘，所述第一模塑单元的内周缘相对于所述第二模塑单元的内周缘更邻近于所述线路板的内周缘。
在根据本申请的感光组件的线路板组件中，所述线路板具有内周缘和外周缘，所述线路板的内周缘形成所述通孔，其中，所述第一模塑单元具有内侧周缘和外侧周缘，所述第二模塑单元具有内侧边缘和外侧边缘，所述第一模塑单元的内侧周缘在所述高度方向上与所述第二模塑单元的内侧周缘对齐，所述第一模塑单元的外侧周缘在所述高度方向上与所述第二模塑单元的外侧周缘对齐。
在根据本申请的感光组件的线路板组件中，所述线路板组件还包括被设置于所述线路板的上表面且被所述第一模塑单元包覆的至少一电子元器件。
在根据本申请的感光组件的线路板组件中，所述第一模塑单元的高度尺寸为0.35mm至0.5mm。
在根据本申请的感光组件的线路板组件中，所述第一模塑单元具有顶表面，所述顶表面的平整度RZ为5um。
在根据本申请的感光组件的线路板组件中，所述第二模塑单元包绕地形成于所述感光芯片的周围。
在根据本申请的感光组件的线路板组件中，所述第二模塑单元的底表面低于所述感光芯片的下表面。
在根据本申请的感光组件的线路板组件中，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
根据本申请的又一方面，还提供了一种线路板组件的制备方法，其包括：
提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；以及
通过模塑工艺在所述线路板的上表面形成第一模塑单元以及在所述线路板的下表面形成第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元对所述线路板进行结构加强。
根据本申请的又一方面，还提供了一种摄像模组，其包括：
感光组件和被保持于所述感光组件的感光路径上的光学镜头；
其中，所述感光组件，包括：
线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔；
感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片的上表面电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔；
模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元；
其中，所述光学镜头的最大外径尺寸与所述感光芯片的长边长度之间的比值为0.85至1.7。
在根据本申请的感光组件的摄像模组中，所述摄像模组进一步包括被安装于所述第一模塑单元的顶表面且用于驱动所述光学镜头的至少一部分相对于所述感光芯片进行移动的马达，其中，所述马达的最大外径尺寸与所述 感光芯片的长边长度之间的比值为0.97-1.82。
在根据本申请的感光组件的摄像模组中，所述第一模塑单元的顶表面的平整度RZ为5um。
在根据本申请的感光组件的摄像模组中，所述光学镜头包括至少一第一光学透镜的第一镜头单元和一第二光学透镜，所述第二光学透镜被安装于所述第一模塑单元，所述第二光学透镜与所述第一模塑单元相配合形成第二镜头单元。
在根据本申请的感光组件的摄像模组中，所述摄像模组的后焦尺寸为0.41mm-0.72mm，所述摄像模组的后焦尺寸为所述第二光学透镜与所述感光芯片之间的距离。
在根据本申请的感光组件的摄像模组中，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.2。
在根据本申请的感光组件的摄像模组中，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.1。
在根据本申请的感光组件的摄像模组中，所述第二光学透镜的最大外径尺寸小于等于所述感光芯片的长边尺寸的1.2倍。
在根据本申请的感光组件的摄像模组中，所述第二光学透镜具有对应于所述感光芯片的两条长边的第一切边和第二切边，以及，对应于所述感光芯片的两条短边的第三切边和第四切边。
在根据本申请的感光组件的摄像模组中，所述第二光学透镜具有突出地形成于其四个转角区域的四个透光区域。
在根据本申请的感光组件的摄像模组中，所述线路板的厚度尺寸为0.05mm-0.4mm，所述第一模塑单元的高度尺寸为0.2mm-0.5mm，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
在根据本申请的感光组件的摄像模组中，所述第二模塑单元的底表面低于所述感光芯片的下表面。
在根据本申请的感光组件的摄像模组中，所述感光组件还包括附着于所述感光芯片的上表面的滤光元件。
在根据本申请的感光组件的摄像模组中，所述感光组件还包括附着于所述第二光学透镜的滤光元件。
在根据本申请的感光组件的摄像模组中，所述线路板包括形成于所述下 表面的多个第一电连接端，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；
其中，所述感光组件还包括多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域。
在根据本申请的感光组件的摄像模组中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘，其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘。
本申请还提供了一种摄像模组，其包括：
感光组件；
被保持于所述感光组件的感光路径上的光学镜头；以及
用于驱动所述感光组件相对于所述光学镜头进行移动的芯片驱动组件；
其中，所述感光组件，包括：
线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔；
感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片的上表面电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔；及
模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元；
其中，所述芯片驱动组件，包括：驱动单元、引线框架、防抖支架和防 抖外壳，其中，所述感光组件被收容于所述防抖外壳内，所述防抖支架被固定于所述防抖外壳内且位于所述感光组件的外侧，所述引线框架延伸于所述感光组件和所述防抖支架之间且所述感光组件通过所述引线框架相对于所述防抖支架可移动，所述驱动单元适于驱动所述感光组件相对于所述防抖支架进行移动以进行光学防抖。
在根据本申请的感光组件的摄像模组中，所述引线框架包括被设置于所述防抖支架的固定板、被设置于所述线路板的移动板和连接所述移动板和所述固定板的弹性连接带。
在根据本申请的感光组件的摄像模组中，所述移动板被固定于且电连接于所述线路板的上表面。
在根据本申请的感光组件的摄像模组中，所述移动板被固定于且电连接于所述线路板的下表面。
在根据本申请的感光组件的摄像模组中，所述驱动单元包括驱动线圈和与所述驱动线圈对应的驱动磁石，其中，所述驱动线圈被设置于所述线路板的上表面且位于所述第一模塑单元的外侧。
在根据本申请的感光组件的摄像模组中，所述第一模塑单元具有外侧周缘和内侧周缘，所述第一模塑单元的外侧周缘邻近于所述驱动线圈，所述第一模塑单元的内侧周缘邻近于所述线路板的内周缘，所述线路板的内周缘形成所述通孔。
在根据本申请的感光组件的摄像模组中，所述感光芯片和所述线路板在所述线路板的下表面的结合处对应于所述线路板的上表面的位置被所述第一模塑单元所包覆。
在根据本申请的感光组件的摄像模组中，所述第二模塑单元具有外侧周缘和内侧周缘，所述第一模塑单元的内侧周缘相对于所述第二模塑单元的内侧周缘更邻近于所述线路板的内周缘。
在根据本申请的感光组件的摄像模组中，所述第一模塑单元沿所述摄像模组设定的高度方向在所述线路板的上表面的第一投影区域的面积小于所述第二模塑单元沿所述高度方向在所述线路板的下表面的第二投影区域的面积。
在根据本申请的感光组件的摄像模组中，所述线路板具有外周缘，所述第二模塑单元的外侧周缘相对于所述第一模塑单元的外侧周缘更邻近所述 线路板的外周缘。
在根据本申请的感光组件的摄像模组中，所述驱动单元包括四个所述驱动线圈，4个所述驱动线圈位于所述第一模塑单元的四个转角处。
在根据本申请的感光组件的摄像模组中，所述移动板包括移动板主体和自所述移动板主体的内侧边框的向内延伸的至少一导电突出部，所述至少一导电突出部电连接于所述线路板的上表面。
在根据本申请的感光组件的摄像模组中，所述至少一导电突出部包括四个所述导电突出部，四个所述导电突出部分别对应于所述第一模塑单元的外侧周缘的四条侧边的中部。
在根据本申请的感光组件的摄像模组中，所述感光组件还包括电连接于所述线路板的上表面的至少一电子元器件，所述至少一电子元器件的至少一部分被包覆于所述第一模塑单元内，所述第一模塑单元的高度尺寸为0.2mm-0.5mm，所述第二模塑单元环绕地形成于所述感光芯片的周围，所述第二模塑单元的底表面低于所述感光芯片的下表面，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
在根据本申请的感光组件的摄像模组中，所述线路板包括形成于所述下表面的多个第一电连接端，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；
其中，所述感光组件还包括多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域。
在根据本申请的感光组件的摄像模组中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘，其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合 的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘。
在根据本申请的感光组件的摄像模组中，所述感光组件进一步包括设置于所述第一模塑单元的第二光学透镜。
在根据本申请的感光组件的摄像模组中，所述摄像模组的后焦尺寸为0.41mm-0.72mm，所述摄像模组的后焦尺寸为所述第二光学透镜与所述感光芯片之间的距离，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.2。
通过对随后的描述和附图的理解，本申请进一步的目的和优势将得以充分体现。
本申请的这些和其它目的、特点和优势，通过下述的详细说明，附图和权利要求得以充分体现。
附图说明
通过结合附图对本申请实施例进行更详细的描述，本申请的上述以及其他目的、特征和优势将变得更加明显。附图用来提供对本申请实施例的进一步理解，并且构成说明书的一部分，与本申请实施例一起用于解释本申请，并不构成对本申请的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1A图示了现有的一种摄像模组的示意图。
图1B图示了现有的另一种摄像模组的示意图。
图1C图示了现有的线路板的减成法的过程示意图。
图1D图示了现有的线路板的半加成法/加成法的过程示意图。
图2图示了根据本申请实施例的摄像模组的示意图。
图3图示了根据本申请实施例的所述摄像模组的感光组件的示意图。
图4图示了根据本申请实施例的所述感光组件的线路板的示意图。
图5图示了根据本申请实施例的所述感光组件的一体电导通结构的局部示意图。
图6A至图6C图示了根据本申请实施例的所述感光组件的电导通过程的示意图。
图6D图示了根据本申请实施例的所述线路板的下表面的示意图。
图7A至图7C图示了根据本申请实施例的所述感光组件的线路板组件的制备过程的示意图。
图8A图示了根据本申请实施例的所述感光组件的一个变形实施的示意图。
图8B图示了根据本申请实施例的所述感光组件的另一个变形实施的示意图。
图9图示了根据本申请实施例的所述摄像模组的一个变形实施的示意图。
图10图示了图9所示意的所述摄像模组的感光组件的俯视示意图。
图11图示了根据本申请实施例的所述摄像模组的感光组件的又一个变形实施的俯视示意图。
图12图示了根据本申请实施例的所述摄像模组的又一变形实施的示意图。
图13图示了根据本申请实施例的所述摄像模组的又一个变形实施的示意图。
图14图示了根据本申请实施例的所述摄像模组的感光组件的局部示意图。
图15图示了根据本申请实施例的所述摄像模组的又一个变形实施的示意图。
具体实施方式
下面，将参考附图详细地描述根据本申请的示例实施例。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是本申请的全部实施例，应理解，本申请不受这里描述的示例实施例的限制。
申请概述
如前所述，为了满足越来越广泛的市场需求，高像素、大芯片、小尺寸、大光圈是现有摄像模组不可逆转的发展趋势。然而，要在同一摄像模组实现高像素、大芯片、小尺寸、大光圈四个方面的需求是有很大难度的。
在现有的摄像模组中，感光芯片贴装于线路板上、用于驱动光学镜头的 马达可以直接安装于线路板上或者安装于被贴装于线路板的镜座上。也就是说，在摄像模组中，线路板是摄像模组中其他部件的安装基板，因此，要想减少摄像模组的整体尺寸(包括X轴方向尺寸、Y轴方向尺寸和Z轴方向尺寸，其中，X轴方向尺寸和Y轴方向尺寸为摄像模组的截面尺寸，而Z轴方向尺寸为摄像模组的高度尺寸)，提供一种截面尺寸跟小且相对更为平整的线路板是关键，这样摄像模组就可以从底层减少摄像模组的器件在纵向上进行堆叠所需的空间，最终实现高像素、大芯片、小尺寸和大光圈的技术要求。
图1A和图1B图示了现有的常用的两种摄像模组的结构示意图，其中，图1A所示意的摄像模组为通过COB工艺制备的摄像模组而图1B所示意的摄像模组为通过FC工艺制备的摄像模组。具体地，COB工艺指的是Chip on Board工艺，即，将感光芯片1P通过黏着剂贴装于线路板2P的上表面，进而通过打金线的方式在感光芯片1P和线路板2P之间铺设电连接引线3P以实现两者之间的电连接，同时，还通过SMT工艺(Surface mounting technology，表面贴装工艺)在所述线路板的上表面贴装电子元器件4P(例如，电容、电感、电阻等)。FC工艺指的是Flip chip工艺(即，芯片倒装工艺)，即，通过焊接工艺将感光芯片1P电连接于线路板2P的下表面，同时，还通过SMT工艺(Surface mounting technology，表面贴装工艺)在线路板2P的上表面贴装电子元器件4P(例如，电容、电感、电阻等)。
无论是通过COB工艺还是通过FC工艺制备的摄像模组，在将镜座5P贴装于线路板2P的上表面时，需考虑镜座5P与电子元器件4P之间的避让问题，即，在Z轴方向上预留0.1mm-0.2mm的间隙(例如，如图1A中所示意的g)来防止镜座5P对电子元器件4P产生干涉。同时，考虑到镜座5P的贴附偏差、电子元器件4P的贴附偏差，胶水烘烤产生的尺寸变化，还需要在最外侧的电子元器件4P和镜座5P之间预留0.2mm-0.4mm左右的横向空间(例如，如图1A中所示意的w)，这导致线路板2P所需的截面尺寸的增加也进而导致摄像模组的高度尺寸和截面尺寸的增加。
并且，考虑到FC工艺的特殊性，其要求线路板具有相对较高的硬度和平整度，因此，现有的用于FC工艺的线路板为陶瓷基板，相较于PCB板或者FPCB板，陶瓷基板在硬度和平整度上具有优势，但考虑到瓷土的特征其内部电路不能设计得过于复杂否则将难以实现；其次，陶瓷基板相对于PCB板或者FPCB板具有相对较大的厚度尺寸，这对于摄像模组缩减其高度方向 上的尺寸是不利的。
现有的PCB板通常由减成法制备，其中，如图1C所示，减成法制备的线路板一般通过在基板上敷铜板，进而通过光化学成像法、网印图形转移或者电镀图形抗蚀法腐蚀掉非图形部分的铜箔或采用机械方式去除不需要部分而制成印制电路板的方式，由于该种方式需要浪费大量铜资源，工艺流程上往往比较复杂。并且，通过减成法制备的线路板的厚度尺寸较大(这里，通过减成法制备的线路板的厚度尺寸小于陶瓷基板的厚度尺寸)，且由于减成法的电路铺设密度较低，因此，在形成同等复杂程度的电路时，其所需的线路板的截面尺寸也较大。考虑到由减成法制备的线路板的技术问题，本申请发明人尝试使用加成法或者半加成法来制备本申请所需的线路板。
如图1D所示，半加成法工艺涉及以下几个步骤：
步骤一：基板覆铜，在线路板基板上镀上一厚度较薄的铜层。
步骤二：曝光显影，在已经镀覆有薄铜层的铜层表面涂覆光阻剂(D/F)用于覆盖所述铜层，再通过紫外曝光装置进行曝光，即把需要导通的位置处暴露出来。也就是，所述紫外曝光装置照射需要显露区域，所述被照射区域光阻剂变性而可溶于显影液，通过显影液清洗洗去所述需显露区域的光阻剂。
步骤三：通过电镀工艺，将所述显露区域的铜厚增加到需要的厚度，即所述显露区域为所述线路板的导通电路部分，通过电镀形成最后可使用的导通电路。
步骤四：闪蚀，去除光阻剂后，通过闪蚀方式去除原光阻剂下方多余的铜层形成所需的线路。
由于半加成法/加成法制备的方法一般通过在绝缘的基板上，利用丝印，电镀或粘贴的方法有选择性的形成导电图形，从而制备出线路板，因此，可见半加成法/加成法的方式是成形导电线路，而减成法的方式是在一整面的导电线路上腐蚀出导电线路。
相较于由减成法制备的线路板，由半加成法或者加成法制备的线路板具有高密度，小孔径，细线路和超薄型等几大特点。由半加成法或者加成法制备的线路板的层与层之间的电气连接主要通过金属化的通孔、盲孔和埋孔(金属化主要采用电镀铜来实现)来完成，而由减成法制得的线路板主要是通过通孔和导电柱来实现层与层之间的电气连接。也就是说，由半加成法或 者加成法制备的线路板可以通过通孔、盲孔和埋孔来完成任意层和区域的连接(即，由半加成法或者加成法制备的线路板具备任意互联的效果)，从而在满足同等电路复杂度要求的前提下能够缩小所述线路板在X轴方向和Y轴方向的尺寸，且堆叠的层数也可以变少，即，所述线路板在Z轴方向上的尺寸也得以减小。
也就是说，采用由加成法或者半加成法工艺制备的线路板能够在满足线路板电路要求的前提下，具有相对较小的截面尺寸和高度尺寸。量化来看，由加成法或者半加成法工艺制备的线路板一般具有下列参数：1、导电线路线宽/线距≤50um/50um；2、布线密度≥50cm/1cm2；3、导通孔(包含盲孔、埋孔)的孔径≤100um，孔环径≤100um；以及，4、导通孔的孔密度≥100万孔/平方米。
相应地，采用由加成法或者半加成法制备的线路板替代现有的由减成法制备的线路板有利于实现摄像模组的高像素、大芯片、小尺寸和大光圈。然而，由加成法或者半加成法的线路板在参与到摄像模组的组装时，也存在新的技术问题。
首先，由于由加成法或者半加成法制备的线路板具有相对较薄的厚度尺寸，即，由加成法或者半加成法制备的线路板具有相对较小的硬度和强度，也就是，在将感光芯片贴装于线路板时，线路板更易发生弯曲而导致感光芯片发生弯曲和变形。同时，尺寸较大的感光芯片本身带有易于变形的特性，在芯片的处理工艺上尤其需要注意，例如对芯片进行模塑封装的工艺中，芯片贴附的工艺中，芯片胶水组装后进行烘烤后的过程中，都可能会造成芯片形状变形，芯片弯曲的不良现象，从而影响最终摄像模组的成像质量。
其次，由于加成法或者半加成法工艺的特殊性，形成于线路板的表面的焊盘的尺寸相对较小，焊盘与焊盘之间的铺设密度较高(即，焊盘与焊盘之间的间隙较小)，因此，在施加诸如油墨层之类的绝缘层时，诸如油墨之类的绝缘介质无法施加到焊盘与焊盘之间，这会影响后续线路板与感光芯片之间的电导通结构的设计。应可以理解，在由减成法工艺制备的线路板与感光芯片的电导通过程中，无需考虑焊盘与焊盘之间的绝缘问题，而对于由加成法或半加成法制备的线路板与感光芯片的电导通过程中，除了要保证线路板与感光芯片之间的电连接还需要保证线路板与感光芯片的每一对电连接端之间的绝缘，因此，这会导致线路板与感光芯片之间的电连接结构变得复杂 且困难。
也就是说，在引入由加成法或半加成法制备的线路板后，通过适当的结构设计和工艺设计来充分利用由加成法或半加成法制备的线路板的优势，并解决其所引入的新的技术问题，以使得最终制备的摄像模组能够满足高像素、大芯片、小尺寸、大光圈的发展趋势和要求。
在介绍了本申请的基本原理之后，下面将参考附图来具体介绍本申请的各种非限制性实施例。
示意性摄像模组和感光组件
如图2所示，根据本申请实施例的摄像模组被阐明，其包括感光组件20以及被保持于所述感光组件20的感光路径上的光学镜头10。在本申请一些实施例中，所述摄像模组还包括用于调整所述光学镜头10与所述感光组件20之间的相对位置关系的驱动组件，以通过所述驱动组价来实现所述摄像模组的光学性能的调整，例如，在一些实施例中，所述摄像模组还包括用于驱动所述光学镜头10以改变所述光学镜头10与所述感光组件20之间的相对位置关系的镜头驱动组件30，再如，在一些实施例中，所述摄像模组还包括用于驱动所述感光组件20以改变所述光学镜头10与所述感光组件20之间的相对位置关系的芯片驱动组件40，对此，并不为本申请所局限。
相应地，在本申请实施例中，所述光学镜头10包括至少一光学透镜，用于采集来自被摄目标的成像光线并将该成像光线传播至所述感光组件20。所述感光组件20包括线路板21、电连接于所述线路板21的感光芯片22、以及，被保持于所述感光芯片22的感光路径上的滤光元件26以及电连接于所述线路板21的至少一电子元器件25。
为了满足摄像模组朝着高像素、大芯片、小尺寸和大光圈的发展趋势，特别地，在本申请实施例中，采用由加成法或者半加成法制备的线路板替代现有的由减成法制备的线路板。具体地，所述线路板21的半加成法工艺或加成法工艺至少包括如下几个步骤：步骤一：基板覆铜，即，在基板上镀上一厚度较薄的铜层；步骤二：曝光显影，即，在已经镀覆有薄铜层的铜层表面涂覆光阻剂来覆盖所述铜层，再通过紫外曝光装置进行曝光，通过这样的方式，把需要导通的位置处暴露出来。也就是，所述紫外曝光装置照射需要显露区域，所述被照射区域光阻剂变性而可溶于显影液，通过显影液清洗洗 去所述需显露区域的光阻剂；步骤三：通过电镀工艺，即，将所述显露区域的铜厚增加到需要的厚度，即所述显露区域为所述线路板21的导通电路部分，通过电镀形成最后可使用的导通电路；以及，步骤四：闪蚀，即，去除光阻剂后，通过闪蚀方式去除原光阻剂下方多余的铜层形成所需的线路。
应注意到，由于半加成法/加成法制备工艺一般通过在绝缘的基板上，利用丝印，电镀或粘贴的方法有选择性的形成导电图形，从而制备出所述线路板21，因此，可见半加成法/加成法的方式是成形导电线路。并且，相较于由减成法制备的线路板，由半加成法或者加成法制备的所述线路板21具有高密度，小孔径，细线路和超薄型等几大特点。更具体地，由半加成法或者加成法制备的所述线路板21的层与层之间的电气连接主要通过金属化的通孔、盲孔和埋孔(金属化主要采用电镀铜来实现)来完成，而由减成法制得的线路板主要是通过通孔和导电柱来实现层与层之间的电气连接。也就是说，由半加成法或者加成法制备的所述线路板21可以通过通孔、盲孔和埋孔来完成任意层和区域的连接(即，由半加成法或者加成法制备的线路板具备任意互联的效果)，从而在满足同等电路复杂度要求的前提下能够缩小所述线路板21在X轴方向和Y轴方向的尺寸且堆叠的层数也可以变少(即，所述线路板21在Z轴方向上的尺寸也得以减小)。
因此，采用由加成法或者半加成法工艺制备的所述线路板21能够在满足线路板电路要求的前提下，具有相对较小的截面尺寸(即，长宽尺寸)和高度尺寸。量化来看，由加成法或者半加成法工艺制备的所述线路板21一般具有下列参数：1、导电线路线宽/线距≤50um/50um；2、布线密度≥50cm/1cm2；3、导通孔(包含盲孔、埋孔)的孔径≤100um，孔环径≤100um；以及，4、导通孔的孔密度≥100万孔/平方米。相应地，采用由加成法或者半加成法制备的所述线路板21替代现有的由减成法制备的线路板有利于实现摄像模组的高像素、大芯片、小尺寸和大光圈。在本申请实施例中，由加成法或半加成法制得的所述线路板21的厚度尺寸为0.2mm。
更具体地，如图2至图4所示，在本申请实施例中，所述线路板21被实施为中心区域具有矩形开口的矩形薄板，也就是说，所述线路板21具有贯穿地设置于其中的通孔210，所述通孔210具有矩形状。应可以理解，在本申请其他示例中，所述通孔210可贯穿地形成于所述线路板21的其他位置，即，所述通孔210的设置位置并不严格限制于所述线路板21的中间区 域。相应地，所述线路板21具有一外周缘2102和一内周缘2101，其中，所述内周缘2101形成所述通孔210，也就是说，所述通孔210的边缘为所述线路板21的内周缘2101。所述线路板21还具有相对的上表面211和下表面212，其中，所述线路板21的上表面211朝向光学器件方向设置，所述线路板21的下表面212与所述线路板21的上表面211相对。
相应地，在本申请实施例中，所述感光芯片22具有一组相对的上表面221和下表面222，其中，所述上表面221具有感光区域2211和围绕所述感光区域2211的非感光区域2212。在一个具体的示例中，所述感光区域2211位于所述感光区域2211的上表面221的中心区域，所述非感光区域2212环绕所述感光区域2211设置并呈回字型结构。如图2至图4所示，在本申请实施例中，在所述感光芯片22被安装并电连接于所述线路板21后，所述感光芯片22的感光区域2211对应于所述通孔210，且优选地所述感光芯片22的感光区域2211通过所述通孔210被完全地暴露。也就是，优选地，在所述感光芯片22被贴装并电连接于所述线路板21时，所述线路板21的内边缘对应于所述感光芯片22的非感光区域2212，所述感光芯片22的感光区域2211完全不被所述线路板21所遮挡。应注意到，在本申请实施例中，所述感光芯片22以倒装的方式被安装于所述线路板21的下表面212，即，所述感光芯片22的上表面221叠置于所述线路板21的下表面212，或者说，所述感光芯片22的上表面221与所述线路板21的下表面212相对地设置。
进一步地，在本申请实施例中，所述线路板21包括形成于其下表面212的多个第一电连接端21210，例如金手指，其中，在本申请一个具体的示例中，所述多个第一电连接端21210靠近所述线路板21内周缘2101且并环绕所述线路板21的内周缘2101设置。相对应地，在本申请实施例中，所述感光芯片22包括形成于其非感光区域2212的多个第二电连接端22121，例如铝垫，其中，在本申请一个具体的示例中，所述感光芯片22的多个第二电连接端22121环绕所述感光区域2211设置。特别地，在本申请实施例中，所述感光芯片22和所述线路板21之间通过多个一体电导通结构23实现电连接，即，所述线路板21的多个第一电连接端21210和所述感光芯片22的多个第二电连接端22121通过所述多个一体电导通结构23实现电连接。
相应地，如图2至图5所示，在本申请实施例中，每一所述一体电导通结构23包括电连接于所述第一电连接端21210的第一电结合件231以及电连接于所述第二电连接端22121的第二电结合件232，所述第一电结合件231与所述第二电结合件232共晶结合，其中，每一所述一体电导通结构23还包括包覆于共晶结合的所述第一电结合件231和所述第二电结合件232的周围的绝缘介质233，以通过所述绝缘介质233使得每一对相互电连接的所述第一电连接端21210和所述第二电连接端22121相互绝缘。所述第一电结合件231和/或所述第二电结合件232可以是锡球、金球、铜柱等由金属材质构成的球体、柱体等结构，所述第一电结合件231和所述第一电连接端21210之间的结合以及所述第二电结合件232和所述第二电连接端22121之间的结合工艺可以是压力焊、回流焊、超声波焊接等工艺。
本领域普通技术人员应知晓，在现有的感光芯片的COB贴装工艺中，将感光芯片的下表面叠置于线路板的上表面并在感光芯片的电连接端与线路板的电连接端之间打金线实现两者之间的相互导通。应特别注意到，在传统的COB工艺中，感光芯片的电连接端与线路板的电连接端在X轴方向和Y轴方向存在一定距离，以适于设置金线进行连接。而在本申请实施例中，由于所述感光芯片22的上表面221相对所述线路板21的下表面212设置，并且所述感光芯片22通过焊接工艺电连接于所述线路板21，在这种技术方案中，所述感光芯片22的多个第二电连接端22121与所述线路板21的多个第一电连接端21210在X轴方向和Y轴方向上必须至少部分重合，通过这样的方式，取消了原先预留给金线的避让距离，使得整个所述感光组件20在X轴方向和Y轴方向上的尺寸可得以减小，即，所述感光组件20的横向尺寸(或者说，截面尺寸)可得以缩减。同时，采用所述感光芯片22倒装的方式，使得所述摄像模组的像面往下沉，这可以使得所述摄像模组的光学总长降低，即，使得所述摄像模组的Z轴方向的尺寸得以缩减(即，使得所述摄像模组的高度尺寸得以缩减)。
本领域普通技术人员应知晓，在通过减成法制备的线路板中，为了对位于线路板的表面的元器件进行保护和绝缘，会进一步地在线路板的表面(包括线路板的下表面、上表面和侧表面)设置绝缘层，通常是油墨层2123。也就是说，在通过减成法制备的线路板中，所述线路板21进一步包括设置于其下表面212的油墨层2123以通过所述油墨层2123使得多个第一电连 接端21210之间相互绝缘。然而，在根据本申请的线路板中，由于所述线路板21通过加成法或者半加成法制成，所述多个第一电连接端21210之间的间距过小，这使得油墨层2123无法填充入所述第一电连接端21210之间，也就是，在根据本申请的线路板中，所述多个第一电连接端21210之间不设有所述油墨层2123，这使得所述感光芯片22和所述线路板21之间的电连接结构的设计和布设变得复杂和困难。
更明确地，在本申请实施例中，如图6D所示，所述线路板21的下表面212具有电导通区域2121和位于所述电导通区域2121周围的周围区域2122，其中，所述线路板21包括形成于所述电导通区域2121的所述多个第一电连接端21210和铺设与所述线路板21内的电气导通线路。特别地，所述线路板21还包括设置于其下表面212的周围区域2122的油墨层2123，且所述第一电连接端21210之间不设有所述油墨层2123。
如图6A至图6C所示，在根据本申请的所述线路板21和所述感光芯片22的电导通工艺中，在所述线路板21的表面涂覆油墨以形成所述油墨层2123后，对所述线路板21进行上锡处理以在所述线路板21的多个第一电连接端21210上形成所述多个第一电结合件231。在本申请一个具体的示例中，上锡操作通过钢网印刷的方式来实现，即，上锡操作通过SMT工艺来完成。具体地，在该具体示例中，所述钢网设置具有多个直径为70um的圆形开孔，所述圆形开孔为下锡孔，与所述线路板21的多个第一电连接端21210一一对应，其中，在上锡工艺中，将锡膏设置于所述钢网上，所述线路板21被设置于所述钢网的下方且所述线路板21的多个第一电连接端21210与所述下锡孔位置对准，进而通过刮刀挂涂锡膏，锡膏受力穿过所述下锡孔落在所述线路板21的多个第一电连接端21210上以完成上锡操作。
特别地，在该具体示例中，所述钢网的圆形开孔的直径设置为70um，该孔径的设置匹配于所述锡膏中锡球230的最小粒径。更明确地，所述圆孔开孔的尺寸设置使得允许至少五个锡球230能够在所述第一电连接端21210的上方进行堆叠。量化来看，在该具体示例中，所述锡膏中锡球230的颗粒直径为5-15um(所述直径为选型的直径，当然也可以是其他直径)，从而满足生产过程中的至少五球原理，即，同一上锡位置处至少可以容纳五个锡膏颗粒下落。也就是，通过所述圆形开孔和所述锡膏中锡球230的粒径之间的匹配，使得每一所述第一电连接端21210沿XY轴方向或者Z轴方向至少需 要有五颗锡球230颗粒堆叠从而使得其后熔融成一个整体的锡球230能够满足生产需求，故所述钢网开孔设置为70um能够基本满足需求。
应可以理解，在具体工艺中，所述圆形开孔的直径与所述第一电连接端21210的截面尺寸相对应，因此，在本申请实施例中，所述第一电连接端21210具有预设截面尺寸以允许至少五颗所述锡球230同时堆叠于所述第一电连接端21210上。量化来看，所述第一电连接端21210的直径为70um，所述锡球230的直径为5um-15um。
值得一提的是，相比于传统钢网开孔的矩形设计，在本申请的技术方案中，将所述钢网的开孔配置为圆形开孔。应注意到，所述圆形开孔在所述线路板21的上锡过程中，不管刮刀与其的相对角度是如何的，其受力情况在各个方向上都相同，从而不会影响锡膏沿着所述圆形开孔的下落，可以极大的避免连锡。并且，所述圆形开孔还需要进行去毛刺和抛光处理，以去除所述圆形开孔周围的毛刺，避免毛刺影响刮刀和锡膏沿着所述圆形开孔下落。在一些实施例中，还可以对所述圆形开孔的内壁进行抛光处理，避免锡膏堵塞或者黏连在所述内壁导致下锡量不足。
还值得一提的是，在本申请一些实施例中，还可以对上锡进行改善。具体地，采用超密间距来进行锡膏印刷，即，控制所述钢网与所述线路板21之间的间隙极小，以使得在印刷过程中，锡膏穿过所述钢网后能够直接压落于所述线路板21的所述第一电连接端21210上，也就是说，在锡膏下落过程中无多余的行程而导致锡膏往印刷孔后续的其他方向移动，避免连锡的产生。
在本申请实施例中，在对所述线路板21的多个第一电连接端21210上锡完成后，使用回流焊工艺对上锡完成后的所述线路板21进行处理，这样将所述第一电连接端21210上的锡膏通过高温融化后再次固化以形成电连接于所述多个第一电连接端21210的所述多个第一电结合件231。应可以理解，可通过相同的植球工艺在每个所述第二电连接端22121上形成一个所述第二电结合件232。当然，在本申请其他示例中，还可以通过其他工艺在所述感光芯片22的多个第二电连接端22121上形成所述多个第二电结合件232，例如，通过通道掩膜电镀工艺、上锡和回流焊处理等，对此，并不为本申请所局限。
在通过植球工艺或者其他工艺在所述线路板21的多个第一电连接端 21210上形成所述多个第一电结合件231以及在所述感光芯片22的多个第二电连接端22121上形成所述多个第二电结合件232后，进一步通过热压键合工艺实现所述线路板21和所述感光芯片22之间的物理固定及电路导通。具体地，在热压工艺中，将热压头设置于所述感光芯片22的下表面222，然后将所述感光芯片22的布置有所述多个第二电连接端22121的一面(即，所述感光芯片22的上表面221)朝向所述线路板21的布置有所述多个第一电连接端21210的一面(即，所述线路板21的下表面212)，继而所述感光芯片22和所述线路板21在一定的压力和预设温度变化的作用下实现两者之间的物理固定和电气导通。应注意的是，在本申请实施例中，可以在形成于线路板的第一电连接端21210上的第一电结合件231上或者在形成于所述感光芯片22的第二电连接端22121上的第二电结合件232上铺设涂覆特定的绝缘介质233，用于防止所述第一电结合件231和所述第二电结合件232间形成的导通结构之间相互之间发生短路，其中，所述绝缘介质233可以是under fill保护胶，或者，NCP助焊剂。
在本申请一个具体的示例中，可以在所述多个第一电结合件231的表面施加所述绝缘介质233，例如，在所述多个第一电结合件231的表面上涂覆NCP助焊剂，在初始涂覆时，所述NCP助焊剂包覆所述多个第一电结合件231，由于所述NCP助焊剂的玻璃化温度点为180℃，而所述第一电结合件231和所述第二电结合件232的熔点在250℃左右，这样在热压键合升温过程中，随着温度的逐步升高并首选达到180℃，此时，所述NCP助焊剂开始软化，而所述第一电结合件231和所述第二电结合件232还未软化(即，所述第一电结合件231和所述第二电结合件232的硬度大于所述NCP助焊剂)，从而在下压过程中，所述第一电结合件231和所述第二电结合件232挤压所述NCP阻焊剂，使得所述助焊剂向所述第一电结合件231和所述第二电结合件232的外侧挤压，所述第一电结合件231和所述第二电结合件232破开所述NCP助焊剂并相互接触，同时所述NCP阻焊剂被挤压至所述第一结合件和所述第二结合件的间隙及周围以防止每一对相互电连接的所述第一电结合件231和所述第二电结合件232之间相互短路。
值得一提的是，所述绝缘介质233的玻璃态表示材料由固态转变为玻璃态，玻璃态不是物质的一个状态，是它的结构，固态物质分为晶体和非晶体，构成晶体的原子(或离子或分子)具有一定的空间结构，晶体具有一定的晶 体形状和固定熔点，而玻璃态就是一种非晶体，非晶体是固体中除晶体以外的固体，它没有固定的形状和固定熔点，具有各向同性，其会随着温度的升高逐渐变软，最后才熔化。所述NCP助焊剂可实现助焊功能，同时提升所述线路板21和所述感光芯片22之间的结合力，同时还可以防止短路。
在热压过程中，在所述绝缘介质233玻璃态后，所述第一电结合件231和所述第二电结合件232相互接触并且随着温度进一步升高至300℃一定时间使得所述线路板21的第一电结合件231和所述感光芯片22的第二电结合件232相互键合后降温。应可以理解，在本申请实施例中，采用热压键合工艺实现所述线路板21和所述感光芯片22之间的直接导通，相较于由COB工艺组装形成的感光芯片和线路板的组件，其能够有效减小感光组件20在截面方向上的尺寸。
值得一提的是，在本申请实施例中，所述第一电结合件231和所述第二电结合件232的制成材料包括但不限于金、锡、镍、钯等或者其中两种或者多种的合金，如图5所示。
应注意到，在本申请实施例中，每一所述一体电导通结构23还包括包覆于共晶结合的所述第一电结合件231和所述第二电结合件232的周围的绝缘介质233，以通过所述绝缘介质233使得每一对相互电连接的所述第一电连接端21210和所述第二电连接端22121相互绝缘。如前所述，在根据本申请实施例的所述线路板21中，形成于所述线路板21的下表面212的多个第一电连接端21210之间没有铺设油墨层2123，导致所述多个第一电连接端21210之间不能相互绝缘。相应地，在本申请的技术方案中，通过在所述第一电结合件231和/或所述第二电结合件232的表面铺设所述绝缘介质233(例如，NCP助焊剂)可以在热压键合工艺后在所述多个第一电连接端21210之间重新填充绝缘介质233，以确保所述线路板21和所述感光芯片22的电连接的准确性和稳定性。
其次，如果没有铺设所述绝缘介质233，所述线路板21和所述感光芯片22之间的物理结合强度仅依赖于所述多个第一电结合件231和所述多个第二电结合件232之间的共晶结合强度，而当所述绝缘介质233被实施为NCP助焊剂或under fill保护胶时，所述绝缘介质233的黏性能够使得所述线路板21的下表面212粘接于所述感光芯片22的上表面221，即，所述绝缘介质233还能够增强所述感光芯片22和所述线路板21之间的物理 结合强度。
也就是说，在本申请实施例中，所述绝缘介质233的铺设一方面考虑到由加成法或半加成法制备的线路板的电路铺设和结构的特殊性，起到绝缘隔离的作用；另一方面，所述绝缘介质233优选地由具有黏性的材料制成以加强所述线路板21和所述感光芯片22之间的物理结合强度。因此，所述绝缘介质233可以发挥电气层面的功效和物理层面的功效。
值得一提的是，在本申请其他实施例中，所述绝缘介质233还可以仅铺设于所述第二电结合件232的表面，或者，同时铺设于所述第一电结合件231和所述第二电结合件232的表面，对此，并不为本申请所局限。
还值得一提的是，虽然在本申请实施例中，以所述绝缘介质233的玻璃化温度为180°，所述第一电结合件231和所述第二电结合件232的熔点温度为250°为示例，但应可以理解，在本申请其他实施例中，所述第一电结合件231和所述第二电结合件232的熔点温度，以及，所述绝缘介质233的玻璃化温度的具体取值并不为本申请所局限，其只需满足：1、所述第一电结合件231和所述第二电结合件232的熔点温度大于所述绝缘介质233的玻璃化温度；2、所述第一电结合件231和所述第二电结合件232的熔点温度与所述绝缘介质233的玻璃化温度之差在预设范围内。针对于所述第一电结合件231和所述第二电结合件232的熔点温度与所述绝缘介质233的玻璃化温度之差在预设范围内，应可以理解，当熔点温度和玻璃化温度之差过大时，所述绝缘介质233的玻璃化与所述第一电结合件231和所述第二电结合件232之间的共晶结合的发生时间之间存在较大间隔，浪费了能量且不利于提高生产效率；而当两者的温度之差相差较小时，所述绝缘介质233的玻璃化与所述第一电结合件231和所述第二电结合件232之间的共晶结合的发生时间相近，这会导致工艺控制难度的增加。
也值得一提的是，由于所述线路板21的第一电结合件231和所述感光芯片22的第二电结合件232都经过植球工艺形成，而植球材料(锡球230、金球等)的直径大小之间存在一定的差异，因此，如果通过单层植球来形成所述第一电结合件231或所述第二电结合件232，由于单层的植球高度会存在一定的差异，导致在热压键合时，相互之间的植球对应高度也会存在差异。进一步地，当所述线路板21和所述感光芯片22之间的对应位置的植球高度差异较大时，容易出现虚焊或者未焊接的情况。为防止此类现象产生，在 本申请一些实施例中，可将单层植球工艺调整为多层植球工艺，例如，将植球调整为双层结构，以通过双层植球弥补这种高度差影响。并且，可以通过双层植球的方式，利用球与球之间相互之间的直径差异之间的互补来提高所述线路板21和所述感光芯片22帖附的平整度。当然，所述植球层数也可以是其他层数。
进一步地，在根据本申请实施例中，所述线路板21由加成法或半加成法制备而成，因此，所述线路板21具有相对较薄的厚度尺寸。另一方面，随着所述感光芯片22的尺寸增大，这导致将所述感光芯片22通过上述工艺贴装并电连接于所述线路板21的下表面212时，所述线路板21更易发生变形弯曲而导致所述感光芯片22发生弯曲，进而导致所述摄像模组产生场曲等不良成像现象。
为了对所述线路板21的结构进行增强以改善所述感光芯片22的场曲问题，在本申请实施例中，在执行所述感光芯片22和所述线路板21之间的电导通工艺之前，进一步对所述线路板21进行模塑处理以通过一体结合于所述线路板21的表面的模塑材料来对所述线路板21的结构进行加强和在一定程度上对所述线路板21的平整度进行优化。
如图2至图5所示，在本申请实施例中，所述感光组件20进一步包括通过模塑工艺一体成型于所述线路板21的表面的模塑体24。相应地，在本申请一个具体的示例中，所述模塑体24包括通过模塑工艺一体结合于所述线路板21的上表面211的第一模塑单元241和通过模塑工艺一体结合于所述线路板21的下表面212的第二模塑单元242。应注意到，在本申请实施例中，所述感光组件20还包括电连接于所述线路板21的表面的至少一电子元器件25(包括但不限于电阻、电容、电感等)，其中，所述至少一电子元器件25的至少一部分被所述第一模塑单元241或所述第二模塑单元242所包覆。例如，在本申请一些实施例中，所述至少一电子元器件25被设置于所述线路板21的上表面211，而所述至少一电子元器件25被同样形成于所述线路板21的上表面211的所述第一模塑单元241所包覆。
优选地，在本申请实施例中，如图7A至图7C所示，对所述线路板21的模塑工艺在对所述线路板21的植球工艺后执行，即，在通过植球工艺在所述线路板21的多个第一电连接端21210上形成所述多个第一电结合件231后，对所述线路板21进行模塑工艺。更优选地，在本申请实施例中,采 样上下同时模塑的方式来对所述线路板21进行模塑，也就是，在模塑时，所述线路板21被模塑夹具夹持并固定，所述线路板21充当所述模塑夹具的一个组件。本领域普通技术人员应知晓，一般模塑过程是单侧模塑(也就是，在线路板的一面上进行模塑)，需要在所述线路板21的上方设置模塑盖体以及在所述线路板21的下方设置模塑载体，其中，所述模塑载体承载并固定所述线路板21，所述模塑盖体向下压合并与所述模塑载体紧密压合以形成成型腔体，所述线路板21位于所述成型腔体的底部，模塑材料灌入所述成型腔体，固化脱模后在所述线路板21的表面上形成模塑结构。相应地，在本申请实施例中，所述线路板21直接被位于其上下两面的压合模具夹持，无需额外的承载模具去承载所述线路板21。
进一步地，在本申请的一些实施例中，如图7A至图7C所示，可将上下压合模具与所述线路板21的两个接触面的轮廓设置为基本相同，这样上下压合模具对于所述线路板21所施加的压力基本在垂直于所述线路板21的方向上是重合的，通过这样的方式，防止上压合模具与下压合模具出现明显错位情况，而导致线路板向上或者向下压弯。应可以理解，在这些实施例中，形成于所述线路板21的上表面211的第一模塑单元241和形成于所述线路板21的下表面212的第二模塑单元242具有相对一致的形状和尺寸。
当然，在本申请其他一些实施例中，所述第一模塑单元241与所述第二模塑单元242的大小和形状也可以具有误差，应可以理解，当所述第一模塑单元241和所述第二模塑单元242具有大小差异时，优选在模塑时，将具有大面积的模塑单元设置于在所述线路板21的下方(此时，所述线路板21可根据实际需求进行翻转)，这样以大模塑层的大压合模具为底部支撑，小压合模具向下压合，大模塑模具能够完整承载主来着小压合模具的压力。例如，当所述第一模塑单元241与所述第二模塑单元242的形状相一致且所述第一模塑单元241的尺寸大于所述第二模塑单元242的尺寸时，可在模塑时将所述线路板21倒置以使得相对较大的所述第一模塑单元241形成于所述线路板21的下方。
值得一提的是，形成于所述线路板21的上表面211和下表面212的所述第一模塑单元241和所述第二模塑单元242可以在一定程度上调整所述线路板21的平整度，使得完成模塑后的所述线路板21相对于未模塑的线路板具有相对更高的平整度。进而，在基于具有相对更高平整度的所述线路 板21的基础上，对所述感光芯片22和所述线路板21进行热压键合工艺，可提高所述感光芯片22与所述线路板21之间的热压键合质量，尤其是平整度方面。
也就是说，在本申请实施例中，如图7A至图7C所示，所述感光组件20的一种制备过程为：首先，提供一线路板21和一感光芯片22，其中，所述线路板21具有相对的上表面211和下表面212，以及，贯穿地形成于所述上表面211和所述下表面212之间的通孔210，所述线路板21包括形成于所述下表面212的多个第一电连接端21210，其中，所述感光芯片22具有相对的上表面221和下表面222，所述上表面221具有感光区域2211和位于所述感光区域2211周围的非感光区域2212，所述感光芯片22包括形成于所述感光芯片22的上表面221的非感光区域2212的多个第二电连接端22121。接着，通过植球工艺分别在所述线路板21的多个第一电连接端21210上形成多个第一电结合件231以及在所述感光芯片22的多个第二电连接端22121上形成多个第二电结合件232。然后，通过模塑工艺在所述线路板21的上表面211形成第一模塑单元241以及在所述线路板21的下表面212形成第二模塑单元242，以通过所述第一模塑单元241和所述第二模塑单元242对所述线路板21进行结构加强。接着，然后，分别在所述第一电结合件231和/或所述第二电结合件232上铺设一层绝缘介质233，其中，所述绝缘介质233的玻璃化温度低于所述第一电结合件231和所述第二电结合件232的熔点温度；最终，通过热压工艺实现所述多个第一电结合件231和所述多个第二电结合件232之间的共晶结合且所述绝缘介质233分别包覆于共晶结合的所述第一电结合件231和所述第二电结合件232的周围，通过这样的方式，将所述感光芯片22电连接于所述线路板21的下表面212，且所述感光芯片22的感光区域2211对应于所述通孔210。
进一步地，如图2所示，在本申请一些实施例中，所述感光芯片22与所述线路板21在所述线路板21的下表面212的结合处对应于所述线路板21的上表面211的位置被所述第一模塑单元241所包覆。应可以理解，在本申请实施例中，所述感光芯片22与所述线路板21在所述线路板21的下表面212的结合处为所述第一电结合件231与所述第二电结合件232的结合处或者说所述第一电连接端21210和所述第二电连接端22121所处的位置。相应地，在本申请实施例中，所述感光芯片22通过热压键合工艺电连 接于所述线路板21的下表面212，因此，所述线路板21的上表面211为热压键合工艺中的承靠面，因此，当所述第一模塑单元241在所述线路板21的上表面211的结合区域覆盖所述感光芯片22与所述线路板21在所述线路板21的下表面212的结合处对应于所述线路板21的上表面211的位置时，所述第一模塑单元241能够在热压键合工艺中对所述线路板21进行加强以防止所述线路板21在热压键合时向上弯曲。
在本申请实施例中，所述线路板21具有内周缘2101和外周缘2102，所述线路板21的内周缘2101形成所述通孔210，所述感光芯片22具有外周缘2102，其中，所述第一模塑单元241具有内侧周缘2411和外侧周缘2412。在本申请一些实施例中，所述第一模塑单元241的内侧周缘2411位于所述感光芯片22与所述线路板21在所述线路板21的下表面212的结合处对应于所述线路板21的上表面211的位置和所述线路板21的内周缘2101之间，这样所述感光芯片22与所述线路板21在所述线路板21的下表面212的结合处对应于所述线路板21的上表面211的位置被所述第一模塑单元241所包覆。更明确地，在本申请的一些实施例中，所述第一模塑单元241的内侧周缘2411与所述线路板21的内周缘2101对齐，所述第二模塑单元242具有内侧边缘2421和外侧边缘2422，所述第一模塑单元241的内侧周缘2411相对于所述第二模塑单元242的内周缘2421更邻近于所述线路板21的内周缘2101。进一步地，在本申请的一些实施例中，所述第一模塑单元241的外侧周缘2412邻近于或者齐平于所述线路板21的外周缘2102，所述第二模塑单元242的外侧周缘2422邻近于或者齐平于所述线路板21的外周缘2102，优选地，所述第一模塑单元241的外侧周缘2412在所述高度方向上与所述第二模塑单元242的外侧周缘2422对齐。
应可以理解，在本申请其他实施例中，所述第一模塑单元241和所述第二模塑单元242在所述线路板21的上表面211和下表面212的结合位置，以及，所述第一模塑单元241和所述第二模塑单元242自身的几何参数配置，并不为本申请所局限。例如，在本申请的另外一些实施例中，所述第一模塑单元241沿所述感光组件20设定的高度方向上在所述线路板21的上表面211的第一投影区域与所述第二模塑单元242沿所述高度方向在所述线路板21的下表面212的第二投影区域共中心轴设置，也就是说，所述第 一模塑单元241与所述线路板21的上表面211的结合区域与所述第二模塑单元242与所述线路板21的下表面212的结合区域同时以所述线路板21的中心轴为轴，通过这样的方式，所述第一模塑单元241对于所述线路板21的上表面211所形成的作用力的分布与所述第二模塑单元242对于所述线路板21的下表面212所形成的作用力的分布相近或者相一致，以通过所述第一模塑单元241和所述第二模塑单元242来提高所述线路板21的平整度。
进一步地，在本申请一些实施例中，如图8A所示，所述第一投影区域和所述第二投影区域具有相同的形状和尺寸，也就是说，所述第一模塑单元241与所述线路板21的上表面211的结合区域与所述第二模塑单元242与所述线路板21的下表面212的结合区域在所述线路板21的上下两侧完全对称，通过这样的方式，使得所述第一模塑单元241对于所述线路板21的上表面211所形成的作用力的分布与所述第二模塑单元242对于所述线路板21的下表面212所形成的作用力的分布相一致。更具体地，在本申请一些实施例中，如图2所示，所述第一投影区域的内周缘对齐于所述第二投影区域的内周缘，所述第一投影区域的外周缘对齐于所述第二投影区域的外周缘。
当然，在本申请其他一些示例中，所述第一投影区域和所述第二投影区域具有相同的形状和不同的尺寸。例如，在一些实施例中，所述第一投影区域的外周缘与所述第二投影区域的外周缘对齐，且所述第一投影区域的内周缘相较于所述第二投影区域的内周缘更邻近于所述线路板21的内周缘2101。再如，如图8B所示，在一些实施例中，所述第一投影区域的内周缘与所述第二投影区域的内周缘对齐，且所述第二投影区域的外周缘相较于所述第一投影区域的外周缘更邻近于所述线路板21的外周缘2102。对此，并不为本申请所局限。
如前所述，在本申请实施例中，如图2至图5所示，所述感光组件20还包括电连接于所述线路板21的表面的至少一电子元器件25(包括但不限于电阻、电容、电感等)，其中，所述至少一电子元器件25的至少一部分被所述第一模塑单元241或所述第二模塑单元242所包覆。更具体地，在本申请一些实施例中，所述至少一电子元器件25形成于所述线路板21的上表面211。相应地，所述第一模塑单元241的底面(所述第一模塑单元241 的底面为所述第一模塑单元241与所述线路板21的上表面211结合的表面)具有一回字型结构，其中，所述第一模塑单元241的底面具有所述内侧周缘2411和所述外侧周缘2412，其中，所述第一模塑单元241的内侧周缘2411位于所述电子元器件25与所述线路板21的内周缘2101之间；所述第一模塑单元241的外侧周缘2412位于所述电子元器件25与所述线路板21的外周缘2102之间，优选地，与所述线路板21的外周缘2102平齐。
特别地，在本申请一些实施例中，所述第一模塑单元241的顶表面到所述线路板21的上表面211之间的距离(也就是说，所述第一模塑单元241的高度尺寸)大于所述电子元器件25的高度，使得所述第一模塑单元241成型后完全包覆所述电子元器件25，对电子元件起到保护作用，防止外力造成电子元件的脱落、受损等。所述第一模塑单元241的高度为0.35mm至0.5mm，优选为大于等于0.4mm。
在本申请一些实施例中，所述第一模塑单元241可进一步代替现有的COB摄像模组中的镜座，为所述镜头驱动组件30或所述光学镜头10提供安装载体。相应地，当所述镜头驱动组件30或所述光学镜头10被安装于所述第一模塑单元241时，相较于COB摄像模组，原先预留的镜座与电子元器件25之间的横向避让距离和纵向避让距离被取消，因此，所述摄像模组及其感光组件20的截面尺寸可进一步地减小，以及，所述摄像模组及其感光组件20的高度尺寸也可进一步地减小。由于模塑工艺自身的工艺特点，模塑结构的表面具有非常高的平整度，量化来看，在本申请实施例中，所述第一模塑单元241的顶面可具有RZ＝5um的平整度，而所述线路板21的平整度RZ一般为20um，因此，将所述镜头驱动组件30或所述光学镜头10安装于所述第一模塑单元241可进一步补偿了因所述线路板21自身的不平整度带来的贴附精度误差。
在本申请实施例中，所述第二模塑单元242一体结合于所述线路板21的下表面212。为了便于说明，将所述第二模塑单元242与所述线路板21的下表面212接触的面被定义为所述第二模塑单元242的顶表面，所述第二模塑单元242远离所述线路板21的下表面212且与之平行的面被定义为所述第二模塑单元242的底表面。应注意到，在本申请实施例中，所述第二模塑单元242的顶表面具有一回字型结构，其具有所述内侧周缘2411和外侧周缘2412。从位置角度来看，在本申请实施例中，所述第二模塑单元242 的内侧周缘2411位于所述感光芯片22的外周缘2102与所述线路板21的外周缘2102之间，优选地，所述第二模塑单元242的内侧周缘2411在投影方向上与所述第一模塑单元241的内侧周缘2411平齐，所述第二模塑单元242的外侧周缘2412在投影方向上与所述第一模塑单元241的外侧周缘2412平齐，以使得所述第二模塑单元242能够最大程度地平衡第一模塑单元241对所述线路板21作用产生的应力造成的线路板翘曲，可以理解的是，所述第一模塑单元241与所述第二模塑单元242在所述线路板21上的投影区域也可以不重合，并具有不同的面积大小。
值得一提的是，由于模塑工艺自身的工艺特点，所述第二模塑单元242的底表面具有相当高的平整度，因此，所述第二模塑单元242更进一步地补偿了所述线路板21自身的不平整度带来的组装精度误差，并将所述线路板21制造时难以避免的不平整与翘曲对成像质量带来的这一不可控的影响因素变为可控的，再在后续组装的过程中通过主动校准与算法来补偿该可控的影响因素对成像造成的影响，如场曲。在本申请实施例中，模塑工艺完成以后，所述第一模塑单元241与所述第二模塑单元242共同对所述线路板21产生作用力，提升线路板整体的平整度，从而在后续热压键合所述感光芯片22和所述感光芯片22、贴附所述光学镜头10或所述镜头驱动组件30等其他工艺过程后，能有效将累计的误差值降到最低。
值得一提的是，所述第二模塑单元242的高度略大于或等于所述感光芯片22的下表面222到所述线路板21的下表面212之间的距离，即，所述第二模塑单元242的底表面略低于所述感光芯片22的下表面222，这样所述第二模塑单元242围绕于所述感光芯片22的四周对所述感光芯片22起到保护的作用。量化来看，在本申请实施例中，所述第二模塑单元242的高度尺寸优选为0.2-0.3mm。在本申请一些示例中，所述感光组件20还包括设置于所述感光芯片22与所述第二模塑单元242之间的胶层，以在所述胶层固化后形成用于保护感光芯片的密封保护结构，用于隔绝灰尘，防止污染感光芯片。
值得一提的是，在制造过程中，优选地，先对所述线路板21进行模塑工艺以在所述线路板21的表面形成所述模塑体24，而后在通过热压键合工艺将所述感光芯片22和所述线路板21结合在一起，其原因为：若先通过热压键合工艺将所述感光芯片22与线路板结合在一起后再进行模塑工艺， 模塑压头压在所述线路板21的表面的抵触位置与所述感光芯片22和所述线路板21之间的电连接结构非常接近，模塑压头对所述线路板21造成的压力可能会破坏所述感光芯片22与所述线路板21之间的电连接结构；其次，模塑流体灌入模具时会对所述线路板21造成较大的冲击力，也可能破坏所述感光芯片22与所述线路板21之间的电连接结构。
应可以理解，大尺寸的感光芯片本身带有易于变形的特性，因此，在对感光芯片的处理工艺上尤其需要注意，例如，对感光芯片进行模塑封装的工艺中，在感光芯片的贴附于线路板的的工艺中，感光芯片贴装后胶水进行烘烤的过程中，都可能会造成感光芯片形状变形，感光芯片弯曲的不良现象，从而影响最终摄像模组的成像质量。相应地，在本申请的技术方案中，所述感光芯片22通过倒装工艺被贴装于所述线路板21的下表面212，由于采用这种无金线的所述一体电导通结构23，由于所述第一电结合件231和所述第二电结合件232的制成材料一般为铜或者锡等金属材料，其热膨胀系数与所述感光芯片22的相接近，因此，在加热的时候由于CTE的相对一致性，会减少产生因为热膨胀后各层之间的热变形产生的应力，在保护所述感光芯片22翘曲变形的效果上会优于COB工艺的感光芯片。另外由于在所述线路板21的上表面211和下表面212设置所述第一模塑单元241和所述第二模塑单元242，其中，所述第一模塑单元241和所述第二模塑单元242通过各自成型过程中对所述线路板21试加的不同大小的应力，不同宽度的应力，这些不同程度的应力通过适当的设计和工艺调整，能够改善上下模塑后的所述线路板21的平整度，具有类似与电熨斗的夹平的效果。
进一步地，在本申请一些实施例中，所述感光组件20还包括设置于所述感光芯片22的下表面212的散热层，其中，所述散热层可以是一被动散热件271，如石墨烯涂层，可在短时间内将热量沿着所述感光芯片22的截面方向均匀化。当然，在本申请的其他示例中，所述散热层还可以铺设于其他位置，例如，可以同时涂附在所述感光芯片22的下表面222与所述第二模塑单元242的下表面，对此，并不为本申请所局限。
为了加强所述感光芯片22的散热，在本申请的一些实施例中，如图13所示，所述感光组件20还可包括一散热件，所述散热件可以是一主动散热件272，用于将所述感光芯片22产生的热量沿着所述感光组件20所设定的Z轴方向进行传导。优选地，在本申请一些实施例中，所述散热件与所述 散热层连接在一起，用于将所述感光芯片22在截面方向的传递热量从Z轴方向传导出所述摄像模组。优选地，所述散热件的厚度不大于所述第二模塑单元242的高度，也就是说，所述散热件的底表面低于所述第二模塑单元242的底表面，其中，所述第二模塑单元242的外侧边缘到所述线路板21的外周缘2102之间留有一避让空间，所述散热件被设置于所述避让空间中。
如图9所示，在本申请一些实施例中，所述感光组件20还包括被安装于所述第一模塑单元241的光学元件，其中，所述光学元件可以是光学透镜(为了便于说明定义为第二光学透镜121)或者滤光元件26。相应地，当所述光学元件被实施为所述第二光学透镜121时，所述第二光学透镜121与所述第一模塑单元241相配合形成所述光学镜头10的第二镜头单元12。也就是说，在本申请一些实施例中，所述光学镜头10为分体式镜头，其包括至少两个镜头单元，例如，第一镜头单元11和第二镜头单元12，其中，所述第一模塑单元241具有用于安装所述第二光学透镜121的安装腔2410，所述第一模塑单元241和所述第二光学透镜121形成所述第二镜头单元12。
应可以理解，当所述光学元件被安装于所述第一模塑单元241时，所述光学元件、所述感光芯片22和所述线路板21相互围合以形成位于三者之间的密封腔，以藉由所述密封腔使得所述感光芯片22的感光区域2211不会因外界灰尘进入而受到污染。
值得一提的是，在本申请实施例中，所述第一模塑单元241通过模塑工艺一体成型于所述线路板21的上表面211，因此，不再需要胶水这类的粘接介质填充在器件之间，从而能够从堆叠方向上降低所述摄像模组及其感光组件20的高度尺寸，另一方面，所述第一模塑单元241的顶表面具有相对较高的平整度，有利于保证其他部件在所述第一模塑单元241上的安装精度的保证。量化来看，在现有的COB组装的摄像模组中，由于镜座/马达底座作为结构件采用安装贴附的方式始终需要避免与电子元器件25(需要Z轴方向、X轴和Y轴方向都避让)，因此相较于模塑体24一体成型的方式，现有技术难以改善XYZ轴三个方向上的尺寸。应可以理解，在通过模塑工艺形成所述第一模塑单元241时，模塑一体成型的高度以所述电子元器件25的最大高度尺寸为准，因此只要能够保护住所述电子元器件25即可，不需要在Z轴方向上预留0.1mm-0.2mm的间隙。而对于在横向空间上，因为不需 要考虑电子元器件25的贴附偏差、胶水烘烤的产生尺寸变化等，因此，不需要在截面方向预留0.2mm-0.4mm左右的空间。
进一步地，在本申请实施例中，所述感光芯片22通过倒装的方式贴附并电连接于所述线路板21的下表面212，即，所述线路板21位于所述感光芯片22的上侧，此时，所述线路板21位于所述光学元件(当所述光学元件被实施为第二光学透镜121时)和所述感光芯片22之间的后焦区域内。应可以理解，由于所述感光芯片22背侧可以不设置所述线路板21，因此能够降低将所述线路板21设置在所述感光芯片22的下侧时造成0.2mm-0.3mm来自于所述线路板21自身厚度造成的Z轴方向堆叠的尺寸，而后焦区域一般1mm-1.5mm的空间足够容纳所述线路板21。
值得一提的是，当所述光学元件被实施为所述第二光学透镜121时，所述第二光学透镜121与所述第一模塑单元241相配合形成所述第二镜头单元12，此时，所述第一模塑单元241相当于所述第二镜头单元12的第二镜筒122。相应地，所述光学镜头10的第一镜头单元11包括第一镜筒112和被收容于所述第一镜筒112内的至少一第一光学透镜111。如图X所示，在本申请一些实施例中，所述光学镜头10的最低的一片镜片为安装于所述第一模塑单元241的所述第二光学透镜121，因此，所述摄像模组的后焦尺寸为所述第二光学透镜121与所述感光芯片22之间的距离。相应地，在该设计方案中，所述第二光学透镜121与所述感光芯片22之间的距离仅仅包括所述线路板21的高度尺寸，所述一体电导通结构23的高度尺寸，所述第二光学透镜121与所述感光芯片22之间的避让间隙，所述第二光学透镜121的贴附间隙，因此相较于现有的通过COB工艺组装的摄像模组，根据本申请实施例的所述摄像模组的后焦尺寸能够得以大幅缩减，从而所述摄像模组的光学总长(Total Track Length，TTL)也能够得以降低。
量化来看，根据本申请实施例的所述摄像模组相对于传统的通过COB工艺组装的摄像模组，其后焦尺寸减小了滤光元件26的高度尺寸(0.1mm-0.2mm)，滤光元件26的贴附间隙(0.02mm-0.04mm)和光学镜头10的最后一片透镜与滤光元件26之间的最小避让空间(0.5mm-1mm)。具体地，根据本申请实施例的所述摄像模组的后焦尺寸为0.41mm-0.72mm，而传统的摄像模组的后焦尺寸为0.62mm-1.24mm，即，相对于传统的COB工艺组装的摄像模组，根据本申请的所述摄像模组实现了40-80％的后焦空间的降低。进 一步地，通过镜头下沉的设计方式，所述摄像模组的后焦尺寸与其光学总长之间的比值为0.05-0.20。
值得一提的是，在本申请一些实施例中，可将所述滤光元件26设置于所述感光芯片22的上表面221，例如，所述滤光元件26被实施为涂覆于所述感光芯片22的上表面221的滤光膜，通过这样的方式，可充分利用所述摄像模组的后焦空间以压缩所述摄像模组及其感光组件20的整体高度尺寸。
如前所述，摄像模组朝着大光圈的方向发展是当下的发展趋势。由于大光圈自带的浅景深的效果，能够突出摄像主体，因此大光圈摄像特别适合运用在人像模式拍摄中。本领域普通技术人员应知晓，一般作为主摄的摄像模组的光圈都要求在F2.0以上，甚至有些光圈要求在F1.4，为了便于说明，从光圈大到小F1.0-F2.0开始，并按照有效焦距为9mm来进行计算，可以得出所需的光学镜头10的最后一片镜片的出光孔径分别为4.5mm(对应于光圈为F2.0)、5mm、6.4mm、9mm(对应于光圈为F1.0)。本领域普通技术人员应知晓，当所述感光芯片22的尺寸越来越大时，所述感光芯片22对应的光学透镜的视场光阑也会变大，因此往往光学透镜所在的视场光阑在原先孔径可以按照视场角90°来进行计算，光学透镜的最大外径尺寸一般为3倍的出光孔径，因此最后一片光学透镜的最大外径尺寸分别为13.5mm、15mm、19.2mm、27mm。相应地，在所述感光芯片22的型号为1i nch的情况下，最后一片光学透镜的最大外径尺寸与所述感光芯片22的长边尺寸的比例为0.85、0.94、1.2、1.6875。应可以理解，在申请实施例中，所述光学镜头10中最邻近于所述感光芯片22的镜片为所述第二光学透镜121，因此，在本申请实施例中，所述第二光学透镜121的最大外径尺寸与所述感光芯片22的长边尺寸之间的比值为0.85-1.7。
在本申请的一些实施例中，考虑到所述光学镜头10的外侧还设有所述镜头驱动组件30的线圈、磁铁以及相关结构器件，一般来说会增加周侧尺寸2mm-3mm，因此带镜头驱动组件30的所述摄像模组的最大外径尺寸为15.5mm、17mm、21.2mm、29mm。相应地，带所述镜头驱动组件30的所述摄像模组的最大外径尺寸与所述感光芯片22的长边尺寸之间的比值在0.97-1.82之间，这些参数能够说明该方案中由于所述线路板21可以做小，因此相对来说，所述感光芯片22的可以适当增大。
应注意到，在本申请实施例中，所述光学镜头10中最邻近所述感光芯片22的光学透镜为安装于所述第一模塑单元241的所述第二光学透镜121，并且，所述光学镜头10中位于最底层的所述第二光学透镜121具有相对最大的外径尺寸。应可以理解，通过增加所述光学镜头10中最后一片光学透镜的尺寸可增加所述光学镜头10的整体通光量。并且，所述第二光学透镜121的最大外径尺寸决定了所述光学镜头10的最大外径尺寸。
相应地，在本申请实施例中，所述第二光学透镜121的最大外径尺寸与所述感光芯片22的长边尺寸之间的比例为1.2-1.7，优选地，所述第二光学透镜121的最大外径尺寸小于等于所述感光芯片22的长边尺寸的1.2倍。应可以理解，由于所述第二光学透镜121的最大外径尺寸与所述感光芯片22的长边长度相接近，因此，在所述光学镜头10的设计中，能够以所述感光芯片22的长边尺寸作为最小尺寸的设计基础，而得益于本申请的所述线路板21及其感光组件20的尺寸小型化，因此，所述光学镜头10和所述镜头驱动组件30的尺寸都可以进一步减少。并且，由于镜片下沉式的设计会使得所述摄像模组的后焦尺寸得以缩减，在后焦尺寸/光学总长＝0.05-0.2的情况下，所述第二光学透镜121的最大外径尺寸也不需要那么大。本领域普通技术人员应知晓，如果光学透镜的孔径过大会带来更大的扩散面积，从而光线经过所述模塑体24会造成暗角等情况，也就是说，在本申请实施例中，所述第二光学透镜121的尺寸没必要做得过大。
为了进一步缩小所述第二光学透镜121所占据的空间尺寸，采用D-cut光学途径以有效地压缩所述第二光学透镜121的有效孔径的外侧空间，从而缩小所述第二光学透镜121的尺寸。如图10所示，在本申请一个具体的示例中，所述第二光学透镜121具有分别对应于所述感光芯片22的两短边的两条切边，其中，两条所述切边相对于所述光学透镜所设定的中心轴对称分布，通过对所述第二光学透镜121的无效区域进行切割不仅可以缩减所述第二光学透镜121的尺寸，还更加便于所述第二光学透镜121的注塑成型。
如图11所示，在本申请另外一个具体的示例中，所述第二光学透镜121具有对应于所述感光芯片22的两条长边的第一切边1211和第二切边1212，以及，对应于所述感光芯片22的两条短边的第三切边1213和第四切边1214。并且，在所述第二光学透镜121的在四个转角区域上设置用于粘接的结构区。
为了保证进一步光线经过所述第二光学透镜121透射到所述感光芯片22上不会出现暗角的情况，在本申请一些实施例中，所述第二光学透镜121具有突出地形成于其四个转角区域的四个透光区域1215，用于透过光线。应可以理解，所述第二光学透镜121中四个转角相对于其所设定的中心的距离最大，因此如果在所述第二光学透镜121组装于所述第一模塑单元241时发生了偏心的问题，容易造成所述感光芯片22对应四角出现暗角的情况。因此，在本申请实施例中，在所述第二光学透镜121的四个转角区域配置四个透光区域1215。
在一种具体的实施方案中，在所述第二光学透镜121的光学区的四个转角处设置对应的自由曲面延伸边以形成所述四个透光区域1215，其中该位于所述第二光学透镜121的四个转角区域的的自由曲面延伸边具有与所述光学区相一致的光学曲率，这相当于变相地增加所述第二光学透镜121的光学区，从而增加所述第二光学透镜121的总透光面积。
在另一种具体的实施方案中，可在所述第二光学透镜121的四个转角处设置四个结构区，并在所述四个结构区的附近做出对应的位于所述第二光学透镜121的四个转角处的光学曲面，从而也能够增加所述第二光学透镜121的有效光学区域的透光面积。
进一步地，在本申请一些实施例中，所述摄像模组具有光学防抖功能以改善用户的拍摄体验。应可以理解，可通过所述镜头驱动组件30来驱动所述光学镜头10在垂直于光轴的平面内移动以进行光学防抖。但是考虑到所述光学镜头10在本申请的一些实施例中采用分体式结构，因此，在本申请实施例中，优选地将防抖驱动对象设置为所述感光组件20，而所述镜头驱动组件30则用于驱动所述光学镜头10的第一镜头单元11沿着所述光轴所设定的方向进行移动以进行光学对焦。
相应地，如图12所示，在本申请实施例中，所述摄像模组还包括用于驱动所述感光组件20在垂直于光轴的平面内进行移动以实现光学防抖的芯片驱动组件40，其中，所述芯片驱动组件40，包括：驱动单元41、引线框架42、防抖支架43和防抖外壳44。相应地，在本申请实施例中，所述感光组件20被收容于所述防抖外壳44内，所述防抖支架43被固定于所述防抖外壳44内且位于所述感光组件20的外侧，所述引线框架42延伸于所 述感光组件20和所述防抖支架43之间且所述感光组件20通过所述引线框架42相对于所述防抖支架43可移动，所述驱动单元41适于驱动所述感光组件20相对于所述防抖支架43进行移动以进行光学防抖。
在本申请实施例中，所述镜头驱动组件30的类型并不为本申请所局限，其包括但不限于：电磁式马达、记忆合金致动器、压电致动器等。例如，在本申请一个具体的示例中，所述镜头驱动组件30被实施为电磁式马达，其包括：用于承载所述第一镜头单元11的第一载体31、用于驱动所述第一载体31以带动所述第一镜头单元11的对焦线圈32和对焦磁石33，用于对所述第一载体31的移动进行限位的第一弹片34和第二弹片35，以及，用于收容所述第一载体31、所述对焦线圈32和所述对焦磁石33、所述第一弹片34和所述第二弹片35的对焦壳体36。
如图12所示，在本申请一个具体的示例中，所述芯片驱动组件40同样被实施为电磁式马达，其中，所述驱动单元41包括驱动线圈411和与所述驱动线圈411对应的驱动磁石412。优选地，在本申请该具体示例中，所述芯片驱动组件40的驱动磁石412与所述镜头驱动组件30的对焦磁石33为同一磁石。更具体地，所述驱动线圈411被设置于所述线路板21的上表面211且位于所述第一模塑单元241的外侧。所述引线框架42包括被设置于所述防抖支架43的固定板421、被设置于所述线路板21的移动板423和连接所述移动板423和所述固定板421的弹性连接带422，其中，所述弹性元件一方面可以为能够运动的所述移动板423提供一种较为稳定的初始状态，另一方面，还可以起到线路导通的作用。应注意到，所述移动板423在其中间区域开设通光孔，所述通光孔对应于所述感光芯片22的感光区域2211，从而使得所述摄像模组光线能够通过所述通光孔到达所述感光芯片22的感光区域2211。
在该具体示例中，所述引线框架42的移动板423与所述线路板21固定相连并电导通，两者之间可通过焊接的方式进行固定。所述引线框架42的固定板421被固定连接于所述防抖支架43，其中，所述防抖支架43被固设于所述防抖壳体内。应可以理解，所述防抖支架43为固定的对象，所述感光组件20通过所述引线框架42被悬持于所述防抖壳体内并相对于所述防抖支架43可发生移动。当所述驱动磁石412与所述驱动线圈411产生电磁感应，使得所述引线框架42提供一定的回复力，进一步使得引线框架 42被驱动发生形变之后仍能回复至原位；当所述引线框架42被驱动发生形变时，带动其相连的所述线路板21进行移动继而带动整个所述感光组件20在垂直于所述光轴的平面内进行移动，以使得所述感光芯片22在X轴方向或者Y轴方向实现光学防抖。
在本申请一些实施例中，如图13所示，所述防抖支架43的内侧端具有散热件，所述散热件包括一主动散热件272以及被动散热件271，所述主动散热件272设置于所述引线框架42的固定部或所述防抖支架43的上表面处，具有主动散热的作用，且所述主动散热件272具有较高的热传导效率，减少所述感光芯片22产生的热量；所述被动散热件271设置于所述感光芯片22的底部。优选地，所述被动散热件271为石墨烯涂层，石墨烯涂层能够向外侧延伸至所述主动散热件272，其横向热传导性很强，且能够配合所述主动散热件272工作，散热效率更高。
从俯视角度看，在本申请实施例中，所述驱动单元41包括四个所述驱动线圈411，其中，四个所述驱动线圈411被设置于所述线路板21的上表面211的四个转角处且位于所述第一模塑单元241的外侧。应注意到，在本申请实施例中，所述线路板21还包括形成于其上表面211的位于每两个所述驱动线圈411之间的多个第三电连接端2111。更明确地，在本申请实施例中，所述多个第三电连接端2111位于所述线路板21的上表面211的四条边的中间处。也就是说，在本申请实施例中，所述第一模塑单元241的覆盖区域为：除去形成于所述线路板21的中间区域的通孔210、除去位于四个转角区域的四个驱动线圈411、除去位于四条边的中间区域的多个第三电连接端2111以外的其余部分。值得一提的是，相较于所述第二模塑单元242，由于所述第一模塑单元241需要设置更多的避让空间，因此，在本申请一些实施例中，所述第一模塑单元241在所述线路板21的上表面211的覆盖区域大于所述第二模塑单元242在所述线路板21的下表面212的覆盖区域。
在本申请实施例中，如图14所示，所述移动板423包括移动板主体4231和自所述移动板主体4231的内侧边框的向内延伸的至少一导电突出部4232，所述至少一导电突出部4232电连接于所述线路板21的上表面211。更明确地，在本申请实施例中，所述至少一导电突出部4232包括四个所述导电突出部4232，四个所述导电突出部4232分别对应于所述第一模塑 单元241的外侧周缘2412的四条侧边的中部，即，分别电连接于位于所述四条侧边的中间区域的所述多个第三电连接端2111。
如图15所示，在本申请的另外一些实施例中，在所述感光组件20中的引线框架42还可设置于所述线路板21的下表面212，此时所述引线框架42的移动板423与所述线路板21的下表面212固定相连并电导通，两者之间通过焊接的方式进行固定。在该具体示例中，所述散热件包括一主动散热件272以及被动散热件271，所述主动散热件272设置于所述引线框架42的固定部或所述防抖支架43的上表面处，具有主动散热的作用，且所述主动散热件272具有较高的热传导效率，减少所述感光芯片22产生的热量，所述被动散热件271设置于所述感光芯片22的底部，优选地，所述被动散热件271为石墨烯涂层，石墨烯涂层能够向外侧延伸至所述引线框架42的移动板423，所述移动板423进而通过线路导通至所述主动散热件272，其横向热传导性很强，且能够配合所述主动散热件272工作，散热效率更高。
本领域的技术人员应理解，上述描述及附图中所示的本发明的实施例只作为举例而并不限制本发明。本发明的目的已经完整并有效地实现。本发明的功能及结构原理已在实施例中展示和说明，在没有背离所述原理下，本发明的实施方式可以有任何变形或修改。

Claims (120)

  1. 一种感光组件，其特征在于，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
    感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；以及
    多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘；
    其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘；
    其中，所述线路板的通孔对应于所述感光芯片的感光区域。
  2. 根据权利要去1所述的感光组件，其中，所述绝缘介质的玻璃化温度小于所述第一电结合件和所述第二电结合件的熔点。
  3. 根据权利要求2所述的感光组件，其中，所述第一电结合件和所述第二电结合件由相同的金属材料制成，所述第一电结合件和所述第二电结合件具有相同的熔点。
  4. 根据权利要求3所述的感光组件，其中，所述第一电结合件和所述第二电结合件的熔点温度与所述绝缘介质的玻璃化温度之差大于等于30° 小于等于80°
  5. 根据权利要求4所述的感光组件，其中，所述绝缘介质的玻璃化温度为180°，所述第一电结合件和所述第二电结合件的熔点为250°。
  6. 根据权利要求5所述的感光组件，其中，所述第一电结合件和所述第二电结合件由锡球制成，所述绝缘介质被实施为NCP助焊剂。
  7. 根据权利要求6所述的感光组件，其中，所述第一电结合件通过回流焊与所述第一电连接端进行电连接，所述第二电结合件通过回流焊与所述第二电连接端进行电连接，所述第一电结合件和所述第二电结合件通过热压工艺实现共晶结合。
  8. 根据权利要求6所述的感光组件，其中，所述第一电连接端具有预设截面尺寸以允许至少五颗所述锡球同时堆叠于所述第一电连接端上，所述第二电连接端具有预设截面尺寸以允许至少五颗所述锡球同时堆叠于所述第二电连接端上。
  9. 根据权利要求8所述的感光组件，其中，所述第一电连接端和所述第二电连接端的直径为70um，所述锡球的直径为5um-15um。
  10. 根据权利要求1所述的感光组件，其中，所述线路板由加成法或半加成法制备而成。
  11. 根据权利要求10所述的感光组件，其中，所述线路板还包括铺设于所述下表面的所述多个第一电连接端的外围的油墨层，其中，在所述多个第一电连接端之间不设有所述油墨层。
  12. 根据权利要求11所述的感光组件，其中，所述多个第一电连接端均匀地且等间距的分布于所述线路板的下表面。
  13. 一种感光组件的电导通方法，其特征在于，包括：
    提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
    通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件；
    分别在所述第一电结合件和/或所述第二电结合件上铺设一层绝缘介质，其中，所述绝缘介质的玻璃化温度低于所述第一电结合件和所述第二电结合件的熔点温度；以及
    通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，通过这样的方式，将所述感光芯片电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔。
  14. 根据权利要求13所述的感光组件的电导通方法，其中，通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件，包括：
    在所述线路板的下表面上叠置钢网，所述钢网具有多个对应于所述多个第一电连接端的圆形开孔；
    将锡膏铺设于所述钢网上并通过刮刀刮图所述锡膏以使得所述锡膏分别落于所述多个第一电连接端上；以及
    通过回流焊对铺设有所述锡膏的所述线路板进行处理，其中，经回流焊处理后的所述锡膏形成所述多个第一电结合件。
  15. 根据权利要求14所述的感光组件的电导通方法，其中，所述圆形开孔的直径配置使得至少所述锡膏中至少五颗锡球可同时被收容于所述圆形开孔内。
  16. 根据权利要求15所述的感光组件的电导通方法，其中，所述圆形开孔的直径为70um，所述锡球的直径为5um-15um。
  17. 根据权利要求13所述的感光组件的电导通方法，其中，通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，包括：
    在加热到所述绝缘介质的玻璃化温度时，所述绝缘介质由固态被转化为玻璃态；以及
    继续加热并压合所述线路板和所述感光芯片，其中，所述第一电结合件和所述第二电结合件破开玻璃态的所述绝缘介质并相互共晶结合，玻璃态的所述绝缘介质被挤压至共晶结合的所述第一电结合件和所述第二电结合件的周围。
  18. 根据权利要求17所述的感光组件的电导通方法，其中，所述线路板还包括铺设于所述下表面的所述多个第一电连接端的外围的油墨层，其中，在所述多个第一电连接端之间不设有所述油墨层。
  19. 一种感光组件，其特征在于，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
    感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
    所述线路板的下表面叠置于所述感光芯片的上表面，所述多个第二电连接端分别对应且电连接于所述多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域；
    模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元，其中， 所述第一模塑单元具有安装腔；以及
    安装于所述安装腔内的第二光学透镜，其中，所述第二光学透镜与所述第一模塑单元相配合以形成第二镜头单元。
  20. 根据权利要求19所述的感光组件，其中，所述感光组件的后焦尺寸为0.41mm-0.72mm。
  21. 根据权利要求19所述的感光组件，其中，所述第二光学透镜的最大外径尺寸与所述感光芯片的长边尺寸之间的比例为1.2-1.7。
  22. 根据权利要求21所述的感光组件，其中，所述第二光学透镜的最大外径尺寸小于等于所述感光芯片的长边尺寸的1.2倍。
  23. 根据权利要求19所述的感光组件，其中，所述第二光学透镜具有分别对应于所述感光芯片的两短边的两条切边，其中，两条所述切边相对于所述光学透镜所设定的中心轴对称分布。
  24. 根据权利要求19所述的感光组件，其中，所述感光组件还包括电连接于所述线路板的上表面的至少一电子元器件，所述至少一电子元器件的至少一部分被包覆于所述第一模塑单元内。
  25. 根据权利要求24所述的感光组件，其中，所述第一模塑单元的高度尺寸为0.2mm-0.5mm。
  26. 根据权利要求25所述的感光组件，其中，所述第一模塑单元的高度尺寸为0.4mm，所述至少一电子元器件的最大高度尺寸小于0.4mm。
  27. 根据权利要求19所述的感光组件，其中，所述第一模塑单元具有顶表面，所述第一模塑单元的顶表面的平整度RZ等于5um。
  28. 根据权利要求19所述的感光组件，其中，所述线路板由半加成法 或加成法制备而得，所述线路板的厚度尺寸为0.05mm-0.4mm。
  29. 根据权利要求19所述的感光组件，其中，所述模塑体还包括一体结合于所述线路板的下表面且环绕所述感光芯片的第二模塑单元，其中，所述第二模塑单元的厚度尺寸大于所述感光芯片的厚度尺寸。
  30. 根据权利要求29所述的感光组件，其中，所述第二模塑单元的厚度尺寸为0.2mm-0.3mm。
  31. 一种摄像模组，其特征在于，包括：
    如权利要求19至30任一所述的感光组件；以及
    被保持于所述感光组件的感光路径上的第一镜头单元，其中，所述第一镜头单元与所述感光组件的第二镜头单元相配合以形成透镜组。
  32. 根据权利要求31所述的摄像模组，其中，所述摄像模组还包括用于驱动所述第一镜头单元相对于所述感光组件进行移动的镜头驱动组件。
  33. 根据权利要求31所述的摄像模组，其中，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.2。
  34. 根据权利要求33所述的摄像模组，其中，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.1。
  35. 一种感光组件，其特征在于，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
    感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
    其中，所述线路板的下表面叠置于所述感光芯片的上表面且所述多个第 一电连接端分别对应并电连接于所述多个第二电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域；以及
    模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元，其中，所述第一模塑单元沿所述感光组件设定的高度方向上在所述线路板的上表面的第一投影区域与所述第二模塑单元沿所述高度方向在所述线路板的下表面的第二投影区域共中心轴设置。
  36. 根据权利要求35所述的感光组件，其中，所述第一投影区域和所述第二投影区域具有相同的形状和尺寸。
  37. 根据权利要求35所述的感光组件，其中，所述第一投影区域和所述第二投影区域具有相同的形状和不同的尺寸。
  38. 根据权利要求36所述的感光组件，其中，所述第一投影区域的内周缘对齐于所述第二投影区域的内周缘，所述第一投影区域的外周缘对齐于所述第二投影区域的外周缘。
  39. 根据权利要求37所述的感光组件，其中，所述第一投影区域的外周缘与所述第二投影区域的外周缘对齐，所述线路板具有形成所述通孔的内周缘，其中，所述第一投影区域的内周缘相较于所述第二投影区域的内周缘更邻近于所述线路板的内周缘。
  40. 根据权利要求37所述的感光组件，其中，所述第一投影区域的内周缘与所述第二投影区域的内周缘对齐，所述线路板具有外周缘，其中，所述第二投影区域的外周缘相较于所述第一投影区域的外周缘更邻近于所述线路板的外周缘。
  41. 根据权利要求35所述的感光组件，其中，所述感光组件还包括被设置于所述线路板的上表面且被所述第一模塑单元包覆的至少一电子元器 件。
  42. 根据权利要求41所述的感光组件，其中，所述第一模塑单元的高度尺寸为0.35mm至0.5mm。
  43. 根据权利要求42所述的感光组件，其中，所述线路板由加成法或半加成法制备而成，所述线路板的厚度尺寸为0.05mm-0.35mm。
  44. 根据权利要求42所述的感光组件，其中，所述第一模塑单元具有顶表面，所述顶表面的平整度RZ为5um。
  45. 根据权利要求42所述的感光组件，其中，所述第一模塑单元的高度尺寸大于所述第二模塑单元的高度尺寸。
  46. 根据权利要求45所述的感光组件，其中，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
  47. 根据权利要求46所述的感光组件，其中，所述第二模塑单元包绕地形成于所述感光芯片的周围。
  48. 根据权利要求47所述的感光组件，其中，所述第二模塑单元的高度尺寸大于所述感光芯片的厚度尺寸。
  49. 根据权利要求35所述的感光组件，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘。
  50. 根据权利要求49所述的感光组件，其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结 合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘；
  51. 根据权利要去50所述的感光组件，其中，所述绝缘介质的玻璃化温度小于所述第一电结合件和所述第二电结合件的熔点。
  52. 一种感光组件的制备方法，其特征在于，包括：
    提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
    通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件；
    通过模塑工艺在所述线路板的上表面形成第一模塑单元以及在所述线路板的下表面形成第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元对所述线路板进行结构加强；
    分别在所述第一电结合件和/或所述第二电结合件上铺设一层绝缘介质，其中，所述绝缘介质的玻璃化温度低于所述第一电结合件和所述第二电结合件的熔点温度；以及
    通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，通过这样的方式，将所述感光芯片电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔。
  53. 一种摄像模组，其特征在于，包括：感光组件和被保持于所述感光组件的感光路径上的光学镜头；
    其中，所述感光组件，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔；
    感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片的上表面电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔；
    模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元；
    其中，所述光学镜头的最大外径尺寸与所述感光芯片的长边长度之间的比值为0.85至1.7。
  54. 根据权利要求53所述的摄像模组，其中，所述摄像模组进一步包括被安装于所述第一模塑单元的顶表面且用于驱动所述光学镜头的至少一部分相对于所述感光芯片进行移动的马达，其中，所述马达的最大外径尺寸与所述感光芯片的长边长度之间的比值为0.97-1.82。
  55. 根据权利要求54所述的摄像模组，其中，所述第一模塑单元的顶表面的平整度RZ为5um。
  56. 根据权利要求54所述的摄像模组，其中，所述光学镜头包括至少一第一光学透镜的第一镜头单元和一第二光学透镜，所述第二光学透镜被安装于所述第一模塑单元，所述第二光学透镜与所述第一模塑单元相配合形成第二镜头单元。
  57. 根据权利要求56所述的摄像模组，其中，所述摄像模组的后焦尺寸为0.41mm-0.72mm，所述摄像模组的后焦尺寸为所述第二光学透镜与所述感光芯片之间的距离。
  58. 根据权利要求56所述的摄像模组，其中，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.2。
  59. 根据权利要求58所述的摄像模组，其中，所述摄像模组的后焦尺 寸与所述摄像模组的光学总长之间的比值为0.05-0.1。
  60. 根据权利要求56所述的摄像模组，其中，所述第二光学透镜的最大外径尺寸小于等于所述感光芯片的长边尺寸的1.2倍。
  61. 根据权利要求60所述的摄像模组，其中，所述第二光学透镜具有对应于所述感光芯片的两条长边的第一切边和第二切边，以及，对应于所述感光芯片的两条短边的第三切边和第四切边。
  62. 根据权利要求61所述的摄像模组，其中，所述第二光学透镜具有突出地形成于其四个转角区域的四个透光区域。
  63. 根据权利要求58所述的摄像模组，其中，所述线路板的厚度尺寸为0.05mm-0.4mm，所述第一模塑单元的高度尺寸为0.2mm-0.5mm，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
  64. 根据权利要求58所述的摄像模组，其中，所述第二模塑单元的底表面低于所述感光芯片的下表面。
  65. 根据权利要求56所述的摄像模组，其中，所述感光组件还包括附着于所述感光芯片的上表面的滤光元件。
  66. 根据权利要求56所述的摄像模组，其中，所述感光组件还包括附着于所述第二光学透镜的滤光元件。
  67. 根据权利要求53所述的摄像模组，其中，所述线路板包括形成于所述下表面的多个第一电连接端，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；
    其中，所述感光组件还包括多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连 接于位于所述线路板的下表面的多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域。
  68. 根据权利要求67所述的摄像模组，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘，其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘。
  69. 一种摄像模组，其特征在于，包括：
    感光组件；
    被保持于所述感光组件的感光路径上的光学镜头；以及
    用于驱动所述感光组件相对于所述光学镜头进行移动的芯片驱动组件；
    其中，所述感光组件，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔；
    感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片的上表面电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔；及
    模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元；
    其中，所述芯片驱动组件，包括：驱动单元、引线框架、防抖支架和防抖外壳，其中，所述感光组件被收容于所述防抖外壳内，所述防抖支架被固定于所述防抖外壳内且位于所述感光组件的外侧，所述引线框架延伸于所述感光组件和所述防抖支架之间且所述感光组件通过所述引线框架相对于所 述防抖支架可移动，所述驱动单元适于驱动所述感光组件相对于所述防抖支架进行移动以进行光学防抖。
  70. 根据权利要求69所述的摄像模组，其中，所述引线框架包括被设置于所述防抖支架的固定板、被设置于所述线路板的移动板和连接所述移动板和所述固定板的弹性连接带。
  71. 根据权利要求70所述的摄像模组，其中，所述移动板被固定于且电连接于所述线路板的上表面。
  72. 根据权利要求70所述的摄像模组，其中，所述移动板被固定于且电连接于所述线路板的下表面。
  73. 根据权利要求71所述的摄像模组，其中，所述驱动单元包括驱动线圈和与所述驱动线圈对应的驱动磁石，其中，所述驱动线圈被设置于所述线路板的上表面且位于所述第一模塑单元的外侧。
  74. 根据权利要求73所述的摄像模组，其中，所述第一模塑单元具有外侧周缘和内侧周缘，所述第一模塑单元的外侧周缘邻近于所述驱动线圈，所述第一模塑单元的内侧周缘邻近于所述线路板的内周缘，所述线路板的内周缘形成所述通孔。
  75. 根据权利要求74所述的摄像模组，其中，所述感光芯片和所述线路板在所述线路板的下表面的结合处对应于所述线路板的上表面的位置被所述第一模塑单元所包覆。
  76. 根据权利要求75所述的摄像模组，其中，所述第二模塑单元具有外侧周缘和内侧周缘，所述第一模塑单元的内侧周缘相对于所述第二模塑单元的内侧周缘更邻近于所述线路板的内周缘。
  77. 根据权利要求76所述的摄像模组，其中，所述第一模塑单元沿所 述摄像模组设定的高度方向在所述线路板的上表面的第一投影区域的面积小于所述第二模塑单元沿所述高度方向在所述线路板的下表面的第二投影区域的面积。
  78. 根据权利要求77所述的摄像模组，其中，所述线路板具有外周缘，所述第二模塑单元的外侧周缘相对于所述第一模塑单元的外侧周缘更邻近所述线路板的外周缘。
  79. 根据权利要求74所述的摄像模组，其中，所述驱动单元包括四个所述驱动线圈，4个所述驱动线圈位于所述第一模塑单元的四个转角处。
  80. 根据权利要求79所述的摄像模组，其中，所述移动板包括移动板主体和自所述移动板主体的内侧边框的向内延伸的至少一导电突出部，所述至少一导电突出部电连接于所述线路板的上表面。
  81. 根据权利要求80所述的摄像模组，其中，所述至少一导电突出部包括四个所述导电突出部，四个所述导电突出部分别对应于所述第一模塑单元的外侧周缘的四条侧边的中部。
  82. 根据权利要求69所述的摄像模组，其中，所述感光组件还包括电连接于所述线路板的上表面的至少一电子元器件，所述至少一电子元器件的至少一部分被包覆于所述第一模塑单元内，所述第一模塑单元的高度尺寸为0.2mm-0.5mm，所述第二模塑单元环绕地形成于所述感光芯片的周围，所述第二模塑单元的底表面低于所述感光芯片的下表面，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
  83. 根据权利要求69所述的摄像模组，其中，所述线路板包括形成于所述下表面的多个第一电连接端，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端分别与所述多个第一电连接端相对应；
    其中，所述感光组件还包括多个一体电导通结构，其中，位于所述感光 芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域。
  84. 根据权利要求83所述的摄像模组，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘，其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘。
  85. 根据权利要求69所述的摄像模组，其中，所述感光组件进一步包括设置于所述第一模塑单元的第二光学透镜。
  86. 根据权利要求85所述的摄像模组，其中，所述摄像模组的后焦尺寸为0.41mm-0.72mm，所述摄像模组的后焦尺寸为所述第二光学透镜与所述感光芯片之间的距离，所述摄像模组的后焦尺寸与所述摄像模组的光学总长之间的比值为0.05-0.2。
  87. 一种感光组件，其特征在于，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，其中，所述线路板包括形成于所述下表面的多个第一电连接端；
    感光芯片，具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，其中，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端，所述多个第二电连接端 分别与所述多个第一电连接端相对应；
    多个一体电导通结构，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，通过这样的方式，所述感光芯片电连接于所述线路板的下表面且所述线路板的通孔对应于所述感光芯片的感光区域；以及
    模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的第二模塑单元。
  88. 根据权利要求87所述的感光组件，其中，所述感光芯片与所述线路板在所述线路板的下表面的结合处对应于所述线路板的上表面的位置被所述第一模塑单元所包覆。
  89. 根据权利要求88所述的感光组件，其中，所述线路板具有内周缘和外周缘，所述线路板的内周缘形成所述通孔，所述感光芯片具有外周缘，其中，所述第一模塑单元具有内侧周缘和外侧周缘，所述第一模塑单元的内侧周缘位于所述感光芯片与所述线路板在所述线路板的下表面的结合处对应于所述线路板的上表面的位置和所述线路板的内周缘之间。
  90. 根据权利要求89所述的感光组件，其中，所述第一模塑单元的内侧周缘与所述线路板的内周缘对齐。
  91. 根据权利要求89所述的感光组件，其中，所述第二模塑单元具有内侧边缘和外侧边缘，所述第一模塑单元的内周缘相对于所述第二模塑单元的内周缘更邻近于所述线路板的内周缘。
  92. 根据权利要求91所述的感光组件，其中，所述第一模塑单元的外侧周缘邻近于或者齐平于所述线路板的外周缘。
  93. 根据权利要求92所述的感光组件，其中，所述第一模塑单元的外侧周缘在所述高度方向上与所述第二模塑单元的外侧周缘对齐。
  94. 根据权利要求92所述的感光组件，其中，所述第一模塑单元的外侧周缘邻近于或者齐平于所述线路板的外周缘。
  95. 根据权利要求87所述的感光组件，其中，所述感光组件还包括被设置于所述线路板的上表面且被所述第一模塑单元包覆的至少一电子元件。
  96. 根据权利要求95所述的感光组件，所述第一模塑单元的高度尺寸为0.35mm至0.5mm。
  97. 根据权利要求96所述的感光组件，其中，所述第一模塑单元具有顶表面，所述顶表面的平整度RZ为5um。
  98. 根据权利要求87所述的感光组件，其中，所述第二模塑单元包绕地形成于所述感光芯片的周围。
  99. 根据权利要求98所述的感光组件，其中，所述第二模塑单元的底表面低于所述感光芯片的下表面。
  100. 根据权利要求98所述的感光组件，其中，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
  101. 根据权利要求87所述的感光组件，其中，位于所述感光芯片的上表面的所述多个第二电连接端通过所述多个一体电导通结构电连接于位于所述线路板的下表面的多个第一电连接端，且每一对相互电连接的所述第一电连接端和所述第二电连接端通过所述多个一体电导通结构进行绝缘。
  102. 根据权利要求101所述的感光组件，其中，每一所述一体电导通结构包括电连接于所述第一电连接端的第一电结合件以及电连接于所述第二电连接端的第二电结合件，所述第一电结合件与所述第二电结合件共晶结合，其中，每一所述一体电导通结构还包括包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围的绝缘介质，以通过所述绝缘介质使得每一 对相互电连接的所述第一电连接端和所述第二电连接端相互绝缘；
  103. 根据权利要去102所述的感光组件，其中，所述绝缘介质的玻璃化温度小于所述第一电结合件和所述第二电结合件的熔点。
  104. 一种感光组件的制备方法，其特征在于，包括：
    提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域的多个第二电连接端；
    通过植球工艺分别在所述线路板的多个第一电连接端上形成多个第一电结合件以及在所述感光芯片的多个第二电连接端上形成多个第二电结合件；
    通过模塑工艺在所述线路板的上表面形成第一模塑单元以及在所述线路板的下表面形成第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元对所述线路板进行结构加强；
    分别在所述第一电结合件和/或所述第二电结合件上铺设一层绝缘介质，其中，所述绝缘介质的玻璃化温度低于所述第一电结合件和所述第二电结合件的熔点温度；以及
    通过热压工艺实现所述多个第一电结合件和所述多个第二电结合件之间的共晶结合且所述绝缘介质分别包覆于共晶结合的所述第一电结合件和所述第二电结合件的周围，通过这样的方式，将所述感光芯片电连接于所述线路板的下表面，且所述感光芯片的感光区域对应于所述通孔。
  105. 一种线路板组件，其特征在于，包括：
    线路板，具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板的下表面具有邻近于所述通孔的电导通区域和位于所述电导通区域的外围的周围区域；其中，所述线路板包括形成于所述电导通区域的多个第一电连接端；以及
    模塑体，包括一体地结合于所述线路板的上表面的第一模塑单元和一体地结合于所述线路板的下表面的周围区域的第二模塑单元。
  106. 根据权利要求105所述的线路板组件，其中，所述线路板还包括铺设于所述周围区域的油墨层，且所述多个第一电连接端之间不设有所述油墨层。
  107. 根据权利要求106所述的线路板组件，其中，所述多个第一电连接端均匀地且等间距的分布于所述电导通区域。
  108. 根据权利要求106所述的线路板组件，其中，所述线路板的厚度尺寸为0.2mm。
  109. 根据权利要求105所述的线路板组件，其中，所述第一电连接端具有预设直径尺寸使得在所述第一电连接端的上方能够叠置至少五颗直径为5um-15um的锡球。
  110. 根据权利要求105所述的线路板组件，其中，所述多个第一电连接端在所述线路板的下表面的铺设位置对应于所述线路板的上表面的位置被所述第一模塑单元所包覆。
  111. 根据权利要求105所述的线路板组件，其中，所述第一模塑单元与所述第二模塑单元在所述线路板组件所设定的高度方向上相互对齐。
  112. 根据权利要求110所述的线路板组件，其中，所述线路板具有内周缘和外周缘，所述线路板的内周缘形成所述通孔，其中，所述第一模塑单元具有内侧周缘和外侧周缘，所述第二模塑单元具有内侧边缘和外侧边缘，所述第一模塑单元的内周缘相对于所述第二模塑单元的内周缘更邻近于所述线路板的内周缘。
  113. 根据权利要求111所述的线路板组件，其中，所述线路板具有内 周缘和外周缘，所述线路板的内周缘形成所述通孔，其中，所述第一模塑单元具有内侧周缘和外侧周缘，所述第二模塑单元具有内侧边缘和外侧边缘，所述第一模塑单元的内侧周缘在所述高度方向上与所述第二模塑单元的内侧周缘对齐，所述第一模塑单元的外侧周缘在所述高度方向上与所述第二模塑单元的外侧周缘对齐。
  114. 根据权利要求105所述的线路板组件，其中，所述线路板组件还包括被设置于所述线路板的上表面且被所述第一模塑单元包覆的至少一电子元器件。
  115. 根据权利要求114所述的线路板组件，其中，所述第一模塑单元的高度尺寸为0.35mm至0.5mm。
  116. 根据权利要求115所述的线路板组件，其中，所述第一模塑单元具有顶表面，所述顶表面的平整度RZ为5um。
  117. 根据权利要求105所述的线路板组件，其中，所述第二模塑单元包绕地形成于所述感光芯片的周围。
  118. 根据权利要求113所述的线路板组件，其中，所述第二模塑单元的底表面低于所述感光芯片的下表面。
  119. 根据权利要求113所述的线路板组件，其中，所述第二模塑单元的高度尺寸为0.2mm-0.3mm。
  120. 一种线路板组件的制备方法，其特征在于，包括：
    提供一线路板和一感光芯片，其中，所述线路板具有相对的上表面和下表面，以及，贯穿地形成于所述上表面和所述下表面之间的通孔，所述线路板包括形成于所述下表面的多个第一电连接端，其中，所述感光芯片具有相对的上表面和下表面，所述上表面具有感光区域和位于所述感光区域周围的非感光区域，所述感光芯片包括形成于所述感光芯片的上表面的非感光区域 的多个第二电连接端；以及
    通过模塑工艺在所述线路板的上表面形成第一模塑单元以及在所述线路板的下表面形成第二模塑单元，以通过所述第一模塑单元和所述第二模塑单元对所述线路板进行结构加强。
PCT/CN2023/078446 2022-03-01 2023-02-27 感光组件及其电导通方法和制备方法、摄像模组 WO2023165442A1 (zh)

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