WO2023165058A1 - 存储器模型的镜像存储实现方法、装置及存储介质 - Google Patents

存储器模型的镜像存储实现方法、装置及存储介质 Download PDF

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Publication number
WO2023165058A1
WO2023165058A1 PCT/CN2022/101758 CN2022101758W WO2023165058A1 WO 2023165058 A1 WO2023165058 A1 WO 2023165058A1 CN 2022101758 W CN2022101758 W CN 2022101758W WO 2023165058 A1 WO2023165058 A1 WO 2023165058A1
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data
update
memory
memory model
behavior information
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PCT/CN2022/101758
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English (en)
French (fr)
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金鑫
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北京百度网讯科技有限公司
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Priority to EP22868421.3A priority Critical patent/EP4261827A4/en
Publication of WO2023165058A1 publication Critical patent/WO2023165058A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56008—Error analysis, representation of errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation

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  • the present disclosure relates to the field of artificial intelligence technology, and in particular to methods, devices, and storage media for implementing image storage of memory models in the fields of artificial intelligence chips and intelligent voice.
  • UVM Universal Verification Methodology
  • the present disclosure provides a method, a device and a storage medium for implementing mirror storage of a memory model.
  • a mirror storage implementation method of a memory model comprising:
  • the data stored in the memory model is correspondingly updated according to the update behavior information.
  • a device for implementing mirror storage of a memory model comprising: an information acquisition module and a data update module;
  • the information acquiring module is configured to acquire update behavior information of this update in response to a data update behavior occurring in a memory in the device under test, and the update behavior information is extracted from the bus;
  • the data update module is configured to update the data stored in the memory model according to the update behavior information.
  • An electronic device comprising:
  • the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can perform the method as described above.
  • a non-transitory computer-readable storage medium storing computer instructions, the computer instructions are used to cause a computer to execute the method as described above.
  • a computer program product comprising computer programs/instructions, when executed by a processor, implements the method as described above.
  • An embodiment in the above disclosure has the following advantages or beneficial effects: the update behavior information corresponding to the data update behavior of the memory in the device under test can be obtained through the bus, and the memory model can be updated correspondingly according to the obtained information, thereby realizing The mirror storage function of the memory model can effectively realize the memory verification in the chip verification based on the stored data, and correspondingly improve the verification effect of the chip verification.
  • FIG. 1 is a flow chart of an embodiment of a mirror storage implementation method of a memory model described in the present disclosure
  • FIG. 2 is a schematic diagram of a verification environment architecture corresponding to the method described in the present disclosure
  • FIG. 3 is a schematic diagram of the composition and structure of the first embodiment 300 of the mirrored storage implementation device of the memory model described in the present disclosure
  • FIG. 4 is a schematic diagram of the composition and structure of the second embodiment 400 of the device for implementing mirrored storage of the memory model in the present disclosure
  • FIG. 5 shows a schematic block diagram of an electronic device 500 that can be used to implement embodiments of the present disclosure.
  • FIG. 1 is a flow chart of an embodiment of a mirror storage implementation method of a memory model described in the present disclosure. As shown in FIG. 1 , the following specific implementation manners are included.
  • step 101 in response to a data update behavior occurring in the memory of the device under test (DUT, Device Under Test), the update behavior information of this update is obtained, and the update behavior information is extracted from the bus.
  • DUT Device Under Test
  • step 102 correspondingly update the data stored in the memory model (mem_model) according to the update behavior information.
  • the current UVM verification platform only supports the mirror storage function of the register model, and does not support the mirror storage function of the memory model, which affects the verification effect.
  • the update behavior information corresponding to the data update behavior of the memory in the device under test can be obtained through the bus, and the memory model can be updated correspondingly according to the obtained information, thereby realizing the mirror storage of the memory model Function, and then based on the stored data, memory verification in chip verification can be effectively realized, and the verification effect of chip verification can be improved accordingly.
  • the memory model may include: a memory model composed of register groups, and in addition, the number of registers in the register group may be equal to the depth of the memory in the device under test, and/or the number of bits of the registers may be equal to the bit width of the memory in the device under test.
  • the memory model can be constructed quickly and efficiently, thus laying a good foundation for subsequent processing.
  • the above memory model can also be instantiated, for example, the memory model can be instantiated in a scoreboard for practical application.
  • the update behavior information of this update can be obtained, and the data stored in the memory model can be correspondingly updated according to the update behavior information.
  • the data update behavior of the memory in the device under test mainly includes two situations, which will be introduced respectively below.
  • the data update behavior may include: external bus input update, that is, the data update behavior of the memory in the device under test occurs on the bus, such as the device under test reads data as a master device (master) or the device under test Data is written as a slave.
  • external bus input update that is, the data update behavior of the memory in the device under test occurs on the bus, such as the device under test reads data as a master device (master) or the device under test Data is written as a slave.
  • the update behavior information may include: update address and data.
  • the update address and data of this update can be obtained, and the update address and data can be extracted from the bus.
  • the data stored in the memory model can be updated correspondingly according to the update behavior information, that is, the data corresponding to the update address in the memory model can be updated to the data in the update behavior information.
  • the bus can support Advanced Peripheral Bus (APB, Advanced Peripheral Bus), Advanced High Performance Bus (AHB, Advanced High Performance Bus) and advanced extensible interface (AXI, Advanced eXtensible Interface) and other interface protocol types, with wide applicability.
  • APIB Advanced Peripheral Bus
  • AHB Advanced High Performance Bus
  • AXI Advanced eXtensible Interface
  • the data update behavior may include: update after internal processing of the device under test, for example, a calculation instruction can be issued to the device under test from the bus, and correspondingly, the device under test will obtain the source data corresponding to the calculation instruction, and Execute the calculation corresponding to the calculation instruction, obtain the calculation result, and then store the calculation result in the destination address area of the memory.
  • the acquired update behavior information may include: calculation instructions.
  • the data stored in the memory model can be updated according to the update behavior information, that is, the source data corresponding to the calculation instruction can be obtained, and the calculation result generated according to the source data can be obtained, and then the calculation result can be updated to the memory model.
  • the source data may be sent to a simulation model (cmodel), and the calculation result obtained after the simulation model executes a calculation corresponding to a calculation instruction according to the source data may be obtained.
  • cmodel simulation model
  • the simulation model is a simulation model of the device under test, and the calculation result of the simulation model can be considered as an ideal and accurate calculation result.
  • the calculated results of the simulation model can be called expected values.
  • the source data corresponding to the calculation instruction can be obtained from the memory model, and the obtained expected value can be updated to the destination address area in the memory model.
  • the expected value mirroring of the memory can be realized, so as to perform subsequent data comparison and the like.
  • the corresponding data in response to the memory data output behavior of the device under test, can be obtained from the memory model according to the output address extracted from the bus, and the output address extracted from the bus can be The data is compared with the data obtained from the memory model.
  • the device under test receives the memory data output command, that is, the memory data output behavior of the device under test is initiated on the bus, such as the device under test as the master device writes data to the external device or the device under test as the slave device is read data, then you can Extract the output address and output data from the bus, correspondingly, according to the output address, the corresponding data can be obtained from the memory model, and the output data can be compared with the data (expected value) obtained from the memory model Comparison.
  • FIG. 2 is a schematic diagram of a verification environment architecture corresponding to the method described in the present disclosure.
  • it can include components such as scoreboard, command agent (cmd_agent) and data transfer agent (data transfer agent), and the command agent can further include sequence (seqr), driver (driver) and monitor ( monitor) and other components, the data transfer agent may further include components such as drivers and monitors, and the scoreboard may further include components such as memory models and simulation models.
  • the executor of the method described in the present disclosure may be a scoreboard.
  • the memory model may be a memory model composed of register groups, the number of registers in the register group may be equal to the depth of the memory in the device under test, and the number of bits in the register may be equal to the bit width of the memory in the device under test.
  • the function verification of a single instruction can be realized.
  • the source data can be moved to the memory of the device under test through the bus.
  • monitors can be used to identify bus behavior and extract information from the bus, and the specific working methods of each monitor are prior art.
  • the scoreboard can update the data in the memory model according to the update behavior information.
  • the corresponding update is performed on the data, that is, the data corresponding to the update address in the memory model is updated to the data in the update behavior information.
  • the scoreboard can update the data in the memory model according to the update behavior information.
  • the data is updated correspondingly, that is, the source data corresponding to the calculation instruction can be obtained, and the calculation result generated according to the source data can be obtained, and then the calculation result can be updated into the memory model.
  • the scoreboard can obtain the source data from the memory model, and can send the source data to the simulation model, and then can obtain the calculation result obtained after the simulation model executes the calculation corresponding to the calculation instruction according to the source data, that is, the expected value, and update into the memory model.
  • the scoreboard can obtain the corresponding data from the memory model according to the output address, and the The output data is compared with the data obtained from the memory model to complete the required data comparison.
  • each single instruction function verification use case can also be flexibly spliced and combined to realize continuous function verification of multiple instructions.
  • the memory model can be constructed quickly and efficiently, and the image storage function of the memory model can be realized, so as to support effective memory verification, and further improve the verification effect of chip verification.
  • FIG. 3 is a schematic diagram of the composition and structure of a first embodiment 300 of an apparatus for implementing mirrored storage of a memory model according to the present disclosure. As shown in FIG. 3 , it may include: an information acquisition module 301 and a data update module 302 .
  • the information acquiring module 301 is configured to acquire update behavior information of this update in response to a data update behavior occurring in the memory of the device under test, and the update behavior information is extracted from the bus.
  • the data update module 302 is configured to update the data stored in the memory model according to the update behavior information.
  • the update behavior information corresponding to the data update behavior of the memory in the device under test can be obtained through the bus, and the memory model can be updated correspondingly according to the obtained information, thereby realizing the mirror storage of the memory model Function, and then based on the stored data, memory verification in chip verification can be effectively realized, and the verification effect of chip verification can be improved accordingly.
  • the memory model may include: a memory model composed of register groups, and in addition, the number of registers in the register group may be equal to the depth of the memory in the device under test, and/or the number of bits of the registers may be equal to the bit width of the memory in the device under test.
  • the above memory model can also be instantiated, for example, the memory model can be instantiated in the scoreboard for practical application.
  • the data update behavior of the memory in the device under test mainly includes two situations, which will be introduced respectively below.
  • the data update behavior may include: external bus input update, that is, the data update behavior of the memory in the device under test occurs on the bus, such as the device under test reads data as a master device or the device under test as a slave device data is written.
  • the update behavior information may include: update address and data.
  • the update address and data of this update can be obtained, and the update address and data can be extracted from the bus.
  • the data update module 302 may update the data stored in the memory model according to the update behavior information, that is, update the data corresponding to the update address in the memory model to the data in the update behavior information.
  • the data update behavior may include: update after internal processing of the device under test, for example, a calculation instruction can be issued to the device under test from the bus, and correspondingly, the device under test will obtain the source data corresponding to the calculation instruction, and Execute the calculation corresponding to the calculation instruction, obtain the calculation result, and then store the calculation result in the destination address area of the memory.
  • the acquired update behavior information may include: calculation instructions.
  • the data update module 302 can update the data stored in the memory model according to the update behavior information, that is, obtain the source data corresponding to the calculation instruction, and obtain the calculation result generated according to the source data, and then can Update the calculation results into the memory model.
  • the data update module 302 may send the source data to the simulation model, and may obtain the calculation result obtained after the simulation model executes the calculation corresponding to the calculation instruction according to the source data.
  • the simulation model is a simulation model of the device under test, and the calculation result of the simulation model can be considered as an ideal and accurate calculation result.
  • the calculated results of the simulation model can be called expected values.
  • the data update module 302 can obtain source data corresponding to the calculation instruction from the memory model, and can update the obtained expected value to the destination address area in the memory model.
  • FIG. 4 is a schematic diagram of the composition and structure of a second embodiment 400 of an apparatus for implementing mirrored storage of a memory model according to the present disclosure. As shown in FIG. 4 , it may include: an information acquisition module 301 , a data update module 302 and a data comparison module 303 .
  • the functions of the information acquiring module 301 and the data updating module 302 are the same as those in the embodiment shown in FIG. 3 , and will not be repeated here.
  • the data comparison module 303 can respond to the memory data output behavior of the device under test, obtain the corresponding data from the memory model according to the output address extracted from the bus, and can compare the output data extracted from the bus with the output data from the memory model. The obtained data are compared.
  • the device under test receives the memory data output command, that is, the memory data output behavior of the device under test is initiated on the bus, such as the device under test as the master device writes data to the external device or the device under test as the slave device is read data, then you can The output address and output data are extracted from the bus.
  • the data comparison module 303 can obtain corresponding data from the memory model according to the output address, and can compare the output data with the obtained data from the memory model. Data (expected value) for comparison.
  • a memory model can be constructed quickly and efficiently, and the mirror storage function of the memory model can be realized, so as to support effective memory verification, and further improve the verification effect of chip verification.
  • Artificial intelligence is a discipline that studies how to make computers simulate certain human thinking processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level technology and software-level technology.
  • Artificial intelligence hardware technology generally includes such Sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing and other technologies
  • artificial intelligence software technology mainly includes computer vision technology, speech recognition technology, natural language processing technology and machine learning/deep learning, big data processing technology, Several major directions such as knowledge graph technology.
  • the data in the embodiments of the present disclosure are not aimed at a specific user, and cannot reflect the personal information of a specific user.
  • the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.
  • FIG. 5 shows a schematic block diagram of an electronic device 500 that can be used to implement embodiments of the present disclosure.
  • Electronic device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, servers, blade servers, mainframes, and other suitable computers.
  • Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices.
  • the components shown herein, their connections and relationships, and their functions, are by way of example only, and are not intended to limit implementations of the disclosure described and/or claimed herein.
  • the device 500 includes a computing unit 501 that can execute according to a computer program stored in a read-only memory (ROM) 502 or loaded from a storage unit 508 into a random-access memory (RAM) 503. Various appropriate actions and treatments. In the RAM 503, various programs and data necessary for the operation of the device 500 can also be stored.
  • the computing unit 501, ROM 502, and RAM 503 are connected to each other through a bus 504.
  • An input/output (I/O) interface 505 is also connected to the bus 504 .
  • the I/O interface 505 includes: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, an optical disk, etc. ; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, and the like.
  • the communication unit 509 allows the device 500 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.
  • the computing unit 501 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 501 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc.
  • the computing unit 501 executes the various methods and processes described above, such as the methods described in this disclosure. For example, in some embodiments, the methods described in the present disclosure may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 508 .
  • part or all of the computer program may be loaded and/or installed on the device 500 via the ROM 502 and/or the communication unit 509.
  • a computer program When a computer program is loaded into RAM 503 and executed by computing unit 501, one or more steps of the methods described in this disclosure may be performed.
  • the computing unit 501 may be configured in any other appropriate way (for example, by means of firmware) to execute the methods described in the present disclosure.
  • Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips Implemented in a system of systems (SOC), complex programmable logic device (CPLD), computer hardware, firmware, software, and/or combinations thereof.
  • FPGAs field programmable gate arrays
  • ASICs application specific integrated circuits
  • ASSPs application specific standard products
  • SOC system of systems
  • CPLD complex programmable logic device
  • computer hardware firmware, software, and/or combinations thereof.
  • programmable processor can be special-purpose or general-purpose programmable processor, can receive data and instruction from storage system, at least one input device, and at least one output device, and transmit data and instruction to this storage system, this at least one input device, and this at least one output device an output device.
  • Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented.
  • the program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing.
  • machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • magnetic storage or any suitable combination of the foregoing.
  • the systems and techniques described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user. ); and a keyboard and pointing device (eg, a mouse or a trackball) through which a user can provide input to the computer.
  • a display device e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor
  • a keyboard and pointing device eg, a mouse or a trackball
  • Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and can be in any form (including Acoustic input, speech input or, tactile input) to receive input from the user.
  • the systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., as a a user computer having a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or including such backend components, middleware components, Or any combination of front-end components in a computing system.
  • the components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN) and the Internet.
  • a computer system may include clients and servers.
  • Clients and servers are generally remote from each other and typically interact through a communication network.
  • the relationship of client and server arises by computer programs running on the respective computers and having a client-server relationship to each other.
  • the server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.
  • steps may be reordered, added or deleted using the various forms of flow shown above.
  • each step described in the present disclosure may be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in the present disclosure can be achieved, no limitation is imposed herein.

Abstract

本公开提供了存储器模型的镜像存储实现方法、装置及存储介质，涉及人工智能芯片以及智能语音等人工智能领域，其中的方法可包括：响应于被测设备中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的；根据所述更新行为信息对存储器模型中存储的数据进行对应更新。应用本公开所述方案，可实现有效的存储器验证等。

Description

存储器模型的镜像存储实现方法、装置及存储介质
本申请要求了申请日为2022年03月01日，申请号为202210195444.X发明名称为“存储器模型的镜像存储实现方法、装置及存储介质”的中国专利申请的优先权。
技术领域
本公开涉及人工智能技术领域，特别涉及人工智能芯片以及智能语音等领域的存储器模型的镜像存储实现方法、装置及存储介质。
背景技术
目前的芯片验证通常基于通用验证方法学(UVM，Universal Verification Methodology)验证平台实现，所述芯片可为智能语音芯片等。但目前的UVM验证平台的功能还有待完善。
发明内容
本公开提供了存储器模型的镜像存储实现方法、装置及存储介质。
一种存储器模型的镜像存储实现方法，包括：
响应于被测设备中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的；
根据所述更新行为信息对存储器模型中存储的数据进行对应更新。
一种存储器模型的镜像存储实现装置，包括：信息获取模块以及数据更新模块；
所述信息获取模块，用于响应于被测设备中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的；
所述数据更新模块，用于根据所述更新行为信息对存储器模型中存储的数据进行对应更新。
一种电子设备，包括：
至少一个处理器；以及
与所述至少一个处理器通信连接的存储器；其中，
所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如以上所述的方法。
一种存储有计算机指令的非瞬时计算机可读存储介质，所述计算机指令用于使计算机执行如以上所述的方法。
一种计算机程序产品，包括计算机程序/指令，所述计算机程序/指令被处理器执行时实现如以上所述的方法。
上述公开中的一个实施例具有如下优点或有益效果：可通过总线获取被测设备中的存储器发生的数据更新行为对应的更新行为信息，并可根据获取到的信息对应更新存储器模型，从而实现了存储器模型的镜像存储功能，进而可基于存储的数据有效地实现芯片验证中的存储器验证，并相应地提升了芯片验证的验证效果等。
应当理解，本部分所描述的内容并非旨在标识本公开的实施例的关键或重要特征，也不用于限制本公开的范围。本公开的其它特征将通过以下的说明书而变得容易理解。
附图说明
附图用于更好地理解本方案，不构成对本公开的限定。其中：
图1为本公开所述存储器模型的镜像存储实现方法实施例的流程图；
图2为本公开所述方法对应的验证环境架构示意图；
图3为本公开所述存储器模型的镜像存储实现装置第一实施例300的组成结构示意图；
图4为本公开所述存储器模型的镜像存储实现装置第二实施例400的组成结构示意图；
图5示出了可以用来实施本公开的实施例的电子设备500的示意性框图。
具体实施方式
以下结合附图对本公开的示范性实施例做出说明，其中包括本公开实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此， 本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变和修改，而不会背离本公开的范围和精神。同样，为了清楚和简明，以下的描述中省略了对公知功能和结构的描述。
另外，应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
图1为本公开所述存储器模型的镜像存储实现方法实施例的流程图。如图1所示，包括以下具体实现方式。
在步骤101中，响应于被测设备(DUT，Device Under Test)中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的。
在步骤102中，根据所述更新行为信息对存储器模型(mem_model)中存储的数据进行对应更新。
目前的UVM验证平台仅支持寄存器模型的镜像存储功能，不支持存储器模型的镜像存储功能，从而影响了验证效果。
采用上述方法实施例所述方案，可通过总线获取被测设备中的存储器发生的数据更新行为对应的更新行为信息，并可根据获取到的信息对应更新存储器模型，从而实现了存储器模型的镜像存储功能，进而可基于存储的数据有效地实现芯片验证中的存储器验证，并相应地提升了芯片验证的验证效果等。
本公开的一个实施例中，存储器模型可包括：由寄存器组构成的存储器模型，另外，寄存器组中的寄存器个数可等于被测设备中的存储器的深度，和/或，寄存器的位数可等于被测设备中的存储器的位宽。
通过上述方式，可快速高效的构建出存储器模型，从而为后续处理奠定了良好的基础。
另外，还可将上述存储器模型实例化，如可在计分板(scoreboard)中实例化存储器模型，以便实际应用。
当被测设备中的存储器发生数据更新行为时，可获取本次更新的更新行为信息，并可根据所述更新行为信息对存储器模型中存储的数据进行对应更新。
被测设备中的存储器发生的数据更新行为主要包括两种情况，以下分别进行介绍。
1)情况一
这种情况下，所述数据更新行为可包括：外部总线输入更新，即总线上发生对被测设备中的存储器的数据更新行为，如被测设备作为主设备(master)读数据或被测设备作为从设备(slave)被写数据。
相应地，所述更新行为信息可包括：更新地址及数据。即可获取本次更新的更新地址及数据，更新地址及数据可从总线上提取得到。
进一步地，可根据所述更新行为信息对存储器模型中存储的数据进行对应更新，即可将存储器模型中所述更新地址对应的数据更新为所述更新行为信息中的数据。
通过上述方式，可实现存储器模型与被测设备中的存储器中的数据的同步更新，另外，所述总线可支持高级外围总线(APB，Advanced Peripheral Bus)、高级高性能总线(AHB，Advanced High Performance Bus)以及高级可扩展接口(AXI，Advanced eXtensible Interface)等各种接口(interface)协议类型，具有广泛适用性。
2)情况二
这种情况下，所述数据更新行为可包括：被测设备内部处理后更新，如可从总线上对被测设备发起计算指令，相应地，被测设备会获取计算指令对应的源数据，并执行计算指令对应的计算，得到计算结果，进而将计算结果存放到存储器的目的地址区域。
由于数据(计算结果)是被测设备内部进行逻辑处理后更新到被测设备内部的存储器中的，因此总线上无法提取到该数据，但是可以从总线上提取到发送给被测设备的计算指令。相应地，获取到的更新行为信息可包括：计算指令。
进一步地，可根据所述更新行为信息对存储器模型中存储的数据进行对应更新，即可获取计算指令对应的源数据，并可获取根据源数据生成的计算结果，进而可将计算结果更新到存储器模型中。
本公开的一个实施例中，可将源数据发送给仿真模型(cmodel)，并可获取仿真模型根据所述源数据执行计算指令对应的计算后得到的所述计算结果。
仿真模型为被测设备的仿真模型，可认为仿真模型的计算结果为理想的、准确的计算结果。相应地，可将仿真模型的计算结果称为期望值。
在实际应用中，可从存储器模型中获取计算指令对应的源数据，并可将获取到的期望值更新到存储器模型中的目的地址区域。
通过上述方式，可实现存储器的期望值镜像，以便进行后续的数据比对等。
具体地，本公开的一个实施例中，响应于被测设备发生存储器数据输出行为，可根据从总线上提取的输出地址，从存储器模型中获取对应的数据，并可将从总线上提取的输出数据与从存储器模型中获取的数据进行比对。
若被测设备接收到存储器数据输出指令，即总线上发起对被测设备的存储器数据输出行为，如被测设备作为主设备向外部设备写数据或被测设备作为从设备被读数据，那么可从总线上提取出输出地址和输出数据，相应地，可根据所述输出地址，从存储器模型中获取对应的数据，并可将所述输出数据与从存储器模型中获取到的数据(期望值)进行比对。
通过上述方式，可有效验证存储器中存储的数据与期望值是否一致，从而实现有效的存储器验证，即实现芯片逻辑功能验证。
基于上述介绍，图2为本公开所述方法对应的验证环境架构示意图。如图2所示，其中可包括计分板、指令代理(cmd_agent)和数据传输代理(data transfer agent)等组成部分，指令代理中可进一步包括序列(seqr)、驱动器(driver)和监视器(monitor)等组成部分，数据传输代理中可进一步包括驱动器和监视器等组成部分，计分板中可进一步包括存储器模型和仿真模型等组成部分。本公开所述方法的执行主体可为计分板。
存储器模型可为由寄存器组构成的存储器模型，寄存器组中的寄存器个数可等于被测设备中的存储器的深度，寄存器的位数可等于被测设备中的存储器的位宽。
基于本公开所述方法，可实现单条指令功能验证。其中，源数据可通过总线搬移到被测设备的存储器中。
另外，如图2所示，可利用监视器来进行总线行为识别以及从总线 上提取信息，各监视器的具体工作方式为现有技术。
其中，若识别到被测设备中的存储器发生外部总线输入更新的数据更新行为，那么针对从总线上提取出的更新地址及数据等更新行为信息，计分板可根据更新行为信息对存储器模型中的数据进行对应更新，即可将存储器模型中所述更新地址对应的数据更新为更新行为信息中的数据。
若识别到被测设备中的存储器发生被测设备内部处理后更新的数据更新行为，那么针对从总线上提取出的计算指令等更新行为信息，计分板可根据更新行为信息对存储器模型中的数据进行对应更新，即可获取计算指令对应的源数据，并可获取根据所述源数据生成的计算结果，进而可将所述计算结果更新到存储器模型中。
具体地，计分板可从存储器模型中获取源数据，并可将源数据发送给仿真模型，进而可获取仿真模型根据源数据执行计算指令对应的计算后得到的计算结果，即期望值，并更新到存储器模型中。
若识别到被测设备发生存储器数据输出行为，那么针对从总线上提取出的输出地址和输出数据，计分板可根据所述输出地址，从存储器模型中获取对应的数据，并可将所述输出数据与从存储器模型中获取到的数据进行比对，从而完成所需的数据比对。
在实际应用中，还可将各单条指令功能验证用例进行灵活拼接组合，以实现多指令连续功能验证等。
需要说明的是，对于前述的方法实施例，为了简单描述，将其表述为一系列的动作组合，但是本领域技术人员应该知悉，本公开并不受所描述的动作顺序的限制，因为依据本公开，某些步骤可以采用其它顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本公开所必须的。
总之，采用本公开所述方法，可快速高效的构建出存储器模型，并可实现存储器模型的镜像存储功能，从而可支持进行有效的存储器验证，进而提升了芯片验证的验证效果等。
以上是关于方法实施例的介绍，以下通过装置实施例，对本公开所述方案进行进一步说明。
图3为本公开所述存储器模型的镜像存储实现装置第一实施例300的组成结构示意图。如图3所示，可包括：信息获取模块301以及数据更新模块302。
信息获取模块301，用于响应于被测设备中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的。
数据更新模块302，用于根据所述更新行为信息对存储器模型中存储的数据进行对应更新。
采用上述装置实施例所述方案，可通过总线获取被测设备中的存储器发生的数据更新行为对应的更新行为信息，并可根据获取到的信息对应更新存储器模型，从而实现了存储器模型的镜像存储功能，进而可基于存储的数据有效地实现芯片验证中的存储器验证，并相应地提升了芯片验证的验证效果等。
本公开的一个实施例中，存储器模型可包括：由寄存器组构成的存储器模型，另外，寄存器组中的寄存器个数可等于被测设备中的存储器的深度，和/或，寄存器的位数可等于被测设备中的存储器的位宽。
另外，还可将上述存储器模型实例化，如可在计分板中实例化存储器模型，以便实际应用。
被测设备中的存储器发生的数据更新行为主要包括两种情况，以下分别进行介绍。
1)情况一
这种情况下，所述数据更新行为可包括：外部总线输入更新，即总线上发生对被测设备中的存储器的数据更新行为，如被测设备作为主设备读数据或被测设备作为从设备被写数据。
相应地，所述更新行为信息可包括：更新地址及数据。即可获取本次更新的更新地址及数据，更新地址及数据可从总线上提取得到。
进一步地，数据更新模块302可根据所述更新行为信息对存储器模型中存储的数据进行对应更新，即可将存储器模型中所述更新地址对应的数据更新为所述更新行为信息中的数据。
2)情况二
这种情况下，所述数据更新行为可包括：被测设备内部处理后更新， 如可从总线上对被测设备发起计算指令，相应地，被测设备会获取计算指令对应的源数据，并执行计算指令对应的计算，得到计算结果，进而将计算结果存放到存储器的目的地址区域。
由于数据(计算结果)是被测设备内部进行逻辑处理后更新到被测设备内部的存储器中的，因此总线上无法提取到该数据，但是可以从总线上提取到发送给被测设备的计算指令。相应地，获取到的更新行为信息可包括：计算指令。
进一步地，数据更新模块302可根据所述更新行为信息对存储器模型中存储的数据进行对应更新，即可获取计算指令对应的源数据，并可获取根据所述源数据生成的计算结果，进而可将计算结果更新到存储器模型中。
本公开的一个实施例中，数据更新模块302可将源数据发送给仿真模型，并可获取所述仿真模型根据源数据执行计算指令对应的计算后得到的所述计算结果。
仿真模型为被测设备的仿真模型，可认为仿真模型的计算结果为理想的、准确的计算结果。相应地，可将仿真模型的计算结果称为期望值。
在实际应用中，数据更新模块302可从存储器模型中获取计算指令对应的源数据，并可将获取到的期望值更新到存储器模型中的目的地址区域。
图4为本公开所述存储器模型的镜像存储实现装置第二实施例400的组成结构示意图。如图4所示，可包括：信息获取模块301、数据更新模块302以及数据比对模块303。
其中，信息获取模块301和数据更新模块302的功能与图3所示实施例中相同，不再赘述。
数据比对模块303可响应于被测设备发生存储器数据输出行为，根据从总线上提取的输出地址，从存储器模型中获取对应的数据，并可将从总线上提取的输出数据与从存储器模型中获取的数据进行比对。
若被测设备接收到存储器数据输出指令，即总线上发起对被测设备的存储器数据输出行为，如被测设备作为主设备向外部设备写数据或被测设备作为从设备被读数据，那么可从总线上提取出输出地址和输出数据，相应地，数据比对模块303可根据所述输出地址，从存储器模型中 获取对应的数据，并可将所述输出数据与从存储器模型中获取到的数据(期望值)进行比对。
图3和图4所示装置实施例的具体工作流程可参照前述方法实施例中的相关说明。
总之，采用本公开所述装置，可快速高效的构建出存储器模型，并可实现存储器模型的镜像存储功能，从而可支持进行有效的存储器验证，进而提升了芯片验证的验证效果等。
本公开所述方案可应用于人工智能领域，特别涉及人工智能芯片以及智能语音等领域。人工智能是研究使计算机来模拟人的某些思维过程和智能行为(如学习、推理、思考、规划等)的学科，既有硬件层面的技术也有软件层面的技术，人工智能硬件技术一般包括如传感器、专用人工智能芯片、云计算、分布式存储、大数据处理等技术，人工智能软件技术主要包括计算机视觉技术、语音识别技术、自然语言处理技术以及机器学习/深度学习、大数据处理技术、知识图谱技术等几大方向。
本公开所述实施例中的数据并不是针对某一特定用户的，并不能反映出某一特定用户的个人信息。
本公开的技术方案中，所涉及的用户个人信息的收集、存储、使用、加工、传输、提供和公开等处理，均符合相关法律法规的规定，且不违背公序良俗。
根据本公开的实施例，本公开还提供了一种电子设备、一种可读存储介质和一种计算机程序产品。
图5示出了可以用来实施本公开的实施例的电子设备500的示意性框图。电子设备旨在表示各种形式的数字计算机，诸如，膝上型计算机、台式计算机、工作台、服务器、刀片式服务器、大型计算机、和其它适合的计算机。电子设备还可以表示各种形式的移动装置，诸如，个人数字助理、蜂窝电话、智能电话、可穿戴设备和其它类似的计算装置。本文所示的部件、它们的连接和关系、以及它们的功能仅仅作为示例，并且不意在限制本文中描述的和/或者要求的本公开的实现。
如图5所示，设备500包括计算单元501，其可以根据存储在只读存储器(ROM)502中的计算机程序或者从存储单元508加载到随机访问存储器(RAM)503中的计算机程序，来执行各种适当的动作和处理。 在RAM 503中，还可存储设备500操作所需的各种程序和数据。计算单元501、ROM 502以及RAM 503通过总线504彼此相连。输入/输出(I/O)接口505也连接至总线504。
设备500中的多个部件连接至I/O接口505，包括：输入单元506，例如键盘、鼠标等；输出单元507，例如各种类型的显示器、扬声器等；存储单元508，例如磁盘、光盘等；以及通信单元509，例如网卡、调制解调器、无线通信收发机等。通信单元509允许设备500通过诸如因特网的计算机网络和/或各种电信网络与其他设备交换信息/数据。
计算单元501可以是各种具有处理和计算能力的通用和/或专用处理组件。计算单元501的一些示例包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、各种专用的人工智能(AI)计算芯片、各种运行机器学习模型算法的计算单元、数字信号处理器(DSP)、以及任何适当的处理器、控制器、微控制器等。计算单元501执行上文所描述的各个方法和处理，例如本公开所述的方法。例如，在一些实施例中，本公开所述的方法可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元508。在一些实施例中，计算机程序的部分或者全部可以经由ROM 502和/或通信单元509而被载入和/或安装到设备500上。当计算机程序加载到RAM 503并由计算单元501执行时，可以执行本公开所述的方法的一个或多个步骤。备选地，在其他实施例中，计算单元501可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行本公开所述的方法。
本文中以上描述的系统和技术的各种实施方式可以在数字电子电路系统、集成电路系统、场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准产品(ASSP)、芯片上系统的系统(SOC)、复杂可编程逻辑设备(CPLD)、计算机硬件、固件、软件、和/或它们的组合中实现。这些各种实施方式可以包括：实施在一个或者多个计算机程序中，该一个或者多个计算机程序可在包括至少一个可编程处理器的可编程系统上执行和/或解释，该可编程处理器可以是专用或者通用可编程处理器，可以从存储系统、至少一个输入装置、和至少一个输出装置接收数据和指令，并且将数据和指令传输至该存储系统、该至少一个输入装置、和该至少一个输出装置。
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
为了提供与用户的交互，可以在计算机上实施此处描述的系统和技术，该计算机具有：用于向用户显示信息的显示装置(例如，CRT(阴极射线管)或者LCD(液晶显示器)监视器)；以及键盘和指向装置(例如，鼠标或者轨迹球)，用户可以通过该键盘和该指向装置来将输入提供给计算机。其它种类的装置还可以用于提供与用户的交互；例如，提供给用户的反馈可以是任何形式的传感反馈(例如，视觉反馈、听觉反馈、或者触觉反馈)；并且可以用任何形式(包括声输入、语音输入或者、触觉输入)来接收来自用户的输入。
可以将此处描述的系统和技术实施在包括后台部件的计算系统(例如，作为数据服务器)、或者包括中间件部件的计算系统(例如，应用服务器)、或者包括前端部件的计算系统(例如，具有图形用户界面或者网络浏览器的用户计算机，用户可以通过该图形用户界面或者该网络浏览器来与此处描述的系统和技术的实施方式交互)、或者包括这种后台部件、中间件部件、或者前端部件的任何组合的计算系统中。可以通 过任何形式或者介质的数字数据通信(例如，通信网络)来将系统的部件相互连接。通信网络的示例包括：局域网(LAN)、广域网(WAN)和互联网。
计算机系统可以包括客户端和服务器。客户端和服务器一般远离彼此并且通常通过通信网络进行交互。通过在相应的计算机上运行并且彼此具有客户端-服务器关系的计算机程序来产生客户端和服务器的关系。服务器可以是云服务器，也可以为分布式系统的服务器，或者是结合了区块链的服务器。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本发公开中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本公开公开的技术方案所期望的结果，本文在此不进行限制。
上述具体实施方式，并不构成对本公开保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本公开的精神和原则之内所作的修改、等同替换和改进等，均应包含在本公开保护范围之内。

Claims (15)

  1. 一种存储器模型的镜像存储实现方法，包括：
    响应于被测设备中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的；
    根据所述更新行为信息对存储器模型中存储的数据进行对应更新。
  2. 根据权利要求1所述的方法，其中，
    所述存储器模型包括：由寄存器组构成的存储器模型；
    所述寄存器组中的寄存器个数等于所述存储器的深度，和/或，所述寄存器的位数等于所述存储器的位宽。
  3. 根据权利要求1所述的方法，其中，
    所述数据更新行为包括：外部总线输入更新；
    所述更新行为信息包括：更新地址及数据；
    所述根据所述更新行为信息对存储器模型中存储的数据进行对应更新包括：将所述存储器模型中所述更新地址对应的数据更新为所述更新行为信息中的数据。
  4. 根据权利要求1所述的方法，其中，
    所述数据更新行为包括：所述被测设备内部处理后更新；
    所述更新行为信息包括：计算指令；
    所述根据所述更新行为信息对存储器模型中存储的数据进行对应更新包括：获取所述计算指令对应的源数据，获取根据所述源数据生成的计算结果，将所述计算结果更新到所述存储器模型中。
  5. 根据权利要求4所述的方法，其中，所述获取根据所述源数据生成的计算结果包括：
    将所述源数据发送给仿真模型；
    获取所述仿真模型根据所述源数据执行所述计算指令对应的计算后得到的所述计算结果。
  6. 根据权利要求1～5中任一项所述的方法，还包括：
    响应于所述被测设备发生存储器数据输出行为，根据从总线上提取的输出地址，从所述存储器模型中获取对应的数据，并将从总线上提取的输出数据与从所述存储器模型中获取的数据进行比对。
  7. 一种存储器模型的镜像存储实现装置，包括：信息获取模块以及数据更新模块；
    所述信息获取模块，用于响应于被测设备中的存储器发生数据更新行为，获取本次更新的更新行为信息，所述更新行为信息为从总线上提取的；
    所述数据更新模块，用于根据所述更新行为信息对存储器模型中存储的数据进行对应更新。
  8. 根据权利要求7所述的装置，其中，
    所述存储器模型包括：由寄存器组构成的存储器模型；
    所述寄存器组中的寄存器个数等于所述存储器的深度，和/或，所述寄存器的位数等于所述存储器的位宽。
  9. 根据权利要求7所述的装置，其中，
    所述数据更新行为包括：外部总线输入更新；
    所述更新行为信息包括：更新地址及数据；
    所述数据更新模块将所述存储器模型中所述更新地址对应的数据更新为所述更新行为信息中的数据。
  10. 根据权利要求7所述的装置，其中，
    所述数据更新行为包括：所述被测设备内部处理后更新；
    所述更新行为信息包括：计算指令；
    所述数据更新模块获取所述计算指令对应的源数据，并获取根据所述源数据生成的计算结果，将所述计算结果更新到所述存储器模型中。
  11. 根据权利要求10所述的装置，其中，
    所述数据更新模块将所述源数据发送给仿真模型，并获取所述仿真模型根据所述源数据执行所述计算指令对应的计算后得到的所述计算结果。
  12. 根据权利要求7～11中任一项所述的装置，还包括：
    数据比对模块，用于响应于所述被测设备发生存储器数据输出行为，根据从总线上提取的输出地址，从所述存储器模型中获取对应的数据，并将从总线上提取的输出数据与从所述存储器模型中获取的数据进行比对。
  13. 一种电子设备，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行权利要求1-6中任一项所述的方法。
  14. 一种存储有计算机指令的非瞬时计算机可读存储介质，其中，所述计算机指令用于使计算机执行权利要求1-6中任一项所述的方法。
  15. 一种计算机程序产品，包括计算机程序/指令，所述计算机程序/指令被处理器执行时实现权利要求1-6中任一项所述的方法。
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