WO2023162194A1 - パターンの検査方法、レジストパターンの製造方法、半導体パッケージ基板の選別方法、及び半導体パッケージ基板の製造方法 - Google Patents

パターンの検査方法、レジストパターンの製造方法、半導体パッケージ基板の選別方法、及び半導体パッケージ基板の製造方法 Download PDF

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Publication number
WO2023162194A1
WO2023162194A1 PCT/JP2022/008187 JP2022008187W WO2023162194A1 WO 2023162194 A1 WO2023162194 A1 WO 2023162194A1 JP 2022008187 W JP2022008187 W JP 2022008187W WO 2023162194 A1 WO2023162194 A1 WO 2023162194A1
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WIPO (PCT)
Prior art keywords
pattern
semiconductor package
resist pattern
package substrate
inspection
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Ceased
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PCT/JP2022/008187
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English (en)
French (fr)
Japanese (ja)
Inventor
哲也 加藤
謙介 吉原
陽介 賀口
夏木 戸田
壮和 粂
博史 小野
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Resonac Corp
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Resonac Corp
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Priority to PCT/JP2022/008187 priority Critical patent/WO2023162194A1/ja
Priority to US18/841,160 priority patent/US20250191978A1/en
Priority to PCT/JP2023/006062 priority patent/WO2023162934A1/ja
Priority to CN202380023625.7A priority patent/CN119096337A/zh
Priority to KR1020247028610A priority patent/KR20240141296A/ko
Priority to JP2024503141A priority patent/JP7758148B2/ja
Priority to TW112106238A priority patent/TW202349528A/zh
Publication of WO2023162194A1 publication Critical patent/WO2023162194A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/62—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
    • G01N21/63—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
    • G01N21/64—Fluorescence; Phosphorescence
    • G01N21/6489—Photoluminescence of semiconductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • G01N21/95607—Inspecting patterns on the surface of objects using a comparative method
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/62—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
    • G01N21/63—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
    • G01N21/64—Fluorescence; Phosphorescence
    • G01N21/645—Specially adapted constructive features of fluorimeters
    • G01N21/6456—Spatial resolved fluorescence measurements; Imaging
    • G01N2021/646—Detecting fluorescent inhomogeneities at a position, e.g. for detecting defects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • G01N21/95607—Inspecting patterns on the surface of objects using a comparative method
    • G01N2021/95615—Inspecting patterns on the surface of objects using a comparative method with stored comparision signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • G01N2021/95638—Inspecting patterns on the surface of objects for PCB's

Definitions

  • the present disclosure relates to a method for inspecting a resist pattern formed on a semiconductor package substrate for mounting a semiconductor element, a method for manufacturing a resist pattern formed on a semiconductor package substrate for mounting a semiconductor element, and a semiconductor package substrate for mounting a semiconductor element. and a method of manufacturing a semiconductor package for mounting a semiconductor element.
  • a resist pattern is formed on the semiconductor package substrate (see Patent Document 1, for example). Thereafter, the semiconductor package substrate is etched or plated to form a conductor pattern on the semiconductor package substrate.
  • resist patterns have some degree of roughness.
  • the roughness of the resist pattern means, for example, that the outline of the resist pattern becomes rough or the line width of the resist pattern varies.
  • the roughness of the resist pattern becomes the roughness of the conductor pattern. For this reason, when the resist pattern is miniaturized, there is a possibility of causing defects such as defective formation of the formed conductor pattern and deterioration of the electrical characteristics of the manufactured semiconductor package.
  • the resist pattern formed on the semiconductor package substrate can be inspected before forming the conductor pattern on the semiconductor package substrate, such defects as described above can be found at an earlier stage in the manufacture of the semiconductor package. . Further, if the conductor pattern can be inspected even after the conductor pattern is formed on the semiconductor package substrate, the defects as described above can be found. Furthermore, by evaluating the yield of resist pattern formation or conductor pattern formation on a semiconductor package substrate, it is possible to improve resist pattern formation and conductor pattern formation on a semiconductor package substrate.
  • the present disclosure provides a pattern inspection method capable of evaluating a pattern even if one of a resist pattern and a conductor pattern formed on a semiconductor package substrate is miniaturized, a resist pattern manufacturing method, It is an object of the present invention to provide a method for sorting semiconductor package substrates and a method for manufacturing semiconductor package substrates.
  • the pattern inspection method of the present disclosure includes a coordinate measurement step of measuring the coordinates of the contour of the pattern in a semiconductor package substrate for mounting a semiconductor device on which a pattern that is either a resist pattern or a conductor pattern is formed; an inspection step for inspecting the pattern based on
  • the coordinates of the contour of the pattern in a semiconductor package substrate for mounting a semiconductor element on which either a resist pattern or a conductor pattern is formed are measured, and the pattern is inspected based on the measured coordinates. inspect. Therefore, even if the pattern formed on the semiconductor package substrate is miniaturized, the pattern can be evaluated. Moreover, the pattern can be evaluated with higher accuracy than when visually inspected.
  • the roughness of the pattern may be calculated based on the measured coordinates.
  • the formation state of the pattern can be appropriately evaluated.
  • variations in the contour of the pattern may be calculated based on the measured coordinates.
  • variations in the contour of the pattern are calculated based on the measured coordinates of the contour, so that the formation state of the pattern can be appropriately evaluated.
  • the line width of the pattern and variations in the line width may be calculated based on the measured coordinates.
  • the line width of the pattern and variations in the line width are calculated based on the coordinates of the measured contour, so that the formation state of the pattern can be appropriately evaluated.
  • the measured coordinates may be compared with the pattern for forming the pattern.
  • the pattern inspection method since the measured contour coordinates are compared with the pattern data for forming the pattern, the pattern formation state can be evaluated with high accuracy.
  • the semiconductor package substrate may have polyethylene terephthalate.
  • the resist pattern can be evaluated.
  • the coordinates of the contour of the pattern may be measured based on reflected light from the semiconductor package substrate, fluorescence from the semiconductor package substrate, or electron beam from the semiconductor package substrate.
  • the coordinates of the contour of the pattern are measured based on the reflected light from the semiconductor package substrate, the fluorescence from the semiconductor package substrate, or the electron beam from the semiconductor package substrate. The coordinates of the contour can be properly measured.
  • the resist pattern manufacturing method of the present disclosure includes a resist pattern forming step of forming a resist pattern on a semiconductor package substrate for mounting a semiconductor element, and after the resist pattern forming step, measuring the coordinates of the outline of the resist pattern on the semiconductor package substrate. and an inspection step of inspecting the resist pattern based on the coordinates.
  • this resist pattern manufacturing method after forming a resist pattern on a semiconductor package substrate for mounting a semiconductor element, the coordinates of the outline of the resist pattern on the semiconductor package substrate are measured, and the resist pattern is inspected based on the measured coordinates. do. Accordingly, even if the resist pattern formed on the semiconductor package substrate is miniaturized, the resist pattern can be evaluated, so that a resist pattern with a small degree of roughness can be manufactured.
  • the coordinates of the outline of the resist pattern may be measured based on reflected light from the semiconductor package substrate, fluorescence from the semiconductor package substrate, or electron beam from the semiconductor package substrate.
  • the coordinates of the outline of the resist pattern are measured based on the reflected light from the semiconductor package substrate, the fluorescence from the semiconductor package substrate, or the electron beam from the semiconductor package substrate. The coordinates of the contours of the pattern can be properly measured.
  • a semiconductor package substrate sorting method of the present disclosure includes a coordinate measurement step of measuring the coordinates of the contour of a pattern in a semiconductor package substrate for mounting a semiconductor element on which a pattern that is either a resist pattern or a conductor pattern is formed; an inspection process for inspecting the pattern based on the coordinates obtained; and an evaluation process for evaluating the pattern based on the inspection result of the inspection process.
  • the coordinates of the contour of the pattern of a semiconductor package substrate for mounting a semiconductor element on which either a resist pattern or a conductor pattern is formed are measured, and based on the measured coordinates, A pattern is inspected and the pattern is evaluated based on the results of this inspection. Therefore, the pattern can be evaluated with higher accuracy than when visually inspected.
  • the pattern may be inspected by calculating the roughness of the pattern based on the measured coordinates, and in the evaluation process, the pattern may be evaluated based on the roughness of the pattern.
  • the formation state of the pattern can be appropriately evaluated.
  • the pattern may be inspected by calculating variations in the contour based on the measured coordinates, and in the evaluation process, the pattern may be evaluated based on the variations in the contour.
  • the formation state of the pattern can be evaluated appropriately.
  • the pattern line width and line width variation may be calculated based on the measured coordinates as the pattern inspection, and in the evaluation process, the pattern may be evaluated based on the line width variation.
  • the pattern formation state can be appropriately evaluated.
  • the measured coordinates and the pattern data for forming the pattern may be compared to inspect the pattern, and in the evaluation process, the pattern may be evaluated based on the results of the comparison between the measured coordinates and the pattern data.
  • the pattern is evaluated based on the result of comparison between the measured contour coordinates and the pattern data for forming the pattern, so the formation state of the pattern can be appropriately evaluated.
  • the coordinates of the contour of the pattern may be measured based on reflected light from the semiconductor package substrate, fluorescence from the semiconductor package substrate, or electron beam from the semiconductor package substrate.
  • the coordinates of the contour of the pattern are measured based on reflected light from the semiconductor package substrate, fluorescence from the semiconductor package substrate, or electron beam from the semiconductor package substrate. The coordinates of the contours of the pattern can be properly measured.
  • a semiconductor package substrate on which a resist pattern is formed and whose evaluation of the resist pattern in the method for selecting semiconductor package substrates described above satisfies the criteria is etched or plated to form a conductor pattern.
  • a conductive pattern forming step is provided.
  • the pattern can be evaluated.
  • FIG. 1(a) is a schematic perspective view for explaining a photosensitive layer forming step in the resist pattern forming step
  • FIG. 1(b) is a schematic perspective view for explaining an exposure step in the resist pattern forming step
  • FIG. 1(c) is a schematic perspective view for explaining the developing step in the resist pattern forming step
  • FIG. 2 is a schematic perspective view for explaining the coordinate measuring process.
  • FIG. 3 is a schematic plan view enlarging a part of the resist pattern and the conductor pattern formed on the semiconductor package substrate.
  • 4(a), 4(b) and 4(c) are schematic perspective views for explaining the formation of the conductor pattern.
  • 5 is a photograph of Example 1.
  • FIG. 6 is a plot diagram of the coordinates of the outline of the resist pattern of Example 1.
  • FIG. FIG. 7 is a diagram in which the plot diagram of FIG. 6 is shifted and superimposed on the photograph of FIG. 4 is a table showing evaluations of Examples 1 and 2.
  • FIG. 1(a) is a schematic
  • a or B may include either one of A and B, or may include both.
  • a pattern inspection method is an inspection method for inspecting a pattern that is either a resist pattern or a conductor pattern.
  • This pattern inspection method includes a resist pattern inspection method for inspecting a resist pattern and a conductor pattern inspection method for inspecting a conductor pattern.
  • the resist pattern inspection method includes a coordinate measurement step of measuring the coordinates of the outline of the resist pattern on a semiconductor package substrate for mounting a semiconductor device on which the resist pattern is formed, and inspecting the resist pattern based on the coordinates measured in the coordinate measurement step. and an inspection step.
  • the resist pattern inspection method may include a resist pattern forming step of forming a resist pattern on the semiconductor package substrate before the coordinate measuring step. Also, the resist pattern inspection method may include other steps.
  • the term "process” includes not only an independent process, but also when the intended action of the process is achieved even if it cannot be clearly distinguished from other processes. .
  • a resist pattern can be said to be a pattern of a photocured product of a photosensitive resin composition, or a relief pattern.
  • the resist pattern forming process includes a photosensitive layer forming process (see FIG. 1(a)) for laminating a photosensitive layer 2 on a semiconductor package substrate 1, and irradiation of a predetermined portion of the photosensitive layer 2 with actinic rays. an exposure step (see FIG. 1(b)) for forming a photocured portion, and a developing step (see FIG. 1(c)) for removing a region other than a predetermined portion of the photosensitive layer 2 from the semiconductor package substrate 1; have The resist pattern forming step may include other steps as required.
  • the semiconductor package substrate 1 includes, for example, an insulating layer 1a and a conductor layer 1b formed on the insulating layer 1a.
  • the insulating layer 1a is, for example, a buildup material or polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • the conductor layer 1b is, for example, copper formed on the insulating layer 1a by electroless plating or sputtering.
  • the photosensitive layer 2 is formed on the conductor layer 1 b of the semiconductor package substrate 1 .
  • the thickness of the semiconductor package substrate 1 may be, for example, 50 ⁇ m or more, 100 ⁇ m or more, or 300 ⁇ m or more. Also, the thickness of the semiconductor package substrate 1 may be, for example, 3000 ⁇ m or less, 2000 ⁇ m or less, or 1500 ⁇ m or less. These minimum and maximum thicknesses of the semiconductor package substrate 1 can be combined as appropriate. For example, the thickness of the semiconductor package substrate 1 may be 50 ⁇ m to 3000 ⁇ m, 100 ⁇ m to 2000 ⁇ m, or 300 ⁇ m to 1500 ⁇ m. The thickness of the semiconductor package substrate 1 is the dimension of the semiconductor package substrate 1 in the direction perpendicular to the main surface of the semiconductor package substrate 1 .
  • the photosensitive layer 2 is a layer formed using a photosensitive resin composition whose properties change (for example, photo-curing) when exposed to light.
  • the photosensitive resin composition forming the photosensitive layer 2 contains, for example, a binder polymer, a photopolymerizable compound, and a photopolymerization initiator.
  • the photosensitive resin composition forming the photosensitive layer 2 may contain a photosensitizer, a polymerization inhibitor, or other components, if necessary.
  • the photosensitive resin composition forming the photosensitive layer 2 includes, for example, dyes such as malachite green, victoria pure blue, brilliant green and methyl violet, tribromophenyl sulfone, leuco crystal violet, diphenylamine, benzylamine, triphenylamine, diethyl Photocoloring agents such as aniline and o-chloroaniline, thermal coloring inhibitors, plasticizers such as p-toluenesulfonamide, pigments, fillers, antifoaming agents, flame retardants, adhesion imparting agents, leveling agents, release accelerators , antioxidants, fragrances, imaging agents, and thermal cross-linking agents.
  • dyes such as malachite green, victoria pure blue, brilliant green and methyl violet
  • tribromophenyl sulfone leuco crystal violet
  • diphenylamine benzylamine
  • triphenylamine diethyl
  • Photocoloring agents such as aniline and o
  • a polymer film (support film) having heat resistance and solvent resistance such as polyester such as polyethylene terephthalate (PET), polyolefin such as polypropylene and polyethylene may be used.
  • the support 3 may be a barrier layer having gas barrier properties such as polyvinyl alcohol (PVA).
  • a photosensitive element comprises, for example, a support, a photosensitive layer, and a protective layer in this order. Then, after removing the protective layer, the photosensitive layer of the photosensitive element is pressed onto the semiconductor package substrate 1 while being heated, whereby the photosensitive layer 2 and the support 3 are formed on the semiconductor package substrate 1 . As a result, a laminate 4 having the semiconductor package substrate 1, the photosensitive layer 2, the support 3, and the support film (not shown) in this order is obtained. An intermediate layer or the like may be arranged between the support 3 and the photosensitive layer 2 .
  • the photosensitive layer 2 is exposed to actinic rays through the support 3 .
  • the exposed portion irradiated with actinic rays is photocured to form a photocured portion 2a (latent image).
  • a known exposure method can be applied, for example, a method of irradiating actinic rays imagewise through a photomask 5 called artwork (mask exposure method), an LDI (Laser Direct Imaging) exposure method, or , a method of irradiating imagewise through a lens using actinic rays on which an image of a photomask is projected (projection exposure method), and the like.
  • the thickness of the resist pattern 6 formed on the semiconductor package substrate 1 may be, for example, 1 ⁇ m or more, 3 ⁇ m or more, or 5 ⁇ m or more. Also, the thickness of the resist pattern 6 formed on the semiconductor package substrate 1 may be, for example, 100 ⁇ m or less, 60 ⁇ m or less, or 40 ⁇ m or less. These minimum and maximum thicknesses of the resist pattern 6 can be combined as appropriate. For example, the thickness of the resist pattern 6 formed on the semiconductor package substrate 1 may be 1 ⁇ m to 100 ⁇ m, 3 ⁇ m to 60 ⁇ m, or 5 ⁇ m to 40 ⁇ m. The thickness of the resist pattern 6 is the height with respect to the semiconductor package substrate 1 in the direction perpendicular to the main surface of the semiconductor package substrate 1 .
  • the coordinates of the outline of the resist pattern on the semiconductor package substrate for mounting the semiconductor element on which the resist pattern is formed are measured.
  • the coordinates of the contour of the pattern are measured based on reflected light from the semiconductor package substrate, fluorescence from the semiconductor package substrate, or electron beam from the semiconductor package substrate, for example.
  • FIG. 2 shows, as an example of the coordinate measurement process, the case where the coordinates of the contour 61 of the resist pattern 6 are measured based on the reflected light from the semiconductor package substrate 1 .
  • inspection light is emitted to the semiconductor package substrate 1 on which the resist pattern 6 is formed. and receives reflected light from the semiconductor package substrate 1 .
  • the wavelength of the inspection light may be, for example, 380 nm or longer, 430 nm or longer, or 600 nm or longer. Also, the wavelength of the inspection light may be, for example, 830 nm or less, 780 nm or less, or 700 nm or less.
  • the wavelength of the inspection light may be 380 nm or more and 830 nm or less, 430 nm or more and 780 nm or less, or 600 nm or more and 700 nm or less.
  • White light using a laser excitation light source or the like may be used as the inspection light.
  • the light receiving area of the semiconductor package substrate 1 that receives reflected light in the coordinate measurement process may be, for example, 100 ⁇ m 2 or more and 2500 cm 2 or less, 500 ⁇ m 2 or more and 1200 cm 2 or less, or 1000 ⁇ m 2 or more and 600 cm 2 or less.
  • the light receiving area is also an area where the semiconductor package substrate 1 is irradiated with inspection light in one measurement.
  • the irradiation method of the inspection light for example, either regular reflection light or diffuse reflection light may be used, or a combination of regular reflection light and diffuse reflection light may be used.
  • the outline 61 of the resist pattern 6 is specified based on the contrast between the reflected light from the resist pattern 6 and the reflected light from the area other than the resist pattern 6. For example, in the received light image of the reflected light, a boundary where contrast such as brightness or chromaticity increases is detected. Then, this detected boundary is specified as the contour 61 of the resist pattern 6, and the coordinates of this specified contour 61 are measured.
  • the coordinates of the contour 61 to be measured are the coordinates of the XY coordinate system (two-axis coordinate system) on the main surface of the semiconductor package substrate 1 . In measuring the coordinates of the contour 61, the coordinates at a plurality of measurement points on the contour 61 are measured.
  • NEXIV VMZ-R4540 manufactured by Nikon Corporation, trade name
  • OPTELICS HYBRID+ Lasertec Co., Ltd.
  • a Computer Numerical Control image measurement system such as a company's product name
  • the contour 61 of the resist pattern 6 is specified based on the contrast between the fluorescence from the resist pattern 6 and the fluorescence from the area other than the resist pattern 6.
  • the coordinates of the specified contour 61 are measured.
  • a fluorescence microscope such as ECLIPS L300N (manufactured by Nikon Corporation, trade name) can be used.
  • the contour 61 of the resist pattern 6 is specified based on the contrast between the electron beam from the resist pattern 6 and the electron beam from the area other than the resist pattern 6 . Then, the coordinates of the specified contour 61 are measured.
  • a CD-SEM Cross-sectional Electron Microscope
  • CS4800 manufactured by Hitachi High-Tech Co., Ltd., trade name
  • the number, spacing, etc. of the measurement points of the contour 61 whose coordinates are measured are not particularly limited, the number of measurement points of the contour 61 whose coordinates are measured is large from the viewpoint of evaluating the resist pattern 6 with high accuracy. The narrower the distance between the measurement points on the contour 61 for measuring the coordinates, the better. From this point of view, for example, the interval between measurement points on the contour 61 whose coordinates are measured may be 0.5 ⁇ m or less, 0.3 ⁇ m or less, or 0.2 ⁇ m or less.
  • the interval between measurement points on the contour 61 whose coordinates are measured may be 0.001 ⁇ m or more, 0.005 ⁇ m or more, or 0.01 ⁇ m or more. The minimum and maximum intervals between these measurement points can be combined as appropriate.
  • the interval between measurement points on the contour 61 whose coordinates are measured may be 0.001 ⁇ m or more and 0.5 ⁇ m or less, 0.005 ⁇ m or more and 0.3 ⁇ m or less, or 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the resist pattern is inspected based on the coordinates measured in the coordinate measurement process.
  • the resist pattern formed on the semiconductor package substrate 1 has some degree of roughness.
  • the contour 61a on one side of the resist pattern 6 and the contour 61b on the other side of the resist pattern 6 do not extend in the extending direction of the resist pattern 6 in a completely linear or curved shape, but rather It often extends in the extending direction of the resist pattern 6 while fluctuating (unevenness) in the width direction of the resist pattern 6 .
  • the contour 61 (the contour 61a on one side or the contour 61b on the other side) of the resist pattern 6 becomes rough, and the line width W of the resist pattern 6 varies. Therefore, in the inspection process, the roughness of the resist pattern 6 is inspected based on the coordinates measured in the coordinate measurement process.
  • the inspection of the resist pattern 6 includes, for example, calculation of variations in the contour 61 of the resist pattern 6, calculation of the line width W of the resist pattern 6 and variations in the line width W, and comparison with pattern data for forming the resist pattern 6. Contrast, do.
  • the variation of the contour 61 of the resist pattern 6 in the width direction of the resist pattern 6 is calculated from the coordinates of a plurality of measurement points of the contour 61 measured in the coordinate measurement process.
  • 3 ⁇ of the contour 61 of the resist pattern 6 is calculated based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process. That is, 3 ⁇ of the contour 61 of the resist pattern 6 is calculated from the coordinates of a plurality of measurement points of the contour 61 measured in the coordinate measurement process.
  • ⁇ is the standard deviation and 3 ⁇ is also called the detection limit.
  • 3 ⁇ of the contour 61 of the resist pattern 6 is also called LER (Line Edge Roughness).
  • the line width W of the resist pattern 6 and the variation in the line width W is calculated from the coordinates of the plurality of measurement points of the contour 61 measured in the coordinate measurement process. Then, from the calculated line widths W, variations in the line width W of the resist pattern 6 in the width direction of the resist pattern 6 are calculated. As the variation in the line width W of the resist pattern 6, for example, 3 ⁇ of the line width W of the resist pattern 6 is calculated based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process.
  • the line width W at a plurality of positions of the resist pattern 6 is calculated from the coordinates of the plurality of measurement points of the contour 61 measured in the coordinate measurement process. Then, 3 ⁇ of the line width W of the resist pattern 6 is calculated from the plurality of line widths W thus calculated. 3 ⁇ of the line width W of the resist pattern 6 is also called LWR (Line Width Roughness).
  • LWR Line Width Roughness
  • the contour 61 of the resist pattern 6 measured in the coordinate measuring process is obtained from the coordinates of a plurality of measurement points of the contour 61 of the resist pattern 6 measured in the coordinate measuring process. Plot multiple measurement points of . Lines formed by this plotting are compared with pattern data for forming the resist pattern 6, and based on the result of this comparison, defects in the resist pattern 6 are detected and the number of detected defects is calculated.
  • a method of inspecting a conductor pattern includes a coordinate measurement step of measuring the coordinates of the outline of the conductor pattern on a semiconductor package board for mounting a semiconductor device on which the conductor pattern is formed, and inspecting the conductor pattern based on the coordinates measured in the coordinate measurement step. and an inspection step.
  • the conductor pattern inspection method may include, before the coordinate measurement step, a conductor pattern forming step of etching or plating the semiconductor package substrate on which the resist pattern is formed to form a conductor pattern on the semiconductor package substrate. Also, the conductor pattern inspection method may include other steps.
  • the coordinates of the outline of the conductor pattern on the semiconductor package substrate for mounting the semiconductor element on which the conductor pattern is formed are measured.
  • the coordinate measurement step of the conductor pattern inspection method can be performed, for example, in the same manner as the coordinate measurement step of the resist pattern inspection method.
  • the resist pattern (resist pattern 6) and the contour (contour 61) are replaced with the conductor pattern (conductor pattern 7) and the contour (contour 71), thereby performing the conductor pattern inspection method.
  • coordinate measurement process can be performed.
  • the conductor pattern when the semiconductor package substrate is etched, the line width of the conductor pattern becomes smaller. For this reason, when inspecting the conductor pattern by comparing it with the pattern data for forming the conductor pattern 7 after etching the semiconductor package substrate, for example, it is necessary to consider that the line width of the conductor pattern is reduced by the etching process. Then, the conductor pattern may be inspected by comparison with pattern data for forming the conductor pattern.
  • the conductor pattern is inspected based on the coordinates measured in the coordinate measurement process.
  • the inspection process of the conductor pattern inspection method can be performed, for example, in the same manner as the inspection process of the resist pattern inspection method. That is, in the inspection process of the resist pattern inspection method, by replacing the resist pattern (resist pattern 6) and the contour (contour 61) with the conductor pattern (conductor pattern 7) and the contour (contour 71), the conductor pattern inspection method can be improved. An inspection process can be performed.
  • a resist pattern manufacturing method includes a resist pattern forming step of forming a resist pattern on a semiconductor package substrate, and a coordinate measuring step of measuring the coordinates of the outline of the resist pattern on the semiconductor package substrate after the resist pattern forming step. and an inspection step of inspecting the resist pattern based on the coordinates measured in the coordinate measurement step.
  • the resist pattern forming step of the resist pattern manufacturing method may be, for example, similar to the resist pattern forming step of the resist pattern inspection method described above.
  • the coordinate measurement step of the resist pattern manufacturing method may be the same as the coordinate measurement step of the resist pattern inspection method described above, for example.
  • the coordinate measurement step of the resist pattern manufacturing method is similar to the coordinate measurement step of the resist pattern inspection method described above, for example.
  • the coordinates of the contour of the pattern are measured based on the electron beam from the .
  • the inspection process of the resist pattern manufacturing method may be the same as the inspection process of the resist pattern inspection method described above, for example.
  • the resist pattern manufacturing method may include other steps.
  • the semiconductor package substrate sorting method is a sorting method for sorting semiconductor package substrates on which either a resist pattern or a conductor pattern is formed.
  • This semiconductor package substrate sorting method includes a semiconductor package substrate sorting method based on a resist pattern for sorting semiconductor package substrates on which a resist pattern is formed, and a semiconductor package substrate sorting method for sorting semiconductor package substrates on which a conductor pattern is formed, based on a conductor pattern. and a method for sorting semiconductor package substrates.
  • a semiconductor package substrate sorting method based on a resist pattern includes a coordinate measurement step of measuring the coordinates of the outline of the resist pattern on the semiconductor package substrate on which the resist pattern is formed, and inspecting the resist pattern based on the coordinates measured in the coordinate measurement step. and an evaluation process for evaluating the resist pattern based on the inspection result of the inspection process.
  • the coordinate measurement step of the semiconductor package substrate screening method based on the resist pattern may be the same as the coordinate measurement step of the resist pattern inspection method described above, for example.
  • the inspection process of the semiconductor package substrate screening method based on the resist pattern may be, for example, the same as the inspection process of the resist pattern inspection method described above.
  • the method for screening semiconductor package substrates based on the resist pattern may include other steps.
  • the roughness of the resist pattern 6 is inspected based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process. Then, the resist pattern 6 is evaluated based on the roughness of the resist pattern 6.
  • the variation of the contour 61 of the resist pattern 6 is calculated based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process as the inspection of the resist pattern 6, in the evaluation process, this The resist pattern 6 is evaluated based on the degree of variation of the contour 61 . That is, if the degree of variation in the contour 61 is below the standard, it is evaluated as good, and if the degree of variation in the contour 61 exceeds the standard, it is evaluated as defective.
  • 3 ⁇ of the contour 61 of the resist pattern 6 is calculated as the variation of the contour 61 of the resist pattern 6 in the inspection process
  • 3 ⁇ of the contour 61 of the resist pattern 6 should be less than a predetermined reference value.
  • 3 ⁇ of the contour 61 of the resist pattern 6 exceeds a predetermined reference value, it is evaluated as defective.
  • the resist pattern 6 is evaluated based on the degree of variation in the line width W.
  • FIG. That is, if the degree of variation in the line width W is below the standard, it is evaluated as good, and if the degree of variation in the line width W1 exceeds the standard, it is evaluated as defective.
  • 3 ⁇ of the line width W of the resist pattern 6 is calculated as the variation in the line width W of the resist pattern 6 in the inspection process, 3 ⁇ of the line width W of the resist pattern 6 does not exceed a predetermined reference value in the evaluation process. If the line width W of the resist pattern 6 is less than the predetermined reference value, it is evaluated as good.
  • the inspection process when the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process and the pattern data for forming the resist pattern 6 are compared as an inspection of the resist pattern 6, in the evaluation process, The resist pattern 6 is evaluated based on this comparison result. For example, in the inspection process, when the number of defects in the resist pattern 6 is calculated by comparing the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process with the pattern data for forming the resist pattern 6, in the evaluation process If the number of defects in the resist pattern 6 is less than a predetermined reference value, the resist pattern 6 is evaluated as good, and if the number of defects in the resist pattern 6 exceeds the predetermined reference value, it is evaluated as defective.
  • a method for selecting a semiconductor package substrate based on a conductor pattern includes a coordinate measurement step of measuring the coordinates of the outline of the conductor pattern on the semiconductor package substrate on which the conductor pattern is formed, and inspecting the conductor pattern based on the coordinates measured in the coordinate measurement step. and an evaluation process for evaluating the conductor pattern based on the inspection result of the inspection process.
  • the coordinate measurement step of the semiconductor package substrate screening method based on the conductor pattern may be the same as the coordinate measurement step of the conductor pattern inspection method described above, for example.
  • the inspection process of the semiconductor package substrate sorting method based on the conductor pattern may be, for example, the same as the inspection process of the above-described conductor pattern inspection method.
  • the method for sorting semiconductor package substrates based on conductor patterns may include other steps.
  • the conductor pattern is evaluated based on the inspection results of the inspection process.
  • the evaluation process of the semiconductor package substrate sorting method based on the conductor pattern can be performed, for example, in the same manner as the evaluation process of the semiconductor package substrate sorting method based on the resist pattern. That is, in the evaluation process of the semiconductor package substrate sorting method based on the resist pattern, by replacing the resist pattern (resist pattern 6) and the contour (contour 61) with the conductor pattern (conductor pattern 7) and the contour (contour 71), the conductor An evaluation process for a pattern-based screening method for semiconductor package substrates may be performed.
  • a semiconductor package substrate on which a resist pattern is formed and whose evaluation of the resist pattern in the method for selecting semiconductor package substrates described above satisfies the criteria is etched or plated to form a conductor.
  • a conductor pattern forming step for forming a pattern is provided. In other words, in the conductor pattern forming step, among the semiconductor package substrates on which the resist pattern is formed, those semiconductor package substrates whose resist pattern evaluation in the semiconductor package substrate selection method does not meet the standards are subjected to etching or plating. do not form conductor patterns.
  • the case where the evaluation of the resist pattern in the semiconductor package substrate sorting method does not meet the criteria is, for example, the case where it is evaluated as defective in the evaluation process.
  • the method for manufacturing a semiconductor package substrate according to this embodiment may include other processes such as a resist pattern removing process, if necessary.
  • a resist pattern formed on a semiconductor package substrate provided with a conductor layer is used as a mask to etch away the conductor layer of the semiconductor package substrate that is not covered with the resist.
  • the resist is removed by removing the resist pattern 6 to form a conductor pattern.
  • a resist pattern 6 formed on the semiconductor package substrate 1 having the conductor layer 1b is used as a mask to remove the conductor layer 1b of the semiconductor package substrate 1 that is not covered with the resist. Copper or solder is plated on it.
  • the resist is removed by removing the resist pattern 6, and as shown in FIG. 4C, the conductor layer 1b covered with the resist is etched. , forming the conductor pattern 7 .
  • the method of plating treatment may be electrolytic plating treatment or electroless plating treatment, and among them, electrolytic plating treatment may be used.
  • the semiconductor package substrate on which the resist pattern is formed and the semiconductor package substrate on which the conductor pattern is formed may contain organic matter.
  • organic substances contained in a semiconductor package substrate on which a resist pattern is formed include phenol resins, epoxy resins, cyanate resins, maleimide resins, allyl resins, polyimide resins, polyphenylene ether resins, butadiene resins, polycarbonate resins, polyester resins, Acrylic resins, styrene resins, fluorine resins, polyethylene terephthalate resins, polyolefin resins, and the like can be mentioned.
  • organic substances contained in semiconductor package substrates on which conductor patterns are formed include phenol resins, epoxy resins, cyanate resins, maleimide resins, allyl resins, polyimide resins, polyphenylene ether resins, butadiene resins, polycarbonate resins, polyester resins, Acrylic resins, styrene resins, fluorine resins, polyethylene terephthalate resins, polyolefin resins, and the like can be mentioned.
  • the outline 61 of the resist pattern 6 or the outline of the conductor pattern 7 in the semiconductor package substrate 1 for mounting a semiconductor element on which the resist pattern 6 or the conductor pattern 7 is formed. 71 are measured, and the resist pattern 6 or conductor pattern 7 is inspected based on the measured coordinates. Therefore, even if the resist pattern 6 or the conductor pattern 7 formed on the semiconductor package substrate 1 is miniaturized, the resist pattern 6 or the conductor pattern 7 can be evaluated. Moreover, the resist pattern 6 or the conductor pattern 7 can be evaluated with higher accuracy than when visually inspected.
  • the roughness of the resist pattern 6 or the conductor pattern 7 is calculated based on the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7. Therefore, the state of formation of the resist pattern 6 or the conductor pattern 7 can be properly evaluated.
  • the variation of the contour 61 of the resist pattern 6 or the contour 61 of the conductor pattern 7 is calculated based on the measured contour 61 or the coordinates of the contour 71. Therefore, the formation state of the resist pattern 6 or the conductor pattern 7 can be properly evaluated.
  • the line width W of the resist pattern 6 or the conductor pattern 7 and the variation in the line width W are determined based on the measured coordinates of the contour 61 or the contour 71 as the inspection of the resist pattern 6 or the conductor pattern 7 . Since it is calculated, the state of formation of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.
  • the measured coordinates of the contour 61 or the contour 71 are compared with the pattern data for forming the resist pattern 6 or the conductor pattern 7.
  • the state of formation of the resist pattern 6 or the conductor pattern 7 can be evaluated with high accuracy.
  • the resist pattern 6 can be evaluated.
  • the outline 61 of the resist pattern 6 or the conductor pattern 7 is detected based on the reflected light from the semiconductor package substrate 1, the fluorescence from the semiconductor package substrate 1, or the electron beam from the semiconductor package substrate 1.
  • the coordinates of the contour 71 can be appropriately measured with high precision.
  • the resist pattern manufacturing method After the resist pattern 6 is formed on the semiconductor package substrate 1 for mounting a semiconductor element, the coordinates of the contour 61 of the resist pattern 6 on the semiconductor package substrate 1 are measured. The resist pattern 6 is inspected based on the determined coordinates. Thus, even if the resist pattern 6 formed on the semiconductor package substrate 1 is miniaturized, the resist pattern 6 can be evaluated, so that the resist pattern 6 with a small degree of roughness can be manufactured.
  • the coordinates of the outline 61 of the resist pattern 6 are measured based on reflected light from the semiconductor package substrate 1, fluorescence from the semiconductor package substrate 1, or electron beam from the semiconductor package substrate 1. By doing so, the coordinates of the contour 61 of the resist pattern 6 can be appropriately measured with high accuracy.
  • the coordinates of the outline 61 of the resist pattern 6 or the outline 71 of the conductor pattern 7 in the semiconductor package substrate 1 for mounting a semiconductor element on which the resist pattern 6 or the conductor pattern 7 is formed are determined.
  • the resist pattern 6 or the conductor pattern 7 is inspected based on the measured coordinates, and the resist pattern 6 or the conductor pattern 7 is evaluated based on the inspection result. Therefore, the resist pattern 6 or the conductor pattern 7 can be evaluated with higher accuracy than in the case of visual inspection.
  • the resist pattern 6 or the conductor pattern 7 is evaluated by the roughness of the resist pattern 6 or the conductor pattern 7 calculated based on the measured coordinates of the contour 61 or the contour 71, the resist pattern 6 or the conductor pattern 7 is evaluated.
  • the formation state of the pattern 6 or the conductor pattern 7 can be evaluated appropriately.
  • the resist pattern 6 or the conductor pattern 7 is evaluated by the variation of the contour 61 or the contour 71 calculated based on the measured coordinates of the contour 61 or the contour 71, the resist pattern 6 or the conductor pattern 7 is evaluated.
  • the state of formation of the conductor pattern 7 can be properly evaluated.
  • the resist pattern 6 or the conductor pattern 7 is evaluated based on the line width W calculated based on the measured coordinates of the contour 61 or the contour 71 and the variation in the line width W, the resist pattern 6 or the formation state of the conductor pattern 7 can be evaluated appropriately.
  • the resist pattern 6 or the conductor pattern 7 is evaluated by comparing the measured coordinates of the contour 61 or the contour 71 with the pattern data for forming the resist pattern 6 or the conductor pattern 7. Therefore, the formation state of the resist pattern 6 or the conductor pattern 7 can be properly evaluated.
  • the contour 61 of the resist pattern 6 or the conductor pattern is detected based on the reflected light from the semiconductor package substrate 1, the fluorescence from the semiconductor package substrate 1, or the electron beam from the semiconductor package substrate 1.
  • the coordinates of the contour 71 of 7 can be appropriately measured with high accuracy.
  • the semiconductor package substrates 1 on which the resist pattern 6 is formed among the semiconductor package substrates 1 on which the resist pattern 6 is formed, the semiconductor package substrates 1 whose evaluation of the resist pattern 6 in the method for selecting the semiconductor package substrate 1 described above satisfies the criteria. is etched or plated to form the conductor pattern 7, it is possible to suppress the occurrence of defects such as defective formation of the conductor pattern 7 and deterioration of the electrical characteristics of the manufactured semiconductor package.
  • FIG. 7 shows a diagram in which the plot diagram of FIG. 6 is superimposed on the photograph of FIG.
  • the present invention can be used as a pattern inspection method, a resist pattern manufacturing method, a semiconductor package substrate sorting method, and a semiconductor package substrate manufacturing method.

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PCT/JP2022/008187 2022-02-28 2022-02-28 パターンの検査方法、レジストパターンの製造方法、半導体パッケージ基板の選別方法、及び半導体パッケージ基板の製造方法 Ceased WO2023162194A1 (ja)

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PCT/JP2022/008187 WO2023162194A1 (ja) 2022-02-28 2022-02-28 パターンの検査方法、レジストパターンの製造方法、半導体パッケージ基板の選別方法、及び半導体パッケージ基板の製造方法
US18/841,160 US20250191978A1 (en) 2022-02-28 2023-02-20 Pattern inspection method, method for manufacturing resist pattern, target substrate selection method, and method for manufacturing target substrate
PCT/JP2023/006062 WO2023162934A1 (ja) 2022-02-28 2023-02-20 パターンの検査方法、レジストパターンの製造方法、対象基板の選別方法、及び対象基板の製造方法
CN202380023625.7A CN119096337A (zh) 2022-02-28 2023-02-20 图案的检查方法、抗蚀剂图案的制造方法、对象基板的分选方法及对象基板的制造方法
KR1020247028610A KR20240141296A (ko) 2022-02-28 2023-02-20 패턴의 검사 방법, 레지스트 패턴의 제조 방법, 대상 기판의 선별 방법, 및 대상 기판의 제조 방법
JP2024503141A JP7758148B2 (ja) 2022-02-28 2023-02-20 パターンの検査方法、レジストパターンの製造方法、対象基板の選別方法、及び対象基板の製造方法
TW112106238A TW202349528A (zh) 2022-02-28 2023-02-21 圖案之檢查方法、抗蝕劑圖案之製造方法、對象基板之分選方法及對象基板之製造方法

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JP2005207802A (ja) 2004-01-21 2005-08-04 Toshiba Corp レジストパターン検査方法及びその検査装置
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JPH07336024A (ja) * 1994-06-07 1995-12-22 Hitachi Ltd 薄膜配線の形成方法
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JP2006215020A (ja) * 2005-01-04 2006-08-17 Hitachi High-Technologies Corp 高精度パターン形状評価方法及びその装置

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