WO2023160192A1 - 一种用于总线的互联装置 - Google Patents

一种用于总线的互联装置 Download PDF

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WO2023160192A1
WO2023160192A1 PCT/CN2022/141063 CN2022141063W WO2023160192A1 WO 2023160192 A1 WO2023160192 A1 WO 2023160192A1 CN 2022141063 W CN2022141063 W CN 2022141063W WO 2023160192 A1 WO2023160192 A1 WO 2023160192A1
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Prior art keywords
read command
read
same
cache unit
unit
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PCT/CN2022/141063
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English (en)
French (fr)
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孙旭
周玉龙
刘刚
李拓
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苏州浪潮智能科技有限公司
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Publication of WO2023160192A1 publication Critical patent/WO2023160192A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G06F16/2455—Query execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G06F16/2458—Special types of queries, e.g. statistical queries, fuzzy queries or distributed queries

Definitions

  • the present application relates to the field of chip technology, in particular to an interconnection device for a bus.
  • AMBA Advanced Microcontroller Bus Architecture Advanced Microcontroller Bus Architecture
  • AMBA bus can be divided into APB (Advanced Peripheral Bus, Advanced Peripheral Bus), AHB (Advanced High-performance Bus, Advanced High-performance Bus) and AXI (Advanced eXtensible Interface, Advanced Extensible Interface)
  • APB Advanced Peripheral Bus, Advanced Peripheral Bus
  • AHB Advanced High-performance Bus, Advanced High-performance Bus
  • AXI Advanced eXtensible Interface, Advanced Extensible Interface
  • the present application is applicable to the AXI bus and the bus with outstanding transaction and out-of-sequence properties similar to the AXI bus.
  • FIG. 1 it is a schematic diagram of the architecture of the AXI bus.
  • the AXI bus is built by basic devices such as Master (master device), Slave (slave device) and Interconnect (intermediate interconnection part, referred to as ICN), which is a multi-master and multi-slave structure.
  • Master master device
  • Slave slave device
  • Interconnect intermediate interconnection part, referred to as ICN
  • the AXI protocol defines 5 independent channels, and each channel completes the handshake mechanism through the VALID (data valid) and READY (receive valid) signals.
  • the five channels are: Read Address Channel (AR), Read Data Channel (RD), Write Address Channel (AW), Write Data Channel (WD) and Write Response Channel (WR).
  • the outstanding transaction feature is one of the reasons why the AXI bus can achieve high-performance transmission.
  • the host can start the next transmission transaction before the current transmission transaction is completed. Therefore there may be multiple ongoing transfer transactions in the system. Assuming that multiple transactions can be processed in parallel by the slave device, the performance of the system can be improved.
  • the master device sends the transmission transaction, waits for the slave device to return data, and then starts the next transmission. Advance transmission can reduce data transmission time in the same application scenario.
  • Out-of-order transmission means that the master device initiates two consecutive transmissions, and the response order of the slave device and the initiation order of the master device may be different.
  • the master device sends two read transactions to slave device 0 and slave device 1 successively. Due to the differences in the structure and response mechanism of the two slave devices, the response time of the two is different, and there may be slave device 1 returning the read transaction first. data, which is then returned by slave 0.
  • DDR Double Data Rate SDRAM, double-rate synchronous dynamic random access memory
  • trans A accesses RAM (random access memory, random access memory), and trans B accesses DDR.
  • the master device can only Receive the return data corresponding to trans A first, and then receive the return data corresponding to trans B.
  • FIG. 2 it is a schematic diagram of the architecture of the AXI bus in an actual application scenario.
  • the AXI bus includes 2 master devices and 2 slave devices.
  • the master device and the slave device implement data transmission through ICN.
  • the specific application scenarios are as follows:
  • Scenario 1 In chronological order, first, Master_0 (master device 0) sends trans_0 (read command 0), reads part of the data from Slave_0 (slave device 0), and the read command ID is 1; then Master_0 sends trans_1 (read command Instruction 1), read part of the data from Slave_1 (slave device 1), and the read instruction ID is also 1.
  • slave device 1 may return data first at this time. Since the IDs of the two operations are the same, for the master device, the data returned first is considered to be the data returned by the first instruction issued. At this time, A data error has occurred which may result in a system error.
  • Master_0 (master device 0) sends a trans (read command) request to Slave_0 (slave device 0);
  • Master_0 (master device 0) sends a trans (read command) request to Slave_1 (slave device 1);
  • Master_1 (master device 1) sends a trans (read command) request to Slave_1 (slave device 1);
  • Master_1 (master device 1) sends a trans (read command) request to Slave_0 (slave device 0).
  • Slave_0 and Slave_1 receive read request channels normally. Assuming that Slave_0 is DDR, DDR has changed the reply order by itself, that is, it receives the request from Master_0 first, but the reply data is going to reply to Master_1 first. If so, Slave_0 tries to reply the data to Master_1, but Master_1 sends Slave_1 request first, and the AXI protocol conditions stipulate the same ID, Master_1 must first accept the reply from Slave_1, then can Master_1 get the reply from Slave_1, Slave_1 will Try to reply to Master_0 first, but the agreement condition specifies the same ID, Master_0 must receive the reply from Slave_0 first. In this way, an infinite loop is formed, and the master and slave devices need each other to send first, forming a deadlock deadlock.
  • An aspect of the embodiments of the present application provides an interconnection device for a bus, specifically including:
  • the decoding unit is configured to determine the slave device corresponding to the read instruction according to the read instruction sent by the master device;
  • the read command ID state recording unit includes a memory
  • the read command ID state record unit is configured to determine the corresponding slave device in response to the decoding unit, and check whether there is a current read command in the interconnection device based on the second port of the memory. the read command with the same ID;
  • the read command ID state recording unit is also configured to route the current read command to the slave device cache unit or the same ID sort cache unit of the corresponding slave device based on the query result, and write the corresponding value to the memory based on the first port of the memory, wherein, Values correspond to query results.
  • the decoding unit is further configured to select the instruction routing direction according to the address of the read instruction sent by the master device and the address space preset by the slave device, so as to determine the slave device corresponding to the read instruction.
  • the decoding unit is further configured to compare the read address of the received read instruction with the address space preset by each slave device, and determine the slave device to which the read instruction needs to be routed.
  • the read command ID state recording unit is further configured to route the current read command to the corresponding slave device if the second port of the memory inquires that there is no read command with the same ID as the current read command in the interconnection device.
  • the slave device caches the unit, and writes a value corresponding to the query result to the memory based on the first port of the memory.
  • the read command ID status recording unit is further configured to update the number of read commands with the same ID recorded in the memory.
  • updating the number of read instructions with the same ID recorded in the memory includes:
  • the read command ID state recording unit performs a RAM write operation through the first port of the memory, connects the ID value of the read command to the address line RAM_A_ADDR of the first port, and pulls up the write enable.
  • the read command ID state recording unit is further configured to route the current read command to the sorting cache unit with the same ID if the second port of the memory inquires that there is a read command with the same ID as the current read command in the interconnection device , and write a value corresponding to the query result to the memory based on the first port of the memory.
  • the read command ID state recording unit is further configured to route the current read command to the same ID if the depth sort_depth of the same ID sorting cache unit is greater than the number of read commands RAM_B_DOUT with the same ID as the current read command, and RAM_B_DOUT>1.
  • the number of read instructions with the same ID recorded in the memory is updated at the same time.
  • the read command ID state recording unit is further configured to pull the ready signal of the read command channel of the bus if the depth sort_depth of the same ID sorting cache unit is equal to the number of read commands with the same ID as the current read command RAM_B_DOUT Low.
  • the interconnection device further includes an instruction arbitration unit configured to transmit the read instruction cached in the slave cache unit and/or the same-ID sort cache unit to the slave device based on the arbitration policy.
  • the interconnection device also includes:
  • the ID decoding unit is configured to cache the data to the corresponding read data cache unit according to the ID of the read instruction corresponding to the data returned from the device, wherein the read data cache unit corresponds to the master device one by one;
  • the read command completion signal generation unit is configured to read data from the read data cache unit and return it to the master device, and generate a read command execution completion flag and a completion command ID corresponding to the data after the data return is completed.
  • the read command completion signal generating unit is further configured to send the completion command ID to the read command ID status recording unit;
  • the read instruction ID state recording unit is also configured to query the number of read instructions in the interconnection device based on the second port of the memory after receiving the completion instruction ID;
  • a value corresponding to the completed instruction ID query result is written into the memory through the first port of the memory.
  • routing the current read instruction to the same ID sorting cache unit includes:
  • the current read command is routed to the cache unit sorted with the same ID.
  • the interconnection device further comprises:
  • the interconnection device contains a read command with the same ID as the current read command, it is judged whether the idle register of the cache unit is in an idle state;
  • the cache unit idle register is in an idle state, assign the ID of the current read instruction to the cache unit sorting register, and configure the cache unit idle register as a non-idle state;
  • the current read command is routed to the same ID sort cache unit
  • the ready signal of the bus read command channel is pulled down to suspend receiving the current read command.
  • the interconnection device contains multiple read commands with the same ID as the current read command, compare the number of read commands with the same ID as the current read command in the interconnection device and the depth of the sorting cache unit with the same ID, and judge whether to The current read command is routed to the sorted cache unit with the same ID.
  • the arbitration policy includes:
  • polling outputs the read instructions cached in the cache unit of the slave device and the sorting cache unit with the same ID.
  • the query result is the number of read commands with the same ID as the current read command in the interconnection device
  • the value corresponding to the query result is the number of read commands with the same ID as the current read command plus 1 in the interconnection device.
  • Figure 1 is a schematic diagram of the architecture of the AXI bus
  • FIG. 2 is a schematic diagram of the architecture of an AXI bus in an actual application scenario
  • FIG. 3 is a schematic structural diagram of an embodiment of an interconnection device for a bus provided by one or more embodiments of the present application;
  • FIG. 4 is a schematic structural diagram of another embodiment of a bus interconnection device provided by one or more embodiments of the present application.
  • FIG. 3 it is a schematic structural diagram of an embodiment of an interconnection device for a bus provided by the present application.
  • a master device 10 , a slave device 20 , and an interconnection device 30 are connected to the bus.
  • the master device 10 includes a master device 0 and a master device 1
  • the slave device 20 includes a slave device 0 and a slave device 1
  • the master device 10 communicates with the slave device 20 through an interconnection device 30 .
  • This embodiment only uses 2 masters and 2 slaves as an example to illustrate the architecture of the interconnection device, but it is not limited to this structure, and it is applicable to multi-master and multi-slave devices.
  • the interconnection device 30 specifically includes a decoding unit (Decoder) 310 , a read command ID status recording unit 320 , a slave cache unit 330 and a same ID sort cache unit 340 .
  • Decoder decoding unit
  • the interconnection device 30 specifically includes a decoding unit (Decoder) 310 , a read command ID status recording unit 320 , a slave cache unit 330 and a same ID sort cache unit 340 .
  • the decoding unit 310 selects the instruction routing direction according to the address sent by the master device and the address space preset by the slave device. Each master device corresponds to a decoding unit. If there are N master devices, there are N decoding units.
  • the read instruction ID state recording unit 320 is composed of a dual-port memory, such as RAM, and control logic.
  • the RAM data bit width is 4bit (bit, which is the smallest unit of electronic information), and the data depth is 2 ar_id_width , where ar_id_width is a read instruction
  • the bit width of the ID for example, the bit width of the read command ID is 8 bits, the data depth is 256, and the address of the RAM is 0-255.
  • the functions of the first port and the second port are predefined. For example, the first port is used for updating the state table, and the second port is used for querying the ID state.
  • Slave device cache unit 330 is composed of FIFO (First In First Out) memory, which is used to cache read instruction information. After decoding unit 310 and read instruction ID state recording unit 320, read instruction is cached to this unit, cached The depth of the unit can be flexibly configured according to the specific use environment.
  • Each slave device corresponds to a slave device side cache unit. If there are N slave devices, there are N cache units.
  • the same ID sorting cache unit 340 is used to cache instructions with the same ID, and its depth can be flexibly configured according to the specific use environment, which is recorded as sort_depth, indicating that it can cache at most sort_depth read instructions with the same ID. Different from the cache unit of the slave device, there is only one sort cache unit with the same ID in the interconnection device.
  • the master device 0 sends a read command (including ID arid of the read command, read address ar_addr, read burst length ar_len, read type ar_burst, etc.) to the decoding unit.
  • a read command including ID arid of the read command, read address ar_addr, read burst length ar_len, read type ar_burst, etc.
  • the decoding unit compares the read address ar_addr of the received read command with the preset address space of each slave device, and determines the slave device location to which the current read command needs to be routed.
  • the read command ID state recording unit After determining the target slave device of the current read command, the read command ID state recording unit first inquires whether there is a read command with the same ID as the current read command in the interconnection device through the second port of the RAM, and outputs the corresponding value RAM_B_DOUT, RAM_B_DOUT is the number of read commands with the same ID as the current read command in the interconnection device. If there is no read command with the same ID as the current read command in the interconnection device, then RAM_B_DOUT is 0; if there is a read command with the same ID as the current read command in the interconnection device, then RAM_B_DOUT is the corresponding number, for example, if there is 1, then RAM_B_DOUT is 1, there are 2, then RAM_B_DOUT is 2.
  • the specific implementation process is: connect the ID arid of the read command to the address RAM_B_ADDR of the second port, and at the same time pull the enable signal of the second port high, and then the data line of the second port outputs the corresponding data RAM_B_DOUT.
  • the read command ID state recording unit writes the value corresponding to the query result of the read command of the same ID into the memory through the first port of the memory according to the query result of the same ID of the second port of the memory, for recording
  • the number of read commands with the same ID for example, the IDs of the read commands sent by the master device are 1, 2, and 3, and the memory will record them respectively, and process the read commands of the three IDs in sequence.
  • the read command ID state recording unit routes the current read command to the slave device cache unit or the same ID sorted cache unit of the corresponding slave device based on the query result. If it is found that there is no read command with the same ID as the current read command in the interconnection device, that is, RAM_B_DOUT is 0, the current command is cached in the slave cache unit; if there is a read command with the same ID as the current read command in the interconnection device. instruction, if RAM_B_DOUT is not 0, the current instruction is cached in the sorting cache unit with the same ID.
  • the read command ID state recording unit is further configured to route the current read command to the corresponding slave device if the second port of the memory inquires that there is no read command with the same ID as the current read command in the interconnection device.
  • the slave device caches the unit, and writes a value corresponding to the query result to the memory based on the first port of the memory.
  • the read command ID state recording unit is further configured to route the current read command to the sorting cache unit with the same ID if the second port of the memory inquires that there is a read command with the same ID as the current read command in the interconnection device , and write a value corresponding to the query result to the memory based on the first port of the memory.
  • the interconnection device further includes an instruction arbitration unit configured to transmit the read instruction cached in the slave cache unit and/or the same-ID sort cache unit to the slave device based on the arbitration policy.
  • the interconnection device further includes a command arbitration unit 380 , which uses a self-defined arbitration strategy to send the read command in the slave device cache unit and/or the same-ID sort cache unit to the corresponding slave device after arbitration.
  • a command arbitration unit 380 uses a self-defined arbitration strategy to send the read command in the slave device cache unit and/or the same-ID sort cache unit to the corresponding slave device after arbitration.
  • Each slave device corresponds to an instruction arbitration unit. If there are N slave devices, there are N instruction arbitration units.
  • the same ID sorting cache unit and instruction arbitration unit ensure that the bus is always running accurately and efficiently, thereby enhancing the reliability and applicability of the SOC system.
  • the interconnection device also includes:
  • the ID decoding unit is configured to cache the data to the corresponding read data cache unit according to the ID of the read instruction corresponding to the data returned from the device, wherein the read data cache unit corresponds to the master device one by one;
  • the read command completion signal generation unit is configured to read data from the read data cache unit and return it to the master device, and generate a read command execution completion flag and a completion command ID corresponding to the data after the data return is completed.
  • FIG. 4 it is a schematic structural diagram of another embodiment of an interconnection device for a bus provided in the present application.
  • a master device 10 , a slave device 20 , and an interconnection device 30 are connected to the bus.
  • the master device 10 includes a master device 0 and a master device 1
  • the slave device 20 includes a slave device 0 and a slave device 1
  • the master device 10 communicates with the slave device 20 through an interconnection device 30 .
  • the interconnection device 30 specifically includes a decoding unit 310 , a read command ID status recording unit 320 , a slave cache unit 330 , a same ID sort cache unit 340 , an ID decoding unit 350 , a read data cache unit 360 , and a read command completion signal generation unit 370 .
  • the ID decoding unit 350 decodes the ID of the command, and routes the data corresponding to the read command returned from the slave device to the corresponding master device.
  • the read data cache unit 360 is composed of FIFO memory in hardware, and is used to cache the returned read data information, and its depth can be flexibly configured according to the specific use environment.
  • Each master device corresponds to a read data cache unit, and if there are N master devices, there are N cache units.
  • the read command completion signal generating unit 370 is configured to generate a flag signal that a read command is completed.
  • the slave device After receiving the read command, the slave device returns the data corresponding to the read command, and returns the data to the master device through the ID decoding unit and the read data cache unit in turn, and the read command completion signal generation unit completes all the read data corresponding to a read command. Generate the corresponding completion signal after returning to the master device.
  • the read instruction received from the slave device is a read instruction processed by the decoding unit, the read instruction ID state recording unit, the slave device cache unit, and the same ID sort cache unit, which ensures that the order of the read instructions received from the slave device is sent according to the read instruction It is received successively in time, thus ensuring that the data returned from the device is also returned in the order in which the master device sends the read commands, avoiding problems such as infinite loops or data errors on the bus, and ensuring the transmission of the read commands and their returned data Speed while also improving the accuracy of transmission.
  • the read command completion signal generating unit is further configured to send the completion command ID to the read command ID status recording unit;
  • the read instruction ID state recording unit is also configured to query the number of read instructions in the interconnection device based on the second port of the memory after receiving the completion instruction ID;
  • a value corresponding to the completed instruction ID query result is written into the memory through the first port of the memory.
  • the read command completion signal generation unit will complete the command ID, i.e. the ID of the read command, and send it to the read command ID state recording unit.
  • querying and writing the completion command ID through the memory is used to return the data that the slave device has returned for the read command.
  • the instructions are cleared from the slave cache unit of the interconnection device or the sort cache unit with the same ID, so as to continue to execute the read instructions of other IDs after all the read instructions of one ID are executed.
  • routing the current read instruction to the same ID sorting cache unit includes:
  • the current read command is routed to the cache unit sorted with the same ID.
  • the interconnection device contains a read command with the same ID as the current read command, then determine whether the idle register of the cache unit is in an idle state;
  • the interconnection device contains multiple read commands with the same ID as the current read command, compare the number of read commands with the same ID as the current read command in the interconnection device and the depth of the sorting cache unit with the same ID, and judge based on the comparison result Whether to route the current read command to the sorted cache unit with the same ID.
  • Step S2 specifically includes the following steps:
  • Step S2 also includes the following steps:
  • the interconnection device further comprises:
  • the interconnection device contains a read command with the same ID as the current read command, it is judged whether the idle register of the cache unit is in an idle state;
  • the cache unit idle register is in an idle state, assign the ID of the current read instruction to the cache unit sorting register, and configure the cache unit idle register as a non-idle state;
  • the arbitration policy includes:
  • the interconnection device includes a lagging instruction, then output the read instruction cached from the cache unit of the device;
  • polling outputs the read instructions cached in the cache unit of the slave device and the sorting cache unit with the same ID.
  • the query result is the number of read commands with the same ID as the current read command in the interconnection device
  • the value corresponding to the query result is the number of read commands with the same ID as the current read command in the interconnection device plus 1.
  • the master device sends a read command (including ID arid of the read command, read address ar_addr, read burst length ar_len, read type ar_burst, etc.) to the decoding unit.
  • the decoding unit compares the read address with the preset address space of each slave device, and determines the slave device to which the current read command needs to be routed.
  • the read command ID state recording unit After determining the purpose of the current read command from the device, enter the read command ID state recording unit, the first port and the second port of the RAM of the read command ID state recording unit use the A port and the B port respectively in the present embodiment to correspondingly It means that the read command ID state recording unit first queries whether there is a read command with the same ID as the current read command in the interconnection device through the B port of the RAM, and outputs the query result.
  • the specific process is to connect the ID arid of the current read command to the address line RAM_B_ADDR of the B port, and at the same time pull the enable signal of the B port of the RAM high, and the data line of the B port outputs the corresponding data RAM_B_DOUT based on the query result.
  • the specific process of updating is as follows: the read command ID state recording unit performs RAM write operation through the A port of the RAM, connects the value of arid to the address line RAM_A_ADDR of the A port, pulls the write enable, and inputs the data value 1.
  • RAM_B_DOUT 1
  • the purpose of configuring the delay register is to mark that in the current interconnection device, a read command with the same ID is included in the slave device cache unit and the same ID sorting cache unit. According to the order of the cache time, when the read command is sent to the destination slave device, Priority is given to sending read commands in the slave unit of the slave device.
  • sort_depth>RAM_B_DOUT>1 it means that there are multiple read commands with the same ID in the interconnection device, and the ID arid of the current read command must be equal to sort_id. At this time, the current read command is routed to sort, and at the same time, the The number of read commands with the same ID recorded is updated.
  • the ready signal of the read command channel of the bus such as the AXI bus, is pulled low, that is, the current command is not received temporarily.
  • the instruction arbitration unit uses a self-defined arbitration strategy to output the read instruction from the cache unit of the slave device or the cache unit sorted by the same ID to the corresponding slave device.
  • the arbitration strategy adopts the combination of fixed priority and round-robin arbitration. details as follows:
  • the arbitration result is always the instruction of the output buffer channel, and the instruction of the sort channel is kept in the cache and will not be output to the subsequent slave device.
  • the result of the arbitration at this time is that the instruction of the buffer channel and the instruction of the sort channel are polled and arbitrated, and output to the subsequent slave device, that is, when the two channels cache the instruction at the same time, the two channels alternately select the output , if only one channel has a cache command, then directly output the channel command.
  • the interconnection device also includes a plurality of registers, and this embodiment only uses some of the registers used for illustration.
  • the master device sends a read command, pre-configure the lag register, the cache unit sorting register, and the cache unit idle register in the interconnection device.
  • setting the lag register to 1 means that there is a lag command in the interconnect device, and setting it to 0 means There are no lagging instructions in the interconnection device; the cache unit sorting register is used to record the number of read instructions with the same ID, and the initial value is 0; the cache unit free register is set to 0 to indicate that the sorting cache unit with the same ID is occupied, and the cache unit free register is set If it is 1, it means that the sorting cache unit with the same ID is in an idle state.
  • the above embodiment is only an example of the configuration of lag registers, cache unit sorting registers, and cache unit idle registers, but is not limited thereto, and users can freely define them according to actual application scenarios.
  • the slave device After receiving the read command, the slave device returns the data corresponding to the read command, and returns the data to the master device through the ID decoding unit Decoder_ID and the read data buffer unit Buffer_D in turn, and the read command completion signal generation unit Comp completes the read command corresponding to the read command. After all the data is returned to the master device, a corresponding completion signal is generated.
  • the specific process is as follows:
  • rlast is the flag signal of the last data of a read operation
  • rvalid is the data valid flag of the read operation
  • rid is the id returned by the read data channel
  • rid is the same as the ID of the read command sent by the host.
  • Comp_done is set to 1 to indicate that the execution of a read instruction is completed, and it is only pulled high for one clock cycle.
  • the comp_id is returned to the read command ID state recording unit, and the B port of the RAM queries the number of read commands with the same ID as comp_id in the interconnection device, and outputs the query result RAM_B_DOUT. Then make the following judgments:
  • the present application at least has the following beneficial technical effects: avoiding data errors caused by the advance transmission and out-of-sequence mechanism of the bus itself, or problems such as the formation of an infinite loop between master and slave devices, and improving the accuracy of read instructions and their returned data during bus data transmission. Accuracy, and ensure the high-speed transmission of the read command and its return data on the bus.

Abstract

本申请公开了一种用于总线的互联装置，包括：解码单元，解码单元配置为根据主设备发送的读指令确定读指令对应的从设备；读指令ID状态记录单元，读指令ID状态记录单元包括存储器，读指令ID状态记录单元配置为响应于解码单元确定对应的从设备，基于存储器的第二端口查询互联装置中是否存在与当前读指令的ID相同的读指令；读指令ID状态记录单元还配置为基于查询结果将当前读指令路由到对应从设备的从设备缓存单元或同ID排序缓存单元，并基于存储器的第一端口向存储器写入对应的值，其中，值与查询结果相对应。通过本申请的方案，在保证总线上数据高速传输的情况下，提高了总线传输读指令及其返回数据的准确性。

Description

一种用于总线的互联装置
相关申请的交叉引用
本申请要求于2022年02月24日提交中国专利局，申请号为202210171742.5，申请名称为“一种用于总线的互联装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，尤其涉及一种用于总线的互联装置。
背景技术
随着集成电路的不断发展，对SOC(System on Chip，片上系统)芯片的处理速度性能的要求越来越高。系统总线作为连接各个模块的中枢桥梁，对SOC系统的性能起到重要影响，特别是在多个主设备和多个从设备的系统中。AMBA(Advanced Microcontroller Bus Architecture高级微控制器总线架构)总线是ARM公司与其他芯片公司包括高通、东芝和爱立信共同研发的，以满足SOC系统对于多用户高性能低功耗的需求，被广泛应用于SOC系统。根据总线开发时间及使用环境，AMBA总线又可分为APB(Advanced Peripheral Bus，高级外围总线)、AHB(Advanced High-performance Bus，高级高性能总线)和AXI(Advanced eXtensible Interface，先进可扩展接口)总线，其支持的功能越来越复杂，速度越来越快，同时开发的难度也越来越大。
本申请适用于AXI总线以及拥有类似AXI总线的超前传输(outstanding transaction)和乱序属性的总线。
以AXI总线为例，如图1所示，为AXI总线的架构示意图。
AXI总线由Master(主设备)、Slave(从设备)和Interconnect(中间互联部分，简称ICN)等基本器件搭建而成，为多主多从的结构。
AXI协议定义了5个独立的通道，每个通道通过VALID(数据有效)和READY(接收有 效)信号完成握手机制。5个通道分别为：读地址通道(AR)、读数据通道(RD)、写地址通道(AW)、写数据通道(WD)和写响应通道(WR)。
超前传输(outstanding transaction)特性是AXI总线能够实现高性能传输的原因之一，主机在当前传输事务完成前，就可以开始下一个传输事务。因此系统中可能存在多个进行中的传输事务。假设多个事务能够被从设备并行处理，可提高系统的性能。在未进行超前传输的场景下，主设备发出传输事务后，等待从设备返回数据后，再开始下一次传输。超前传输在同一应用场景中能够减少数据的传输时间。
乱序传输，指的是主设备连续发起了两次传输，对于从设备的应答顺序和主设备的发起顺序可以是不同的。例如，主设备先后发送两个读事务分别至从设备0和从设备1，由于两个从设备的结构、应答机制等存在不同，两者的响应时间不同，可能存在先从设备1首先返回读数据，之后由从设备0返回数据。
对于很多从设备，是具有响应重排序功能的，典型的例子DDR(Double Data Rate SDRAM，双倍速率同步动态随机存储器)，DDR先收到trans A的请求，再收到trans B的请求，但回复可能先回trans B，再回trans A。
AXI协议中规定，主设备连发的两个传输事物具有同样的ID，比如trans A访问RAM(random access memory，随机存储器)，trans B访问DDR，同样的ID，则接收回复时主设备只能先接收trans A对应的返回数据，再接收transB对应的返回数据。
如图2所示，为一实际应用场景的AXI总线的架构示意图，AXI总线包含2个主设备，2个从设备，主设备和从设备通过ICN实现数据传输。具体的应用场景如下：
情景1：按照时间先后顺序，首先由Master_0(主设备0)发送trans_0(读指令0)，读取从Slave_0(从设备0)的部分数据，读指令ID为1；之后由Master_0发送trans_1(读指令1)，读取从Slave_1(从设备1)的部分数据，读指令ID也为1。
由于超前传输和乱序操作机制，此时从设备1可能先返回数据，由于两次操作的ID相同，因此对主设备，首先返回的数据即认为是首先发出的指令返回的数据，此时便出现数据错误，由此可能导致系统错误。
情景2：按照如下的时间顺序：
Master_0(主设备0)发trans(读指令)请求给Slave_0(从设备0)；
Master_0(主设备0)发trans(读指令)请求给Slave_1(从设备1)；
Master_1(主设备1)发trans(读指令)请求给Slave_1(从设备1)；
Master_1(主设备1)发trans(读指令)请求给Slave_0(从设备0)。
Slave_0和Slave_1接收读请求通道正常。假设Slave_0是DDR，DDR自己调换了回复顺序，即它先收到Master_0的请求，但是回复数据却准备先回复Master_1的。如果这样，Slave_0尝试把数据回复给Master_1，但是Master_1先发的Slave_1请求，且AXI协议条件规定了同ID，Master_1必须先接受Slave_1的回复，那么Master_1能否拿到Slave_1的回复呢，Slave_1就会尝试先回复Master_0，而协议条件规定了同ID，Master_0必须先接收Slave_0的回复。这样，就形成了一个死循环，主从设备互相需求对方先发，就形成了死锁deadlock。
发明内容
本申请实施例的一方面提供了一种用于总线的互联装置，具体包括：
解码单元，解码单元配置为根据主设备发送的读指令确定读指令对应的从设备；
读指令ID状态记录单元，读指令ID状态记录单元包括存储器，读指令ID状态记录单元配置为响应于解码单元确定对应的从设备，基于存储器的第二端口查询互联装置中是否存在与当前读指令的ID相同的读指令；和
读指令ID状态记录单元还配置为基于查询结果将当前读指令路由到对应从设备的从设备缓存单元或同ID排序缓存单元，并基于存储器的第一端口向存储器写入对应的值，其中，值与查询结果相对应。
在一些实施方式中，解码单元进一步配置为根据主设备发送的读指令的地址和从设备预设的地址空间进行指令路由方向的选择，以确定读指令对应的从设备。
在一些实施方式中，解码单元进一步配置为将接收到的读指令的读地址与每一个从设备预设的地址空间相比较，确定读指令需要路由到的从设备。
在一些实施方式中，读指令ID状态记录单元进一步配置为若是存储器的第二端口查询到互联装置中不存在与当前读指令的ID相同的读指令，则将当前读指令路由到对应从设备的从设备缓存单元，并基于存储器的第一端口向存储器写入与查询结果相对应的值。
在一些实施方式中，读指令ID状态记录单元进一步配置为对存储器中记录的同一ID的读指令的数量进行更新。
在一些实施方式中，对存储器中记录的同一ID的读指令的数量进行更新，包括：
读指令ID状态记录单元通过存储器的第一端口进行RAM写操作，将读指令的ID值连接到第一端口的地址线RAM_A_ADDR上，拉高写使能。
在一些实施方式中，读指令ID状态记录单元进一步配置为若是存储器的第二端口查询到互联装置中存在与当前读指令的ID相同的读指令，则将当前读指令路由到同ID排序缓存单元，并基于存储器的第一端口向存储器写入与查询结果相对应的值。
在一些实施方式中，读指令ID状态记录单元进一步配置为若缓存单元空闲寄存器sort_idle＝1，则将当前读指令路由到同ID排序缓存单元中，同时对存储器中记录的同一ID的读指令的数量进行更新。
在一些实施方式中，读指令ID状态记录单元进一步配置为若缓存单元空闲寄存器sort_idle＝0，则对比当前读指令的arid值与缓存单元空闲寄存器的sort_id，若arid＝sort_id，则将当前读指令路由到同ID排序缓存单元中，同时对存储器中记录的同一ID的读指令的数量进行更新，若arid！＝sort_id，则将总线读指令通道的ready信号拉低。
在一些实施方式中，读指令ID状态记录单元进一步配置为若同ID排序缓存单元的深度sort_depth大于当前读指令的ID相同的读指令的数量RAM_B_DOUT，且RAM_B_DOUT>1，将当前读指令路由到同ID排序缓存单元中，同时对存储器中记录的同一ID的读指令的数量进行更新。
在一些实施方式中，读指令ID状态记录单元进一步配置为若此时同ID排序缓存单元的深度sort_depth等于当前读指令的ID相同的读指令的数量RAM_B_DOUT，将总线的读指令通道的ready信号拉低。在一些实施方式中，互联装置还包括指令仲裁单元，指令仲裁单元配置为基于仲裁策略将缓存在从设备缓存单元和/或同ID排序缓存单元中的读指令传输到从设备。
在一些实施方式中，互联装置还包括：
ID解码单元，ID解码单元配置为根据从设备返回的数据对应的读指令的ID将数据缓存到对应的读数据缓存单元，其中，读数据缓存单元与主设备一一对应；和
读指令完成信号生成单元，读指令完成信号生成单元配置为从读数据缓存单元读取数据返回给主设备，并在数据返回完成后生成读指令执行完成标志和数据对应的完成指令ID。
在一些实施方式中，读指令完成信号生成单元进一步配置为将完成指令ID发送到读指令ID状态记录单元；
读指令ID状态记录单元还配置为接收到完成指令ID后基于存储器的第二端口查询互联装置中与完成指令ID相同的读指令的数量；
对比完成指令ID和缓存单元排序寄存器的值是否相同；和
基于对比结果和存储器的第二端口的完成指令ID查询结果，通过存储器的第一端口向存储器写入与完成指令ID查询结果相对应的值。
在一些实施方式中，将当前读指令路由到同ID排序缓存单元包括：
基于互联装置中与当前读指令的ID相同的读指令的数量和/或缓存单元空闲寄存器是否为空闲状态，将当前读指令路由到同ID排序缓存单元。
在一些实施方式中，互联装置进一步包括：
若是互联装置中包含一个与当前读指令的ID相同的读指令，则判断缓存单元空闲寄存器是否为空闲状态；
若是缓存单元空闲寄存器为空闲状态，则将当前读指令的ID赋值给缓存单元排序寄存器，并将缓存单元空闲寄存器配置为非空闲状态；
配置滞外寄存器以将当前读指令标记为滞外指令；和
将当前读指令路由到同ID排序缓存单元。
在一些实施方式中，进一步包括：
若是缓存单元空闲寄存器为非空闲状态，则对比当前读指令的ID和缓存单元排序寄存器的值是否相同；
若是当前读指令的ID和缓存单元排序寄存器的值相同，则将当前读指令路由到同ID排序缓存单元；和
若是当前读指令的ID和缓存单元排序寄存器的值不相同，则拉低总线读指令通道的ready信号以暂缓接收当前读指令。
在一些实施方式中，进一步包括：
若是互联装置中包含多个与当前读指令的ID相同的读指令，则对比互联装置中与当前读指令的ID相同的读指令数量与同ID排序缓存单元的深度，并基于对比结果判断是否将当前读指令路由到同ID排序缓存单元。
在一些实施方式中，仲裁策略包括：
基于滞外寄存器判断互联装置是否包含滞外指令；
若是互联装置包含滞外指令，则输出从设备缓存单元中缓存的读指令；和
若是互联装置不包含滞外指令，则轮询输出从设备缓存单元和同ID排序缓存单元中缓存的读指令。
在一些实施方式中，查询结果为互联装置中与当前读指令的ID相同的读指令的数量；
与查询结果相对应的值为互联装置中与当前读指令的ID相同的读指令的数量加1。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1为AXI总线的架构示意图；
图2为一实际应用场景的AXI总线的架构示意图；
图3为本申请一个或多个实施例提供的用于总线的互联装置的一实施例的架构示意图；
图4为本申请一个或多个实施例提供的总线的互联装置的又一实施例的架构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本申请实施例进一步详细说明。
需要说明的是，本申请实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便， 不应理解为对本申请实施例的限定，后续实施例对此不再一一说明。
如图3所示，为本申请提供的用于总线的互联装置的一实施例的架构示意图。总线上连接有主设备10、从设备20、互联装置30。主设备10包括主设备0、主设备1，从设备20包括从设备0和从设备1，主设备10通过互联装置30与从设备20通信连接。
本实施例仅以2主2从设备为例对互联装置的架构进行举例说明，但不仅限于此结构，其对多主多从设备都适用。
互联装置30具体包括解码单元(Decoder)310、读指令ID状态记录单元320和从设备缓存单元330和同ID排序缓存单元340。
解码单元310根据主设备发送指令的地址和从设备预设的地址空间进行指令路由方向的选择，每一个主设备对应一个解码单元，若有N个主设备，则有N个解码单元。
读指令ID状态记录单元320，由双端口存储器，例如RAM，和控制逻辑构成，RAM数据位宽为4bit(比特，是构成电子信息的最小单位)，数据深度为2 ar_id_width,其中ar_id_width为读指令ID的位宽，例如读指令ID的位宽为8bit，则数据深度为256，RAM的地址为0-255。双端口存储器中，预先定义好第一端口和第二端口的功能，例如，其中第一端口用于状态表的更新，第二端口用于ID状态的查询。
从设备缓存单元330，由FIFO(First In First Out，先进先出)存储器构成，用于缓存读指令信息，经过解码单元310和读指令ID状态记录单元320后，读指令被缓存至此单元，缓存单元的深度可以根据具体的使用环境灵活配置每一个从设备对应一个从设备端缓存单元，若有N个从设备，则有N个缓存单元。
同ID排序缓存单元340，用于缓存具有相同ID的指令，其深度可以根据具体的使用环境灵活配置，记为sort_depth，表明其最大可以缓存sort_depth个同ID读指令。与从设备缓存单元不同的是，同ID排序缓存单元在互联装置中只有一个。
下面具体实施例对上述互联装置的应用过程进行说明。
主设备0发送读指令(包括读指令的ID arid、读地址ar_addr、读突发长度ar_len、读类型ar_burst等)至解码单元。
解码单元将接收到的读指令的读地址ar_addr与每一个从设备预设的地址空间相比较，确定当前读指令需要路由到的从设备位置。
在确定当前读指令的目的从设备后，读指令ID状态记录单元，首先通过RAM的第二端口查询互联装置中是否有与当前读指令的ID相同的读指令，并输出相应的值RAM_B_DOUT，RAM_B_DOUT为互联装置中当前读指令的ID相同的读指令的数量。若互联装置中没有与当前读指令的ID相同的读指令，则RAM_B_DOUT为0；若互联装置中有与当前读指令的ID相同的读指令，则RAM_B_DOUT为相应的数量，例如有1个，则RAM_B_DOUT为1，有2个，则RAM_B_DOUT为2。具体的实现过程为：将读指令的ID arid连接到第二端口的地址RAM_B_ADDR上，同时将第二端口的使能信号拉高，此时第二端口的数据线便输出对应的数据RAM_B_DOUT。
读指令ID状态记录单元根据存储器的第二端口的相同ID的读指令的查询结果，通过存储器的第一端口向存储器中写入与相同ID的读指令的查询结果相对应的值，用于记录互联装置中，相同ID的读指令的数量，例如主设备发送的读指令的ID有1、2、3三种，则存储器分别记录下来，依次对三种ID的读指令进处理。
读指令ID状态记录单元基于查询结果将当前读指令路由到对应从设备的从设备缓存单元或同ID排序缓存单元。若查询到互联装置中没有与当前读指令的ID相同的读指令，即RAM_B_DOUT为0，则将当前指令缓存到从设备缓存单元；若查询到互联装置中有与当前读指令的ID相同的读指令，则RAM_B_DOUT不为0，则将当前指令缓存到同ID排序缓存单元。在互联装置中没有或只有一条与当前读指令的ID相同的读指令时，始终输出从设备缓存单元中缓存的读指令；在互联装置中有多于一条与当前读指令的ID相同的读指令时，轮询从从设备缓存单元和同ID排序缓存单元中输出缓存的读指令。
通过本申请的互联装置，避免了由于总线自身的超前传输和乱序机制导致的数据错误、或主从设备间形成死循环等问题，提高了总线数据传输时读指令及其返回数据的准确性，且保证了读指令及其返回数据在总线上的高速传输。
在一些实施方式中，读指令ID状态记录单元进一步配置为若是存储器的第二端口查询到互联装置中不存在与当前读指令的ID相同的读指令，则将当前读指令路由到对应从设备的从设备缓存单元，并基于存储器的第一端口向存储器写入与查询结果相对应的值。
在一些实施方式中，读指令ID状态记录单元进一步配置为若是存储器的第二端口查询到互联装置中存在与当前读指令的ID相同的读指令，则将当前读指令路由到同ID排序缓存单元，并基于存储器的第一端口向存储器写入与查询结果相对应的值。
在一些实施方式中，互联装置还包括指令仲裁单元，指令仲裁单元配置为基于仲裁策略将缓存在从设备缓存单元和/或同ID排序缓存单元中的读指令传输到从设备。
结合图3，互联装置还包括指令仲裁单元380，使用自定义的仲裁策略，将从设备缓存单元和/或同ID排序缓存单元中的读指令经仲裁后相对应指令发送至相应的从设备。每一个从设备对应一个指令仲裁单元，若有N个从设备，则有N个指令仲裁单元。通过同ID排序缓存单元和指令仲裁单元保证了总线始终处于准确高效的运行，进而增强了SOC系统的可靠性和适用性。
在一些实施方式中，互联装置还包括：
ID解码单元，ID解码单元配置为根据从设备返回的数据对应的读指令的ID将数据缓存到对应的读数据缓存单元，其中，读数据缓存单元与主设备一一对应；
读指令完成信号生成单元，读指令完成信号生成单元配置为从读数据缓存单元读取数据返回给主设备，并在数据返回完成后生成读指令执行完成标志和数据对应的完成指令ID。
如图4所示，为本申请提供的用于总线的互联装置又一实施例架构示意图。
总线上连接有主设备10、从设备20、互联装置30。主设备10包括主设备0、主设备1，从设备20包括从设备0和从设备1，主设备10通过互联装置30与从设备20通信连接。
互联装置30具体包括解码单元310、读指令ID状态记录单元320和从设备缓存单元330、同ID排序缓存单元340、ID解码单元350、读数据缓存单元360、读指令完成信号生成单元370。
ID解码单元350，根据对指令的ID进行解码，将从设备返回的读指令对应的数据路由到对应的主设备。
读数据缓存单元360，硬件上由FIFO存储器构成，用于缓存返回的读数据信息，其深度可以根据具体的使用环境灵活配置。每一个主设备对应一个读数据缓存单元，若有N个主设备，则有N个缓存单元。
读指令完成信号生成单元370，用于产生一次读指令完成的标志信号。
从设备在接收到读指令后，返回读指令对应的数据，并依次通过ID解码单元、读数 据缓存单元将数据返回到主设备，读指令完成信号生成单元在完成一个读指令对应的读数据全部返回主设备后生成对应的完成信号。
从设备接收到的读指令为经过解码单元、读指令ID状态记录单元和从设备缓存单元、同ID排序缓存单元处理的读指令，保证了从设备接收到的读指令的顺序为按照读指令发送的时间先后接收的，从而保证了从设备返回的数据为也是按照主设备发送读指令的先后顺序返回的，避免了总线出现死循环或数据错误等问题，在保证读指令及其返回数据的传输速度的同时还提高了传输的准确性。
在一些实施方式中，读指令完成信号生成单元进一步配置为将完成指令ID发送到读指令ID状态记录单元；
读指令ID状态记录单元还配置为接收到完成指令ID后基于存储器的第二端口查询互联装置中与完成指令ID相同的读指令的数量；
对比完成指令ID和缓存单元排序寄存器的值是否相同；
基于对比结果和存储器的第二端口的完成指令ID查询结果，通过存储器的第一端口向存储器写入与完成指令ID查询结果相对应的值。
结合图4，读指令完成信号生成单元将完成指令ID，即读指令的ID，发送至读指令ID状态记录单元，读指令ID状态记录单元接收到完成指令ID后，通过存储器的第二端口在互联装置中查询是否有与完成指令ID相同的读指令，并输出查询到的与完成指令ID相同的读指令的数量，并通过存储器的第一端口向存储器中写入相应的值，此处的值为从互联装置中查询到的与完成指令ID相同的读指令的数量减1，此处通过存储器进行完成指令ID查询并写入是用于将从设备已经针对读指令返回数据的那一条读指令从互联装置的从设备缓存单元或同ID排序缓存单元中清除，以便在一个ID的读指令全部执行完成后继续执行其它ID的读指令。
在一些实施方式中，将当前读指令路由到同ID排序缓存单元包括：
基于互联装置中与当前读指令的ID相同的读指令的数量和/或缓存单元空闲寄存器是否为空闲状态，将当前读指令路由到同ID排序缓存单元。
通过以下步骤对本实施例中的路由过程进行说明：
S1、基于互联装置中与当前读指令的ID相同的读指令的数量和/或缓存单元空闲寄存 器是否为空闲状态；
S2、若是互联装置中包含一个与当前读指令的ID相同的读指令，则判断缓存单元空闲寄存器是否为空闲状态；
S3、若是互联装置中包含多个与当前读指令的ID相同的读指令，则对比互联装置中与当前读指令的ID相同的读指令数量与同ID排序缓存单元的深度，并基于对比结果判断是否将当前读指令路由到同ID排序缓存单元。
步骤S2具体包括如下步骤：
S201、若是缓存单元空闲寄存器为空闲状态，则将当前读指令的ID赋值给缓存单元排序寄存器，并将缓存单元空闲寄存器配置为非空闲状态；
S203、配置滞外寄存器以将当前读指令标记为滞外指令；
S205、将当前读指令路由到同ID排序缓存单元。
步骤S2还包括如下步骤：
S207、若是缓存单元空闲寄存器为非空闲状态，则对比当前读指令的ID和缓存单元排序寄存器的值是否相同；
S209、若是当前读指令的ID和缓存单元排序寄存器的值相同，则将当前读指令路由到同ID排序缓存单元；
S211、若是当前读指令的ID和缓存单元排序寄存器的值不相同，则拉低总线读指令通道的ready信号以暂缓接收当前读指令。
在一些实施方式中，互联装置进一步包括：
若是互联装置中包含一个与当前读指令的ID相同的读指令，则判断缓存单元空闲寄存器是否为空闲状态；
若是缓存单元空闲寄存器为空闲状态，则将当前读指令的ID赋值给缓存单元排序寄存器，并将缓存单元空闲寄存器配置为非空闲状态；
配置滞外寄存器以将当前读指令标记为滞外指令；
将当前读指令路由到同ID排序缓存单元。
在一些实施方式中，仲裁策略包括：
基于滞外寄存器判断互联装置是否包含滞外指令；
若是互联装置包含滞外指令，则输出从设备缓存单元中缓存的读指令；
若是互联装置不包含滞外指令，则轮询输出从设备缓存单元和同ID排序缓存单元中缓存的读指令。
在一些实施方式中，查询结果为互联装置中与当前读指令的ID相同的读指令的数量；
与查询结果相对应值为互联装置中与当前读指令的ID相同的读指令的数量加1。
结合图4，通过具体实施例对本申请的具体实施方式进行说明。
首先对主设备发送读指令到从设备的过程进行举例说明。
主设备发送读指令(包括读指令的ID arid、读地址ar_addr、读突发长度ar_len、读类型ar_burst等)至解码单元。解码单元将读地址与每一个从设备预设的地址空间相比较，确定当前读指令需要路由到的从设备。
在确定当前读指令的目的从设备后，进入读指令ID状态记录单元，读指令ID状态记录单元的RAM的第一端口和第二端口在本实施例中分别用A端口和B端口来相应地表示，读指令ID状态记录单元首先通过RAM的B端口查询互联装置中是否有与当前读指令的ID相同的读指令并输出查询结果。具体过程为将当前读指令的ID arid连接到B端口的地址线RAM_B_ADDR上，同时将RAM的B端口的使能信号拉高，B端口的数据线基于查询结果，输出对应数据RAM_B_DOUT。
若RAM_B_DOUT＝0，则说明在互联装置中没有与当前读指令的ID相同的读指令，读指令ID状态记录单元根据解码单元确定的目的从设备，将其路由到对应的从设备缓存单元中，同时对RAM中记录的同一ID的读指令的数量进行更新。更新的具体过程为：读指令ID状态记录单元通过RAM的A端口进行RAM写操作，将arid的值连接到A端口的地址线RAM_A_ADDR上，拉高写使能，数据输入值1。
若RAM_B_DOUT＝1，则说明在互联装置中有一个与当前读指令的ID相同的读指令，此时进行如下处理和判断：
1)若缓存单元空闲寄存器sort_idle＝1，则将当前读指令其路由到同ID排序缓存单元中，同时对RAM中记录的同一ID的读指令的数量进行更新。更新的具体过程为：通过 RAM的A端口进行RAM写操作，将arid的值连接到A端口的地址线RAM_A_ADDR上，拉高RAM的A端口的写使能RAM_A_WEN，向RAM中写入数据输入值RAM_A_DIN＝RAM_B_DOUT+1＝2。将arid的值赋给缓存单元排序寄存器sort_id，同时将缓存单元空闲寄存器sort_idle改成为0，标志着此缓存排序单元被占用，且缓存的是读指令的ID为sort_id的指令。之后将滞外寄存器out_st改写为1。配置滞外寄存器是为了标记当前互联装置中，在从设备缓存单元和同ID排序缓存单元中包含一条ID相同的读指令，根据缓存时间的先后顺序，在将读指令发送给目的从设备时，优先发送从设备缓从单元中的读指令。
2)若缓存单元空闲寄存器sort_idle＝0，则对比当前arid与sort_id，有以下两种情况：
a)若arid＝sort_id，则将当前读指令路由到sort中，同时对RAM中记录的同一ID的读指令的数量进行更新。更新的具体过程为：通过RAM的A端口进行RAM写操作，将arid的值连接到A端口的地址线RAM_A_ADDR上，拉高RAM的A端口的写使能RAM_A_WEN，向RAM中写入数据输入值RAM_A_DIN＝RAM_B_DOUT+1＝2。
b)若arid！＝sort_id，则将总线读指令通道的ready信号拉低，即由于当前读指令与先前的读指令的ID不同，暂时不接收当前读指令，等待互联装置将先前ID的读指令处理完成后，再接收新的ID的读指令。
3)若sort_depth>RAM_B_DOUT>1，则说明在互联装置中有多个ID相同的读指令，且当前读指令的ID arid一定等于sort_id，此时将当前读指令路由到sort中，同时对RAM中记录的同一ID的读指令的数量进行更新。更新的具体过程为：通过RAM的A端口进行RAM写操作，将arid的值连接到A端口的地址线RAM_A_ADDR上，拉高RAM的A端口的写使能RAM_A_WEN，向RAM中写入数据输入值RAM_A_DIN＝RAM_B_DOUT+1。
4)若此时sort_depth＝RAM_B_DOUT，则说明在互联装置中有多个ID相同的读指令，且缓冲空间已满，此时无法再进行缓存。此时将总线，例如AXI总线，的读指令通道的ready信号拉低，即暂时不接收当前指令。
指令仲裁单元，使用自定义的仲裁策略，将从设备缓存单元或同ID排序缓存单元中的读指令输出到对应的从设备。
仲裁策略采用固定优先级和轮训仲裁的两种模型相结合的方式。具体如下：
当滞外寄存器out_st为1时，此时仲裁结果始终为输出buffer通道的指令，sort通道的指令保持缓存，不会向后级从设备输出。
当滞外寄存器out_st为0时，此时仲裁结果为buffer通道的指令和sort通道的指令轮询仲裁，向后级从设备输出，即当两个通道同时缓存指令时，两个通道交替选择输出，若只有一个通道有缓存指令，则直接输出此通道指令。
需要说明的是，互联装置中还包括多个寄存器，本实施例仅以用到的部分寄存器进行说明。在主设备发送读指令之前，预先在互联装置中配置滞外寄存器、缓存单元排序寄存器、缓存单元空闲寄存器，例如，将滞外寄存器设置为1表示互联装置中存在滞外指令，设置为0表示互联装置中不存在滞外指令；缓存单元排序寄存器用于记录同ID的读指令的数量，初始值为0；缓存单元空闲寄存器设置为0表示同ID排序缓存单元被占用，缓存单元空闲寄存器设置为1表示同ID排序缓存单元为空闲状态。以上本实施例中仅为对滞外寄存器、缓存单元排序寄存器、缓存单元空闲寄存器的配置举例，但不限于此，用户可以根据实际应用场景自由定义。
下面对从设备接收到读指令后返回对应的数据到主设备的过程进行说明。
从设备在接收到读指令后，返回读指令对应的数据，并依次通过ID解码单元Decoder_ID、读数据缓存单元Buffer_D将数据返回到主设备，读指令完成信号生成单元Comp完成一个读指令对应的读数据全部返回主设备后生成对应的完成信号。具体过程如下：
rlast为一次读操作的最后一个数据的标志信号，rvalid为读操作的数据有效标志，rid为读数据通道返回id，rid与主机发出的读指令的ID相同。
当主设备从缓存单元中读取返回数据完成了，返回到后，读指令完成信号生成单元Comp将完成寄存器comp_done的值改写为1，并生成对应的完成指令ID comp_id，comp_id＝arid(返回的数据对应的读指令的ID)。
comp_done置为1表示一次读指令执行完成，只拉高一个时钟周期。
将comp_id返回至读指令ID状态记录单元，RAM的B端口查询互联装置中与comp_id相同ID的读指令的数量，并输出查询结果RAM_B_DOUT。之后进行如下判 断：
1)若comp_id＝sort_id，表示返回的为当前ID的读指令对应的数据。此时若RAM_B_DOUT＝1，对RAM中记录的当前ID的读指令的数量进行更新，即将B端口读出的数据减1后再通过A端口写入，具体为：RAM_A_DIN＝RAM_B_DOUT-1＝0，RAM_A_ADDR＝comp_id，RAM_A_WEN＝1。同时将缓存单元空闲寄存器sort_idle改写为1，标志着同ID排序缓存单元中当前ID的读指令即将全部读完，可以再接收其他ID的指令。若RAM_B_DOUT>1，对RAM中记录的当前ID的读指令的数量进行更新，即将B端口读出的数据减1后再通过A端口写入，具体为：RAM_A_DIN＝RAM_B_DOUT-1，RAM_A_ADDR＝comp_id，RAM_A_WEN＝1。此时将滞外寄存器out_st改写为0，但不改变sort_idle状态。
2)若comp_id！＝sort_id，表示返回的不是当前ID的读指令对应的数据。此时将B端口读出的数据减1后(即为0)再通过A端口写入，即将RAM_A_DIN＝0，RAM_A_ADDR＝comp_id,RAM_A_WEN＝1。
本申请至少具有以下有益技术效果：避免了由于总线自身的超前传输和乱序机制导致的数据错误、或主从设备间形成死循环等问题，提高了总线数据传输时读指令及其返回数据的准确性，且保证了读指令及其返回数据在总线上的高速传输。
本领域技术人员还将明白的是，结合这里的公开所描述的各种示例性逻辑块、模块、电路可以被实现为电子硬件、计算机软件或两者的组合。为了清楚地说明硬件和软件的这种可互换性，已经就各种示意性组件、方块、模块、电路和步骤的功能对其进行了一般性的描述。这种功能是被实现为软件还是被实现为硬件取决于具体应用以及施加给整个系统的设计约束。本领域技术人员可以针对每种具体应用以各种方式来实现的功能，但是这种实现决定不应被解释为导致脱离本申请实施例公开的范围。
以上是本申请公开的示例性实施例，但是应当注意，在不背离权利要求限定的本申请实施例公开的范围的前提下，可以进行多种改变和修改。根据这里描述的公开实施例的方法权利要求的功能、步骤和/或动作不需以任何特定顺序执行。上述本申请实施例公开实施例序号仅仅为了描述，不代表实施例的优劣。此外，尽管本申请实施例公开的元素可以以个体形式描述或要求，但除非明确限制为单数，也可以理解为多个。
应当理解的是，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一 个”旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本申请实施例公开的范围(包括权利要求)被限于这些例子；在本申请实施例的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，并存在如上的本申请实施例的不同方面的许多其它变化，为了简明它们没有在细节中提供。因此，凡在本申请实施例的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本申请实施例的保护范围之内。

Claims (20)

  1. 一种用于总线的互联装置，其特征在于，包括：
    解码单元，所述解码单元配置为根据主设备发送的读指令确定所述读指令对应的从设备；
    读指令ID状态记录单元，所述读指令ID状态记录单元包括存储器，所述读指令ID状态记录单元配置为响应于所述解码单元确定所述对应的从设备，基于存储器的第二端口查询互联装置中是否存在与当前读指令的ID相同的读指令；和
    所述读指令ID状态记录单元还配置为基于查询结果将所述当前读指令路由到对应从设备的从设备缓存单元或同ID排序缓存单元，并基于存储器的第一端口向所述存储器写入对应的值，其中，所述值与所述查询结果相对应。
  2. 根据权利要求1所述的装置，其特征在于，所述解码单元进一步配置为根据主设备发送的读指令的地址和从设备预设的地址空间进行指令路由方向的选择，以确定所述读指令对应的从设备。
  3. 根据权利要求2所述的装置，其特征在于，所述解码单元进一步配置为将接收到的所述读指令的读地址与每一个从设备预设的地址空间相比较，确定所述读指令需要路由到的从设备。
  4. 根据权利要求1所述的装置，其特征在于，所述读指令ID状态记录单元进一步配置为若是所述存储器的第二端口查询到所述互联装置中不存在与所述当前读指令的ID相同的读指令，则将所述当前读指令路由到对应从设备的从设备缓存单元，并基于所述存储器的第一端口向所述存储器写入与所述查询结果相对应的值。
  5. 根据权利要求4所述的装置，其特征在于，所述读指令ID状态记录单元进一步配置为对存储器中记录的同一ID的读指令的数量进行更新。
  6. 根据权利要求5所述的装置，其特征在于，所述对存储器中记录的同一ID的读指令的数量进行更新，包括：
    所述读指令ID状态记录单元通过存储器的第一端口进行RAM写操作，将读指令的ID值连接到第一端口的地址线RAM_A_ADDR上，拉高写使能。
  7. 根据权利要求1所述的装置，其特征在于，所述读指令ID状态记录单元进一步 配置为若是所述存储器的第二端口查询到所述互联装置中存在与所述当前读指令的ID相同的读指令，则将所述当前读指令路由到所述同ID排序缓存单元，并基于所述存储器的第一端口向所述存储器写入与所述查询结果相对应的值。
  8. 根据权利要求7所述的装置，其特征在于，所述读指令ID状态记录单元进一步配置为若缓存单元空闲寄存器sort_idle＝1，则将所述当前读指令路由到所述同ID排序缓存单元中，同时对存储器中记录的同一ID的读指令的数量进行更新。
  9. 根据权利要求7所述的装置，其特征在于，所述读指令ID状态记录单元进一步配置为若缓存单元空闲寄存器sort_idle＝0，则对比当前读指令的arid值与所述缓存单元空闲寄存器的sort_id，若arid＝sort_id，则将所述当前读指令路由到所述同ID排序缓存单元中，同时对存储器中记录的同一ID的读指令的数量进行更新，若arid！＝sort_id，则将总线读指令通道的ready信号拉低。
  10. 根据权利要求7所述的装置，其特征在于，所述读指令ID状态记录单元进一步配置为若所述同ID排序缓存单元的深度sort_depth大于所述当前读指令的ID相同的读指令的数量RAM_B_DOUT，且RAM_B_DOUT>1，将所述当前读指令路由到所述同ID排序缓存单元中，同时对存储器中记录的同一ID的读指令的数量进行更新。
  11. 根据权利要求7所述的装置，其特征在于，所述读指令ID状态记录单元进一步配置为若此时所述同ID排序缓存单元的深度sort_depth等于所述当前读指令的ID相同的读指令的数量RAM_B_DOUT，将总线的读指令通道的ready信号拉低。
  12. 根据权利要求1所述的装置，其特征在于，还包括指令仲裁单元，所述指令仲裁单元配置为基于仲裁策略将缓存在所述从设备缓存单元和/或所述同ID排序缓存单元中的读指令传输到从设备。
  13. 根据权利要求1至12任一项所述的装置，其特征在于，还包括：
    ID解码单元，所述ID解码单元配置为根据从设备返回的数据对应的读指令的ID将所述数据缓存到对应的读数据缓存单元，其中，所述读数据缓存单元与所述主设备一一对应；和
    读指令完成信号生成单元，所述读指令完成信号生成单元配置为从所述读数据缓存单元读取数据返回给所述主设备，并在所述数据返回完成后生成读指令执行完成标志和所述数据对应的完成指令ID。
  14. 根据权利要求13所述的装置，其特征在于，所述读指令完成信号生成单元进一步配置为将所述完成指令ID发送到所述读指令ID状态记录单元；
    所述读指令ID状态记录单元还配置为接收到所述完成指令ID后基于所述存储器的第二端口查询所述互联装置中与所述完成指令ID相同的读指令的数量；
    对比所述完成指令ID和缓存单元排序寄存器的值是否相同；和
    基于对比结果和所述存储器的第二端口的完成指令ID查询结果，通过所述存储器的第一端口向所述存储器写入与所述完成指令ID查询结果相对应的值。
  15. 根据权利要求7所述的装置，其特征在于，将所述当前读指令路由到所述同ID排序缓存单元包括：
    基于所述互联装置中与所述当前读指令的ID相同的读指令的数量和/或缓存单元空闲寄存器是否为空闲状态，将所述当前读指令路由到所述同ID排序缓存单元。
  16. 根据权利要求15所述的装置，其特征在于，进一步包括：
    若是所述互联装置中包含一个与所述当前读指令的ID相同的读指令，则判断缓存单元空闲寄存器是否为空闲状态；
    若是所述缓存单元空闲寄存器为空闲状态，则将所述当前读指令的ID赋值给缓存单元排序寄存器，并将所述缓存单元空闲寄存器配置为非空闲状态；
    配置滞外寄存器以将所述当前读指令标记为滞外指令；和
    将所述当前读指令路由到同ID排序缓存单元。
  17. 根据权利要求16所述的装置，其特征在于，进一步包括：
    若是缓存单元空闲寄存器为非空闲状态，则对比当前读指令的ID和缓存单元排序寄存器的值是否相同；
    若是当前读指令的ID和缓存单元排序寄存器的值相同，则将当前读指令路由到同ID排序缓存单元；和
    若是当前读指令的ID和缓存单元排序寄存器的值不相同，则拉低总线读指令通道的ready信号以暂缓接收当前读指令。
  18. 根据权利要求15所述的装置，其特征在于，进一步包括：
    若是互联装置中包含多个与当前读指令的ID相同的读指令，则对比互联装置中与当前读指令的ID相同的读指令数量与同ID排序缓存单元的深度，并基于对比结果判断是否将当前读指令路由到同ID排序缓存单元。
  19. 根据权利要求12所述的装置，其特征在于，所述仲裁策略包括：
    基于滞外寄存器判断所述互联装置是否包含滞外指令；
    若是所述互联装置包含滞外指令，则输出所述从设备缓存单元中缓存的读指令；和
    若是所述互联装置不包含滞外指令，则轮询输出所述从设备缓存单元和所述同ID排序缓存单元中缓存的读指令。
  20. 根据权利要求1所述的装置，其特征在于，所述查询结果为所述互联装置中与所述当前读指令的ID相同的读指令的数量；
    与所述查询结果相对应的所述值为所述互联装置中与所述当前读指令的ID相同的读指令的数量加1。
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