WO2023159685A1 - 休眠控制方式和休眠控制电路 - Google Patents
休眠控制方式和休眠控制电路 Download PDFInfo
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- WO2023159685A1 WO2023159685A1 PCT/CN2022/080483 CN2022080483W WO2023159685A1 WO 2023159685 A1 WO2023159685 A1 WO 2023159685A1 CN 2022080483 W CN2022080483 W CN 2022080483W WO 2023159685 A1 WO2023159685 A1 WO 2023159685A1
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- 230000007958 sleep Effects 0.000 title claims abstract description 56
- 230000005540 biological transmission Effects 0.000 claims abstract description 640
- 230000003993 interaction Effects 0.000 claims abstract description 17
- 230000005059 dormancy Effects 0.000 claims description 132
- 230000002452 interceptive effect Effects 0.000 claims description 82
- 238000000034 method Methods 0.000 claims description 27
- 230000003111 delayed effect Effects 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 108010001267 Protein Subunits Proteins 0.000 claims 1
- 230000008667 sleep stage Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 238000012546 transfer Methods 0.000 description 5
- 238000005265 energy consumption Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present disclosure relates to the field of semiconductor circuit design, in particular to a dormancy control method and a dormancy control circuit.
- DRAM Dynamic Random Access Memory
- DRAM has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, and is suitable as a storage device for mobile devices.
- An embodiment of the present disclosure provides a sleep control method, which is applied to a data transmission circuit, including: the data transmission circuit includes: at least two data transmission structures; each data transmission structure includes a storage transmission end, a bus transmission end, and an interactive transmission end, Among them, the storage transmission end is used to connect the storage area, the bus transmission end is used to connect the data bus, and the interactive transmission end is used to connect another data transmission structure; in the sleep stage, the dormant data is transmitted to the data bus; the bus transmission end is connected to the storage The transmission end turns on the sending end of the interactive transmission end, and turns off the receiving end of the interactive transmission end, so that the data input from the bus transmission end is output through the storage transmission end and the interactive transmission end.
- the sleep data transmitted to the data bus is high-level data.
- the storage transmission end includes: a first transmission end and a second transmission end, the first transmission end and the second transmission end are connected to the same storage area, and the first transmission end is used to transmit low-order data, and the second transmission end is used to transmit high-order data.
- the bus transmission end includes: the fifth transmission end and the sixth transmission end, the fifth transmission end is used for data interactive transmission between the data transmission structure and the data bus, and the sixth transmission end is used for the data transmission structure to the data bus
- the interactive transmission end includes: the seventh transmission end and the eighth transmission end, and the seventh transmission end and the eighth transmission end are used for data interactive transmission between two data transmission structures
- the sending end of the second transmission end; the sending end of the seventh transmission end and the sending end of the eighth transmission end are turned on, and the receiving end of the seventh transmission end and the receiving end of the eighth transmission end are turned off.
- the storage transmission end also includes: a third transmission end and a fourth transmission end, the third transmission end and the fourth transmission end are connected to the same storage area, the first transmission end and the third transmission end are connected to different storage areas, and the third transmission end The end is used to transmit low-order data, and the fourth transmission end is used to transmit high-order data; the bus transmission end and the storage transmission end are turned on, the sending end of the interactive transmission end is turned on, and the receiving end of the interactive transmission end is turned off at the same time. It also includes: turning on the first The sender of the third transfer end and the sender of the fourth transfer end.
- the first transmission end and the second transmission end are used for data interaction with the data bus connected to different data transmission structures; in the sleep phase, the first transmission end and the second transmission end are used to send the data
- the dormant data input by the data bus connected to the transmission structure; in the working stage, the first transmission end and the third transmission end alternately perform data transmission, the second transmission end and the fourth transmission end alternately perform data transmission, and the first transmission end and the second transmission end alternately perform data transmission.
- the transmitting end performs data transmission at the same time, and the third transmitting end and the fourth transmitting end perform data transmission at the same time; in the dormant stage, the first transmitting end, the second transmitting end, the third transmitting end and the fourth transmitting end simultaneously perform data transmission.
- the data transmission structure includes: an input unit for receiving dormancy data and a dormancy input control signal, configured to input dormancy data based on the dormancy input control signal; an output unit for receiving dormancy data and a dormancy output control signal, It is configured to output the dormancy data based on the dormancy output control signal; the latch unit is connected to the output unit and is used for latching the dormancy data output by the output unit.
- the input unit includes: a plurality of input controllers, each input controller corresponds to a bus transmission end or an interactive transmission end, and each input controller receives dormant data; each input controller is used to receive the corresponding bus transmission end Or the dormancy input control signal of the interactive transmission end; in the dormancy stage, based on the dormancy input control signal, the input controller corresponding to the bus transmission end is turned on.
- the output unit includes: a plurality of output controllers, each output controller corresponds to a storage transmission end or an interactive transmission end, and each output controller receives dormant data; each output controller is used to receive a corresponding storage transmission end or the dormant output control signal of the interactive transmission end; in the dormant stage, based on the dormant output control signal, the output controllers corresponding to the storage transmission end and the interactive transmission end are turned on.
- the latch unit includes: a first inverter and a second inverter connected end to end, and the input end of the first inverter and the output end of the second inverter are connected in parallel with the output end of the output unit.
- the data transmission structure further includes: an input selection unit, configured to receive the dormancy input control signal, configured to generate a strobe corresponding to the dormancy input control signal, the strobe pulse corresponding to the effective port represented by the dormancy input control signal Corresponding, and there is a selection delay between the strobe pulse and the dormancy input control signal; the trigger unit, the clock terminal is connected to the input selection unit, the input terminal is connected to the input unit, and the output terminal is connected to the output unit, and is configured to, based on the strobe pulse, output Dormant data.
- an input selection unit configured to receive the dormancy input control signal, configured to generate a strobe corresponding to the dormancy input control signal, the strobe pulse corresponding to the effective port represented by the dormancy input control signal Corresponding, and there is a selection delay between the strobe pulse and the dormancy input control signal
- the trigger unit the clock terminal is connected to the input selection unit, the input terminal is connected
- the input selection unit includes: a trigger subunit for receiving the dormancy input control signal, and generating an indication signal if the dormancy input control signal is received; a delay subunit connected to the trigger subunit for delaying the indication signal; The conversion subunit is connected with the delay subunit, and is used for converting the delayed indication signal into a strobe pulse.
- the trigger unit is composed of D flip-flops.
- a dormancy control circuit which is applied to the above dormancy control method, including: a data providing unit configured to, in the dormancy phase, send dormancy data to a data bus; a first data control unit configured to In the dormant phase, the storage transmission end and the bus transmission end are turned on, the data transmission circuit is controlled to receive the dormancy data transmitted by the data bus, and send the dormancy data to the storage area; the second data control unit is configured to, in the dormancy phase, Turning on the interactive transmission end, controlling the data transmission structure to send dormancy data to another data transmission structure, and refusing to receive the dormancy data sent by another data transmission structure.
- the first data control unit includes: a first data receiving subunit, used to receive the dormancy input control signal and a dormancy output control signal; a first control unit, connected to the first data receiving subunit, for receiving the dormancy input control signal
- the bus transmission end is turned on, and the storage transmission end is turned on according to the sleep output control signal.
- the second data control unit includes: a second data receiving subunit for receiving the dormancy input control signal and a dormancy output control signal; a second control unit connected to the second data receiving subunit for outputting the control signal according to the dormancy Turn on the sending end of the interactive transmission end, and turn off the receiving end of the interactive transmission end according to the dormancy input control signal.
- FIG. 1 is a schematic structural diagram of a refresh circuit provided by an embodiment of the present disclosure
- Fig. 2 is a schematic structural diagram of a preprocessing module provided by an embodiment of the present disclosure
- Fig. 3 is a schematic structural diagram of a counting unit provided by an embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of an address processing module provided by an embodiment of the present disclosure.
- FIG. 5 is a schematic structural diagram of a storage judgment module and a processing output module provided by an embodiment of the present disclosure
- FIG. 6 is a schematic flowchart of a sleep control method provided by an embodiment of the present disclosure.
- FIG. 7 is a schematic diagram of a circuit structure used in a sleep phase of a data transmission circuit provided by an embodiment of the present disclosure.
- the present disclosure provides a data transmission circuit; in addition, an embodiment of the present disclosure provides a sleep control method, aiming at improving the data transmission circuit for reading and writing data transmission efficiency of the memory, providing a data transmission circuit sleep control mode.
- Fig. 1 is a schematic structural diagram of a data transmission circuit provided in this embodiment
- Fig. 2 is a schematic structural diagram of a control module provided in this embodiment
- Fig. 3 is a schematic diagram of a specific connection mode of a data transmission structure provided in this embodiment
- Fig. 4 is a schematic diagram of the specific structure of the data transmission structure when data is read in this embodiment
- FIG. 5 is a schematic diagram of the specific structure of the data transmission structure when data is written in this embodiment
- FIG. 6 is a sleep control method provided by this embodiment
- Fig. 7 is a schematic diagram of the circuit structure used by the data transmission circuit provided by this embodiment in the dormant phase.
- the dormancy control method provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
- the data transmission circuit is applied to a memory, and the memory includes a data bus 103 and a plurality of storage areas 102 for improving the read and write data transmission efficiency of the memory, specifically including: at least two data transmission structures 101 .
- Each data transmission structure includes a storage transmission end 111, a bus transmission end 112 and an interactive transmission end 113, wherein the storage transmission end 111 is used for connecting the storage area 102, the bus transmission end 112 is used for connecting the data bus 103, and the interactive transmission end 113 is used for For connecting to another data transfer structure.
- the data input from the storage transmission terminal 111 is output through the bus transmission terminal 112 or output through the interactive transmission terminal 113, and the data input from the bus transmission terminal 112 is output through the storage transmission terminal 111 or output through the interactive transmission terminal 113,
- the data input from the interactive transmission terminal 113 is output through the bus transmission terminal 112 or the storage transmission terminal 111, and the data input from the interactive transmission terminal 113 is input by the bus transmission terminal 112 or the storage transmission terminal 111 in another data transmission structure 101 the data;
- the control module 104 is connected to the data transmission structure 101, and receives the input control signal and the adjustment control signal provided by the associated memory.
- the dormancy control method includes step 10 (in the dormancy phase, controlling the data bus to transmit dormancy data) and step 20 (controlling the dormancy data to be written into the data transmission structure through the bus transmission end, and through the storage transmission end and the interaction The output of the transport port, and the control data transfer structure does not accept the dormant data input through the interactive transport port).
- step 10 in the sleep phase, transmit dormant data to the data bus 103, so that the data bus 103 transmits dormant data; for step 20, turn on the bus transmission end 112 and the storage transmission end 111, and turn on the interactive transmission end 113 and close the receiving end of the interactive transmission end 113, so that the data input from the bus transmission end 112 is output through the storage transmission end 111 and the interactive transmission end 113.
- the dormant data transmitted on the data bus 103 is written into the storage transmission end 111, and by turning on the sending end of the interactive transmission end 112, the dormancy data transmitted on the data bus 103 is made Data can be transmitted to the interactive transmission end 112, so that the storage transmission end 111, the bus transmission end 112 and the interactive transmission end 113 of the data transmission structure 101 all transmit dormant data to realize sleep; in addition, by closing the receiving end of the interactive transmission end 113, That is, while the interactive transmission terminal 113 is transmitting dormancy data, the data transmission structure 101 does not receive the dormancy data sent by another data transmission structure 101, that is, it is guaranteed that the writing of dormant data in the data transmission structure 101 is only realized through the bus transmission terminal 112 , to avoid timing disorder of the input data of the data transmission structure 101 in the sleep mode.
- the dormant data transmitted to the data bus 103 is high-level data, that is, in the dormant phase, the storage transmission end 111, the bus transmission end 112 and the interactive transmission end 113 are set high; in other implementations
- the dormancy data transmitted to the data bus 103 is low-level data, that is, in the dormancy stage, the storage transmission end 111, the bus transmission end 112 and the interaction transmission end 113 are set low to further reduce power consumption.
- control module 104 is configured to, based on the adjustment control signal, delay the output of the input control signal to generate an output control signal corresponding to the input control signal, and the input control signal and The output control signal is used to indicate the data transmission path of the data transmission structure 101 .
- the adjustment control signal is generated based on the memory belonging to the data transmission circuit, and is used to control the delay between the corresponding input control signal and output control signal.
- the data transmission paths of the two data transmission structures 101 are controlled by the control module 104, so that different data transmission structures can transmit data at the same time, corresponding to the same data transmission structure 101, the data transmission of different storage areas 102 can be realized alternately, making the data transmission more compact , thereby improving the data transfer efficiency of the memory.
- the number of data transmission structures can be any even number greater than 2, and the data transmission circuit is formed between two data transmission structures, so as to further improve the data transmission efficiency of the memory.
- the signal delay between the input control signal and the output control signal is controlled by the adjustment control signal, which is beneficial to avoid opening the output terminal earlier or later than the preset timing, and ensure that the data transmission structure accurately outputs the corresponding input data.
- the storage transmission end 111 includes: a first transmission end A and a second transmission end B, the first transmission end A and the second transmission end B are connected to the same storage area, and the first transmission end A and the second transmission end B are connected to the same storage area, and the first transmission end A
- the transmission end A is used to transmit low-order data
- the second transmission end B is used to transmit high-order data
- the bus transmission end 112 includes: the fifth transmission end E and the sixth transmission end F
- the interactive transmission end 113 includes: the seventh transmission end G and The eighth transmission terminal H; wherein, the fifth transmission terminal E is used for data interactive transmission between the data transmission structure 101 and the data bus 103, and the sixth transmission terminal F is used for one-way transmission from the data transmission structure 101 to the data bus 103 Data transmission;
- the seventh transmission terminal G and the eighth transmission terminal H are used for data interactive transmission between two data transmission structures 101 .
- both the seventh transmission terminal G and the eighth transmission terminal H can be used for data interactive transmission between two data transmission structures 101;
- the right data transmission structure transmits data through the seventh transmission terminal, and the right data transmission structure transmits data to the left data transmission structure through the eighth transmission terminal.
- turn on the bus transmission end 112 and the storage transmission end 111 turn on the sending end of the interactive transmission end 113, and turn off the receiving end of the interactive transmission end 113, including: turn on the receiving end of the fifth transmission end E, turn on Turn on the sending end of the sixth transmission end F, turn on the sending end of the first transmission end A and the sending end of the second transmission end B, turn on the sending end of the seventh transmission end G and the sending end of the eighth transmission end H, And close the receiving end of the seventh transmitting end G and the receiving end of the eighth transmitting end H.
- the left data transmission structure transmits data to the right data transmission structure through the seventh transmission end
- the right data transmission structure transmits data to the left data transmission structure through the eighth transmission end.
- For the data transmission structure on the left turn on the sending end of the seventh transmission end end, and turn off the receiving end of the eighth transmission end; for the data transmission structure on the right, turn on the sending end of the eighth transmission end, and turn off the receiving end of the seventh transmission end.
- the storage transmission end 111 further includes: a third transmission end C and a fourth transmission end D, the third transmission end C and the fourth transmission end D are connected to the same storage area, the first transmission end A and the third transmission end The transmission terminal C is connected to different storage areas, and the third transmission terminal is used to transmit low-order data, and the fourth transmission terminal is used to transmit high-order data.
- the first transmission terminal A and the second transmission terminal B can be used to transmit the high-order data and low-order data of the same data, for example, for the transmission of 16-bit data, the first transmission terminal A is used to transmit the low-order 8 bits data, the second transmission terminal B is used to transmit high 8-bit data; the first transmission terminal A and the second transmission terminal B can also be used to transmit different data, for example, for the transmission of 8-bit data, the first transmission terminal A and the second transmission terminal B are used to transmit different data.
- the first transmission terminal A and the second transmission terminal B are respectively used for data interaction with the data bus 103 connected to different data transmission structures 101;
- the second transmission terminal B is used to send the dormant data input by the data bus 103 connected to the data transmission structure 101;
- the first transmission terminal A and the third transmission terminal C perform data transmission alternately, and the second transmission terminal B and the fourth transmission terminal B
- the transmission terminal D performs data transmission alternately, the first transmission terminal A and the second transmission terminal B perform data transmission at the same time, and the third transmission terminal C and the fourth transmission terminal D perform data transmission at the same time; in the dormant stage, the first transmission terminal A, The second transmission end B, the third transmission end C and the fourth transmission end D simultaneously transmit data.
- the input control signals include: Sel A, Sel B, Sel C, Sel D, Sel E, Sel F, Sel G, and Sel H;
- the output control signals include: Drv A , Drv B, Drv C, Drv D, Drv E, Drv F, Drv G, and Drv H.
- the input control signal corresponding to the first transmission terminal A is Sel A, and the output control signal is Drv A;
- the input control signal corresponding to the second transmission terminal B is Sel B, and the output control signal is Drv B;
- the third transmission terminal C corresponds to The input control signal is Sel C, the output control signal is Drv C;
- the input control signal corresponding to the fourth transmission terminal D is Sel D, and the output control signal is Drv D;
- the input control signal corresponding to the fifth transmission terminal E is Sel E,
- the output control signal is Drv E;
- the input control signal corresponding to the sixth transmission terminal F is Sel F, and the output control signal is Drv F;
- the input control signal corresponding to the seventh transmission terminal G is Sel G, and the output control signal is Drv G;
- the input control signal corresponding to the eight transmission terminals H is Sel H, and the output control signal is Drv H.
- the data transmission structure 101 includes: an input unit 201, configured to receive at least one input data and an input control signal, configured to, based on the input control signal, output an input corresponding to the input control signal data.
- the output unit 203 is configured to receive the input data output by the input unit 201 and at least one output control signal, and is configured to output the input data based on a valid port represented by the output control signal.
- the latch unit 204 is connected to the output unit 203 and is used for latching the input data output by the output unit 203 .
- the data transmission structure 101 includes: an input unit 201 for receiving dormancy data XM and dormancy input control signal KR, configured to input dormancy data XM based on dormancy input control signal KR.
- the output unit 203 is configured to receive the sleep data XM and the sleep output control signal KC, and is configured to output the sleep data XM based on the sleep output control signal KC.
- the latch unit 204 is connected to the output unit 203 and is used for latching the dormancy data XM output by the output unit 203 .
- the input unit 201 includes: a plurality of input controllers 211, each input controller 211 corresponds to the storage transmission end 111, the bus transmission end 112 or the interaction transmission end 113; each input controller 211 is used to receive the corresponding The input data and the input control signal of the storage transmission end 111, the bus transmission end 112 or the interactive transmission end 113 are configured, and the input controller 211 is configured to turn on the corresponding port based on the input control signal to output the input data of the corresponding port.
- the read data is read from the data transmission structure 101 connected by the first transmission terminal A, the second transmission terminal B, the third transmission terminal C or the fourth transmission terminal D.
- the data in the storage area can also be read out from the storage area connected to another data transmission structure 101 through the seventh transmission terminal G and the eighth transmission terminal H.
- the input data Data A of the first transmission terminal A is connected to an input controller 211, and the input controller is controlled by the input control signal Sel A, and when the input control signal Sel A is received, the input data Data A of the first transmission terminal A is output.
- the input data Data B of the second transmission terminal B is connected to an input controller 211, the input controller is controlled by the input control signal Sel B, and when the input control signal Sel B is received, the input data Data of the second transmission terminal B is output B
- the input data Data C of the third transmission terminal C is connected to an input controller 211, the input controller is controlled by the input control signal Sel C, and when the input control signal Sel C is received, the input data Data C of the third transmission terminal C is output C
- the input data Data D of the fourth transmission terminal D is connected to an input controller 211, the input controller is controlled by the input control signal Sel D, and when the input control signal Sel D is received, the input data Data of the fourth transmission terminal D is output D
- the input data Data G of the seventh transmission terminal G is connected to an
- the write data is written into the data transmission structure 101 through the fifth transmission terminal E, and another data transmission can also be written through the seventh transmission terminal G and the eighth transmission terminal H. Write data received by structure 101.
- the input data Data E of the fifth transmission terminal E is connected to an input controller 211, the input controller is controlled by the input control signal Sel E, and when the input control signal Sel E is received, the input data Data E of the fifth transmission terminal E is output E;
- the input data Data G of the seventh transmission terminal G is connected to an input controller 211, the input controller is controlled by the input control signal Sel G, and when the input control signal Sel G is received, the input data Data G of the seventh transmission terminal G is output G;
- the input data Data H of the eighth transmission terminal H is connected to an input controller 211, the input controller is controlled by the input control signal Sel H, and when the input control signal Sel H is received, the input data Data H of the eighth transmission terminal H is output H.
- it also includes a mask unit 202, which is used to generate mask data DM according to the input data Data E of the fifth transmission end E, and the mask data DM is processed by the input controller 211 corresponding to the fifth transmission end E. Input, to realize the selection input of the data on the data bus 103.
- a mask unit 202 which is used to generate mask data DM according to the input data Data E of the fifth transmission end E, and the mask data DM is processed by the input controller 211 corresponding to the fifth transmission end E. Input, to realize the selection input of the data on the data bus 103.
- the memory includes a data mask function and a data inversion function.
- the data mask When the data mask is valid, the corresponding 8-bit data is not written. To save power, reverse the written 8-bit data.
- the data mask (DM) and data bus inversion (DBI) functions are turned on at the same time, since both the data mask signal and the data bus inversion signal need to use the same data port, only one input can be selected.
- This disclosure selects the input data inversion signal, that is to say, when data is written, the input data and the data inversion signal are transmitted to the data transmission structure together.
- the valid data inversion signal When the data inversion signal is valid, the input data Data E representing synchronous input Inversion is required, because there is no need for inversion if the input data Data E is not written, therefore, the valid data inversion signal also indicates that the input data Data E needs to be written; when the data inversion signal is invalid, if the input data For normal input, 0s should account for the majority of the input data. That is to say, when the data inversion signal is invalid, it is necessary to detect whether 0s account for half or more of the input data. Turn and input normally, if 0 accounts for a minority and 1 accounts for a majority, it means that the input data at this time indicates that the data mask signal is valid, and the corresponding 8-bit input data is masked and not stored in the storage array.
- the fifth transmission terminal E receives the 8-bit original data to be written, and the inversion unit 207 receives the inversion control signal DBI, and the inversion control signal DBI at this time represents the data inversion signal Effective, for example, the inversion control signal DBI is 1, and the data input by the input unit 201 is inverted to be output to the output unit 203; when the data inversion signal is invalid, it is determined according to the content of Data E that the fifth transmission terminal E receives the data to be written.
- the 8-bit original data or mask data DM input specifically, when the data inversion signal is invalid, the input and output Data E is compiled by the mask unit 202 to judge whether the data mask signal is valid (assuming that it is 1 effectively, invalid is 0), if the data mask DM is valid, it means that the 8-bit original data does not need to be written.
- the fifth transmission terminal E receives the mask data DM. If the data mask DM is invalid, it means that the 8-bit original data needs to be written. Write, at this time, the fifth transmission terminal E receives the input data Data E.
- any data transmission structure only inverts the data input by the corresponding fifth transmission terminal E, that is, when writing data, the inversion control subunit 221 receives the inversion control signal DBI will only be the input data Data
- the inverting control signal corresponding to E is not the inverting control signal corresponding to the input data Data G and Data H. This is because for the data input by the seventh input terminal Sel G and the eighth input terminal Sel H, that is, the data input by the data bus 103 through another data transmission structure, the input data is at the inverting unit 207 of another data transmission structure.
- the above data inversion process has been completed in .
- the input unit 201 includes: a plurality of input controllers 211, each input controller corresponds to the bus transmission end 112 or the interactive transmission end 113, and each input controller 211 receives the dormancy data XM; Each input controller 211 is used for receiving the dormancy input control signal KR corresponding to the bus transmission end 112 or the interactive transmission end 113; in the dormancy phase, based on the dormancy input control signal KR, the input controller 211 corresponding to the bus transmission end is turned on.
- the dormancy input control signal KR is transmitted to the fifth transmission terminal E, the seventh transmission terminal G and the eighth transmission terminal H to turn on the fifth transmission terminal E and turn off the seventh transmission terminal G and the eighth transmission terminal H , so that the dormant data XM is written into the data transmission structure 101 from the data bus 103 through the fifth transmission terminal E. Since the seventh transmission terminal G and the eighth transmission terminal H are closed, that is, the receiving end of the interactive transmission terminal 113 is closed, sleep The data XM cannot be written into another data transmission structure 101 through the seventh transmission terminal G or the eighth transmission terminal H, so as to avoid data timing confusion.
- the output unit 203 includes: a plurality of output controllers 212, each output controller 212 corresponds to the storage transmission end 111, the bus transmission end 112 or the interaction transmission end 113; each output controller 212 is used to receive the corresponding The input data and the output control signal of the storage transmission end 111 , the bus transmission end 112 or the interactive transmission end 113 are stored, and the output controller 212 is configured to be turned on based on the output control signal to output the input data.
- the read data is read to the data bus 103 through the fifth transmission terminal E or the sixth transmission terminal F, or can be read through the seventh transmission terminal G and the eighth transmission terminal H. output to another data transmission structure 101 , and finally read to another corresponding data bus 103 through the corresponding fifth transmission terminal E or sixth transmission terminal F of another data transmission structure 101 .
- the output controller 212 connected to the fifth transmission terminal E is controlled by the output control signal Drv E, and when the output control signal Drv E is received, the data is output through the fifth transmission terminal E;
- the output controller connected to the seventh transmission terminal G 212 is controlled by the output control signal Drv G, and when the output control signal Drv G is received, the data is output through the seventh transmission terminal G;
- the output controller 212 connected to the eighth transmission terminal H is controlled by the output control signal Drv H, and when received The control signal Drv H is output, and the data is output through the eighth transmission terminal H.
- write data is written into the data transmission structure 101 connected through the first transmission terminal A, the second transmission terminal B, the third transmission terminal C or the fourth transmission terminal D.
- the storage area can also be written into a storage area connected to another data transmission structure 101 through the seventh transmission terminal G and the eighth transmission terminal H.
- the output controller 212 connected to the first transmission terminal A is controlled by the output control signal Drv A, and when the output control signal Drv A is received, the data is output through the first transmission terminal A;
- the output controller connected to the second transmission terminal B 212 is controlled by the output control signal Drv B, and when the output control signal Drv B is received, the data is output through the second transmission terminal B;
- the output controller 212 connected to the third transmission terminal C is controlled by the output control signal Drv C, and when received
- the output control signal Drv C outputs the data through the third transmission terminal C;
- the output controller 212 connected to the fourth transmission terminal D is controlled by the output control signal Drv D, and when the output control signal Drv D is received, the data is transmitted through the fourth transmission terminal Terminal D output;
- the output controller 212 connected to the seventh transmission terminal G is controlled by the output control signal Drv G, and when the output control signal Drv G is received, the data is output through the seventh transmission terminal G;
- the output connected to the eighth transmission terminal H The controller
- the output unit 203 includes: a plurality of output controllers 212, each output controller 212 corresponds to the storage transmission end 111 or the interaction transmission end 113, and each output controller 212 receives the dormancy data XM; each data The controller is used to receive the dormant output control signal KC corresponding to the storage transmission end 111 or the interactive transmission end 113; in the dormant stage, based on the dormancy output control signal KC, the output controller 212 corresponding to the storage transmission end 111 and the interactive transmission end 113 is turned on .
- the sleep output control signal KC is transmitted to the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, the fourth transmission terminal D, the seventh transmission terminal G and the eighth transmission terminal H, To turn on the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, the fourth transmission terminal D, the seventh transmission terminal G and the eighth transmission terminal H, so that the dormant data XM passes through the first transmission terminal A, The output of the second transmission terminal B, the third transmission terminal C, the fourth transmission terminal D, the seventh transmission terminal G and the eighth transmission terminal H are turned on because the seventh transmission terminal G and the eighth transmission terminal H are turned on.
- the dormant data XM is transmitted to another data transmission end through the seventh transmission end G and the eighth transmission end H, so that the interactive transmission end 113 transmits the dormancy data XM.
- the latch unit 204 includes: a first inverter 214 and a second inverter 213 connected end to end, and the input terminal of the first inverter 214 and the output terminal of the second inverter 213 are connected to The output terminals of the output unit 203 are connected in parallel, and the output terminals of the output unit 203 are connected in parallel through the latch unit 204 to realize the preservation of the output data of the output unit 203;
- the latch unit includes: The first inverter and the second inverter are connected, and the first inverter and the input terminal and the output terminal of the second inverter are connected in series with the output port of the input unit, and the output terminal of the output unit is connected through the latch unit connected in series to realize inversion latching of the output data of the output unit, and then to save the output data of the output unit through series connection of inverters.
- the input of the data is delayed to further ensure the accuracy of the data during the multiplex transmission.
- the data transmission structure further includes: an input selection unit 205 and a trigger unit 206 .
- the input selection unit 205 is configured to receive at least one input control signal, and is configured to generate a gate pulse corresponding to the input control signal, the gate pulse corresponds to the effective port represented by the input control signal, and the gate pulse is consistent with There is a selection delay between the input control signals; the trigger unit 206, the clock terminal is connected to the input selection unit 205, the input terminal is connected to the input unit 201, and the output terminal is connected to the output unit 203, and is configured to, based on the strobe pulse, receive the input terminal. The input data is transferred to the output.
- the data transmission structure further includes: an input selection unit 205 and a trigger unit 206 .
- the input selection unit 205 is used to receive the dormancy input control signal KR, specifically, to receive the dormancy input control signal KR_E corresponding to the fifth transmission terminal, the dormancy input control signal KR_G corresponding to the seventh transmission terminal and the eighth transmission terminal Corresponding dormancy input control signal KR_H; the input selection unit 205 is configured to generate a gate pulse corresponding to the dormancy input control signal KR, the gate pulse corresponds to the effective port represented by the dormancy input control signal KR, and the gate pulse and There is a selection delay between the dormancy input control signal KR; the trigger unit 206, the clock end is connected to the input selection unit 205, the input end is connected to the input unit 201, and the output end is connected to the output unit 203, configured to output dormancy data based on the strobe pulse XM.
- the input selection unit 205 includes: a trigger subunit 215, which is used to receive at least one input control signal, and generates an indication signal if an input control signal is received; a delay subunit 216, connected to the trigger subunit 215, for The indication signal is delayed; the conversion subunit 217 is connected to the delay subunit 216, and is used for converting the delayed indication signal into a gate pulse.
- the indication signal is delayed by the delay subunit 216 to ensure that the data transmission structure accurately outputs the corresponding input data; the specific delay parameters of the delay subunit 216 are set based on the associated memory. In some embodiments, the delay subunit 216 The specific delay parameters can be adjusted by the staff.
- the trigger subunit 215 is realized by an OR gate.
- the trigger subunit 215 When data is read, with reference to FIG. , the trigger subunit 215 generates an indication signal based on the active level of the input control signal Sel A, Sel B, Sel C, Sel D, Sel G or Sel H, and after the indication signal is delayed by the delay subunit 216, the conversion subunit 217 Convert to a strobe pulse to drive the trigger unit 206; when data is written, with reference to FIG.
- the effective level of Sel G or Sel H generates an indication signal, and after being delayed by the delay subunit 216, the indication signal is converted into a gate pulse by the conversion subunit 217 to drive the trigger unit 206.
- the input selection unit 205 includes: a trigger subunit 215, configured to receive at least one sleep input control signal KR, specifically, to receive the sleep input control signal KR_E corresponding to the fifth transmission end, and the seventh transmission end corresponding to The dormancy input control signal KR_G and the dormancy input control signal KR_H corresponding to the eighth transmission end; if the trigger subunit 215 receives the dormancy input control signal KR, an indication signal is generated; the delay subunit 216 is connected to the trigger subunit 215 for The indication signal is delayed; the conversion subunit 217 is connected to the delay subunit 216, and is used for converting the delayed indication signal into a gate pulse.
- a trigger subunit 215 configured to receive at least one sleep input control signal KR, specifically, to receive the sleep input control signal KR_E corresponding to the fifth transmission end, and the seventh transmission end corresponding to The dormancy input control signal KR_G and the dormancy input control signal KR_H corresponding to the eighth transmission end
- the indication signal is delayed by the delay subunit 216 to ensure that the data transmission structure accurately outputs the corresponding input data; the specific delay parameters of the delay subunit 216 are set based on the associated memory. In some embodiments, the delay subunit 216 The specific delay parameters can be adjusted by the staff.
- the trigger unit is composed of a D flip-flop.
- the data transmission structure 101 further includes: an inversion unit 207, disposed between the trigger unit 206 and the input unit 201, configured to output the input data or invert the input data based on the inversion control signal After output.
- an inversion unit 207 disposed between the trigger unit 206 and the input unit 201, configured to output the input data or invert the input data based on the inversion control signal After output.
- the data is output directly or after inversion through the inversion unit to reduce the data energy consumption of the data transmission structure 101; specifically, because the low-level energy consumption during data transmission is relatively low Less energy consumption can be saved by transmitting data at a low level.
- the inversion control signal is used to control the data inversion before transmission; If the high-level data is less than the low-level data, the data is directly transmitted through the inversion control signal.
- the inverting unit 207 includes: an inversion control subunit 221 for receiving an inversion control signal, and generating a first control signal and a second control signal based on the inversion control signal; a first selection subunit 222 And the second selection subunit 223, the input terminal is used to receive the input data after parallel connection, and the output terminal is connected to the trigger unit 206; the first selection subunit 222 is configured to, based on the conduction of the first control signal, invert the input data and output ; The second selection subunit 223 is configured to directly output the input data based on the conduction of the second control signal.
- first control signal and the second control signal can be used as two signals to drive the first selection subunit 222 and the second selection subunit 223, or can be used as high and low levels of the same signal to drive the first selection subunit. unit 222 and a second selection subunit 223 .
- the inversion unit 207 further includes: a judging subunit 224 configured to receive input data and generate an inversion control signal based on the input data.
- the signal driving method mentioned in this embodiment is described as an example of whether the signal exists. Drive, that is, the signal exists, and it is driven according to whether the level of the signal is an active level.
- the dormant data transmitted on the data bus can be written into the storage area, and by turning on the sending end of the interactive transmission end, the dormant data transmitted on the data bus can be transmitted to the interactive transmission end , so that the storage transmission end, the bus transmission end and the interactive transmission end of the data transmission structure all transmit dormant data to realize dormancy; in addition, by closing the receiving end of the interactive transmission end, that is, while the interactive transmission end is transmitting dormant data, the data transmission structure does not Do not receive the dormant data sent by another data transmission structure, that is, ensure that the writing of dormant data in the data transmission structure is only realized through the bus transmission end, avoiding the timing confusion of the input data of the data transmission structure in the dormancy mode.
- Another embodiment of the present disclosure provides a sleep control circuit, which is applied to the above embodiment of the sleep control method, and provides a sleep control method for the data transmission circuit for improving the efficiency of data transmission for reading and writing of the memory.
- Sleep control circuitry including:
- the data providing unit is configured to, in the sleep stage, send sleep data to the data bus.
- the first data control unit is configured to, in the dormancy stage, turn on the storage transmission end and the bus transmission end, control the data transmission circuit to receive the dormancy data transmitted by the data bus, and send the dormancy data to the storage area.
- the second data control unit is configured to, in the sleep phase, turn on the interactive transmission end, control the data transmission structure to send sleep data to another data transmission structure, and refuse to receive the sleep data sent by another data transmission structure.
- the first data control unit includes:
- the first data receiving subunit is used for receiving the dormancy input control signal and the dormancy output control signal.
- the first control unit is connected to the first data receiving subunit, and is used for turning on the bus transmission end according to the dormancy input control signal, and turning on the storage transmission end according to the dormancy output control signal.
- the second data control unit includes:
- the second data receiving subunit is used for receiving the dormancy input control signal and the dormancy output control signal.
- the second control unit is connected to the second data receiving subunit, and is used to turn on the sending end of the interactive transmission end according to the dormancy output control signal, and turn off the receiving end of the interactive transmission end according to the dormancy input control signal.
- the dormant data transmitted on the data bus can be written into the storage area, and by turning on the sending end of the interactive transmission end, the dormant data transmitted on the data bus can be transmitted to the interactive transmission end , so that the storage transmission end, the bus transmission end and the interactive transmission end of the data transmission structure all transmit dormant data to realize dormancy; in addition, by closing the receiving end of the interactive transmission end, that is, while the interactive transmission end is transmitting dormant data, the data transmission structure does not Do not receive the dormant data sent by another data transmission structure, that is, ensure that the writing of dormant data in the data transmission structure is only realized through the bus transmission end, avoiding the timing confusion of the input data of the data transmission structure in the dormancy mode.
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Abstract
本公开涉及半导体电路设计领域，特别涉及一种休眠控制方式和休眠控制电路，包括：数据传输电路包括：至少两个数据传输结构(101)；每一数据传输结构(101)包括存储传输端(111)、总线传输端(112)和交互传输端(113)，其中，存储传输端(111)用于连接存储区域(102)，总线传输端(112)用于连接数据总线(103)，交互传输端(113)用于连接另一数据传输结构(101)；在休眠阶段，向数据总线(103)传输休眠数据；导通总线传输端(112)和存储传输端(111)，导通交互传输端(113)的发送端，并关闭交互传输端(113)的接收端，以使得从总线传输端(112)输入的数据，通过存储传输端(111)和交互传输端(113)输出。
Description
交叉引用
本公开要求于2022年02月24日递交的名称为“休眠控制方式和休眠控制电路”、申请号为202210174059.7的中国专利申请的优先权，其通过引用被全部并入本公开。
本公开涉及半导体电路设计领域，特别涉及一种休眠控制方式和休眠控制电路。
动态随机存储存储器(Dynamic Random Access Memory，DRAM)具有数据非易失性、省电、体积小，以及无机械结构等特性，适宜作为移动设备的存储设备。
随着技术的进步，消费者对移动设备的性能要求越来越高，使得存储设备传输速率成为评判存储设备优良的关键参数，如何提高存储器的数据传输效率，是当下技术人员亟待解决的问题。
发明内容
本公开实施例提供了一种休眠控制方式，应用于数据传输电路，包括：数据传输电路包括：至少两个数据传输结构；每一数据传输结构包括存储传输端、总线传输端和交互传输端，其中，存储传输端用于连接存储区域，总线传输端用于连接数据总线，交互传输端用于连接另一数据传输结构；在休眠阶段，向数据总线传输休眠数据；导通总线传输端和存储传输端，导通交互传输端的发送端，并关闭交互传输端的接收端，以使得从总线传输端输入的数据，通过存储传输端和交互传输端输出。
另外，向数据总线传输的休眠数据为高电平数据。
另外，存储传输端包括：第一传输端和第二传输端，第一传输端和第二传输端连接相同存储区域，且第一传输端用于传输低位数据，第二传输端用于 传输高位数据；总线传输端包括：第五传输端和第六传输端，第五传输端用于所属数据传输结构与数据总线之间的数据交互传输，第六传输端用于所属数据传输结构向数据总线的单向数据传输；交互传输端包括：第七传输端和第八传输端，第七传输端和第八传输端用于两个数据传输结构之间的数据交互传输；导通总线传输端和存储传输端，导通交互传输端的发送端，并关闭交互传输端的接收端，包括：导通第五传输端的接收端，导通第六传输端的发送端；导通第一传输端的发送端和第二传输端的发送端；导通第七传输端的发送端和第八传输端的发送端，并关闭第七传输端的接收端和第八传输端的接收端。
另外，存储传输端还包括：第三传输端和第四传输端，第三传输端和第四传输端连接相同存储区域，第一传输端和第三传输端连接不同存储区域，且第三传输端用于传输低位数据，第四传输端用于传输高位数据；导通总线传输端和存储传输端，导通交互传输端的发送端，并同时关闭交互传输端的接收端，还包括：导通第三传输端的发送端和第四传输端的发送端。
另外，在工作阶段，第一传输端和第二传输端分别用于与不同数据传输结构连接的数据总线进行数据交互；在休眠阶段，第一传输端和的第二传输端用于发送所属数据传输结构连接的数据总线输入的休眠数据；在工作阶段，第一传输端和第三传输端交替进行数据传输，第二传输端和第四传输端交替进行数据传输，第一传输端和第二传输端同时进行数据传输，第三传输端和第四传输端同时进行数据传输；在休眠阶段，第一传输端、第二传输端、第三传输端和第四传输端同时进行数据发送。
另外，数据传输结构，包括：输入单元，用于接收休眠数据和休眠输入控制信号，被配置为，基于休眠输入控制信号，输入休眠数据；输出单元，用于接收休眠数据和休眠输出控制信号，被配置为，基于休眠输出控制信号，输出休眠数据；锁存单元，连接输出单元，用于锁存输出单元输出的休眠数据。
另外，输入单元，包括：多个输入控制器，每一输入控制器对应于总线传输端或交互传输端，且每一输入控制器都接收休眠数据；每一输入控制器用于接收对应总线传输端或交互传输端的休眠输入控制信号；在休眠阶段，基于休眠输入控制信号，导通对应于总线传输端的输入控制器。
另外，输出单元，包括：多个输出控制器，每一输出控制器对应于存储 传输端或交互传输端，且每一输出控制器都接收休眠数据；每一输出控制器用于接收对应存储传输端或交互传输端的休眠输出控制信号；在休眠阶段，基于休眠输出控制信号，导通对应于存储传输端和交互传输端的输出控制器。
另外，锁存单元包括：首尾连接的第一反相器和第二反相器，且第一反相器的输入端和第二反相器的输出端与输出单元的输出端并联。
另外，数据传输结构，还包括：输入选择单元，用于接收休眠输入控制信号，被配置为，生成对应于休眠输入控制信号的选通脉冲，选通脉冲与休眠输入控制信号表征的有效端口相对应，且选通脉冲与休眠输入控制信号之间具有选择延时；触发单元，时钟端连接输入选择单元，输入端连接输入单元，输出端连接输出单元，被配置为，基于选通脉冲，输出休眠数据。
另外，输入选择单元，包括：触发子单元，用于接收休眠输入控制信号，若接收到休眠输入控制信号，生成指示信号；延迟子单元，连接触发子单元，用于对指示信号进行延时；转换子单元，连接延迟子单元，用于将延时后的指示信号转换为选通脉冲。
另外，触发单元由D触发器构成。
本公开另一实施例提供了一种休眠控制电路，应用于上述休眠控制方式，包括：数据提供单元，被配置为，在休眠阶段，向数据总线发送休眠数据；第一数据控制单元，被配置为，在休眠阶段，导通存储传输端和总线传输端，控制数据传输电路接收数据总线传输的休眠数据，并向存储区域发送休眠数据；第二数据控制单元，被配置为，在休眠阶段，导通交互传输端，控制数据传输结构向另一数据传输结构发送休眠数据，并拒绝接收另一数据传输结构发送的休眠数据。
另外，第一数据控制单元，包括：第一数据接收子单元，用于接收休眠输入控制信号和休眠输出控制信号；第一控制单元，连接第一数据接收子单元，用于根据休眠输入控制信号导通总线传输端，并根据休眠输出控制信号导通存储传输端。
另外，第二数据控制单元，包括：第二数据接收子单元，用于接收休眠输入控制信号和休眠输出控制信号；第二控制单元，连接第二数据接收子单元，用于根据休眠输出控制信号导通交互传输端的发送端，并根据休眠输入控制信 号关闭交互传输端的接收端。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领缺普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的刷新电路的结构示意图；
图2为本公开一实施例提供的预处理模块的结构示意图；
图3为本公开一实施例提供的计数单元的结构示意图；
图4为本公开一实施例提供的地址处理模块的结构示意图；
图5为本公开一实施例提供的存储判断模块和处理输出模块的结构示意图；
图6为本公开一实施例提供的休眠控制方式的流程示意图；
图7为本公开一实施例提供的数据传输电路在休眠阶段所应用的电路结构示意图。
随着技术的进步，消费者对移动设备的性能要求越来越高，使得存储设备传输速率成为评判存储设备优良的关键参数，如何提高存储器的数据传输效率，是当下技术人员亟待解决的问题。
基于上述问题，本公开提供一种数据传输电路；另外，本公开一实施例提供了一种休眠控制方式，针对以提高存储器的读写数据传输效率的数据传输电路，提供一种该数据传输电路的休眠控制方式。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。 以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的数据传输电路的结构示意图，图2为本实施例提供的控制模块的具体结构示意图，图3为本实施例提供的数据传输结构的一种具体连接方式示意图，图4为本实施例提供的数据读出时数据传输结构的具体结构示意图，图5为本实施例提供的数据写入时数据传输结构的具体结构示意图，图6为本实施例提供的休眠控制方式的流程示意图，图7为本实施例提供的数据传输电路在休眠阶段所应用的电路结构示意图，以下结合附图对本实施例提供的休眠控制方式作进一步详细说明，具体如下：
参考图1，数据传输电路，应用于存储器，存储器包括数据总线103和多个存储区域102，用于提高存储器的读写数据传输效率，具体包括：至少两个数据传输结构101。
每一数据传输结构包括存储传输端111、总线传输端112和交互传输端113，其中，存储传输端111用于连接存储区域102，总线传输端112用于连接数据总线103，交互传输端113用于连接另一数据传输结构。
在工作阶段，从存储传输端111输入的数据，通过总线传输端112输出或通过交互传输端113输出，从总线传输端112输入的数据，通过存储传输端111输出或者通过交互传输端113输出，从交互传输端113输入的数据，通过总线传输端112输出或通过存储传输端111输出，从交互传输端113输入的数据为另一数据传输结构101中的总线传输端112或存储传输端111输入的数据；控制模块104，连接数据传输结构101，并接收所属存储器提供的输入控制信号和调整控制信号。
参考图6，在休眠阶段，休眠控制方式包括步骤10(在休眠阶段，控制数据总线传输休眠数据)和步骤20(控制休眠数据通过总线传输端写入数据传输结构，并通过存储传输端和交互传输端输出，并控制数据传输结构不接收通过交互传输端输入的休眠数据)。
具体地，对于步骤10，在休眠阶段，向数据总线103传输休眠数据，以使数据总线103传输休眠数据；对于步骤20，导通总线传输端112和存储传输端111，导通交互传输端113的发送端，并关闭交互传输端113的接收端，以使 得从总线传输端112输入的数据，通过存储传输端111和交互传输端113输出。
通过导通总线传输端112和存储传输端111，使得数据总线103上传输的休眠数据写入到存储传输端111中，通过导通交互传输端112的发送端，使得数据总线103上传输的休眠数据可以传输至交互传输端112中，从而实现数据传输结构101的存储传输端111、总线传输端112和交互传输端113都传输休眠数据实现休眠；另外，通过关闭交互传输端113的接收端，即交互传输端113在传输休眠数据的同时，数据传输结构101并不接收另一数据传输结构101发送的休眠数据，即保证对数据传输结构101中休眠数据的写入仅通过总线传输端112实现，避免了在休眠模式下数据传输结构101的输入数据时序混乱。
在本实施例中，在休眠阶段，向数据总线103传输的休眠数据为高电平数据，即在休眠阶段，将存储传输端111、总线传输端112和交互传输端113置高；在其他实施例中，在休眠阶段，向数据总线103传输的休眠数据为低电平数据，即在休眠阶段，将存储传输端111、总线传输端112和交互传输端113置低，以进一步减少休眠阶段下的功耗。
参考图1，并结合图2，在工作阶段下，控制模块104被配置为，基于调整控制信号，对输入控制信号进行延迟输出，以生成对应于输入控制信号的输出控制信号，输入控制信号和输出控制信号用于指示数据传输结构101的数据传输路径。
其中，调整控制信号基于数据传输电路所属存储器生成，用于控制相应输入控制信号和输出控制信号之间的延迟。
通过控制模块104控制两个数据传输结构101的数据传输路径，使得不同的数据传输结构能够同时传输数据，对应同一数据传输结构101，可以实现不同存储区域102的数据交替传输，使得数据传输更加紧凑，从而提高存储器的数据传输效率。
需要说明的是，在其他实施例中，数据传输结构的数量可以为任意大于2的偶数，两两数据传输结构之间构成上述数据传输电路，从而实现对存储器数据传输效率的进一步提高。
具体地，输入控制信号与输出控制信号之间的信号延迟由调整控制信号控制，有利于避免输出端相对于预设时序提前打开或延后打开，保证数据传输 结构准确输出对应的输入数据。
参考图1和图3，在一些实施例中，存储传输端111包括：第一传输端A和第二传输端B，第一传输端A和第二传输端B连接相同存储区域，且第一传输端A用于传输低位数据，第二传输端B用于传输高位数据；总线传输端112包括：第五传输端E和第六传输端F；交互传输端113包括：第七传输端G和第八传输端H；其中，第五传输端E用于所属数据传输结构101与数据总线103之间的数据交互传输，第六传输端F用于所属数据传输结构101向数据总线103的单向数据传输；第七传输端G和第八传输端H用于两个数据传输结构101之间的数据交互传输。
需要说明的是，本实施例中，第七传输端G和第八传输端H都可以用于两个数据传输结构101之间的数据交互传输；在其他实施例中，左侧数据传输结构向右侧数据传输结构传输数据通过第七传输端实现，右侧数据传输结构向左侧数据传输结构传输数据通过第八传输端实现。
在休眠阶段，导通总线传输端112和存储传输端111，导通交互传输端113的发送端，并关闭交互传输端113的接收端，包括：导通第五传输端E的接收端，导通第六传输端F的发送端，导通第一传输端A的发送端和第二传输端B的发送端，导通第七传输端G的发送端和第八传输端H的发送端，并关闭第七传输端G的接收端和第八传输端H的接收端。
在其他实施例中，若左侧数据传输结构向右侧数据传输结构传输数据通过第七传输端实现，右侧数据传输结构向左侧数据传输结构传输数据通过第八传输端实现，此时，导通第七传输端的发送端和第八传输端的发送端，并关闭第七传输端的接收端和第八传输端的接收端需要相应调整为，对于左侧数据传输结构，导通第七传输端的发送端，并关闭第八传输端的接收端；对于右侧数据传输结构，导通第八传输端的发送端，并关闭第七传输端的接收端。
在另一些实施例中，存储传输端111还包括：第三传输端C和第四传输端D，第三传输端C和第四传输端D连接相同存储区域，第一传输端A和第三传输端C连接不同存储区域，且第三传输端用于传输低位数据，第四传输端用于传输高位数据。
此时，在休眠阶段，导通总线传输端112和存储传输端111，导通交互传 输端113的发送端，并关闭交互传输端113的接收端，还包括：导通第三传输端C的发送端和第四传输端D的发送端。
需要说明的是，对于第一传输端A和第二传输端B，可以用于传输同一数据的高位数据和低位数据，例如对于16位数据的传输，第一传输端A用于传输低8位的数据，第二传输端B用于传输高8位的数据；第一传输端A和第二传输端B也可以用于传输不同数据，例如，对于8位数据的传输，第一传输端A和第二传输端B用于传输不同的数据。
需要说明的是，在工作阶段，第一传输端A和第二传输端B分别用于与不同数据传输结构101连接的数据总线103进行数据交互；在休眠阶段，第一传输端A和的第二传输端B用于发送所属数据传输结构101连接的数据总线103输入的休眠数据；在工作阶段，第一传输端A和第三传输端C交替进行数据传输，第二传输端B和第四传输端D交替进行数据传输，第一传输端A和第二传输端B同时进行数据传输，第三传输端C和第四传输端D同时进行数据传输；在休眠阶段，第一传输端A、第二传输端B、第三传输端C和第四传输端D同时进行数据发送。
在一些实施例中，参考图2并且结合图3，输入控制信号包括：Sel A、Sel B、Sel C、Sel D、Sel E、Sel F、Sel G和Sel H；输出控制信号包括：Drv A、Drv B、Drv C、Drv D、Drv E、Drv F、Drv G和Drv H。
其中，第一传输端A对应的输入控制信号为Sel A，输出控制信号为Drv A；第二传输端B对应的输入控制信号为Sel B，输出控制信号为Drv B；第三传输端C对应的输入控制信号为Sel C，输出控制信号为Drv C；第四传输端D对应的输入控制信号为Sel D，输出控制信号为Drv D；第五传输端E对应的输入控制信号为Sel E，输出控制信号为Drv E；第六传输端F对应的输入控制信号为Sel F，输出控制信号为Drv F；第七传输端G对应的输入控制信号为Sel G，输出控制信号为Drv G；第八传输端H对应的输入控制信号为Sel H，输出控制信号为Drv H。
在工作阶段，参考图4和图5，数据传输结构101，包括：输入单元201，用于接收至少一个输入数据和输入控制信号，被配置为，基于输入控制信号，输出输入控制信号对应的输入数据。输出单元203，用于接收输入单元201输出 的输入数据和至少一个输出控制信号，被配置为，基于输出控制信号表征的有效端口输出输入数据。锁存单元204，连接输出单元203，用于锁存输出单元203输出的输入数据。
在休眠阶段，参考图7，数据传输结构101，包括：输入单元201，用于接收休眠数据XM和休眠输入控制信号KR，被配置为，基于休眠输入控制信号KR，输入休眠数据XM。输出单元203，用于接收休眠数据XM和休眠输出控制信号KC，被配置为，基于休眠输出控制信号KC，输出休眠数据XM。锁存单元204，连接输出单元203，用于锁存输出单元203输出的休眠数据XM。
在工作阶段，输入单元201包括：多个输入控制器211，每一输入控制器211对应于存储传输端111、总线传输端112或交互传输端113；每一输入控制器211用于接收对应的存储传输端111、总线传输端112或交互传输端113的输入数据和输入控制信号，输入控制器211被配置为，基于输入控制信号导通对应的端口，以输出对应端口的输入数据。
具体地，对于数据的读出，参考图4，读出数据通过第一传输端A、第二传输端B、第三传输端C或第四传输端D读出该数据传输结构101所连接的存储区域的数据，也可以通过第七传输端G和第八传输端H读出另一数据传输结构101所连接的存储区域的数据。
其中，第一传输端A的输入数据Data A连接一输入控制器211，该输入控制器通过输入控制信号Sel A控制，当接收到输入控制信号Sel A，输出第一传输端A的输入数据Data A；第二传输端B的输入数据Data B连接一输入控制器211，该输入控制器通过输入控制信号Sel B控制，当接收到输入控制信号Sel B，输出第二传输端B的输入数据Data B；第三传输端C的输入数据Data C连接一输入控制器211，该输入控制器通过输入控制信号Sel C控制，当接收到输入控制信号Sel C，输出第三传输端C的输入数据Data C；第四传输端D的输入数据Data D连接一输入控制器211，该输入控制器通过输入控制信号Sel D控制，当接收到输入控制信号Sel D，输出第四传输端D的输入数据Data D；第七传输端G的输入数据Data G连接一输入控制器211，该输入控制器通过输入控制信号Sel G控制，当接收到输入控制信号Sel G，输出第七传输端G的输入数据Data G；第八传输端H的输入数据Data H连接一输入控制器211，该输入控制器通过输入控制信号Sel H控制，当接收到输入控制信号Sel H，输出第八传输 端H的输入数据Data H。
具体地，对于数据的写入，参考图5，写入数据通过第五传输端E写入该数据传输结构101，也可以通过第七传输端G和第八传输端H写入另一数据传输结构101所接收的写入数据。
其中，第五传输端E的输入数据Data E连接一输入控制器211，该输入控制器通过输入控制信号Sel E控制，当接收到输入控制信号Sel E，输出第五传输端E的输入数据Data E；第七传输端G的输入数据Data G连接一输入控制器211，该输入控制器通过输入控制信号Sel G控制，当接收到输入控制信号Sel G，输出第七传输端G的输入数据Data G；第八传输端H的输入数据Data H连接一输入控制器211，该输入控制器通过输入控制信号Sel H控制，当接收到输入控制信号Sel H，输出第八传输端H的输入数据Data H。
在一些实施例中，还包括掩码单元202，用于根据第五传输端E的输入数据Data E生成掩码数据DM，掩码数据DM通过第五传输端E对应的输入控制器211进行数据输入，以实现对数据总线103上数据的选择输入。
具体地，存储器包含数据掩码功能和数据反转功能，当数据掩码有效时，对应的8位数据不写入，当写入的8位数据中1占多数时，若传输通路传0更省电，则对写入的8位数据进行反转。在同时开启数据掩码(data mask，DM)和数据反转(databus inversion，DBI)功能时，由于数据掩码信号和数据反转信号都需要利用到同一数据端口，因此只能择一输入，本公开选择输入数据反转信号，也就是说，在进行数据写入时，输入数据和数据反转信号一同传输至数据传输结构，当数据反转信号有效时，表征同步输入的输入数据Data E需要进行反转，由于如果不写入输入数据Data E就没有进行反转的必要，因此，数据反转信号有效还表征输入数据Data E需要写入；当数据反转信号无效时，若输入数据为正常输入，则输入数据中0应当占多数，也就是说，当数据反转信号无效时，需要检测输入数据中0是否占半数或半数以上，若占半数或半数以上，则不经过数据反转且正常输入，若0占少数且1占多数，则说明此时输入数据表征的是数据掩码信号有效，屏蔽对应的8位输入数据，不存入存储阵列中。
也就是说，当数据反转信号有效时，第五传输端E接收待写入的8位原始数据，反相单元207接收反相控制信号DBI，此时的反相控制信号DBI表征 数据翻转信号有效，例如反相控制信号DBI为1，并将输入单元201输入的数据进行翻转以输出至输出单元203；当数据反转信号无效时，根据Data E的内容确定第五传输端E接收待写入的8位原始数据或者掩码数据DM，具体的，当数据反转信号无效时，通过掩码单元202对输入输出Data E进行编译，判断数据掩码信号是否有效(假设有效为1，无效为0)，若数据掩码DM表征有效，则说明8位原始数据无需写入，此时第五传输端E接收掩码数据DM，若数据掩码DM表征无效，则说明8位原始数据需要写入，此时第五传输端E接收输入数据Data E。
需要说明的是，任一数据传输结构仅对对应的第五传输端E输入的数据进行反相，即进行数据写入时，翻转控制子单元221接收反相控制信号DBI只会是输入数据Data E对应的反相控制信号，而不会是输入数据Data G和Data H对应的反相控制信号。这是因为对于第七输入端Sel G和第八输入端Sel H输入的数据，即数据总线103通过另一数据传输结构输入的数据，此时输入数据在另一数据传输结构的反相单元207中已完成上述数据反相过程。
在休眠阶段，参考图7，输入单元201包括：多个输入控制器211，每一输入控制器对应于总线传输端112或交互传输端113，且每一输入控制器211都接收休眠数据XM；每一输入控制器211用于接收对应总线传输端112或交互传输端113的休眠输入控制信号KR；在休眠阶段，基于休眠输入控制信号KR，导通对应于总线传输端的输入控制器211。
具体地，休眠输入控制信号KR传输至第五传输端E、第七传输端G和第八传输端H，以导通第五传输端E，关断第七传输端G和第八传输端H，使得休眠数据XM通过第五传输端E，从数据总线103写入数据传输结构101，由于关闭了第七传输端G和第八传输端H，即关闭了交互传输端113的接收端，休眠数据XM无法通过第七传输端G或第八传输端H写入另一数据传输结构101，避免造成数据时序混乱。
在工作阶段，输出单元203包括：多个输出控制器212，每一输出控制器212对应于存储传输端111、总线传输端112或交互传输端113；每一输出控制器212用于接收对应的存储传输端111、总线传输端112或交互传输端113的输入数据和输出控制信号，输出控制器212被配置为，基于输出控制信号导通，以输出输入数据。
具体地，对于数据的读出，参考图4，读出数据通过第五传输端E或第六传输端F读出至数据总线103，也可以通过第七传输端G和第八传输端H读出至另一数据传输结构101，最终通过另一数据传输结构101对应的第五传输端E或第六传输端F读出至对应的另一数据总线103。
其中，连接第五传输端E的输出控制器212通过输出控制信号Drv E控制，当接收到输出控制信号Drv E，将数据通过第五传输端E输出；连接第七传输端G的输出控制器212通过输出控制信号Drv G控制，当接收到输出控制信号Drv G，将数据通过第七传输端G输出；连接第八传输端H的输出控制器212通过输出控制信号Drv H控制，当接收到输出控制信号Drv H，将数据通过第八传输端H输出。
具体地，对于数据的写入，参考图5，写入数据通过第一传输端A、第二传输端B、第三传输端C或第四传输端D写入该数据传输结构101所连接的存储区域，也可以通过第七传输端G和第八传输端H写入另一数据传输结构101所连接的存储区域。
其中，连接第一传输端A的输出控制器212通过输出控制信号Drv A控制，当接收到输出控制信号Drv A，将数据通过第一传输端A输出；连接第二传输端B的输出控制器212通过输出控制信号Drv B控制，当接收到输出控制信号Drv B，将数据通过第二传输端B输出；连接第三传输端C的输出控制器212通过输出控制信号Drv C控制，当接收到输出控制信号Drv C，将数据通过第三传输端C输出；连接第四传输端D的输出控制器212通过输出控制信号Drv D控制，当接收到输出控制信号Drv D，将数据通过第四传输端D输出；连接第七传输端G的输出控制器212通过输出控制信号Drv G控制，当接收到输出控制信号Drv G，将数据通过第七传输端G输出；连接第八传输端H的输出控制器212通过输出控制信号Drv H控制，当接收到输出控制信号Drv H，将数据通过第八传输端H输出。
在休眠阶段，输出单元203包括：多个输出控制器212，每一输出控制器212对应于存储传输端111或交互传输端113，且每一输出控制器212都接收休眠数据XM；每一数据控制器用于接收对应存储传输端111或交互传输端113的休眠输出控制信号KC；在休眠阶段，基于休眠输出控制信号KC，导通对应于存储传输端111和交互传输端113的输出控制器212。
具体地，参考图7，休眠输出控制信号KC传输至第一传输端A、第二传输端B、第三传输端C、第四传输端D、第七传输端G和第八传输端H，以导通第一传输端A、第二传输端B、第三传输端C、第四传输端D、第七传输端G和第八传输端H，使得休眠数据XM通过第一传输端A、第二传输端B、第三传输端C、第四传输端D、第七传输端G和第八传输端H输出，由于导通了第七传输端G和第八传输端H，即开启了交互传输端113的发送端，休眠数据XM通过第七传输端G和第八传输端H向另一数据传输端传输，从而实现交互传输端113传输休眠数据XM。
在本实施例中，锁存单元204包括：首尾相连的第一反相器214和第二反相器213，且第一反相器214的输入端和第二反相器213的输出端与输出单元203的输出端并联，通过锁存单元204与输出单元203的输出端并联，以实现对输出单元203输出数据的保存；需要说明的是，在其他实施例中，锁存单元包括：首尾相连的第一反相器和第二反相器，且第一反相器和输入端和第二反相器的输出端与输入单元的输出端口串联，通过锁存单元与输出单元的输出端串联，以实现对输出单元输出数据的反相锁存，后续通过串联反相器，以实现出输出单元输出数据的保存。
在一些实施例中，还通过对数据的输入进行延迟，以进一步保证数据在多路传输过程中的准确性。
具体地，在工作阶段，数据传输结构，参考图4和图5，还包括：输入选择单元205和触发单元206。
其中，输入选择单元205，用于接收至少一个输入控制信号，被配置为，生成对应于输入控制信号的选通脉冲，选通脉冲与输入控制信号表征的有效端口相对应，且选通脉冲与输入控制信号之间具有选择延时；触发单元206，时钟端连接输入选择单元205，输入端连接输入单元201，输出端连接输出单元203，被配置为，基于选通脉冲，将输入端接收的输入数据传输至输出端。
在休眠阶段，数据传输结构，参考图7，还包括：输入选择单元205和触发单元206。
其中，输入选择单元205，用于接收休眠输入控制信号KR，具体地，用于接收第五传输端对应的休眠输入控制信号KR_E，第七传输端对应的休眠输入 控制信号KR_G和第八传输端对应的休眠输入控制信号KR_H；输入选择单元205被配置为，生成对应于休眠输入控制信号KR的选通脉冲，选通脉冲与休眠输入控制信号KR表征的有效端口相对应，且选通脉冲与休眠输入控制信号KR之间具有选择延时；触发单元206，时钟端连接输入选择单元205，输入端连接输入单元201，输出端连接输出单元203，被配置为，基于选通脉冲，输出休眠数据XM。
在工作阶段，输入选择单元205，包括：触发子单元215，用于接收至少一个输入控制信号，若接收到输入控制信号，生成指示信号；延迟子单元216，连接触发子单元215，用于对指示信号进行延时；转换子单元217，连接延迟子单元216，用于将延时后的指示信号转换为选通脉冲。
通过延时子单元216对指示信号进行延迟，保证数据传输结构准确输出对应的输入数据；延时子单元216的具体延时参数基于所属存储器设定，在一些实施例中，延时子单元216的具体延时参数可以通过工作人员进行调配。
在本实施例中触发子单元215通过或门实现，在数据读出时，参考图4，输入控制信号Sel A、Sel B、Sel C、Sel D、Sel G或Sel H输入触发子单元215中，触发子单元215基于输入控制信号Sel A、Sel B、Sel C、Sel D、Sel G或Sel H的有效电平生成指示信号，指示信号经过延迟子单元216延时后，由转换子单元217转换为选通脉冲以驱动触发单元206；在数据写入时，参考图5，输入控制信号Sel E、Sel G或Sel H输入触发子单元215中，触发子单元215基于输入控制信号Sel E、Sel G或Sel H的有效电平生成指示信号，指示信号经过延迟子单元216延时后，由转换子单元217转换为选通脉冲以驱动触发单元206。
在休眠阶段，输入选择单元205，包括：触发子单元215，用于接收至少一个休眠输入控制信号KR，具体地，用于接收第五传输端对应的休眠输入控制信号KR_E，第七传输端对应的休眠输入控制信号KR_G和第八传输端对应的休眠输入控制信号KR_H；若触发子单元215接收到休眠输入控制信号KR，生成指示信号；延迟子单元216，连接触发子单元215，用于对指示信号进行延时；转换子单元217，连接延迟子单元216，用于将延时后的指示信号转换为选通脉冲。
通过延时子单元216对指示信号进行延迟，保证数据传输结构准确输出 对应的输入数据；延时子单元216的具体延时参数基于所属存储器设定，在一些实施例中，延时子单元216的具体延时参数可以通过工作人员进行调配。
在一些实施例中，触发单元由D触发器构成。
在一些实施例中，数据传输结构101还包括：反相单元207，设置在触发单元206和输入单元201之间，被配置为，基于反相控制信号，输出输入数据，或者将输入数据反相后输出。
通过将数据量化后输出反相控制信号，通过反相单元对数据直接输出或反相后输出，以降低数据传输结构101的数据能耗；具体地，由于数据传输时低电平的耗能较少，通过低电平传输数据能够节省能耗，通过对数据进行量化，若数据中的高电平数据多于低电平数据，则通过反相控制信号控制数据反相后传输；若数据中的高电平数据少于低电平数据，则通过反相控制信号控制数据直接传输。
参考图4和图5，反相单元207包括：翻转控制子单元221，用于接收反相控制信号，并基于反相控制信号生成第一控制信号和第二控制信号；第一选择子单元222和第二选择子单元223，并联后输入端用于接收输入数据，输出端连接触发单元206；第一选择子单元222被配置为，基于第一控制信号导通，将输入数据反相后输出；第二选择子单元223被配置为，基于第二控制信号导通，将输入数据直接输出。
需要说明的是，第一控制信号和第二控制信号可以作为两个信号来驱动第一选择子单元222和第二选择子单元223，也可以作为同一信号的高低电平来驱动第一选择子单元222和第二选择子单元223。
参考图4，在一些实施例中，反相单元207还包括：判断子单元224，用于接收输入数据并基于输入数据生成反相控制信号。
需要说明的是，本实施例中提到的信号驱动方式中是以信号是否存在为例进行的描述，在具体的应用中，可以根据信号是否存在进行驱动，也可以根据信号的高低电平进行驱动，即信号存在，根据信号的电平是否为有效电平进行驱动。
通过导通总线传输端和存储传输端，使得数据总线上传输的休眠数据写 入到存储区域中，通过导通交互传输端的发送端，使得数据总线上传输的休眠数据可以传输至交互传输端中，从而实现数据传输结构的存储传输端、总线传输端和交互传输端都传输休眠数据实现休眠；另外，通过关闭交互传输端的接收端，即交互传输端在传输休眠数据的同时，数据传输结构并不接收另一数据传输结构发送的休眠数据，即保证对数据传输结构中休眠数据的写入仅通过总线传输端实现，避免了在休眠模式下数据传输结构的输入数据时序混乱。
本公开又一实施例提供一种休眠控制电路，应用于上述休眠控制方式实施例，针对以提高存储器的读写数据传输效率的数据传输电路，提供一种该数据传输电路的休眠控制方式。
下面对本实施例提供的休眠控制电路进行详细说明，具体如下：
休眠控制电路，包括：
数据提供单元，被配置为，在休眠阶段，向数据总线发送休眠数据。
第一数据控制单元，被配置为，在休眠阶段，导通存储传输端和总线传输端，控制数据传输电路接收数据总线传输的休眠数据，并向存储区域发送休眠数据。
第二数据控制单元，被配置为，在休眠阶段，导通交互传输端，控制数据传输结构向另一数据传输结构发送休眠数据，并拒绝接收另一数据传输结构发送的休眠数据。
具体地，第一数据控制单元，包括：
第一数据接收子单元，用于接收休眠输入控制信号和休眠输出控制信号。
第一控制单元，连接第一数据接收子单元，用于根据休眠输入控制信号导通总线传输端，并根据休眠输出控制信号导通存储传输端。
具体地，第二数据控制单元，包括：
第二数据接收子单元，用于接收休眠输入控制信号和休眠输出控制信号。
第二控制单元，连接第二数据接收子单元，用于根据休眠输出控制信 号导通交互传输端的发送端，并根据休眠输入控制信号关闭交互传输端的接收端。
通过导通总线传输端和存储传输端，使得数据总线上传输的休眠数据写入到存储区域中，通过导通交互传输端的发送端，使得数据总线上传输的休眠数据可以传输至交互传输端中，从而实现数据传输结构的存储传输端、总线传输端和交互传输端都传输休眠数据实现休眠；另外，通过关闭交互传输端的接收端，即交互传输端在传输休眠数据的同时，数据传输结构并不接收另一数据传输结构发送的休眠数据，即保证对数据传输结构中休眠数据的写入仅通过总线传输端实现，避免了在休眠模式下数据传输结构的输入数据时序混乱。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。
Claims (15)
- 一种休眠控制方式，应用于数据传输电路，包括：所述数据传输电路包括：至少两个数据传输结构；每一所述数据传输结构包括存储传输端、总线传输端和交互传输端，其中，所述存储传输端用于连接存储区域，所述总线传输端用于连接数据总线，所述交互传输端用于连接另一所述数据传输结构；在休眠阶段，向所述数据总线传输休眠数据；导通所述总线传输端和所述存储传输端，导通所述交互传输端的发送端，并关闭所述交互传输端的接收端，以使得从所述总线传输端输入的数据，通过所述存储传输端和所述交互传输端输出。
- 根据权利要求1所述的休眠控制方式，其中，向所述数据总线传输的休眠数据为高电平数据。
- 根据权利要求1所述的休眠控制方式，其中，包括：所述存储传输端包括：第一传输端和第二传输端，所述第一传输端和所述第二传输端连接相同所述存储区域，且所述第一传输端用于传输低位数据，所述第二传输端用于传输高位数据；所述总线传输端包括：第五传输端和第六传输端，所述第五传输端用于所属所述数据传输结构与所述数据总线之间的数据交互传输，所述第六传输端用于所属所述数据传输结构向所述数据总线的单向数据传输；所述交互传输端包括：第七传输端和第八传输端，所述第七传输端和所述第八传输端用于两个所述数据传输结构之间的数据交互传输；所述导通所述总线传输端和所述存储传输端，导通所述交互传输端的发送端，并关闭所述交互传输端的接收端，包括：导通所述第五传输端的接收端，导通所述第六传输端的发送端；导通所述第一传输端的发送端和所述第二传输端的发送端；导通所述第七传输端的发送端和所述第八传输端的发送端，并关闭所述第七传输端的接收端和所述第八传输端的接收端。
- 根据权利要求3所述的休眠控制方式，其中，包括：所述存储传输端还包括：第三传输端和第四传输端，所述第三传输端和所述第四传输端连接相同所述存储区域，所述第一传输端和所述第三传输端连接不同所述存储区域，且所述第三传输端用于传输低位数据，所述第四传输端用于传输高位数据；所述导通所述总线传输端和所述存储传输端，导通所述交互传输端的发送端，并同时关闭所述交互传输端的接收端，还包括：导通所述第三传输端的发送端和所述第四传输端的发送端。
- 根据权利要求4所述的休眠控制方式，其中，包括：在工作阶段，所述第一传输端和所述第二传输端分别用于与不同所述数据传输结构连接的所述数据总线进行数据交互；在所述休眠阶段，所述第一传输端和所述的第二传输端用于发送所属所述数据传输结构连接的所述数据总线输入的所述休眠数据；在所述工作阶段，所述第一传输端和所述第三传输端交替进行数据传输，所述第二传输端和所述第四传输端交替进行数据传输，所述第一传输端和所述第二传输端同时进行数据传输，所述第三传输端和所述第四传输端同时进行数据传输；在所述休眠阶段，所述第一传输端、所述第二传输端、所述第三传输端和所述第四传输端同时进行数据发送。
- 根据权利要求1所述的休眠控制方式，其中，所述数据传输结构，包括：输入单元，用于接收所述休眠数据和休眠输入控制信号，被配置为，基于所述休眠输入控制信号，输入所述休眠数据；输出单元，用于接收所述休眠数据和休眠输出控制信号，被配置为，基于所述休眠输出控制信号，输出所述休眠数据；锁存单元，连接所述输出单元，用于锁存所述输出单元输出的所述休眠数据。
- 根据权利要求6所述的休眠控制方式，其中，所述输入单元，包括：多个输入控制器，每一所述输入控制器对应于所述总线传输端或所述交互传输端，且每一所述输入控制器都接收所述休眠数据；每一所述输入控制器用于接收对应所述总线传输端或所述交互传输端的所述休眠输入控制信号；在所述休眠阶段，基于所述休眠输入控制信号，导通对应于所述总线传输端的所述输入控制器。
- 根据权利要求6所述的休眠控制方式，其中，所述输出单元，包括：多个输出控制器，每一所述输出控制器对应于所述存储传输端或所述交互传输端，且每一所述输出控制器都接收所述休眠数据；每一所述输出控制器用于接收对应所述存储传输端或所述交互传输端的所述休眠输出控制信号；在所述休眠阶段，基于所述休眠输出控制信号，导通对应于所述存储传输端和所述交互传输端的所述输出控制器。
- 根据权利要求6所述的休眠控制方式，其中，所述锁存单元包括：首尾连接的第一反相器和第二反相器，且所述第一反相器的输入端和所述第二反相器的输出端与所述输出单元的输出端并联。
- 根据权利要求6所述的休眠控制方式，其中，所述数据传输结构，还包括：输入选择单元，用于接收所述休眠输入控制信号，被配置为，生成对应于所述休眠输入控制信号的选通脉冲，所述选通脉冲与所述休眠输入控制信号表征的有效端口相对应，且所述选通脉冲与所述休眠输入控制信号之间具有选择延时；触发单元，时钟端连接所述输入选择单元，输入端连接所述输入单元，输出端连接所述输出单元，被配置为，基于所述选通脉冲，输出所述休眠数据。
- 根据权利要求10所述的休眠控制方式，其中，输入选择单元，包括：触发子单元，用于接收所述休眠输入控制信号，若接收到所述休眠输入控制信号，生成指示信号；延迟子单元，连接所述触发子单元，用于对所述指示信号进行延时；转换子单元，连接所述延迟子单元，用于将延时后的所述指示信号转换为所述选通脉冲。
- 根据权利要求10所述的休眠控制方式，其中，所述触发单元由D触发器构成。
- 一种休眠控制电路，应用于权利要求1～12任一项所述的休眠控制方式，包括：数据提供单元，被配置为，在休眠阶段，向数据总线发送休眠数据；第一数据控制单元，被配置为，在所述休眠阶段，导通所述存储传输端和所述总线传输端，控制所述数据传输电路接收所述数据总线传输的所述休眠数据，并向存储区域发送所述休眠数据；第二数据控制单元，被配置为，在所述休眠阶段，导通所述交互传输端，控制所述数据传输结构向另一所述数据传输结构发送所述休眠数据，并拒绝接收另一所述数据传输结构发送的所述休眠数据。
- 根据权利要求13所述的休眠控制电路，其中，所述第一数据控制单元，包括：第一数据接收子单元，用于接收休眠输入控制信号和休眠输出控制信号；第一控制单元，连接所述第一数据接收子单元，用于根据所述休眠输入控制信号导通所述总线传输端，并根据所述休眠输出控制信号导通所述存储传输端。
- 根据权利要求13所述的休眠控制电路，其中，所述第二数据控制单元，包括：第二数据接收子单元，用于接收休眠输入控制信号和休眠输出控制信号；第二控制单元，连接所述第二数据接收子单元，用于根据所述休眠输出控制信号导通所述交互传输端的发送端，并根据所述休眠输入控制信号关闭所述交互传输端的接收端。
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| CN101605081A (zh) * | 2008-06-13 | 2009-12-16 | 威盛电子(中国)有限公司 | 数据传输装置、数据接收装置以及控制数据传输的方法 |
| CN110321168A (zh) * | 2018-03-31 | 2019-10-11 | 深圳忆联信息系统有限公司 | 芯片休眠控制方法及装置 |
| CN212675545U (zh) * | 2020-08-27 | 2021-03-09 | 长鑫存储技术(上海)有限公司 | 数据传输电路和存储器 |
| US20210232209A1 (en) * | 2019-03-21 | 2021-07-29 | Gowin Semiconductor Corporation, Ltd. | Method and system for providing a sleep mode to a configurable logic block using an intermittent power saving logic |
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| CN101605081A (zh) * | 2008-06-13 | 2009-12-16 | 威盛电子(中国)有限公司 | 数据传输装置、数据接收装置以及控制数据传输的方法 |
| CN110321168A (zh) * | 2018-03-31 | 2019-10-11 | 深圳忆联信息系统有限公司 | 芯片休眠控制方法及装置 |
| US20210232209A1 (en) * | 2019-03-21 | 2021-07-29 | Gowin Semiconductor Corporation, Ltd. | Method and system for providing a sleep mode to a configurable logic block using an intermittent power saving logic |
| CN212675545U (zh) * | 2020-08-27 | 2021-03-09 | 长鑫存储技术(上海)有限公司 | 数据传输电路和存储器 |
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