WO2023159733A1 - 存储电路、数据传输电路和存储器 - Google Patents

存储电路、数据传输电路和存储器 Download PDF

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Publication number
WO2023159733A1
WO2023159733A1 PCT/CN2022/087829 CN2022087829W WO2023159733A1 WO 2023159733 A1 WO2023159733 A1 WO 2023159733A1 CN 2022087829 W CN2022087829 W CN 2022087829W WO 2023159733 A1 WO2023159733 A1 WO 2023159733A1
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Prior art keywords
data
transmission
input
storage
output
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PCT/CN2022/087829
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English (en)
French (fr)
Inventor
李红文
尚为兵
高恩鹏
冀康灵
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22732383.9A priority Critical patent/EP4258265A4/en
Priority to JP2022542070A priority patent/JP2024510356A/ja
Priority to KR1020227022484A priority patent/KR20230128961A/ko
Priority to US17/807,027 priority patent/US20230267976A1/en
Publication of WO2023159733A1 publication Critical patent/WO2023159733A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to, but is not limited to, a storage circuit, a data transfer circuit and a memory.
  • DRAM Dynamic Random Access Memory
  • DRAM has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, and is suitable as a storage device for mobile devices.
  • the present disclosure provides a storage circuit, a data transmission circuit and a memory, so as to improve the efficiency of reading and writing data transmission of the memory and ensure the accuracy of data transmission.
  • An exemplary embodiment of the present disclosure provides a storage circuit disposed adjacent to a data transmission area, including: at least one storage structure disposed parallel to the data transmission area, each storage structure including a storage structure disposed adjacently in a first direction
  • the first storage array and the second storage array the distance between the first storage array and the data transmission area is smaller than the distance between the second storage array and the data transmission area, the first direction is the direction close to the data transmission area;
  • the first storage array contains The read-write module and the forwarding module
  • the second storage array contains the read-write module
  • the first storage array performs data interaction with the data transmission area based on the read-write module in the first storage array
  • the second storage array based on the The read-write module and the forwarding module in the first storage array perform data transmission with the data transmission area.
  • the data reading and writing to the second storage array avoids the forwarding of the data through the reading and writing module of the first storage array, thereby separating the data transmission paths of the first storage array and the second storage array, which can be realized later Alternately read and write the data in the first storage array and the second storage array, thereby reducing the difference in data read delay of different storage arrays, preventing the read data with longer delay from truncating the read data with shorter delay, and improving the Data transmission margin; in addition, by separating the data transmission paths of the first storage array and the second storage array, in the process of data reading and writing, only need to judge whether the data belongs to the writing process or the reading process, the data can be confirmed
  • the direction of transmission avoids the complicated data path judgment process when using the same data transmission path, so as to achieve higher data transmission rate and accuracy of data transmission.
  • the first storage array and the second storage array include: an even number of storage blocks arranged continuously in the first direction, and every two adjacent non-repeating storage blocks share a read-write module, the read-write module is set between two corresponding storage blocks.
  • the storage block further includes: a plurality of storage sub-blocks arranged continuously in a second direction perpendicular to the first direction, and the plurality of storage sub-blocks share the same read-write module.
  • the read-write modules in the first storage array and the read-write modules in the second storage array are arranged together along the first direction, and in the second direction perpendicular to the first direction, the forwarding module is arranged On the opposite side of the read-write module; through the regular setting of the read-write module and the forwarding module, the data transmission wires between the read-write module and the forwarding module can be arranged neatly, and the shortest data transmission wire can reduce the data transmission wire. resistance, improving the rate and accuracy of data transmission.
  • a forwarding module is arranged on the opposite side of each reading and writing module; through short-distance transmission between multiple forwarding modules and multiple forwarding of data, the risk of data errors during transmission is reduced. possibility.
  • the data transmission wires between the read-write module, the forwarding module and the data transmission area are arranged between adjacent power wires, and the power wires are configured to receive and transmit power signals to the first storage
  • the array and the second storage array provide power signals; the data transmission wires are arranged between the power wires, which does not increase the layout area occupied by the storage array.
  • the data transmission wires include low-order transmission wires and high-order transmission wires, wherein the low-order transmission wires are configured to transmit low-order data in the storage array, and the high-order transmission wires are configured to transmit high-order data in the storage array , to further improve the efficiency of data transmission and the accuracy of data transmission.
  • An exemplary embodiment of the present disclosure also provides a data transmission circuit, which is set in the data transmission area, and includes: at least two data transmission structures, each data transmission structure is connected to at least one storage circuit provided by the above-mentioned embodiment, configured It is the data reading and writing of the storage circuit; each data transmission structure includes a storage transmission end, a bus transmission end and an interactive transmission end, wherein the storage transmission end is configured to connect to the storage circuit, and the bus transmission end is configured to connect to the data bus for interactive transmission A port configured to connect to another data transfer structure; data input from a storage transfer port, output via a bus transfer port or output via an interactive transfer port; data input from a bus transfer port, output via a storage transfer port or output via an interactive transfer port ; The data input from the interactive transmission end is output through the bus transmission end or through the storage transmission end, wherein the data input from the interactive transmission end is the data input from the bus transmission end or the storage transmission end in another data transmission structure; control The module is connected to the data transmission structure, and receives the input control signal
  • the data transmission structure includes: an input unit configured to receive at least one input data and an input control signal, and output input data corresponding to the input control signal based on the input control signal; an output unit configured to In order to receive the input data output by the input unit and at least one output control signal, it is configured to output the input data based on the effective port represented by the output control signal; the latch unit is connected to the output unit and is configured to latch the input data output by the output unit .
  • the input unit includes: a plurality of input controllers, each corresponding to a storage transmission end, a bus transmission end or an interactive transmission end; each input controller is configured to receive a corresponding storage Input data and an input control signal of a transmission end, a bus transmission end or an interactive transmission end; the input controller is configured to be turned on based on the input control signal to output the input data.
  • the output unit includes: a plurality of output controllers, each corresponding to a storage transmission end, a bus transmission end or an interactive transmission end; each output controller is configured to receive a corresponding storage The input data and the output control signal outputted by the input unit of the transmission end, the bus transmission end or the interactive transmission end; the output controller is configured to be turned on based on the output control signal to output the input data.
  • the data transmission structure further includes: an input selection unit configured to receive at least one input control signal, generate a gate pulse corresponding to the input control signal, and the gate pulse is represented by the input control signal
  • the effective port corresponds, and there is a selection delay between the strobe pulse and the input control signal
  • the trigger unit, the clock terminal is connected to the input selection unit, the input terminal is connected to the input unit, and the output terminal is connected to the output unit, which is configured to be based on the strobe pulse , which transfers the input data received at the input to the output.
  • the input selection unit includes: a trigger subunit, configured to receive at least one input control signal, and generate an indication signal if an input control signal is received; a delay subunit, connected to the trigger subunit, is configured to configured to delay the indication signal; the conversion subunit is connected to the delay subunit and is configured to convert the delayed indication signal into a gate pulse.
  • the data transmission structure further includes: an inversion unit, disposed between the trigger unit and the input unit, configured to output the input data or invert the input data based on the inversion control signal After output.
  • an inversion unit disposed between the trigger unit and the input unit, configured to output the input data or invert the input data based on the inversion control signal After output.
  • the inversion unit includes: an inversion control subunit configured to receive an inversion control signal, and generate a first control signal and a second control signal based on the inversion control signal; the first selector After the unit and the second selection subunit are connected in parallel, the input terminal is configured to receive input data, and the output terminal is connected to the trigger unit; the first selection subunit is configured to invert the input data and then output it based on the conduction of the first control signal; The second selection subunit is configured to output the input data based on the second control signal being turned on.
  • the storage transmission end includes: a first transmission end, a second transmission end, a third transmission end, and a fourth transmission end;
  • the bus transmission end includes: a fifth transmission end and a sixth transmission end;
  • the transmission end includes: the seventh transmission end and the eighth transmission end; the first transmission end, the second transmission end, the third transmission end, and the fourth transmission end are respectively connected to the first storage array and the second storage array, and the first transmission end and the third transmission end are configured to transmit low-bit data, the second transmission end and the fourth transmission end are configured to transmit high-bit data;
  • the fifth transmission end and the sixth transmission end are configured to belong to the data transmission structure and data Data exchange transmission between buses;
  • the seventh transmission end and the eighth transmission end are configured as data exchange transmission between two data transmission structures.
  • the fifth transmission end is configured for interactive data transmission between the data transmission structure and the data bus; the sixth transmission end is configured for unidirectional data transmission from the data transmission structure to the data bus.
  • Exemplary embodiments of the present disclosure also provide a memory.
  • the storage circuit provided by the above embodiments is used to set up a memory array, so as to improve the read-write data transmission efficiency of the memory and ensure the accuracy of data transmission.
  • FIG. 1 is a schematic diagram of a virtual structure of a storage circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a storage circuit provided by an embodiment of the present disclosure
  • FIG. 3 is another specific structural schematic diagram of a storage circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a data transmission circuit provided by another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a control module provided by another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a specific connection mode of a data transmission structure provided by another embodiment of the present disclosure.
  • FIG. 7 is a specific structural diagram of a data transmission structure during data readout provided by another embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a data transmission structure during data writing provided by another embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a virtual structure of the storage circuit provided in this embodiment
  • FIG. 2 is a schematic diagram of a specific structure of the storage circuit provided in this embodiment
  • FIG. 3 is a schematic diagram of another specific structure of the storage circuit provided in this embodiment.
  • the storage circuit disposed adjacent to the data transfer area 100, includes:
  • each storage structure 400 includes: a first storage array 401 and a second storage array 402 adjacently arranged in the first direction X, wherein the first direction X is Close to the direction of the data transmission area 100, and the distance between the first storage array 401 and the data transmission area 100 is smaller than the distance between the second storage array 402 and the data transmission area 100, that is, in the same storage structure 400, the first storage array 401 is close to the data
  • the transmission area 100 is disposed, and the second storage array 402 is disposed away from the data transmission area 100 .
  • the first storage array 401 performs data interaction with the data transmission area based on the read-write module 410 in the first storage array 401; for the second storage array 402, Including: a read-write module 410 , the second storage array 402 performs data interaction with the data transmission area 100 based on the read-write module 410 in the second storage array 402 and the forwarding module 420 in the first storage array 401 .
  • the read-write module 410 is configured to directly interact with the storage units in the storage array to which it belongs. During the data read-write process, the input written from the data transmission area 100 passes The writing module 410 transmits, thereby realizing the writing of different storage units in the storage array; and for the storage array that is far away from the data transmission area 100, by setting the forwarding module in the storage array that is closer to the data transmission area 100 420. Implement fast and accurate transfer of data to a corresponding storage array.
  • the data reading and writing to the second storage array 402 avoids the forwarding of the data through the reading and writing module 410 of the first storage array 401, so that the first storage array 401 and the second storage array 402
  • the data transmission path is separated, and the data in the first storage array 401 and the second storage array 402 can be alternately read and written in the follow-up, so as to reduce the difference in the data read delay of different storage arrays and avoid reading data with a long delay Truncate the read data with a short delay to improve the data transmission margin; in addition, by separating the data transmission paths of the first storage array 401 and the second storage array 402, in the process of reading and writing data, only need to judge the data Belonging to the writing process or reading process, the data transmission direction can be confirmed, avoiding the complicated data path judgment process when using the same data transmission path, so as to achieve higher data transmission rate and accuracy of data transmission.
  • the first storage array 401 and the second storage array 402 include: an even number of storage blocks 430 arranged continuously in the first direction X, and every two adjacent storage blocks 430 that do not repeat The blocks share a read-write module 410 , and the read-write module is arranged between two corresponding storage blocks 430 .
  • each storage block 430 includes a plurality of storage units, and the storage block 430 performs data reading and writing through adjacently arranged read-write modules 410; more specifically, the storage block 430 includes a plurality of word lines and a plurality of bit lines , each memory cell corresponds to a word line and a bit line, by turning on a specific word line and a bit line, the target memory cell in the memory block 430 is connected to the read-write module 410, thereby realizing the reading-write module 410 to the memory block Data reading and writing of different storage units in 430.
  • the read-write modules 410 in the first storage array 401 and the read-write modules in the second storage array 402 are arranged together along the first direction X, and in a direction perpendicular to the first direction X In the second direction, the forwarding module 420 is disposed on the opposite side of the reading and writing module 410 .
  • the data transmission wires between the read-write module 410 and the forwarding module 420 can be arranged regularly, and the resistance of the data transmission wire can be reduced through the shortest data transmission wire, and the efficiency of data transmission can be improved. speed and accuracy.
  • a forwarding module 420 is provided on the opposite side of each read-write module 410, and through short-distance transmission between multiple forwarding modules 420 and multiple forwarding of data, the data transmission process is reduced. Possibility of errors.
  • the forwarding module 420 is provided on the opposite side of each read-write module 410, which does not constitute a limitation to this embodiment. In other embodiments, the number of forwarding modules can be reduced accordingly. Still can realize above-mentioned technical effect.
  • the data transmission wires between the read-write module 410, the forwarding module 420 and the data transmission area 100 are arranged between adjacent power wires, and the power wires are used to receive and transmit power signals to the first storage
  • the array 401 and the second storage array 402 provide power signals.
  • the data reading and writing process of each memory cell in the first memory array 401 and the second memory array 402 requires a process of charging and discharging, and the charging of the memory cell requires the internal power supply of the memory, that is, in the layout of the memory cell During the design process, it is necessary to set up a corresponding power network to connect the internal power supply.
  • the power network includes power wires extending in different directions.
  • the data transmission wires are arranged between the power wires, and the power wires can be used as shielding wires to suppress adjacent data transmission. Data interference between wires, without adding additional shielding wires, and without adding additional layouts.
  • the data transmission wires also include low-bit transmission wires and high-bit data wires, wherein the status transmission wires are used to transmit status data in the storage array, and the high-bit transmission wires are used to transmit storage data. High data in the array.
  • the low-bit transmission wires are used to transmit 1-8 bits of data
  • the high-bit transmission wires are used to transmit 9-16 bits of data.
  • the low-order transmission wire and the high-order transmission wire are used to transmit data stored in different storage arrays, that is, the low-order transmission wire and the high-order transmission wire are used as parallel data transmission wires. Data transmission to further improve the efficiency of data transmission and the accuracy of data transmission.
  • the storage block 430 further includes: a plurality of storage sub-blocks 440 arranged continuously in the second direction perpendicular to the first direction X, and the plurality of storage sub-blocks 440 share the same read-write module 410 That is, a plurality of storage sub-blocks 440 belonging to the same storage block 430 arranged in a direction parallel to the data transmission area 100 share an adjacent read-write module 410 .
  • a storage structure 400 includes only the first storage array 401 and the second storage array 402 as an example to describe the distance; in practical applications, the storage structure 400 may also include a third storage array, At this time, the corresponding forwarding module 420 is set in the first storage array and the second storage array, thereby realizing the data reading and writing of the third storage array; correspondingly, it is also possible to continue to set the fourth storage array, etc.;
  • the specific implementation schemes in which different data transmission paths are set should all belong to the protection scope of this patent.
  • this embodiment uses a storage structure 400 arranged in parallel as an example and does not constitute a limitation to this embodiment.
  • multiple storage structures are included in the first direction X, and each The data transmission method of the storage structure is the same as the storage structure illustrated above.
  • the data reading and writing of the second storage array 402 avoids the forwarding of the data through the reading and writing module 410 of the first storage array 401, so that the first storage array 401 and the second storage array 402
  • the data transmission path is separated, and the data in the first storage array 401 and the second storage array 402 can be alternately read and written in the follow-up, so as to reduce the difference in the data read delay of different storage arrays and avoid reading data with a long delay Truncate the read data with a short delay to improve the data transmission margin; in addition, by separating the data transmission paths of the first storage array 401 and the second storage array 402, in the process of reading and writing data, only need to judge the data Belonging to the writing process or reading process, the data transmission direction can be confirmed, avoiding the complicated data path judgment process when using the same data transmission path, so as to achieve higher data transmission rate and accuracy of data transmission.
  • a logical unit may be a physical unit, or a part of a physical unit, or may be realized by a combination of multiple physical units.
  • units that are not closely related to solving the technical problems raised by the present disclosure are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.
  • Another embodiment of the present disclosure provides a data transmission circuit to improve the efficiency of data transmission for reading and writing of a memory.
  • Fig. 4 is a schematic diagram of the structure of the data transmission circuit provided in this embodiment
  • Fig. 5 is a schematic diagram of the specific structure of the control module provided in this embodiment
  • Fig. 6 is a schematic diagram of a specific connection mode of the data transmission structure provided in this embodiment
  • Fig. 7 is a schematic diagram of the specific structure of the data transmission structure when data is read out provided by this embodiment
  • FIG. 8 is a schematic diagram of the specific structure of the data transmission structure when data is written in this embodiment.
  • the circuit is described in further detail as follows:
  • the data transmission circuit is set in the data transmission area 100, including:
  • each data transmission structure is connected to at least one storage circuit provided by the above-mentioned embodiment, for reading and writing data of the storage circuit;
  • Each data transmission structure includes a storage transmission end 111, a bus transmission end 112 and an interactive transmission end 113, wherein the storage transmission end 111 is used for connecting the storage area 102, the bus transmission end 112 is used for connecting the data bus 103, and the interactive transmission end 113 is used for It is connected to the interactive transmission end 113 of another data transmission structure.
  • the data input from the storage transmission terminal 111 is output through the bus transmission terminal 112 or through the interactive transmission terminal 113
  • the data input from the bus transmission terminal 112 is output through the storage transmission terminal 111 or through the interactive transmission terminal 113.
  • the data input by the transmission terminal 113 is output through the bus transmission terminal 112 or output through the storage transmission terminal 111
  • the data input from the interactive transmission terminal 113 is the data input by the bus transmission terminal 112 or the storage transmission terminal 111 in another data transmission structure 101 .
  • the control module 104 is connected to the data transmission structure 101, and receives the input control signal and the adjustment control signal provided by the associated memory.
  • control module 104 is configured to, based on the adjustment control signal, delay the output of the input control signal to generate an output control signal corresponding to the input control signal, and the input control signal and the output control signal are used for Indicates the data transfer path of the data transfer structure 101 .
  • the adjustment control signal is generated based on the memory belonging to the data transmission circuit, and is used to control the delay between the corresponding input control signal and output control signal.
  • the data transmission paths of the two data transmission structures 101 are controlled by the control module 104, so that different data transmission structures transmit data alternately, corresponding to the same data transmission structure 101, data transmission in different storage areas 102 can be realized, through the alternate transmission of multiple data , making the data transmission more compact, thereby improving the data transmission efficiency of the memory.
  • the number of data transmission structures can be any even number greater than 2, and the data transmission circuit is formed between two data transmission structures, so as to further improve the data transmission efficiency of the memory.
  • the signal delay between the input control signal and the output control signal is controlled by the adjustment control signal, which is beneficial to avoid opening the output terminal earlier or later than the preset timing, and ensure that the data transmission structure accurately outputs the corresponding input data.
  • the storage transmission end 111 includes: a first transmission end A, a second transmission end B, a third transmission end C, and a fourth transmission end D;
  • the bus transmission end 112 includes: the first transmission end The fifth transmission terminal E and the sixth transmission terminal F;
  • the interactive transmission terminal 113 includes: the seventh transmission terminal G and the eighth transmission terminal H.
  • the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, and the fourth transmission terminal D are connected to different storage areas 102 of the memory, and the first transmission terminal A and the third transmission terminal C are used to transmit low-order data, The second transmission terminal B and the fourth transmission terminal D are used to transmit high-order data; the fifth transmission terminal E and the sixth transmission terminal F are used for data interactive transmission between the data transmission structure 101 and the data bus 103; the seventh transmission terminal G and the eighth transmission terminal H are used for data interactive transmission between the two data transmission structures 101 .
  • the first transmission terminal A and the second transmission terminal B can be used to transmit the high-order data and low-order data of the same data, for example, for the transmission of 16-bit data, the first transmission terminal A is used to transmit the low-order 8 bits data, the second transmission terminal B is used to transmit high 8-bit data; the first transmission terminal A and the second transmission terminal B can also be used to transmit different data, for example, for the transmission of 8-bit data, the first transmission terminal A and the second transmission terminal B are used to transmit different data.
  • the fifth transmission terminal E is used for data interactive transmission between the data transmission structure 101 and the data bus 103
  • the sixth transmission terminal F is used for a single transmission from the data transmission structure 101 to the data bus 103.
  • the data can only be input through the fifth transmission terminal E, and through the fifth transmission terminal E.
  • Setting the ECC module at the transmission end E can complete the on-die ECC (on die ECC) detection of the data, and will not additionally increase the circuit layout settings required for ECC detection when using the above data transmission circuit for data transmission.
  • the input control signals include: Sel A, Sel B, Sel C, Sel D, Sel E, Sel F, Sel G, and Sel H;
  • the output control signals include: Drv A , Drv B, Drv C, Drv D, Drv E, Drv F, Drv G, and Drv H.
  • the input control signal corresponding to the first transmission terminal A is Sel A, and the output control signal is Drv A;
  • the input control signal corresponding to the second transmission terminal B is Sel B, and the output control signal is Drv B;
  • the third transmission terminal C corresponds to The input control signal is Sel C, the output control signal is Drv C;
  • the input control signal corresponding to the fourth transmission terminal D is Sel D, and the output control signal is Drv D;
  • the input control signal corresponding to the fifth transmission terminal E is Sel E,
  • the output control signal is Drv E;
  • the input control signal corresponding to the sixth transmission terminal F is Sel F, and the output control signal is Drv F;
  • the input control signal corresponding to the seventh transmission terminal G is Sel G, and the output control signal is Drv G;
  • the input control signal corresponding to the eight transmission terminals H is Sel H, and the output control signal is Drv H.
  • the data input from the storage transmission end 111 is output through the bus transmission end 112 or through the interaction transmission end 113, that is, from the first transmission end A, the second transmission end B, the third transmission end C and
  • the data read by the fourth transmission terminal D can be read by the fifth transmission terminal E and the sixth transmission terminal F or by the seventh transmission terminal G and the eighth transmission terminal H.
  • the data input from the bus transmission end 112 is output through the storage transmission end 111 or output through the interactive transmission end 113, that is, the data written from the fifth transmission end E can be passed through the first transmission end A, the second transmission end B, the second transmission end Write through the third transmission terminal C and the fourth transmission terminal D or write through the seventh transmission terminal G and the eighth transmission terminal H.
  • the data input from the interactive transmission terminal 113 is output through the bus transmission terminal 112 or output through the storage transmission terminal 111, that is, the data input from the seventh transmission terminal G and the eighth transmission terminal H can pass through the first transmission terminal A and the second transmission terminal A.
  • the transmission terminal B, the third transmission terminal C and the fourth transmission terminal D write or read through the fifth transmission terminal E and the sixth transmission terminal F.
  • the data transmission structure 101 includes: an input unit 201 configured to receive at least one input data and an input control signal, and output input data corresponding to the input control signal based on the input control signal.
  • the output unit 203 is configured to receive the input data output by the input unit 201 and at least one output control signal, and is configured to output the input data based on a valid port represented by the output control signal.
  • the latch unit 204 connected to the output unit 203 , is configured to latch input data output by the output unit 203 .
  • the input unit 201 includes: a plurality of input controllers 211, each input controller 211 corresponds to the storage transmission end 111, the bus transmission end 112 or the interaction transmission end 113; each input controller 211 is configured to receive the corresponding storage transmission end 111.
  • the input data and the input control signal of the bus transmission end 112 or the interactive transmission end 113, the input controller 211 is configured to turn on the corresponding port based on the input control signal, so as to output the input data of the corresponding port.
  • the read data is read through the first transmission terminal A, the second transmission terminal B, the third transmission terminal C or the fourth transmission terminal D to read the data transmission structure 101 connected.
  • the data in the storage area can also be read out from the storage area connected to another data transmission structure 101 through the seventh transmission terminal G and the eighth transmission terminal H.
  • the input data Data A of the first transmission terminal A is connected to an input controller 211, and the input controller is controlled by the input control signal Sel A, and when the input control signal Sel A is received, the input data Data A of the first transmission terminal A is output.
  • the input data Data B of the second transmission terminal B is connected to an input controller 211, the input controller is controlled by the input control signal Sel B, and when the input control signal Sel B is received, the input data Data of the second transmission terminal B is output B
  • the input data Data C of the third transmission terminal C is connected to an input controller 211, the input controller is controlled by the input control signal Sel C, and when the input control signal Sel C is received, the input data Data of the third transmission terminal C is output C
  • the input data Data D of the fourth transmission terminal D is connected to an input controller 211, the input controller is controlled by the input control signal Sel D, and when the input control signal Sel D is received, the input data Data of the fourth transmission terminal D is output D
  • the input data Data G of the seventh transmission terminal G is connected to an input
  • the write data is written into the data transmission structure 101 through the fifth transmission terminal E, and another data transmission can also be written through the seventh transmission terminal G and the eighth transmission terminal H. Write data received by structure 101.
  • the input data Data E of the fifth transmission terminal E is connected to an input controller 211, the input controller is controlled by the input control signal Sel E, and when the input control signal Sel E is received, the input data Data E of the fifth transmission terminal E is output E;
  • the input data Data G of the seventh transmission terminal G is connected to an input controller 211, the input controller is controlled by the input control signal Sel G, and when the input control signal Sel G is received, the input data Data G of the seventh transmission terminal G is output G;
  • the input data Data H of the eighth transmission terminal H is connected to an input controller 211, the input controller is controlled by the input control signal Sel H, and when the input control signal Sel H is received, the input data Data H of the eighth transmission terminal H is output H.
  • a masking unit 202 is also included, configured to generate mask data DM according to the input data Data E of the fifth transmission end E, and the mask data DM is processed by the input controller 211 corresponding to the fifth transmission end E. Data input, to realize the selection input of data on the data bus 103 .
  • the memory includes a data mask function and a data inversion function.
  • the data mask When the data mask is valid, the corresponding 8-bit data is not written. To save power, reverse the written 8-bit data.
  • the data mask (DM) and data bus inversion (DBI) functions are turned on at the same time, since both the data mask signal and the data bus inversion signal need to use the same data port, only one input can be selected.
  • This disclosure selects the input data inversion signal, that is to say, when data is written, the input data and the data inversion signal are transmitted to the data transmission structure together.
  • the valid data inversion signal When the data inversion signal is valid, the input data Data E representing synchronous input Inversion is required, because there is no need for inversion if the input data Data E is not written, therefore, the valid data inversion signal also indicates that the input data Data E needs to be written; when the data inversion signal is invalid, if the input data For normal input, 0s should account for the majority of the input data. That is to say, when the data inversion signal is invalid, it is necessary to detect whether 0s account for half or more of the input data. Turn and input normally, if 0 accounts for a minority and 1 accounts for a majority, it means that the input data at this time indicates that the data mask signal is valid, and the corresponding 8-bit input data is masked and not stored in the storage array.
  • the fifth transmission terminal E receives the 8-bit original data to be written, and the inversion unit 207 receives the inversion control signal DBI, and the inversion control signal DBI at this time represents the data inversion signal Effective, for example, the inversion control signal DBI is 1, and the data input by the input unit 201 is inverted to be output to the output unit 203; when the data inversion signal is invalid, it is determined according to the content of Data E that the fifth transmission terminal E receives the data to be written.
  • the 8-bit original data or mask data DM input specifically, when the data inversion signal is invalid, the input and output Data E is compiled by the mask unit 202 to judge whether the data mask signal is valid (assuming that it is 1 effectively, invalid is 0), if the data mask DM is valid, it means that the 8-bit original data does not need to be written.
  • the fifth transmission terminal E receives the mask data DM. If the data mask DM is invalid, it means that the 8-bit original data needs to be written. Write, at this time, the fifth transmission terminal E receives the input data Data E.
  • any data transmission structure only inverts the data input by the corresponding fifth transmission terminal E, that is, when writing data, the inversion control subunit 221 receives the inversion control signal DBI will only be the input data Data
  • the inverting control signal corresponding to E is not the inverting control signal corresponding to the input data Data G and Data H. This is because for the data input by the seventh input terminal Sel G and the eighth input terminal Sel H, that is, the data input by the data bus 103 through another data transmission structure, the input data is at the inverting unit 207 of another data transmission structure.
  • the above data inversion process has been completed in .
  • the output unit 203 includes: a plurality of output controllers 212, each output controller 212 corresponds to the storage transmission end 111, the bus transmission end 112 or the interaction transmission end 113; each output controller 212 is configured to receive the corresponding storage transmission end 111 , the input data and the output control signal of the bus transmission end 112 or the interactive transmission end 113 , the output controller 212 is configured to be turned on based on the output control signal to output the input data.
  • the read data is read to the data bus 103 through the fifth transmission terminal E or the sixth transmission terminal F, or can be read through the seventh transmission terminal G and the eighth transmission terminal H. output to another data transmission structure 101 , and finally read to another corresponding data bus 103 through the corresponding fifth transmission terminal E or sixth transmission terminal F of another data transmission structure 101 .
  • the output controller 212 connected to the fifth transmission terminal E is controlled by the output control signal Drv E, and when the output control signal Drv E is received, the data is output through the fifth transmission terminal E;
  • the output controller connected to the seventh transmission terminal G 212 is controlled by the output control signal Drv G, and when the output control signal Drv G is received, the data is output through the seventh transmission terminal G;
  • the output controller 212 connected to the eighth transmission terminal H is controlled by the output control signal Drv H, and when received The control signal Drv H is output, and the data is output through the eighth transmission terminal H.
  • write data is written into the data transmission structure 101 connected through the first transmission terminal A, the second transmission terminal B, the third transmission terminal C or the fourth transmission terminal D.
  • the storage area can also be written into a storage area connected to another data transmission structure 101 through the seventh transmission terminal G and the eighth transmission terminal H.
  • the output controller 212 connected to the first transmission terminal A is controlled by the output control signal Drv A, and when the output control signal Drv A is received, the data is output through the first transmission terminal A;
  • the output controller connected to the second transmission terminal B 212 is controlled by the output control signal Drv B, and when the output control signal Drv B is received, the data is output through the second transmission terminal B;
  • the output controller 212 connected to the third transmission terminal C is controlled by the output control signal Drv C, and when received
  • the output control signal Drv C outputs the data through the third transmission terminal C;
  • the output controller 212 connected to the fourth transmission terminal D is controlled by the output control signal Drv D, and when the output control signal Drv D is received, the data is transmitted through the fourth transmission terminal Terminal D output;
  • the output controller 212 connected to the seventh transmission terminal G is controlled by the output control signal Drv G, and when the output control signal Drv G is received, the data is output through the seventh transmission terminal G;
  • the output connected to the eighth transmission terminal H The controller
  • the latch unit 204 includes: a first inverter 214 and a second inverter 213 connected end to end, and the input terminal of the first inverter 214 and the output terminal of the second inverter 213 are connected to The output terminals of the output unit 203 are connected in parallel, and the output terminals of the output unit 203 are connected in parallel through the latch unit 204 to realize the preservation of the output data of the output unit 203;
  • the latch unit includes: The first inverter and the second inverter are connected, and the first inverter and the input terminal and the output terminal of the second inverter are connected in series with the output port of the input unit, and the output terminal of the output unit is connected through the latch unit connected in series to realize inversion latching of the output data of the output unit, and then to save the output data of the output unit through series connection of inverters.
  • the input of the data is delayed to further ensure the accuracy of the data during the multiplex transmission.
  • the data transmission structure further includes: an input selection unit 205 and a trigger unit 206 .
  • the input selection unit 205 is configured to receive at least one input control signal, and generate a gate pulse corresponding to the input control signal, the gate pulse corresponds to the effective port represented by the input control signal, and the gate pulse corresponds to the input control signal There is a selection delay between them; the trigger unit 206, the clock terminal is connected to the input selection unit 205, the input terminal is connected to the input unit 201, and the output terminal is connected to the output unit 203, which is configured to transmit the input data received by the input terminal based on the strobe pulse to the output.
  • the input selection unit 205 includes: a trigger subunit 215, configured to receive at least one input control signal, if an input control signal is received, an indication signal is generated; a delay subunit 216, connected to the trigger subunit 215, is configured to respond to the indication signal Delaying; the conversion subunit 217, connected to the delay subunit 216, is configured to convert the delayed indication signal into a strobe pulse.
  • the indication signal is delayed by the delay subunit 216 to ensure that the data transmission structure accurately outputs the corresponding input data; the specific delay parameters of the delay subunit 216 are set based on the associated memory. In some embodiments, the delay subunit 216 The specific delay parameters can be adjusted by the staff.
  • the trigger subunit 215 is realized by an OR gate.
  • the trigger subunit 215 When data is read, with reference to FIG. , the trigger subunit 215 generates an indication signal based on the active level of the input control signal Sel A, Sel B, Sel C, Sel D, Sel G or Sel H, and after the indication signal is delayed by the delay subunit 216, the conversion subunit 217 Convert to a strobe pulse to drive the trigger unit 206; when data is written, with reference to FIG.
  • the effective level of Sel G or Sel H generates an indication signal, and after being delayed by the delay subunit 216, the indication signal is converted into a gate pulse by the conversion subunit 217 to drive the trigger unit 206.
  • the trigger unit is composed of a D flip-flop.
  • the data transmission structure 101 further includes: an inversion unit 207, disposed between the trigger unit 206 and the input unit 201, configured to output the input data or invert the input data based on the inversion control signal After output.
  • an inversion unit 207 disposed between the trigger unit 206 and the input unit 201, configured to output the input data or invert the input data based on the inversion control signal After output.
  • the data is output directly or after inversion through the inversion unit to reduce the data energy consumption of the data transmission structure 101; specifically, because the low-level energy consumption during data transmission is relatively low Less energy consumption can be saved by transmitting data at a low level.
  • the inversion control signal is used to control the data inversion before transmission; If the high-level data is less than the low-level data, the data is directly transmitted through the inversion control signal.
  • the inverting unit 207 includes: an inversion control subunit 221 configured to receive an inversion control signal, and generate a first control signal and a second control signal based on the inversion control signal; the first selection subunit 222 and the second selection subunit 223, after parallel connection, the input terminal is configured to receive input data, and the output terminal is connected to the trigger unit 206; the first selection subunit 222 is configured to invert the input data based on the conduction of the first control signal Output later; the second selection subunit 223 is configured to output the input data directly based on the conduction of the second control signal.
  • first control signal and the second control signal can be used as two signals to drive the first selection subunit 222 and the second selection subunit 223, or can be used as high and low levels of the same signal to drive the first selection subunit. unit 222 and a second selection subunit 223 .
  • the inversion unit 207 further includes: a judging subunit 224 configured to receive input data and generate an inversion control signal based on the input data.
  • the data transmission paths of the two data transmission structures 101 are controlled by the control module 104, so that different data transmission structures transmit data alternately, and corresponding to the same data transmission structure 101, data transmission in different storage areas 102 can be realized.
  • the alternate transmission makes the data transmission more compact, thereby improving the data transmission efficiency of the memory.
  • the signal driving method mentioned in this embodiment is described as an example of whether the signal exists. Drive, that is, the signal exists, and it is driven according to whether the level of the signal is an active level.
  • a logical unit may be a physical unit, or a part of a physical unit, or may be realized by a combination of multiple physical units.
  • units that are not closely related to solving the technical problems raised by the present disclosure are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.
  • Another embodiment of the present disclosure provides a memory.
  • the storage circuit provided by the above embodiments is used to set up a memory array, so as to improve the efficiency of reading and writing data transmission of the memory and ensure the accuracy of data transmission.
  • the memory is a DRAM chip, wherein the memory of the DRAM chip conforms to the DDR2 memory specification.
  • the memory is a DRAM chip, wherein the memory of the DRAM chip conforms to the DDR3 memory specification.
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR4 memory specification.
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR5 memory specification.
  • the embodiments of the present disclosure may be provided as a method, an apparatus (device), or a computer program product. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein.
  • Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data , including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can be used in Any other medium, etc. that stores desired information and can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more processes of the flowchart and/or one or more blocks of the block diagram
  • the storage circuit provided in the present disclosure can improve the read-write data transmission efficiency of the memory and ensure the accuracy of data transmission.

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Abstract

本公开是关于一种存储电路、数据传输电路和存储器。所述存储电路包括：平行于数据传输区域设置的至少一个存储结构，每一存储结构包括在第一方向上相邻设置的第一存储阵列和第二存储阵列，第一存储阵列与数据传输区域的距离小于第二存储阵列与数据传输区域的距离，第一方向为靠近数据传输区域的方向；第一存储阵列中包含读写模块和转发模块，第二存储阵列中包含读写模块，第一存储阵列基于第一存储阵列中的读写模块与数据传输区域进行数据交互，第二存储阵列基于第二存储阵列中的读写模块和第一存储阵列中的转发模块与数据传输区域进行数据传输。

Description

存储电路、数据传输电路和存储器
本公开基于2022年02月24日提交中国专利局、申请号为202210174060.X,发明名称为“存储电路、数据传输电路和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种存储电路、数据传输电路和存储器。
背景技术
动态随机存储存储器(Dynamic Random Access Memory，DRAM)具有数据非易失性、省电、体积小，以及无机械结构等特性，适宜作为移动设备的存储设备。
随着技术的进步，消费者对移动设备的性能要求越来越高，使得存储设备传输速率成为评判存储设备优良的关键参数。
发明内容
为克服相关技术中存在的问题，本公开提供一种存储电路、数据传输电路和存储器，以提高存储器的读写数据传输效率，并保证数据传输的准确性。
本公开示例性的实施例中提供了一种存储电路，相邻于数据传输区域设置，包括：平行于数据传输区域设置的至少一个存储结构，每一存储结构包括在第一方向上相邻设置的第一存储阵列和第二存储阵列，第一存储阵列与数据传输区域的距离小于第二存储阵列与数据传输区域的距离，第一方向为靠近数据传输区域的方向；第一存储阵列中包含读写模块和转发模块，第二存储阵列中包含读写模块，第一存储阵列基于第一存储阵列中的读写模块与数据传输区域进行数据交互，第二存储阵列基于第二存储阵列中的读写模块和第一存储阵列中的转发模块与数据传输区域进行数据传输。
通过转发模块的设置，对第二存储阵列的数据读写避免了数据经过第一存储阵列的读写模的转发，从而将第一存储阵列和第二存储阵列的数据传输路径分离，后续可以实现交替读写第一存储阵列和第二存储阵列中的数据，从而减小不同存储阵列数据读出延时的差值，避免延迟较长的读出数据截短延迟较短的读出数据，提升数据传输裕度；另外，通过将第一存储阵列和第二存储阵列的数据传输路径分离，在进行数据读写的过程中，只需判断数据属于写入过程或读出过程，即可确认数据的传输方向，避免了使用同一数据传输路径时，繁杂的数据通路判断过程，从而达到更高的数据传输速率，和数据传输的准确性。
在一示例性的实施例中，第一存储阵列和第二存储阵列中，包括：在第一方向上连续设置的偶数个存储块，且相邻每两个不重复的存储块共用一读写模块，读写模块设置于对应的两个存储块之间。
在一示例性的实施例中，存储块还包括：在垂于第一方向的第二方向上连续设置的多个存储子块，多个存储子块共用同一读写模块。
在一示例性的实施例中，第一存储阵列中的读写模块和第二存储阵列中的读写模块共同沿第一方向排列，在垂直于第一方向的第二方向上，转发模块设置于读写模块的相对一侧；通过对读写模块和转发模块的规整设置，使得读写模块与转发模块之间的数据传输导线可以规整设置，通过最短的数据传输导线，降低数据传输导线的电阻，提高数据传输的速率和准确性。
在一示例性的实施例中，每一读写模块的相对一侧设置有一转发模块；通过多个转发模 块之间近距离传输和对数据的多次转发，降低数据在传输过程中出现错误的可能性。
在一示例性的实施例中，读写模块、转发模块与数据传输区域之间的数据传输导线设置在相邻电源导线之间，电源导线被配置为接收和传输电源信号，以向第一存储阵列和第二存储阵列提供电源信号；将数据传输导线设置在电源导线之间，不会额外增大存储阵列所占用的版图面积。
在一示例性的实施例中，数据传输导线包括低位传输导线和高位传输导线，其中，低位传输导线被配置为传输存储阵列中的低位数据，高位传输导线被配置为传输存储阵列中的高位数据，以进一步提高数据的传输效率和数据传输的准确性。
本公开示例性的实施例还提供了一种数据传输电路，设置在数据传输区域中，包括：至少两个数据传输结构，每一数据传输结构连接至少一个上述实施例提供的存储电路，被配置为存储电路的数据读写；每一数据传输结构包括存储传输端、总线传输端和交互传输端，其中，存储传输端被配置为连接存储电路，总线传输端被配置为连接数据总线，交互传输端被配置为连接另一数据传输结构；从存储传输端输入的数据，通过总线传输端输出或通过交互传输端输出；从总线传输端输入的数据，通过存储传输端输出或通过交互传输端输出；从交互传输端输入的数据，通过总线传输端输出或通过存储传输端输出，其中，从交互传输端输入的数据为另一数据传输结构中的总线传输端或存储传输端输入的数据；控制模块，连接数据传输结构，并接收所属存储器提供的输入控制信号和调整控制信号，控制模块被配置为，基于调整控制信号对输入控制信号进行延迟输出，以生成对应于输入控制信号的输出控制信号，输入控制信号和输出控制信号被配置为指示数据传输结构的数据传输路径。
在一示例性的实施例中，数据传输结构，包括：输入单元，被配置为接收至少一个输入数据和输入控制信号，基于输入控制信号，输出输入控制信号对应的输入数据；输出单元，被配置为接收输入单元输出的输入数据和至少一个输出控制信号，被配置为，基于输出控制信号表征的有效端口输出输入数据；锁存单元，连接输出单元，被配置为锁存输出单元输出的输入数据。
在一示例性的实施例中，输入单元，包括：多个输入控制器，每一输入控制器对应于存储传输端、总线传输端或交互传输端；每一输入控制器被配置为接收对应存储传输端、总线传输端或交互传输端的输入数据和输入控制信号；输入控制器被配置为，基于输入控制信号导通，以输出输入数据。
在一示例性的实施例中，输出单元，包括：多个输出控制器，每一输出控制器对应于存储传输端、总线传输端或交互传输端；每一输出控制器被配置为接收对应存储传输端、总线传输端或交互传输端的输入单元输出的输入数据和输出控制信号；输出控制器被配置为，基于输出控制信号导通，以输出输入数据。
在一示例性的实施例中，数据传输结构，还包括：输入选择单元，被配置为接收至少一个输入控制信号，生成对应于输入控制信号的选通脉冲，选通脉冲与输入控制信号表征的有效端口相对应，且选通脉冲与输入控制信号之间具有选择延时；触发单元，时钟端连接输入选择单元，输入端连接输入单元，输出端连接输出单元，被配置为，基于选通脉冲，将输入端接收的输入数据传输至输出端。
在一示例性的实施例中，输入选择单元，包括：触发子单元，被配置为接收至少一个输入控制信号，若接收到输入控制信号，生成指示信号；延迟子单元，连接触发子单元，被配置为对指示信号进行延时；转换子单元，连接延迟子单元，被配置为将延时后的指示信号转换为选通脉冲。
在一示例性的实施例中，数据传输结构，还包括：反相单元，设置在触发单元和输入单 元之间，被配置为，基于反相控制信号，输出输入数据，或将输入数据反相后输出。
在一示例性的实施例中，反相单元，包括：翻转控制子单元，被配置为接收反相控制信号，并基于反相控制信号生成第一控制信号和第二控制信号；第一选择子单元和第二选择子单元，并联后输入端被配置为接收输入数据，输出端连接触发单元；第一选择子单元被配置为，基于第一控制信号导通，将输入数据反相后输出；第二选择子单元被配置为，基于第二控制信号导通，将输入数据输出。
在一示例性的实施例中，存储传输端包括：第一传输端、第二传输端、第三传输端和第四传输端；总线传输端包括：第五传输端和第六传输端；交互传输端包括：第七传输端和第八传输端；第一传输端、第二传输端与第三传输端、第四传输端分别连接第一存储阵列和第二存储阵列，且第一传输端和第三传输端被配置为传输低比特位数据，第二传输端和第四传输端被配置为传输高比特位数据；第五传输端和第六传输端被配置为所属数据传输结构与数据总线之间的数据交互传输；第七传输端和第八传输端被配置为两个数据传输结构之间的数据交互传输。
在一示例性的实施例中，第五传输端被配置为所属数据传输结构与数据总线之间的数据交互传输；第六传输端被配置为所属数据传输结构向数据总线的单向数据传输。
本公开示例性的实施例还提供了一种存储器，采用上述实施例提供的存储电路进行存储阵列的设置，以提高存储器的读写数据传输效率，并保证数据传输的准确性。
附图说明
构成本公开的一部分的附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开一实施例提供的存储电路的虚拟结构示意图；
图2为本公开一实施例提供的存储电路的一种具体结构示意图；
图3为本公开一实施例提供的存储电路的另一种具体结构示意图；
图4为本公开另一实施例提供的数据传输电路的结构示意图；
图5为本公开另一实施例提供的控制模块的具体结构示意图；
图6为本公开另一实施例提供的数据传输结构的一种具体连接方式示意图；
图7为本公开另一实施例提供的数据读出时数据传输结构的具体结构示意图；
图8为本公开另一实施例提供的数据写入时数据传输结构的具体结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
图1为本实施例提供的存储电路的虚拟结构示意图，图2为本实施例提供的存储电路的一种具体结构示意图，图3为本实施例提供的存储电路的另一种具体结构示意图，以下结合附图对本实施例提供的存储电路作进一步详细说明，具体如下：
参考图1，存储电路，相邻于数据传输区域100设置，包括：
平行于数据传输区域100设置的至少一个存储结构400，每一存储结构400包括：在第 一方向X上相邻设置的第一存储阵列401和第二存储阵列402，其中，第一方向X为靠近数据传输区域100的方向，且第一存储阵列401与数据传输区域100的距离小于第二存储阵列402与数据传输区域100的距离，即在同一存储结构400中，第一存储阵列401靠近数据传输区域100设置，第二存储阵列402远离数据传输区域100设置。
对于第一存储阵列401，包括：读写模块410和转发模块420，第一存储阵列401基于第一存储阵列401中的读写模块410与数据传输区域进行数据交互；对于第二存储阵列402，包括：读写模块410，第二存储阵列402基于第二存储阵列402中的读写模块410和第一存储阵列401中的转发模块420与数据传输区域100进行数据交互。
即本公开实施例中，读写模块410被配置为与所属存储阵列中存储单元的直接交互，在数据读写过程中，从数据传输区域100写入的输入，通过存储阵列中的多个读写模块410进行传递，从而实现对存储阵列中不同存储单元的写入；而对于与数据传输区域100距离较远的存储阵列，通过在与数据传输区域100距离较近的存储阵列中设置转发模块420，实现将数据快速且准确地传递至相应存储阵列。
具体地，通过转发模块420的设置，对第二存储阵列402的数据读写避免了数据经过第一存储阵列401的读写模块410的转发，从而将第一存储阵列401和第二存储阵列402的数据传输路径分离，后续可以实现交替读写第一存储阵列401和第二存储阵列402中的数据，从而减小不同存储阵列数据读出延时的差值，避免延迟较长的读出数据截短延迟较短的读出数据，提升数据传输裕度；另外，通过将第一存储阵列401和第二存储阵列402的数据传输路径分离，在进行数据读写的过程中，只需判断数据属于写入过程或读出过程，即可确认数据的传输方向，避免了使用同一数据传输路径时，繁杂的数据通路判断过程，从而达到更高的数据传输速率，和数据传输的准确性。
参考图2，在本实施例中，第一存储阵列401和第二存储阵列402中，包括：在第一方向X上连续设置的偶数个存储块430，且相邻每两个不重复的存储块共用一读写模块410，读写模块设置于对应的两个存储块430之间。
具体地，每一存储块430中包括多个存储单元，存储块430通过相邻设置的读写模块410进行数据读写；更具体地，存储块430中包括多根字线和多根位线，每一存储单元都对应有一字线和一位线，通过导通特定字线和位线，以使存储块430中的目标存储单元连接读写模块410，从而实现读写模块410对存储块430中不同存储单元的数据读写。
参考图2和图3，在一些实施例中，第一存储阵列401中的读写模块410和第二存储阵列402中的读写模块共同沿第一方向X排列，在垂直于第一方向X的第二方向上，转发模块420设置于读写模块410的相对一侧。通过对读写模块410和转发模块的规整设置，使得读写模块410与转发模块420之间的数据传输导线可以规整设置，通过最短的数据传输导线，降低数据传输导线的电阻，提高数据传输的速率和准确性。
进一步地，在本实施例中，每一读写模块410的相对一侧设置有转发模块420，通过多个转发模块420之间近距离传输和对数据的多次转发，降低数据在传输过程中出现错误的可能性。
需要说明的是，本实施例附图中每一读写模块410的相对一侧都设置有转发模块420并不构成对本实施例的限定，在其他实施例中，可以相应减少转发模块的数量，仍可实现上述技术效果。
在具体的电路设计中，读写模块410、转发模块420与数据传输区域100之间的数据传输导线设置在相邻电源导线之间，电源导线用于接收和传输电源信号，以向第一存储阵列401和第二存储阵列402提供电源信号。
具体地，第一存储阵列401和第二存储阵列402中各存储单元的数据读写过程都需要进行充放电的过程，而对存储单元的充电需要借助存储器的内部电源，即在存储单元版图的设计过程中，需要设置相应的电源网络以连接内部电源，电源网络包括沿不同方向延伸的电源导线，将数据传输导线设置在电源导线之间，可以利用电源导线作为屏蔽线，抑制相邻数据传输导线之间的数据干扰，同时无需增加额外的屏蔽线，无需增加额外的版图。
另外，在一些实施例中，参考图2和图3，数据传输导线还包括低位传输导线和高位数据导线，其中，地位传输导线用于传输存储阵列中的地位数据，高位传输导线用于传输存储阵列中的高位数据。
在一个例子中，若存储阵列一次传输16bit数据，此时，低位传输导线用于传输第1～8bit的数据，高位传输导线用于传输9～16bit数据。另外，在一些实施例中，若存储阵列一次传输8bit数据，此时低位传输导线和高位传输导线用于传输不同存储阵列存储的数据，即将低位传输导线和高位传输导线作为并列的数据传输导线进行数据传输，以进一步提高数据的传输效率和数据传输的准确性。
在一些实施例中，参考图3，存储块430还包括：在垂直于第一方向X的第二方向上连续设置的多个存储子块440，多个存储子块440共用同一读写模块410，即在平行于数据传输区域100方向上设置的属于同一存储块430的多个存储子块440共用相邻设置的读写模块410。
需要说明的是，本实施例以一个存储结构400中仅包含第一存储阵列401和第二存储阵列402为例进行距离说明；在实际应用中，存储结构400中还可以包括第三存储阵列，此时在第一存储阵列和第二存储阵列中设置相应的转发模块420，从而实现第三存储阵列的数据读写；相应地，还可以继续设置第四存储阵列等；即为每一存储阵列都设置不同的数据传输路径的具体实施方案，都应该属于本专利的保护范围。
需要说明的是，本实施例以平行设置的一个存储结构400进行举例说明并不构成对本实施例的限定，在其他实施例中，在第一方向X上还包括多个存储结构，且每个存储结构的数据传输方式与上述举例说明的存储结构相同。
本实施例通过转发模块420的设置，对第二存储阵列402的数据读写避免了数据经过第一存储阵列401的读写模块410的转发，从而将第一存储阵列401和第二存储阵列402的数据传输路径分离，后续可以实现交替读写第一存储阵列401和第二存储阵列402中的数据，从而减小不同存储阵列数据读出延时的差值，避免延迟较长的读出数据截短延迟较短的读出数据，提升数据传输裕度；另外，通过将第一存储阵列401和第二存储阵列402的数据传输路径分离，在进行数据读写的过程中，只需判断数据属于写入过程或读出过程，即可确认数据的传输方向，避免了使用同一数据传输路径时，繁杂的数据通路判断过程，从而达到更高的数据传输速率，和数据传输的准确性。
本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
需要说明的是，上述实施例所提供的存储电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的存储电路实施例。
本公开另一实施例提供一种数据传输电路，以提高存储器的读写数据传输效率。
图4为本实施例提供的数据传输电路的结构示意图，图5为本实施例提供的控制模块的 具体结构示意图，图6为本实施例提供的数据传输结构的一种具体连接方式示意图，图7为本实施例提供的数据读出时数据传输结构的具体结构示意图，图8为本实施例提供的数据写入时数据传输结构的具体结构示意图，以下结合附图对本实施例提供的数据传输电路作进一步详细说明，具体如下：
参考图4，数据传输电路，设置在数据传输区域100中，包括：
至少两个数据传输结构101，每一数据传输结构连接至少一个上述实施例提供的存储电路，用于存储电路的数据读写；
每一数据传输结构包括存储传输端111、总线传输端112和交互传输端113，其中，存储传输端111用于连接存储区域102，总线传输端112用于连接数据总线103，交互传输端113用于连接另一数据传输结构的交互传输端113。
其中，从存储传输端111输入的数据，通过总线传输端112输出或通过交互传输端113输出，从总线传输端112输入的数据，通过存储传输端111输出或者通过交互传输端113输出，从交互传输端113输入的数据，通过总线传输端112输出或通过存储传输端111输出，从交互传输端113输入的数据为另一数据传输结构101中的总线传输端112或存储传输端111输入的数据。
控制模块104，连接数据传输结构101，并接收所属存储器提供的输入控制信号和调整控制信号。
参考图4，并结合图5，控制模块104被配置为，基于调整控制信号，对输入控制信号进行延迟输出，以生成对应于输入控制信号的输出控制信号，输入控制信号和输出控制信号用于指示数据传输结构101的数据传输路径。
其中，调整控制信号基于数据传输电路所属存储器生成，用于控制相应输入控制信号和输出控制信号之间的延迟。
通过控制模块104控制两个数据传输结构101的数据传输路径，使得不同的数据传输结构交替传输数据，对应同一数据传输结构101，可以实现不同存储区域102的数据传输，通过多路数据的交替传输，使得数据传输更加紧凑，从而提高存储器的数据传输效率。
需要说明的是，在其他实施例中，数据传输结构的数量可以为任意大于2的偶数，两两数据传输结构之间构成上述数据传输电路，从而实现对存储器数据传输效率的进一步提高。
具体地，输入控制信号与输出控制信号之间的信号延迟由调整控制信号控制，有利于避免输出端相对于预设时序提前打开或延后打开，保证数据传输结构准确输出对应的输入数据。在一些实施例中，参考图4和图6，存储传输端111包括：第一传输端A、第二传输端B、第三传输端C和第四传输端D；总线传输端112包括：第五传输端E和第六传输端F；交互传输端113包括：第七传输端G和第八传输端H。
第一传输端A、第二传输端B与第三传输端C、第四传输端D连接所属存储器的不同存储区域102，且第一传输端A和第三传输端C用于传输低位数据，第二传输端B和第四传输端D用于传输高位数据；第五传输端E和第六传输端F用于所属数据传输结构101与数据总线103之间的数据交互传输；第七传输端G和第八传输端H用于两个数据传输结构101之间的数据交互传输。
需要说明的是，对于第一传输端A和第二传输端B，可以用于传输同一数据的高位数据和低位数据，例如对于16位数据的传输，第一传输端A用于传输低8位的数据，第二传输端B用于传输高8位的数据；第一传输端A和第二传输端B也可以用于传输不同数据，例如，对于8位数据的传输，第一传输端A和第二传输端B用于传输不同的数据。
进一步地，在一些实施例中，第五传输端E用于所属数据传输结构101与数据总线103之间的数据交互传输，第六传输端F用于所属数据传输结构101向数据总线103的单向数据传输；通过对第五传输端E和第六传输端F的特殊设置，使得数据由数据总线103输入数据传输结构101时，只能通过第五传输端E进行数据输入，通过在第五传输端E设置ECC模块即可完成对数据的片上ECC(on die ECC)的检测，并不会额外增加使用上述数据传输电路进行数据传输时，进行ECC检测所需的电路版图设置。
在一些实施例中，参考图5并且结合图6，输入控制信号包括：Sel A、Sel B、Sel C、Sel D、Sel E、Sel F、Sel G和Sel H；输出控制信号包括：Drv A、Drv B、Drv C、Drv D、Drv E、Drv F、Drv G和Drv H。
其中，第一传输端A对应的输入控制信号为Sel A，输出控制信号为Drv A；第二传输端B对应的输入控制信号为Sel B，输出控制信号为Drv B；第三传输端C对应的输入控制信号为Sel C，输出控制信号为Drv C；第四传输端D对应的输入控制信号为Sel D，输出控制信号为Drv D；第五传输端E对应的输入控制信号为Sel E，输出控制信号为Drv E；第六传输端F对应的输入控制信号为Sel F，输出控制信号为Drv F；第七传输端G对应的输入控制信号为Sel G，输出控制信号为Drv G；第八传输端H对应的输入控制信号为Sel H，输出控制信号为Drv H。
参考图4和图6，从存储传输端111输入的数据，通过总线传输端112输出或通过交互传输端113输出，即从第一传输端A、第二传输端B、第三传输端C和第四传输端D读出的数据，可以通过第五传输端E和第六传输端F读出或通过第七传输端G和第八传输端H读出。
从总线传输端112输入的数据，通过存储传输端111输出或者通过交互传输端113输出，即从第五传输端E写入的数据，可以通过第一传输端A、第二传输端B、第三传输端C和第四传输端D写入或通过第七传输端G和第八传输端H写入。
从交互传输端113输入的数据，通过总线传输端112输出或通过存储传输端111输出，即从第七传输端G和第八传输端H输入的数据，可以通过第一传输端A、第二传输端B、第三传输端C和第四传输端D写入或通过第五传输端E和第六传输端F读出。
参考图7和图8，数据传输结构101，包括：输入单元201，被配置为接收至少一个输入数据和输入控制信号，基于输入控制信号，输出输入控制信号对应的输入数据。
输出单元203，被配置为接收输入单元201输出的输入数据和至少一个输出控制信号，被配置为，基于输出控制信号表征的有效端口输出输入数据。
锁存单元204，连接输出单元203，被配置为锁存输出单元203输出的输入数据。
输入单元201包括：多个输入控制器211，每一输入控制器211对应于存储传输端111、总线传输端112或交互传输端113；每一输入控制器211被配置为接收对应的存储传输端111、总线传输端112或交互传输端113的输入数据和输入控制信号，输入控制器211被配置为，基于输入控制信号导通对应的端口，以输出对应端口的输入数据。
具体地，对于数据的读出，参考图7，读出数据通过第一传输端A、第二传输端B、第三传输端C或第四传输端D读出该数据传输结构101所连接的存储区域的数据，也可以通过第七传输端G和第八传输端H读出另一数据传输结构101所连接的存储区域的数据。
其中，第一传输端A的输入数据Data A连接一输入控制器211，该输入控制器通过输入控制信号Sel A控制，当接收到输入控制信号Sel A，输出第一传输端A的输入数据Data A；第二传输端B的输入数据Data B连接一输入控制器211，该输入控制器通过输入控制信号Sel B控制，当接收到输入控制信号Sel B，输出第二传输端B的输入数据Data B；第三传输端C 的输入数据Data C连接一输入控制器211，该输入控制器通过输入控制信号Sel C控制，当接收到输入控制信号Sel C，输出第三传输端C的输入数据Data C；第四传输端D的输入数据Data D连接一输入控制器211，该输入控制器通过输入控制信号Sel D控制，当接收到输入控制信号Sel D，输出第四传输端D的输入数据Data D；第七传输端G的输入数据Data G连接一输入控制器211，该输入控制器通过输入控制信号Sel G控制，当接收到输入控制信号Sel G，输出第七传输端G的输入数据Data G；第八传输端H的输入数据Data H连接一输入控制器211，该输入控制器通过输入控制信号Sel H控制，当接收到输入控制信号Sel H，输出第八传输端H的输入数据Data H。
具体地，对于数据的写入，参考图8，写入数据通过第五传输端E写入该数据传输结构101，也可以通过第七传输端G和第八传输端H写入另一数据传输结构101所接收的写入数据。
其中，第五传输端E的输入数据Data E连接一输入控制器211，该输入控制器通过输入控制信号Sel E控制，当接收到输入控制信号Sel E，输出第五传输端E的输入数据Data E；第七传输端G的输入数据Data G连接一输入控制器211，该输入控制器通过输入控制信号Sel G控制，当接收到输入控制信号Sel G，输出第七传输端G的输入数据Data G；第八传输端H的输入数据Data H连接一输入控制器211，该输入控制器通过输入控制信号Sel H控制，当接收到输入控制信号Sel H，输出第八传输端H的输入数据Data H。
在一些实施例中，还包括掩码单元202，被配置为根据第五传输端E的输入数据Data E生成掩码数据DM，掩码数据DM通过第五传输端E对应的输入控制器211进行数据输入，以实现对数据总线103上数据的选择输入。
具体地，存储器包含数据掩码功能和数据反转功能，当数据掩码有效时，对应的8位数据不写入，当写入的8位数据中1占多数时，若传输通路传0更省电，则对写入的8位数据进行反转。在同时开启数据掩码(data mask，DM)和数据反转(databus inversion，DBI)功能时，由于数据掩码信号和数据反转信号都需要利用到同一数据端口，因此只能择一输入，本公开选择输入数据反转信号，也就是说，在进行数据写入时，输入数据和数据反转信号一同传输至数据传输结构，当数据反转信号有效时，表征同步输入的输入数据Data E需要进行反转，由于如果不写入输入数据Data E就没有进行反转的必要，因此，数据反转信号有效还表征输入数据Data E需要写入；当数据反转信号无效时，若输入数据为正常输入，则输入数据中0应当占多数，也就是说，当数据反转信号无效时，需要检测输入数据中0是否占半数或半数以上，若占半数或半数以上，则不经过数据反转且正常输入，若0占少数且1占多数，则说明此时输入数据表征的是数据掩码信号有效，屏蔽对应的8位输入数据，不存入存储阵列中。
也就是说，当数据反转信号有效时，第五传输端E接收待写入的8位原始数据，反相单元207接收反相控制信号DBI，此时的反相控制信号DBI表征数据翻转信号有效，例如反相控制信号DBI为1，并将输入单元201输入的数据进行翻转以输出至输出单元203；当数据反转信号无效时，根据Data E的内容确定第五传输端E接收待写入的8位原始数据或者掩码数据DM，具体的，当数据反转信号无效时，通过掩码单元202对输入输出Data E进行编译，判断数据掩码信号是否有效(假设有效为1，无效为0)，若数据掩码DM表征有效，则说明8位原始数据无需写入，此时第五传输端E接收掩码数据DM，若数据掩码DM表征无效，则说明8位原始数据需要写入，此时第五传输端E接收输入数据Data E。
需要说明的是，任一数据传输结构仅对对应的第五传输端E输入的数据进行反相，即进行数据写入时，翻转控制子单元221接收反相控制信号DBI只会是输入数据Data E对应的反相控制信号，而不会是输入数据Data G和Data H对应的反相控制信号。这是因为对于第七输入端Sel G和第八输入端Sel H输入的数据，即数据总线103通过另一数据传输结构输入 的数据，此时输入数据在另一数据传输结构的反相单元207中已完成上述数据反相过程。
输出单元203包括：多个输出控制器212，每一输出控制器212对应于存储传输端111、总线传输端112或交互传输端113；每一输出控制器212被配置为接收对应的存储传输端111、总线传输端112或交互传输端113的输入数据和输出控制信号，输出控制器212被配置为，基于输出控制信号导通，以输出输入数据。
具体地，对于数据的读出，参考图7，读出数据通过第五传输端E或第六传输端F读出至数据总线103，也可以通过第七传输端G和第八传输端H读出至另一数据传输结构101，最终通过另一数据传输结构101对应的第五传输端E或第六传输端F读出至对应的另一数据总线103。
其中，连接第五传输端E的输出控制器212通过输出控制信号Drv E控制，当接收到输出控制信号Drv E，将数据通过第五传输端E输出；连接第七传输端G的输出控制器212通过输出控制信号Drv G控制，当接收到输出控制信号Drv G，将数据通过第七传输端G输出；连接第八传输端H的输出控制器212通过输出控制信号Drv H控制，当接收到输出控制信号Drv H，将数据通过第八传输端H输出。
具体地，对于数据的写入，参考图8，写入数据通过第一传输端A、第二传输端B、第三传输端C或第四传输端D写入该数据传输结构101所连接的存储区域，也可以通过第七传输端G和第八传输端H写入另一数据传输结构101所连接的存储区域。
其中，连接第一传输端A的输出控制器212通过输出控制信号Drv A控制，当接收到输出控制信号Drv A，将数据通过第一传输端A输出；连接第二传输端B的输出控制器212通过输出控制信号Drv B控制，当接收到输出控制信号Drv B，将数据通过第二传输端B输出；连接第三传输端C的输出控制器212通过输出控制信号Drv C控制，当接收到输出控制信号Drv C，将数据通过第三传输端C输出；连接第四传输端D的输出控制器212通过输出控制信号Drv D控制，当接收到输出控制信号Drv D，将数据通过第四传输端D输出；连接第七传输端G的输出控制器212通过输出控制信号Drv G控制，当接收到输出控制信号Drv G，将数据通过第七传输端G输出；连接第八传输端H的输出控制器212通过输出控制信号Drv H控制，当接收到输出控制信号Drv H，将数据通过第八传输端H输出。
在本实施例中，锁存单元204包括：首尾相连的第一反相器214和第二反相器213，且第一反相器214的输入端和第二反相器213的输出端与输出单元203的输出端并联，通过锁存单元204与输出单元203的输出端并联，以实现对输出单元203输出数据的保存；需要说明的是，在其他实施例中，锁存单元包括：首尾相连的第一反相器和第二反相器，且第一反相器和输入端和第二反相器的输出端与输入单元的输出端口串联，通过锁存单元与输出单元的输出端串联，以实现对输出单元输出数据的反相锁存，后续通过串联反相器，以实现出输出单元输出数据的保存。
在一些实施例中，还通过对数据的输入进行延迟，以进一步保证数据在多路传输过程中的准确性。
具体地，数据传输结构，参考图7和图8，还包括：输入选择单元205和触发单元206。
其中，输入选择单元205，被配置为接收至少一个输入控制信号，生成对应于输入控制信号的选通脉冲，选通脉冲与输入控制信号表征的有效端口相对应，且选通脉冲与输入控制信号之间具有选择延时；触发单元206，时钟端连接输入选择单元205，输入端连接输入单元201，输出端连接输出单元203，被配置为，基于选通脉冲，将输入端接收的输入数据传输至输出端。
输入选择单元205，包括：触发子单元215，被配置为接收至少一个输入控制信号，若接收到输入控制信号，生成指示信号；延迟子单元216，连接触发子单元215，被配置为对指示信号进行延时；转换子单元217，连接延迟子单元216，被配置为将延时后的指示信号转换为选通脉冲。
通过延时子单元216对指示信号进行延迟，保证数据传输结构准确输出对应的输入数据；延时子单元216的具体延时参数基于所属存储器设定，在一些实施例中，延时子单元216的具体延时参数可以通过工作人员进行调配。
在本实施例中触发子单元215通过或门实现，在数据读出时，参考图7，输入控制信号Sel A、Sel B、Sel C、Sel D、Sel G或Sel H输入触发子单元215中，触发子单元215基于输入控制信号Sel A、Sel B、Sel C、Sel D、Sel G或Sel H的有效电平生成指示信号，指示信号经过延迟子单元216延时后，由转换子单元217转换为选通脉冲以驱动触发单元206；在数据写入时，参考图5，输入控制信号Sel E、Sel G或Sel H输入触发子单元215中，触发子单元215基于输入控制信号Sel E、Sel G或Sel H的有效电平生成指示信号，指示信号经过延迟子单元216延时后，由转换子单元217转换为选通脉冲以驱动触发单元206。
在一些实施例中，触发单元由D触发器构成。
在一些实施例中，数据传输结构101还包括：反相单元207，设置在触发单元206和输入单元201之间，被配置为，基于反相控制信号，输出输入数据，或者将输入数据反相后输出。
通过将数据量化后输出反相控制信号，通过反相单元对数据直接输出或反相后输出，以降低数据传输结构101的数据能耗；具体地，由于数据传输时低电平的耗能较少，通过低电平传输数据能够节省能耗，通过对数据进行量化，若数据中的高电平数据多于低电平数据，则通过反相控制信号控制数据反相后传输；若数据中的高电平数据少于低电平数据，则通过反相控制信号控制数据直接传输。
参考图7和图8，反相单元207包括：翻转控制子单元221，被配置为接收反相控制信号，并基于反相控制信号生成第一控制信号和第二控制信号；第一选择子单元222和第二选择子单元223，并联后输入端被配置为接收输入数据，输出端连接触发单元206；第一选择子单元222被配置为，基于第一控制信号导通，将输入数据反相后输出；第二选择子单元223被配置为，基于第二控制信号导通，将输入数据直接输出。
需要说明的是，第一控制信号和第二控制信号可以作为两个信号来驱动第一选择子单元222和第二选择子单元223，也可以作为同一信号的高低电平来驱动第一选择子单元222和第二选择子单元223。
参考图7，在一些实施例中，反相单元207还包括：判断子单元224，被配置为接收输入数据并基于输入数据生成反相控制信号。
本实施例通过控制模块104控制两个数据传输结构101的数据传输路径，使得不同的数据传输结构交替传输数据，对应同一数据传输结构101，可以实现不同存储区域102的数据传输，通过多路数据的交替传输，使得数据传输更加紧凑，从而提高存储器的数据传输效率。
需要说明的是，本实施例中提到的信号驱动方式中是以信号是否存在为例进行的描述，在具体的应用中，可以根据信号是否存在进行驱动，也可以根据信号的高低电平进行驱动，即信号存在，根据信号的电平是否为有效电平进行驱动。
本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为 了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
需要说明的是，上述实施例所提供的数据传输电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的数据传输电路实施例。
本公开又一实施例提供一种存储器，采用上述实施例提供的存储电路进行存储阵列的设置，以提高存储器的读写数据传输效率，并保证数据传输的准确性。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR2内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR3内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR4内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR5内存规格。
本领域技术人员应明白，本公开的实施例可提供为方法、装置(设备)、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质上实施的计算机程序产品的形式。计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质,包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质等。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本公开是参照根据本公开实施例的方法、装置(设备)和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其 他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括所述要素的物品或者设备中还存在另外的相同要素。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开的意图也包含这些改动和变型在内。
工业实用性
本公开中提供的存储电路，能够提高存储器的读写数据传输效率，并保证数据传输的准确性。

Claims (18)

  1. 一种存储电路，相邻于数据传输区域设置，所述存储电路包括：
    平行于所述数据传输区域设置的至少一个存储结构，每一所述存储结构包括在第一方向上相邻设置的第一存储阵列和第二存储阵列，所述第一存储阵列与所述数据传输区域的距离小于所述第二存储阵列与所述数据传输区域的距离，所述第一方向为靠近所述数据传输区域的方向；
    所述第一存储阵列中包含读写模块和转发模块，所述第二存储阵列中包含读写模块，所述第一存储阵列基于所述第一存储阵列中的所述读写模块与所述数据传输区域进行数据交互，所述第二存储阵列基于所述第二存储阵列中的读写模块和所述第一存储阵列中的所述转发模块与所述数据传输区域进行数据传输。
  2. 根据权利要求1所述的存储电路，其中，所述第一存储阵列和所述第二存储阵列中，包括：在所述第一方向上连续设置的偶数个存储块，且相邻每两个不重复的所述存储块共用一所述读写模块，所述读写模块设置于对应的两个所述存储块之间。
  3. 根据权利要求2所述的存储电路，其中，所述存储块还包括：在垂于所述第一方向的第二方向上连续设置的多个存储子块，所述多个存储子块共用同一所述读写模块。
  4. 根据权利要求1或2所述的存储电路，其中，所述第一存储阵列中的所述读写模块和所述第二存储阵列中的所述读写模块共同沿所述第一方向排列，在垂直于所述第一方向的第二方向上，所述转发模块设置于所述读写模块的相对一侧。
  5. 根据权利要求4所述的存储电路，其中，所述每一所述读写模块的相对一侧设置有一所述转发模块。
  6. 根据权利要求1所述的存储电路，其中，所述读写模块、所述转发模块与所述数据传输区域之间的数据传输导线设置在相邻电源导线之间，所述电源导线被配置为接收和传输电源信号，以向所述第一存储阵列和所述第二存储阵列提供所述电源信号。
  7. 根据权利要求6所述的存储电路，其中，所述数据传输导线包括低位传输导线和高位传输导线，其中，所述低位传输导线被配置为传输存储阵列中的低位数据，所述高位传输导线被配置为传输所述存储阵列中的高位数据。
  8. 一种数据传输电路，设置在数据传输区域中，包括：
    至少两个数据传输结构，每一所述数据传输结构连接至少一个权利要求1-7中任一项所述的存储电路，被配置为所述存储电路的数据读写；
    每一所述数据传输结构包括存储传输端、总线传输端和交互传输端，其中，所述存储传输端被配置为连接所述存储电路，所述总线传输端被配置为连接数据总线，所述交互传输端被配置为连接另一所述数据传输结构；
    从所述存储传输端输入的数据，通过所述总线传输端输出或通过所述交互传输端输出；
    从所述总线传输端输入的数据，通过所述存储传输端输出或通过所述交互传输端输出；
    从所述交互传输端输入的数据，通过所述总线传输端输出或通过所述存储传输端输出，其中，从所述交互传输端输入的数据为另一所述数据传输结构中的所述总线传输端或所述存储传输端输入的数据；
    控制模块，连接所述数据传输结构，并接收所属存储器提供的输入控制信号和调整控制信号，所述控制模块被配置为，基于所述调整控制信号对所述输入控制信号进行延迟输出，以生成对应于所述输入控制信号的输出控制信号，所述输入控制信号和所述输出控制信号被配置为指示所述数据传输结构的数据传输路径。
  9. 根据权利要求8所述的数据传输电路，其中，所述数据传输结构，包括：
    输入单元，被配置为接收至少一个输入数据和所述输入控制信号，基于所述输入控制信 号，输出所述输入控制信号对应的所述输入数据；
    输出单元，被配置为接收所述输入单元输出的所述输入数据和至少一个所述输出控制信号，被配置为，基于所述输出控制信号表征的有效端口输出所述输入数据；
    锁存单元，连接所述输出单元，被配置为锁存所述输出单元输出的所述输入数据。
  10. 根据权利要求9所述的数据传输电路，其中，所述输入单元，包括：
    多个输入控制器，每一所述输入控制器对应于所述存储传输端、所述总线传输端或所述交互传输端；
    每一所述输入控制器被配置为接收对应所述存储传输端、所述总线传输端或所述交互传输端的所述输入数据和所述输入控制信号；
    所述输入控制器被配置为，基于所述输入控制信号导通，以输出所述输入数据。
  11. 根据权利要求9所述的数据传输电路，其中，所述输出单元，包括：
    多个输出控制器，每一所述输出控制器对应于所述存储传输端、所述总线传输端或所述交互传输端；
    每一所述输出控制器被配置为接收对应所述存储传输端、所述总线传输端或所述交互传输端的所述输入单元输出的所述输入数据和所述输出控制信号；
    所述输出控制器被配置为，基于所述输出控制信号导通，以输出所述输入数据。
  12. 根据权利要求9所述的数据传输电路，其中，所述数据传输结构，还包括：
    输入选择单元，被配置为接收至少一个所述输入控制信号，生成对应于所述输入控制信号的选通脉冲，所述选通脉冲与所述输入控制信号表征的有效端口相对应，且所述选通脉冲与所述输入控制信号之间具有选择延时；
    触发单元，时钟端连接所述输入选择单元，输入端连接所述输入单元，输出端连接所述输出单元，被配置为，基于所述选通脉冲，将所述输入端接收的所述输入数据传输至所述输出端。
  13. 根据权利要求12所述的数据传输电路，其中，输入选择单元，包括：
    触发子单元，被配置为接收至少一个所述输入控制信号，若接收到所述输入控制信号，生成指示信号；
    延迟子单元，连接所述触发子单元，被配置为对所述指示信号进行延时；
    转换子单元，连接所述延迟子单元，被配置为将延时后的所述指示信号转换为所述选通脉冲。
  14. 根据权利要求12所述的数据传输电路，其中，所述数据传输结构，还包括：反相单元，设置在所述触发单元和所述输入单元之间，被配置为，基于反相控制信号，输出所述输入数据，或将所述输入数据反相后输出。
  15. 根据权利要求14所述的数据传输电路，其中，所述反相单元，包括：
    翻转控制子单元，被配置为接收所述反相控制信号，并基于所述反相控制信号生成第一控制信号和第二控制信号；
    第一选择子单元和第二选择子单元，并联后输入端被配置为接收所述输入数据，输出端连接所述触发单元；
    所述第一选择子单元被配置为，基于所述第一控制信号导通，将所述输入数据反相后输出；
    所述第二选择子单元被配置为，基于所述第二控制信号导通，将所述输入数据输出。
  16. 根据权利要求8所述的数据传输电路，其中，所述存储传输端包括：第一传输端、第二传输端、第三传输端和第四传输端；所述总线传输端包括：第五传输端和第六传输端；所述交互传输端包括：第七传输端和第八传输端；
    所述第一传输端、所述第二传输端与所述第三传输端、所述第四传输端分别连接第一存 储阵列和第二存储阵列，且所述第一传输端和所述第三传输端被配置为传输低比特位数据，所述第二传输端和所述第四传输端被配置为传输高比特位数据；所述第五传输端和所述第六传输端被配置为所属所述数据传输结构与所述数据总线之间的数据交互传输；所述第七传输端和所述第八传输端被配置为两个所述数据传输结构之间的数据交互传输。
  17. 根据权利要求16所述的数据传输电路，包括：
    所述第五传输端被配置为所属所述数据传输结构与所述数据总线之间的数据交互传输；
    所述第六传输端被配置为所属所述数据传输结构向所述数据总线的单向数据传输。
  18. 一种存储器，采用权利要求1-7任一项所述的存储电路进行存储阵列的设置。
PCT/CN2022/087829 2022-02-24 2022-04-20 存储电路、数据传输电路和存储器 WO2023159733A1 (zh)

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