WO2021159412A1 - 一种存储器、网络设备及数据访问方法 - Google Patents

一种存储器、网络设备及数据访问方法 Download PDF

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Publication number
WO2021159412A1
WO2021159412A1 PCT/CN2020/075139 CN2020075139W WO2021159412A1 WO 2021159412 A1 WO2021159412 A1 WO 2021159412A1 CN 2020075139 W CN2020075139 W CN 2020075139W WO 2021159412 A1 WO2021159412 A1 WO 2021159412A1
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Prior art keywords
read
channel
memory
bus group
write
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PCT/CN2020/075139
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English (en)
French (fr)
Inventor
张先富
王正波
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华为技术有限公司
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Priority to EP20918817.6A priority Critical patent/EP4089543A4/en
Priority to PCT/CN2020/075139 priority patent/WO2021159412A1/zh
Priority to CN202080078353.7A priority patent/CN114667509A/zh
Publication of WO2021159412A1 publication Critical patent/WO2021159412A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of memory technology, and in particular to a memory, network equipment, and data access method.
  • the memory and the processor are respectively used as two important components of electronic equipment to store information and process information, and their performance directly affects the performance of network equipment.
  • the performance of the processor has been rapidly improved at a rate of approximately 60% per year, while the performance of the memory has only been improved at a rate of approximately 10% per year.
  • the unbalanced development speed has caused the current storage access speed to seriously lag behind the processor’s computing speed.
  • the storage bottleneck has made it difficult for high-performance processors to perform their due functions. Great constraints.
  • the bus bit width refers to the number of bits of the storage data bus
  • the operating frequency refers to the stored clock frequency
  • the transmission rate refers to the number of times each data bus transmits data in a clock pulse cycle.
  • the size of the storage bandwidth depends on the three factors of bus bit width, operating frequency and transmission rate.
  • DDR storage uses double data rate.
  • Each data line can prefetch 2 bits of data from the memory cell, and transmit 1 bit of data on the rising and falling edges of the clock pulse.
  • the transfer rate of the clock cycle is 2, and the data transfer volume of DDR storage at the same frequency is twice that of single data rate storage.
  • the transfer rates of DDR2 storage and DDR3 storage are 4 times and 8 times that of single data rate storage, respectively.
  • This application provides a memory, a network device, and a data access method, which are used to implement the same device's requirements for different storage bandwidths.
  • a memory in a first aspect, includes: at least one channel, at least one channel including a first channel; Take the data of the first channel, and the first read-write bus group is used to read the data of the first channel or write data to the first channel.
  • the first channel in the memory corresponds to the first read bus group and the first read and write bus group.
  • the first read-write bus group is used as a read bus group or a write bus group, and the first read bus group and the first read-write bus group access the first channel of the memory.
  • the read and write bandwidth requirements are balanced (for example, the read and write bandwidth is 50% read and 50% write)
  • the first read and write bus group is used as the write bus group to read and write the memory together with the first read bus.
  • the first read and write bus group is used as the read bus group to read the data of the memory together with the first read bus. In this way, the requirements of the same memory for different read and write bandwidths can be realized.
  • At least one channel further includes a second channel, the second channel corresponds to the second read and write bus group, and the second read and write bus group is used to read the data or direction of the second channel. Write data in the second channel.
  • the second channel may correspond to the second read and write bus group, so that the second channel of the memory can be accessed through the second read and write bus.
  • the bus bit widths of the first read-write bus group and the second read-write bus group are different.
  • the bit widths of the data buses included in the first read-write bus group and the second read-write bus group are different, and/or the address buses included in the two have different bit widths, and the bit widths of the data buses may be different. Including different bit widths of read data lines and/or different bit widths of write data lines.
  • At least one read-write bus has different read-write functions in the first read-write bus group and the second read-write bus group.
  • the read and write functions of the first read and write bus group and the second read and write bus group may be different, for example, the first read and write bus group supports bit mask writing, and the second read and write bus group supports byte Mask writing, thereby improving the flexibility of access to the memory.
  • the second channel also corresponds to a second read bus group, and the second read bus group is used to read data of the second channel.
  • the second channel in the memory corresponds to a second read bus group and a second read and write bus group.
  • the second read and write bus group When accessing the second channel of the memory, it can be based on the read and write bandwidth requirements for data read and write.
  • the bus bit widths of the first read bus group and the second read bus group are different.
  • the bit widths of the data buses included in the first read bus group and the second read bus group are different, and/or the bit widths of the address buses included in the two are different.
  • At least one read bus group has a different read function from the first read bus group and the second read bus group.
  • the read functions of the first read bus group and the second read bus group may be different.
  • the first read bus group supports bit mask reading
  • the second read bus group supports byte mask reading.
  • both the read bus group and the read-write bus group include a control bus, an address bus, and a data bus.
  • the memory includes N SRAMs stacked three-dimensionally, and N is an integer greater than 1.
  • a memory composed of N SRAMs stacked three-dimensionally can meet the requirements of the same storage device for different storage bandwidths.
  • each of the at least one channel includes multiple memory banks, and the multiple memory banks included in each channel are correspondingly provided with a read bus group and a read and write bus. Group.
  • each channel in the memory can realize the requirements of the same channel for different read and write bandwidths.
  • a network device in a second aspect, includes a processor and a memory.
  • the processor is used to access the memory.
  • the memory is the memory provided in the first aspect or any possible implementation of the first aspect.
  • the network device is a network switching and forwarding device.
  • the network switching and forwarding device includes a router or a switch.
  • a data access method is provided, which is applied to a network device including a processor and a memory.
  • the memory includes a first channel.
  • the first channel corresponds to a first read bus group and a first read and write bus group.
  • the method includes: The processor accesses the first channel in the memory through the first read bus group and the first read and write bus group.
  • the processor accessing the first channel in the memory through the first read bus group and the first read-write bus group includes: the processor enables the first read-write bus group It is a write bus group; the processor reads the data of the first channel in the memory through the first read bus group, and writes data to the first channel in the memory through the first read-write bus group.
  • the processor accesses the first channel of the memory through the first read bus group and the first read-write bus group, and further includes: the processor enables the first read-write bus group To read the bus group; the processor reads the data of the first channel in the memory through the first read bus group and the first read-write bus.
  • the memory further includes a second channel corresponding to the second read-write bus group
  • the method further includes: the processor accesses the memory through the second read-write bus group The second channel.
  • the second channel also corresponds to a second read bus group
  • the method further includes: the processor reads the data in the second channel through the second read bus group.
  • any of the network devices and data access methods provided above includes the memory provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the memory provided above. Here No longer.
  • Figure 1 is a schematic diagram of the comparison of processor performance and memory performance growth
  • FIG. 2 is a schematic structural diagram of an HBM provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a memory provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a network device provided by an embodiment of this application.
  • FIG. 5 is a schematic flowchart of a data access method provided by an embodiment of the application.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • And/or describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one item (a) or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the embodiments of the present application use words such as "first" and "second” to distinguish the same items or similar items that have substantially the same function and effect.
  • the first threshold and the second threshold are only for distinguishing different thresholds, and the order of their order is not limited. Those skilled in the art can understand that words such as “first” and “second” do not limit the number and execution order.
  • the memory and the processor are respectively used as two important components of electronic equipment to store information and process information, and their performance directly affects the performance of network equipment.
  • the memory and the processor are respectively used as two important components of electronic equipment to store information and process information, and their performance directly affects the performance of network equipment.
  • the performance of the processor has been rapidly improved at a rate of about 60% per year, while the performance of the memory has only been improved by about 10% per year.
  • the annual speed improvement gap between the two is about 50%. %.
  • Accumulated over a long period of time the unbalanced development speed has caused the current storage access speed to seriously lag behind the processor’s computing speed.
  • the storage bottleneck has made it difficult for high-performance processors to perform their due functions.
  • Great constraints In fact, as early as 1994, scientists analyzed and predicted this problem, and named this storage bottleneck that seriously hindered the performance of the processor as a memory wall.
  • the bus bit width refers to the number of bits of the storage data bus
  • the operating frequency refers to the stored clock frequency
  • the transmission rate refers to the number of times each data bus transmits data in a clock pulse cycle.
  • the size of the storage bandwidth depends on the three factors of bus bit width, operating frequency and transmission rate.
  • Increasing the storage transfer rate A method to increase the storage bandwidth by increasing the transfer rate.
  • DDR storage uses double data rate. Each data line can prefetch 2 bits of data from the memory cell, and transmit 1 bit of data on the rising and falling edges of the clock pulse.
  • the transfer rate of the clock cycle is 2, and the data transfer volume of DDR storage at the same frequency is twice that of single data rate storage.
  • the transfer rates of DDR2 storage and DDR3 storage are 4 times and 8 times that of single data rate storage, respectively.
  • Rambus's "Gigabyte Bandwidth" technology can increase the transmission rate to 32, thereby greatly increasing the storage bandwidth.
  • the above-mentioned methods of increasing storage bandwidth are difficult to play to their advantages for network devices such as switches and routers. This is because these network devices require different storage bandwidths for forwarding different data such as business messages and business table entries.
  • the read and write bandwidth required for business messages is 50% read and 50% write, while the service table The required read and write bandwidth for this item is 95% read and 5% write.
  • the embodiments of the present application provide a memory, a network device, and a data access method, which are used to meet the requirements of the same storage device for different storage bandwidths, and at the same time, it can also increase the storage bandwidth.
  • the technical solution of the present application can be applied to various memories, such as flash and random access memory (RAM).
  • RAM random access memory
  • the technical solution of the present application can be applied to various types of RAM, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), and synchronous dynamic random access memory. (synchronous DRAM, SDRAM), etc.
  • DRAM may also include multi-rate DRAM and high bandwidth memory (HBM).
  • DRAMs with multiple data rates may include double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, and so on.
  • SRAM is a type of random access memory RAM.
  • static means that as long as the memory is powered on, the data stored in it can be kept constantly.
  • DRAM dynamic random access memory
  • the data stored in the SRAM needs to be updated periodically.
  • volatile memory which is different from the ROM or flash memory that can store data after a power failure.
  • DDR SDRAM can be abbreviated as DDR, and its data transmission speed is twice or more than the system clock. Due to the increase in speed, its transmission performance is better than traditional SDRAM. DDR SDRAM can transmit data on both the rising and falling edges of the system clock.
  • Table 1 below lists the bus clock, internal rate, prefetch, transfer rate, and voltage of several SDRAMs with different data rates such as DDR, DDR2, DDR3, and DDR4. (voltage).
  • Table 2 lists the number of pins (pins) of several SDRAMs with different data rates when implemented with different types of memory modules.
  • Different types of memory modules can include dual inline memory modules (DIMMs) , Small outline (small outline dual inline memory modules, SO-DIMM) and micro dual inline memory modules (micro DIMM).
  • HBM is a high-performance DRAM based on 3D stacking process initiated by Samsung Electronics, Advanced Micro Devices and SK Hynix, that is, stacking and packaging multiple DRAM dies such as 2/4/8 based on the 3D stacking process.
  • the formed memory has high bandwidth characteristics.
  • HBM is suitable for applications with high memory bandwidth requirements, such as graphics processors, network switching and forwarding equipment (such as routers, switches), etc.
  • DDR4 or GDDR5 Compared with DDR4 or GDDR5, HBM achieves a higher bandwidth with a smaller volume and less power.
  • FIG. 2 is a schematic structural diagram of an HBM die provided by an embodiment of the application.
  • the HBM die may include a logic die and multiple memory dies.
  • the micro-bumps are stacked together and connected to the logic die.
  • the logic die may be a die integrated with control logic, and the control logic may be a memory controller, which can be specifically used to manage and control the reading and writing of multiple memory dies.
  • the storage unit in the memory die is divided into multiple banks (banks), and the multiple banks are divided into multiple channels (channels) according to their corresponding data bus, address bus, and control bus.
  • the memory bank in the same channel uses the same one or more buses to read and write data.
  • the bus mentioned here includes data bus, address bus and control bus; memory banks in different channels use different Bus reads and writes data.
  • each memory die may include two channels (channels), each channel may be 128 bits (bit), a channel may also be called a channel, and a channel may include multiple memory banks. (bank).
  • the HBM die includes 4 memory dies, each memory die includes two channels CH0 and CH1, and each channel includes 8 memory banks as an example.
  • Figure 2 (a) is the HBM bare The top view of the chip, (b) in Figure 2 is the side view of the HBM die.
  • the multiple memory dies in Figure 2 can be multiple DRAM dies, or multiple SRAM dies, that is, multiple DRAMs can be formed in a three-dimensional stacking manner as shown in Figure 2 above.
  • a plurality of SRAMs may also be formed in a three-dimensional stacking manner as shown in FIG. 2 above.
  • the embodiment of the present application does not limit the specific type of the memory die.
  • the three-dimensional stacked DRAM memory has one channel corresponding to a set of data buses, because it is limited by the DRAM timing parameters.
  • the bandwidth of a channel is close to the sum of all memory banks in a channel.
  • SRAM does not have the timing parameter limitation similar to DRAM
  • the bandwidth of a single memory bank matches the bandwidth of a single channel, so a memory composed of multiple SRAMs stacked three-dimensionally It can support multiple sets of bus access, so that bandwidth can be improved by expanding multiple sets of buses.
  • the embodiment of the present application provides a memory that supports multiple sets of bus access.
  • Figure 3 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • the memory includes at least one channel, at least one channel includes a first channel, and the first channel corresponds to the first read bus group and the first read and write bus group.
  • the read bus group is used to read the data of the first channel
  • the first read-write bus group is used to read the data of the first channel or write data to the first channel.
  • the memory may be a memory composed of multiple SRAMs stacked three-dimensionally.
  • the at least one channel may include one or more channels
  • the first channel may be any one of the at least one channel
  • each channel may include a plurality of continuous storage banks
  • the plurality of continuous storage banks may be correspondingly provided with One read bus group and one read and write bus group.
  • at least one channel includes C channels, each channel includes B consecutive memory banks, and the first channel is the first channel among the C channels for illustration, and C is a positive integer.
  • the first read bus group may include a control bus, an address bus, and a data bus.
  • the control bus may include a clock line CLK and a chip enable line CEN
  • the address bus may include m1 address lines A[m1-1:0]
  • the data bus may include n1 read lines.
  • m1 and n1 are positive integers, for example, m1 is equal to 32 and n1 is equal to 128.
  • each type of bus in the first read bus group can be shown in Table 3 below.
  • the input and output type of the clock line CLK is input, and the power supply is VDDP/VDD, which is defined as system clock input
  • the input and output type of the chip enable line CEN is input, and the power supply is VDDP/VDD is defined as chip enable input, and is active low
  • the input and output type of address bus A[m1-1:0] is input, and the power supply is VDDP/VDD is defined as the address input bus interface
  • the input and output type of the data bus Q[n1-1:0] is output, and the power supply is VDDP/VDD, which is defined as the read output data bus used by the read interface. data bus for read port).
  • the first read-write bus group may also include a control bus, an address bus, and a data bus.
  • the control bus may include a clock line CLK, a chip enable line CEN, and a write enable line WEN
  • the address bus may include m2 address lines A[m2-1:0]
  • the data bus may include n2 read data lines Q[n2-1:0] and n3 write data lines D[n3-1:0].
  • m1 and n1 are positive integers, for example, m2 is equal to 64, n2 is equal to 128, and n3 is equal to 128.
  • each type of bus in the first read-write bus group can be shown in Table 4 below.
  • the input and output type of the clock line CLK is input, and the power supply is VDDP/VDD, which is defined as system clock input
  • the input and output type of the chip enable line CEN is input, and the power supply is VDDP/VDD is defined as chip enable input, and is active low
  • the input and output type of address bus A[m2-1:0] is input, and the power supply is VDDP/VDD is defined as the address input bus interface
  • the input and output type of the read data bus Q[n2-1:0] is output, and the power supply is VDDP/VDD, which is defined as the read output data bus used by the read interface (read output data bus for read port)
  • the input and output type of the write enable line WEN is input, and the power supply is VDDP/VDD, which is defined as write enable input, and it is active at low level. low
  • the first read and write bus group can be used as a read bus group, that is, through the clock line CLK, the chip enable line CEN, the address bus A[m2-1:0] and the read bus group.
  • the data address Q[n2-1:0] can read the data in the first channel in the memory.
  • the first read and write bus group can be used as the write bus group, that is, through the clock line CLK, chip enable line CEN, address bus A[m2-1:0] and write data address D [n3-1:0] Can write data to the first channel in the memory.
  • the first read and write bus group can be used as the write bus group, and the data in the first channel can be read based on the first read bus group.
  • the first channel in the memory corresponds to the first read bus group and the first read and write bus group.
  • the first channel of the memory When accessing the first channel of the memory, it can be based on the read and write bandwidth requirements for data read and write.
  • At least one channel further includes a second channel, the second channel corresponds to the second read and write bus group, and the second read and write bus group is used to read data from the second channel or send data to the second channel.
  • Write data
  • the second channel is the C-th channel as an example.
  • the descriptions of the second read-write bus group and the various types of buses included in the first read-write bus group are basically the same. For details, please refer to the description of the first read-write bus group, which is not repeated here in the embodiment of the present application.
  • the first read-write bus group and the second read-write bus group may adopt a homogeneous bus architecture or a heterogeneous bus architecture.
  • the homogeneous bus architecture means that all buses in the first read-write bus group and the second read-write bus group are exactly the same. For example, the bit widths of various types of buses are the same, and the read and write functions of the same type of buses Are the same.
  • Heterogeneous bus architecture refers to the existence of different buses in the first read bus group and the second read and write bus group, for example, there are different types of buses, and/or the bit widths of the same type of buses are different, and/or the same type The read and write functions of the type of bus are different.
  • the bus bit widths of the first read-write bus group and the second read-write bus group are different, which may specifically mean that the bit widths of the data buses included in the two are different, and/or the two include The bit width of the address bus is different, and the bit width of the data bus is different, which may include the bit width of the read data line and/or the bit width of the write data line.
  • the second read-write bus group includes m3 address lines, n4 read data lines, and n5
  • the bus bit widths of the first read-write bus group and the second read-write bus group are different, which may specifically include: m2 and m3 are not equal, n2 and n4 are not equal, and/or n3 and n5 are not equal.
  • the read and write functions of at least one read and write bus in the first read and write bus group and the second read and write bus group are different, which may specifically refer to the read function of the read data line included in the two. Different, and/or the write functions of the write data lines included in the two are different.
  • the first read and write bus group includes n2 read data lines and n3 write data lines
  • the second read and write bus group includes n4 read data lines and n5 write data lines
  • both read and write Different functions can specifically include: n2 read data lines support bit mask reading, n3 write data lines support bit mask writing, n4 read data lines support byte mask reading, and n5 write data The line supports byte mask writing.
  • the corresponding definition of the write data bus D[n3-1:0] can be used as the write interface
  • the ratio closes the mask bus, and the high level is valid (bit write mask bus for write port, active high), as shown in Table 5 below.
  • the second channel can correspond to one set of buses or two sets of buses.
  • the second channel may only correspond to the second read and write bus, that is, the second channel can only be accessed through the second read and write bus.
  • the second channel can also correspond to the second read bus, that is, the second channel is similar to the first channel and can correspond to a set of read bus and a set of read and write bus.
  • the second channel also corresponds to the second read bus group, and the second read bus group is used to read the data of the second channel.
  • the descriptions of the various types of buses included in the second read bus group and the first read bus group are basically the same. For details, please refer to the description of the first read bus group, which is not repeated in this embodiment of the present application.
  • the bus bit widths of the first read bus group and the second read bus group are different, which may specifically mean that the bit widths of the read data lines included in the two are different, and/or the addresses included in the two
  • the bit width of the bus is different.
  • the read function of at least one read bus is different between the first read bus group and the second read bus group.
  • the first channel or the second channel can also correspond to buses with other functions.
  • Other functions can include data bus inversion (DBI), data input mask (DM), and clock enable ( clock enable, CKE), parity (parity, PAR), data error (DERR), strobes (strobes), address error (AERR), etc., which will not be described in detail in the embodiments of this application .
  • the memory may also be other memory, for example, a memory formed by stacking multiple Flash dies, a memory formed by multiple MRAM dies, etc., which is not specifically limited in the embodiment of the present application.
  • the network device includes a memory 201 and a processor 202 coupled with the memory 201.
  • the memory 201 may be the memory provided in FIG. 3, which can be used to store instructions, data, etc.; the processor 202 is used to control and manage the actions of the network device.
  • the network device further includes a communication interface 203 and a bus 204.
  • the memory 201, the processor 202 and the communication interface 203 are connected via the bus 204, and the communication interface 203 is used to support communication between the network device and other devices.
  • the processor 202 may be a central processing unit, a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in conjunction with the disclosure of this application.
  • the processor may also be a combination that implements computing functions, for example, a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on.
  • the bus 204 may be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus, etc.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • the bus 204 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 4 to represent it, but it does not mean that there is only one bus or one type of bus.
  • the network device is a network switching and forwarding device.
  • the network switching and forwarding equipment may include routers or switches, etc.
  • FIG. 5 is a schematic flowchart of a data access method provided by an embodiment of the application.
  • the method can be applied to a network device including a processor and a memory.
  • the memory includes a first channel, and the first channel corresponds to the first read bus group and For the first read and write bus group, the method may include the following steps.
  • S301 The processor accesses the first channel in the memory through the first read bus group and the first read-write bus group.
  • the memory may include at least one channel, and the first channel may be any one of the at least one channel. It should be noted that, for the relevant description of the memory, reference may be made to the description in FIG. 3, and details are not repeated here in the embodiment of the present application.
  • the first read bus group may include a control bus, an address bus, and a data bus.
  • the control bus may include a clock line CLK and a chip enable line CEN
  • the address bus may include m1 address lines.
  • the data bus may include n1 read data lines Q[n1-1:0].
  • m1 and n1 are positive integers, for example, m1 is equal to 32 and n1 is equal to 128.
  • the first read-write bus group may also include a control bus, an address bus, and a data bus.
  • the control bus may include a clock line CLK, a chip enable line CEN, and a write enable line WEN
  • the address bus may include m2 address lines A[m2-1:0]
  • the data bus may include n2 read data lines Q[n2-1:0] and n3 write data lines D[n3-1:0].
  • the processor enables the first read and write bus group to be a write bus group, for example, the write enable line WEN is set to a low level, so that the first read and write bus group is used as a write bus group; through the first read bus
  • the group reads the data of the first channel in the memory, for example, to enable the chip enable line CEN, on the rising and falling edge of the clock signal corresponding to the clock line CLK, through the address line A[m1-1:0] and the read data line Q [n1-1:0] Read the data in the first channel; write data to the first channel in the memory through the first read-write bus group, for example, enable the chip enable line CEN, which corresponds to the clock line CLK The rising and falling edges of the clock signal write data into the first channel through the address line A[m2-1:0] and the write data line D[n3-1:0].
  • the processor enables the first read and write bus group to be a read bus group, for example, the write enable line WEN is set to a high level, so that the first read and write bus group is used as a read bus group; through the first read bus group And the first read-write bus to read the data of the first channel in the memory, for example, to enable the chip enable line CEN, on the rising and falling edges of the clock signal corresponding to the clock line CLK, respectively through the address line A[m1-1:0 ] And read data line Q[n3-1:0], as well as address line A[m2-1:0] and read data line Q[n2-1:0] to read the data in the first channel.
  • the write enable line WEN is set to a high level, so that the first read and write bus group is used as a read bus group; through the first read bus group And the first read-write bus to read the data of the first channel in the memory, for example, to enable the chip enable line CEN, on the rising and falling edges of the clock signal corresponding to the clock
  • the first channel in the memory corresponds to the first read bus group and the first read and write bus group.
  • the first channel of the memory When accessing the first channel of the memory, it can be based on the read and write bandwidth requirements for data read and write.
  • the processor may enable the first read and write bus group to be a write bus group, and read the services of the first channel in the memory through the first read bus group. Message, and write a service message to the first channel in the memory through the first read-write bus group.
  • the processor can enable the first read and write bus group to be a read bus group, and read the data in the memory through the first read bus group and the first read and write bus group. The business table entry of the first channel.
  • the memory further includes a second channel, and the second channel corresponds to the second read-write bus group.
  • the method further includes S302: the processor accesses the second read-write bus group through the second read-write bus group. aisle.
  • the specific process of the processor accessing the second channel in the memory through the second read-write bus group is similar to the specific process of accessing the first channel in the memory through the first read-write bus group in S301.
  • S301 For related descriptions, the embodiments of the application will not repeat them here.
  • the second channel can correspond to one set of buses or two sets of buses.
  • the second channel may only correspond to the second read and write bus, that is, the second channel can only be accessed through the second read and write bus.
  • the second channel can also correspond to the second read bus, that is, the second channel is similar to the first channel and can correspond to a set of read bus and a set of read and write bus.
  • the second channel also corresponds to a second read bus group
  • the method further includes S303: the processor reads the data in the second channel through the second read bus group.
  • the specific process of the processor accessing the second channel in the memory through the second read bus group is similar to the specific process of accessing the first channel in the memory through the first read bus group in S301.
  • S301 the relevant information in S301. Description, the embodiments of this application will not be repeated here.
  • S301 and S302 and S303 may be in no particular order, and S302 and S303 may also be in no particular order.
  • S302 and S303 are located after S301, and S302 and S303 are executed in parallel as an example for illustration.
  • the memory in the network device may include multiple channels.
  • the memory may be a memory composed of N SRAMs stacked three-dimensionally. If each SRAM includes two channels, the memory may include 2N channels. .
  • One or more of the multiple channels can be similar to the first channel or the second channel, and a read bus group and a read and write bus group are set correspondingly, so that when a channel is accessed, the corresponding read of the channel can be used.
  • the bus group and the read-write bus group access the channel.
  • any channel in the memory can correspond to a read bus group and a read and write bus group.
  • the processor accesses the memory, the processor can read and write according to the read and write bandwidth of the data.
  • the read-write bus group corresponding to the same channel is adaptively used as a read-write bus group or a write-bus group, and then the memory is accessed according to this read bus group and this read-write bus group, so as to realize the same network device for different reads Write bandwidth requirements.

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Abstract

一种存储器、网络设备及数据访问方法，涉及存储器技术领域，用于实现同一存储设备对于不同存储带宽的需求。该存储器包括：至少一个通道，所述至少一个通道包括第一通道；所述第一通道对应第一读总线组和第一读写总线组，所述第一读总线组用于读取所述第一通道的数据，所述第一读写总线组用于读取所述第一通道的数据或向第一通道中写入数据。

Description

一种存储器、网络设备及数据访问方法 技术领域
本申请涉及存储器技术领域，尤其涉及一种存储器、网络设备及数据访问方法。
背景技术
存储器和处理器分别作为电子设备存储信息和处理信息两个重要部件，其性能的高低直接影响着网络设备的性能。近几十年来，如图1所示，处理器的性能大概以每年大约60％的速度快速提升，而存储器的性能则只有每年10％左右的提升速度。长期累积下来，不均衡的发展速度造成了当前存储的存取速度严重滞后于处理器的计算速度，存储瓶颈导致高性能处理器难以发挥出应有的功效，这对日益增长的高性能计算形成了极大的制约。
存储带宽是用于衡量存储器的存取速度的参数，是指单位时间内通过数据总线传输的数据量，可以用公式“存储带宽＝(传输倍率×总线位宽×工作频率)÷8”计算得到，单位为“字节/秒”(byte/s)。总线位宽是指存储数据总线的位数，工作频率是指存储的时钟频率，传输倍率是指每条数据总线在一个时钟脉冲周期内传输数据的次数。显然，存储带宽的大小取决于总线位宽、工作频率和传输倍率这三个因素。
现有技术中，通常采用提高存储传输倍率的方式来提高存储带宽。例如DDR存储是双倍数据率(double data rate)，其每条数据线都能够从存储单元预取2位数据，并分别在时钟脉冲的上升沿和下降沿各传输1位数据，即在一个时钟周期的传输倍率为2，在相同频率下DDR存储的数据传输量是单倍数据率存储的2倍。同理，DDR2存储、DDR3存储的传输倍率分别为单倍数据率存储的4倍和8倍。
但是，上述提升存储带宽的方式，对于交换器和路由器等网络设备却很难发挥其优势。这是因为这些网络设备对于转发业务报文和业务表项等不同的数据所需要的存储带宽是不同的，通常业务报文所需的读写带宽为50％读和50％写，而业务表项所需的读写带宽为95％读和5％写。因此，如何满足同一设备对于不同存储带宽的需求是一个亟待解决的技术问题。
发明内容
本申请提供一种存储器、网络设备及数据访问方法，用于实现同一设备对于不同存储带宽的需求。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种存储器，该存储器包括：至少一个通道，至少一个通道包括第一通道；第一通道对应第一读总线组和第一读写总线组，第一读总线组用于读取第一通道的数据，第一读写总线组用于读取第一通道的数据或向第一通道中写入数据。
上述技术方案中，存储器中的第一通道对应有第一读总线组和第一读写总线组，在访问该存储器的第一通道时，可以根据数据读写时的读写带宽的需求，适应性地将第一读写总线组作为读总线组或写总线组，进而第一读总线组和第一读写总线组访问该存储器的第一通道。比如，在读写带宽需求均衡(比如，读写带宽为50％读和50％ 写)的情况下，将第一读写总线组作为写总线组和第一读总线一起读写该存储器，在读带宽需求大于写带宽需求(比如，读写带宽为95％读和5％写)时，将第一读写总线组作为读总线组和第一读总线一起读取该存储器的数据。这样，可以实现同一存储器对于不同读写带宽的需求。
在第一方面的一种可能的实现方式中，至少一个通道还包括第二通道，第二通道对应第二读写总线组，第二读写总线组用于读取第二通道的数据或向第二通道中写入数据。上述可能的实现方式中，第二通道可以对应第二读写总线组，从而通过第二读写总线可以访问该存储器的第二通道。
在第一方面的一种可能的实现方式中，第一读写总线组和第二读写总线组的总线位宽不同。上述可能的实现方式中，第一读写总线组和第二读写总线组包括的数据总线的位宽不同，和/或二者包括的地址总线的位宽不同，数据总线的位宽不同可以包括读数据线的位宽不同、和/或写数据线的位宽不同。
在第一方面的一种可能的实现方式中，第一读写总线组和第二读写总线组中存在至少一条读写总线的读写功能不同。上述可能的实现方式中，第一读写总线组和第二读写总线组的读写功能可以不同，比如，第一读写总线组支持比特掩码写，第二读写总线组支持字节掩码写，从而提高了该存储器的访问灵活性。
在第一方面的一种可能的实现方式中，第二通道还对应第二读总线组，第二读总线组用于读取第二通道的数据。上述可能的实现方式中，存储器中的第二通道对应有第二读总线组和第二读写总线组，在访问该存储器的第二通道时，可以根据数据读写时的读写带宽的需求，适应性地将第二读写总线组作为读总线组或写总线组，进而使用第二读总线组和第二读写总线组访问该存储器的第二通道，从而实现同一存储器对于不同读写带宽的需求。
在第一方面的一种可能的实现方式中，第一读总线组和第二读总线组的总线位宽不同。上述可能的实现方式中，第一读总线组和第二读总线组包括的数据总线的位宽不同，和/或二者包括的地址总线的位宽不同。
在第一方面的一种可能的实现方式中，第一读总线组和第二读总线组存在至少一条读总线的读功能不同。上述可能的实现方式中，第一读总线组和第二读总线组的读功能不同可以不同，比如，第一读总线组支持比特掩码读，第二读总线组支持字节掩码读，从而提高了该存储器的访问灵活性。
在第一方面的一种可能的实现方式中，读总线组和读写总线组中均包括控制总线、地址总线和数据总线。
在第一方面的一种可能的实现方式中，该存储器包括三维堆叠的N个静态随机存储器SRAM，N为大于1的整数。上述可能的实现方式中，可以使得三维堆叠的N个SRAM构成的存储器能够实现同一存储设备对于不同存储带宽的需求。
在第一方面的一种可能的实现方式中，至少一个通道中的每个通道包括多个存储库，每个通道包括的所述多个存储库对应设置有一个读总线组和一个读写总线组。上述可能的实现方式中，可以使得该存储器中的每个通道可以实现同一通道对于不同读写带宽的需求。
第二方面，提供一种网络设备，网络设备包括处理器和存储器，处理器用于访问 存储器，存储器为第一方面或者第一方面的任一种可能的实现方式所提供的存储器。
在第二方面的一种可能的实现方式中，网络设备为网络交换及转发设备。
在第二方面的一种可能的实现方式中，网络交换及转发设备包括路由器或者交换器。
第三方面，提供一种数据访问方法，应用于包括处理器和存储器的网络设备中，存储器包括第一通道，第一通道对应第一读总线组和第一读写总线组，该方法包括：该处理器通过第一读总线组和第一读写总线组访问存储器中的第一通道。
在第三方面的一种可能的实现方式中，该处理器通过第一读总线组和第一读写总线组访问存储器中的第一通道，包括：该处理器使能第一读写总线组为写总线组；该处理器通过第一读总线组读取存储器中的第一通道的数据，以及通过第一读写总线组向存储器中的第一通道写入数据。
在第三方面的一种可能的实现方式中，该处理器通过第一读总线组和第一读写总线组访问存储器的第一通道，还包括：该处理器使能第一读写总线组为读总线组；处理器通过第一读总线组和第一读写总线读取存储器中的第一通道的数据。
在第三方面的一种可能的实现方式中，该存储器还包括第二通道，第二通道对应第二读写总线组，该方法还包括：该处理器通过第二读写总线组访问存储器中的第二通道。
在第三方面的一种可能的实现方式中，第二通道还对应第二读总线组，该方法还包括：该处理器通过第二读总线组读取第二通道中的数据。
可以理解地，上述提供的任一种网络设备和数据访问方法均包含了上文所提供的存储器，因此，其所能达到的有益效果可参考上文所提供的存储器中的有益效果，此处不再赘述。
附图说明
图1为处理器性能和存储器性能的增长比较示意图；
图2为本申请实施例提供的一种HBM的结构示意图；
图3为本申请实施例提供的一种存储器的示意图；
图4为本申请实施例提供的一种网络设备的示意图；
图5为本申请实施例提供的一种数据访问方法的流程示意图。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。另外，本申请实施例采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。例如，第一阈值和第二阈值仅仅是为了区分不同的阈值，并不对其先后顺序进行限定。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在介绍本申请实施例之前，首先对本申请实施例所涉及的技术背景进行介绍说明。
存储器和处理器分别作为电子设备存储信息和处理信息两个重要部件，其性能的高低直接影响着网络设备的性能。存储器和处理器分别作为电子设备存储信息和处理信息两个重要部件，其性能的高低直接影响着网络设备的性能。近几十年来，如图1所示，处理器的性能大概以每年大约60％的速度快速提升，而存储器的性能则只有每年10％左右的提升速度，二者每年的速度提升差距大约为50％。长期累积下来，不均衡的发展速度造成了当前存储的存取速度严重滞后于处理器的计算速度，存储瓶颈导致高性能处理器难以发挥出应有的功效，这对日益增长的高性能计算形成了极大的制约。事实上，早在1994年就有科学家分析和预测了这一问题，并将这种严重阻碍处理器性能发挥的存储瓶颈命名为存储墙(Memory Wall)。
存储带宽是用于衡量存储器的存取速度的参数，是指单位时间内通过数据总线传输的数据量，可以用公式“存储带宽＝(传输倍率×总线位宽×工作频率)÷8”计算得到，单位为“字节/秒”(byte/s)。总线位宽是指存储数据总线的位数，工作频率是指存储的时钟频率，传输倍率是指每条数据总线在一个时钟脉冲周期内传输数据的次数。显然，存储带宽的大小取决于总线位宽、工作频率和传输倍率这三个因素。
提高存储总线位宽：在现有采用独立存储芯片的架构下，进一步增加存储位宽受到了存储芯片数据线引脚数量的限制，所以通过增加位宽来提升存储带宽的方式，需要采用能有效消除这种引脚限制的新型存储架构。例如存储与处理器集成技术，就具有通过增加存储位宽来明显提升存储带宽的特点。
提高存储工作频率：单纯依靠提高工作频率来提升存储带宽的方法，会受到存储芯片发热量和工艺难度增加等方面的制约，所以采用这种方法进一步提高存储带宽的空间非常有限。
提高存储传输倍率：通过增加传输倍率来提升存储带宽的方法。例如DDR存储是双倍数据率(double data rate)，其每条数据线都能够从存储单元预取2位数据，并分别在时钟脉冲的上升沿和下降沿各传输1位数据，即在一个时钟周期的传输倍率为2，在相同频率下DDR存储的数据传输量是单倍数据率存储的2倍。同理，DDR2存储、DDR3存储的传输倍率分别为单倍数据率存储的4倍和8倍。而Rambus的“百万兆字节带宽”技术则可将传输倍率提高到32，从而大幅度提升存储的带宽。
但是，上述提升存储带宽的方式，对于交换器和路由器等网络设备却很难发挥其优势。这是因为这些网络设备对于转发业务报文和业务表项等不同的数据所需要的存储带宽是不同的，通常业务报文所需的读写带宽为50％读和50％写，而业务表项所需的读写带宽为95％读和5％写。基于此，本申请实施例提供一种存储器、网络设备和数据访问方法，用于满足同一存储设备对于不同存储带宽的需求，同时也可以提升存储带宽。
本申请的技术方案可以应用于各种存储器中，比如flash和随机存取存储器 (random access memory，RAM)等。在一种可能的实施例中，本申请的技术方案可应用于各种类型的RAM中，静态随机存取存储器(static RAM，SRAM)、动态随机存储器(dynamic RAM，DRAM)、同步动态随机存储器(synchronous DRAM，SDRAM)等。DRAM还可以包括多倍速率的DRAM和高带宽存储器(high bandwidth memory，HBM)等。多倍数据率的DRAM可以包括双倍数据率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、DDR2 SDRAM、DDR3 SDRAM、DDR4 SDRAM、以及DDR5 SDRAM等。
下面分别以SRAM、DDR SDRAM和HBM为例，对不同存储器的特点进行介绍说明。
SRAM是随机存取存储器RAM的一种。所谓的“静态”是指这种存储器只要保持通电，里面储存的数据就可以恒常保持。相对之下，动态随机存取存储器(DRAM)里面所储存的数据就需要周期性地更新。然而，当电力供应停止时，SRAM储存的数据还是会消失(被称为volatile memory)，这与在断电后还能储存资料的ROM或闪存是不同的。
DDR SDRAM可以简称为DDR，其数据传输速度为系统时钟的两倍或多倍，由于速度增加，其传输性能优于传统的SDRAM。DDR SDRAM在系统时钟的上升沿和下降沿都可以进行数据传输。
下面表1列举了DDR、DDR2、DDR3和DDR4等几种不同倍数据率的SDRAM的总线时钟(bus clock)、内部速率(internal rate)、预取(prefetch)、转移速率(transfer rate)和电压(voltage)。表2列举了几种不同倍数据率的SDRAM采用不同类型的存储模块实现时的引脚数(pins)，不同类型的存储模块可以包括双列直插式存储模块(dual inline memory modules，DIMM)、小轮廓(small outline dual inline memory modules，SO-DIMM)和微型双列直插式存储模块(micro dual inline memory modules，micro DIMM)。
表1
Figure PCTCN2020075139-appb-000001
表2
Figure PCTCN2020075139-appb-000002
Figure PCTCN2020075139-appb-000003
HBM是三星电子、超微半导体和SK海力士发起的一种基于3D堆栈工艺的高性能DRAM，即基于3D堆栈工艺将2/4/8等多个DRAM裸片(die)堆叠在一起并封装形成的具有高带宽特性的存储器。HBM适用于高存储器带宽需求的应用场合，比如图形处理器、网络交换及转发设备(如路由器、交换器)等。相比较DDR4或GDDR5而言，HBM以更小的体积、更少的功率达到了更高的带宽。
图2为本申请实施例提供的一种HBM裸片的结构示意图，HBM裸片可以包括逻辑裸片(logic die)和多个存储器裸片，多个存储器裸片通过硅穿孔(TSV)和微凸起(micro-bump)堆叠在一起且与逻辑裸片相连接。逻辑裸片可以是集成有控制逻辑的裸片，该控制逻辑可以是存储器控制器，具体可用于管理和控制器多块存储器裸片的读写等。
存储器裸片中的存储单元被划分至多个存储库(bank),多个存储库根据与其对应的数据总线、地址总线和控制总线被划分至多个通道(channel)。换个角度来说，在同一通道中的存储库，通过同样的一个或多个总线进行读写数据，这里说的总线包括数据总线、地址总线和控制总线；不同通道中的存储库则使用不同的总线读写数据。
在本申请实施例中，每个存储器裸片中可以包括两个通道(channel)，每个通道可以为128比特(bit)，一个通道也可以称为一个信道，一个通道可以包括多个存储库(bank)。图2中以HBM裸片包括4个存储器裸片，每个存储器裸片包括CH0和CH1两个通道、每个通道包括8个存储库为例进行说明，图2中的(a)为HBM裸片的俯视图，图2中的(b)为HBM裸片的侧视图。
需要说明的是，图2中的多个存储器裸片可以是多个DRAM裸片，也可以是多个SRAM裸片，即可以将多个DRAM按照上述图2所示的三维堆叠方式构成一种存储器，也可以将多个SRAM按照上述图2所示的三维堆叠方式构成一种存储器，本申请实施例对于存储器裸片的具体类型不作限定。
另外，三维堆叠的多个SRAM构成的存储器与三维堆叠的DRAM构成的存储器的区别在于：三维堆叠的DRAM构成的存储器都是一个通道对应一组数据总线，原因是受限于DRAM时序参数限制，一个通道的带宽与一个通道内所有存储库的总和是接近的。但是，对三维堆叠的多个SRAM构成的存储器，由于SRAM不存在类似于DRAM的时序参数限制，单个存储库的带宽跟单个通道的带宽是匹配的，所以三维堆叠的多个SRAM构成的存储器可以支持多组总线访问，从而通过扩展多组总线可以提升带宽。基于此，本申请实施例提供了一种支持多组总线访问的存储器。
图3为本申请实施例提供的一种存储器的结构示意图，该存储器包括至少一个通道，至少一个通道包括第一通道，第一通道对应第一读总线组和第一读写总线组，第 一读总线组用于读取第一通道的数据，第一读写总线组用于读取第一通道的数据或向第一通道中写数据。可选的，该存储器可以为三维堆叠的多个SRAM构成的存储器。
其中，至少一个通道可以包括一个或者多个通道，第一通道可以为至少一个通道中的任一通道，每个通道可以包括多个连续的存储库，这多个连续的存储库可以对应设置有一个读总线组和一个读写总线组。比如，图3中以至少一个通道包括C个通道，每个通道包括B个连续的存储库，第一通道为C个通道中的第1个通道为例进行说明，C为正整数。
另外，第一读总线组可以包括控制总线、地址总线和数据总线。比如，在第一读总线组中，控制总线可以包括一条时钟线CLK和一条芯片使能线CEN，地址总线可以包括m1条地址线A[m1-1:0]，数据总线可以包括n1条读数据线Q[n1-1:0]。m1和n1为正整数，比如m1等于32、n1等于128。
关于第一读总线组中每种类型的总线描述可以如下表3所示。具体的，时钟线CLK的输入输出类型为输入(input)，电源为VDDP/VDD，定义为系统时钟输入(system clock input)；芯片使能线CEN的输入输出类型为输入(input)，电源为VDDP/VDD，定义为芯片使能输入(chip enable input)，且为低电平下有效(active low)；地址总线A[m1-1:0]的输入输出类型为输入(input)，电源为VDDP/VDD，定义为地址输入总线接口；数据总线Q[n1-1:0]的输入输出类型为输出(output)，电源为VDDP/VDD，定义为读接口使用的读输出数据总线(read output data bus for read port)。
表3第一读总线组
Figure PCTCN2020075139-appb-000004
第一读写总线组也可以包括控制总线、地址总线和数据总线。比如，在第一读写总线组中，控制总线可以包括一条时钟线CLK、一条芯片使能线CEN和一条写使能线WEN，地址总线可以包括m2条地址线A[m2-1:0]，数据总线可以包括n2条读数据线Q[n2-1:0]和n3条写数据线D[n3-1:0]。m1和n1为正整数，比如m2等于64、n2等于128、n3等于128。
关于第一读写总线组中每种类型的总线描述可以如下表4所示。具体的，时钟线CLK的输入输出类型为输入(input)，电源为VDDP/VDD，定义为系统时钟输入(system clock input)；芯片使能线CEN的输入输出类型为输入(input)，电源为VDDP/VDD，定义为芯片使能输入(chip enable input)，且为低电平下有效(active low)；地址总线A[m2-1:0]的输入输出类型为输入(input)，电源为VDDP/VDD，定义为地址输入总线接口；读数据总线Q[n2-1:0]的输入输出类型为输出(output)，电源为VDDP/VDD，定义为读接口使用的读输出数据总线(read output data bus for read port)；写使能线WEN的输入输出类型为输入(input)，电源为VDDP/VDD，定义为写使能输入(write  enable input)，且为低电平下有效(active low)；写数据总线D[n3-1:0]的输入输出类型为输入(input)，电源为VDDP/VDD，定义为写接口使用的写输入数据总线(write input data bus for write port)。
表4第一读写总线组
Figure PCTCN2020075139-appb-000005
具体的，当写使能线WEN为高电平时，第一读写总线组可以作为读总线组，即通过时钟线CLK、芯片使能线CEN、地址总线A[m2-1:0]和读数据地址Q[n2-1:0]可以读取该存储器中第一通道中的数据。当写使能线WEN为低电平时，第一读写总线组可以作为写总线组，即通过时钟线CLK、芯片使能线CEN、地址总线A[m2-1:0]和写数据地址D[n3-1:0]可以向该存储器中的第一通道写入数据。比如，在访问该存储器的第一通道时，若读带宽和写带宽基本一致，则可以将第一读写总线组作为写总线组，基于第一读总线组读取第一通道中的数据，基于第一读写总线组向第一通道中写入数据；若读带宽大于写带宽，则可以将第一读写总线组作为读总线组，基于第一读总线组和第一读写总线组读取第一通道中的数据。
在本申请实施例中，存储器中的第一通道对应有第一读总线组和第一读写总线组，在访问该存储器的第一通道时，可以根据数据读写时的读写带宽的需求，适应性地将第一读写总线组作为读总线组或写总线组，进而基于第一读总线组和第一读写总线组访问该存储器的第一通道，从而实现同一存储器对于不同读写带宽的需求。
进一步的，如图3所示，至少一个通道还包括第二通道，第二通道对应第二读写总线组，第二读写总线组用于读取第二通道的数据或向第二通道中写数据，图3中以第二通道为第C个通道为例进行说明。其中，第二读写总线组与第一读写总线组包括的各种类型的总线的描述基本一致，具体可以参见第一读写总线组的描述，本申请实施例在此不再赘述。
可选的，第一读写总线组和第二读写总线组可以采用同构总线架构，也可以采用异构总线架构。同构总线架构是指第一读写总线组和第二读写总线组中所有的总线是完全相同的，比如，各种类型的总线位宽是相同的，同种类型的总线的读写功能是相同的。异构总线架构是指第一读总线组和第二读写总线组中存在不同的总线，比如，存在不同类型的总线，和/或同种类型的总线的位宽不同，和/或同种类型的总线的读写功能是不同的。
在一种可能的实施例中，第一读写总线组和第二读写总线组的总线位宽不同，具体可以是指二者包括的数据总线的位宽不同，和/或二者包括的地址总线的位宽不同，数据总线的位宽不同可以包括读数据线的位宽不同、和/或写数据线的位宽不同。示例性的，若第一读写总线组中包括m2条地址线、n2条读数据线和n3条写数据线，第二读写总线组包括m3条地址线、n4条读数据线和n5条写数据线，则第一读写总线组和第二读写总线组的总线位宽不同具体可以包括：m2与m3不相等，n2与n4不相等，和/或n3与n5不相等。
在另一种可能的实施例中，第一读写总线组和第二读写总线组中存在至少一条读写总线的读写功能不同，具体可以是指二者包括的读数据线的读功能不同，和/或二者包括的写数据线的写功能不同。示例性的，若第一读写总线组中包括n2条读数据线和n3条写数据线，第二读写总线组包括n4条读数据线和n5条写数据线，则二者的读写功能不同具体可以包括：n2条读数据线支持比特(bit)掩码读，n3条写数据线支持比特掩码写，n4条读数据线支持字节(byte)掩码读，n5条写数据线支持字节掩码写。
比如，以第一读写总线组中的写数据总线D[n3-1:0]支持bit掩码写为例，则写数据总线D[n3-1:0]对应的定义可以为写接口使用的比特写掩码总线，且高电平有效(bit write mask bus for write port,active high)，如下表5所示。
表5
Figure PCTCN2020075139-appb-000006
在实际应用中，第二通道可以对应一组总线，也可以对应两组总线。比如，当第二通道对应一组总线时，第二通道可以仅对应第二读写总线，即只能通过第二读写总线访问第二通道。当第二通道对应两组总线时，第二通道除了对应第二读写总线，还可以对应第二读总线，即第二通道与第一通道类似，可以对应一组读总线和一组读写总线。
进一步的，如图3所示，第二通道还对应第二读总线组，第二读总线组用于读取第二通道的数据。其中，第二读总线组与第一读总线组包括的各种类型的总线的描述基本一致，具体可以参见第一读总线组的描述，本申请实施例在此不再赘述。
在一种可能的实施例中，第一读总线组和第二读总线组的总线位宽不同，具体可以是指二者包括的读数据线的位宽不同，和/或二者包括的地址总线的位宽不同。在另一种可能的实施例中，第一读总线组和第二读总线组存在至少一条读总线的读功能不同。
需要说明的是，关于第一读总线组和第二读总线组的总线位宽不同、以及读总线的读功能不同的相关描述，具体可以参见第一读写总线组和第二读写总线中的相关描述，本申请实施例在此不再赘述。
在实际应用中，第一通道或第二通道还可以对应其他功能的总线，其他功能可以包括数据总线倒置(data bus inversion，DBI)、数据输入屏蔽(data input mask，DM)、时钟使能(clock enable，CKE)、校验(parity，PAR)、数据错误(data error，DERR)、选通(strobes)和地址错误(address error，AERR)等，本申请实施例对此不再进行详细描述。
在一种可能的实施例中，该存储器还可以是其他存储器，比如，多个Flash裸片堆叠构成的存储器、多个MRAM裸片构成的存储器等，本申请实施例对此不作具体限制。
图4为本申请实施例提供的一种网络设备的结构示意图，该网络设备包括存储器201，以及与存储器201耦合的处理器202。其中，存储器201可以为图3所提供的存储器，具有可用于存储指令、数据等；处理器202用于对该网络设备的动作进行控制管理等。进一步的，该网络设备还包括通信接口203和总线204，存储器201、处理器202和通信接口203通过总线204连接，通信接口203用于支持该网络设备与其他设备之间进行通信。
其中，处理器202可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线204可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。所述总线204可以分为地址总线、数据总线、控制总线等。为便于表示，图4中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在一种可能的实施例中，该网络设备为网络交换及转发设备。可选的，网络交换及转发设备可以包括路由器或者交换器等。
图5为本申请实施例提供的一种数据访问方法的流程示意图，该方法可应用于包括处理器和存储器的网络设备中，该存储器包括第一通道，第一通道对应第一读总线组和第一读写总线组，该方法可以包括以下步骤。
S301：处理器通过第一读总线组和第一读写总线组访问该存储器中的第一通道。
其中，该存储器可以包括至少一个通道，第一通道可以为至少一个通道中的任一通道。需要说明的是，关于该存储器的相关描述，可以参考图3中的描述，本申请实施例在此不再赘述。
第一读总线组可以包括控制总线、地址总线和数据总线，比如，在第一读总线组中，控制总线可以包括一条时钟线CLK和一条芯片使能线CEN，地址总线可以包括m1条地址线A[m1-1:0]，数据总线可以包括n1条读数据线Q[n1-1:0]。m1和n1为正整数，比如m1等于32、n1等于128。
第一读写总线组也可以包括控制总线、地址总线和数据总线。比如，在第一读写总线组中，控制总线可以包括一条时钟线CLK、一条芯片使能线CEN和一条写使能线WEN，地址总线可以包括m2条地址线A[m2-1:0]，数据总线可以包括n2条读数据线Q[n2-1:0]和n3条写数据线D[n3-1:0]。
具体的，处理器使能第一读写总线组为写总线组，比如，将写使能线WEN设置为低电平，以使第一读写总线组作为写总线组；通过第一读总线组读取存储器中的第一通道的数据，比如，使能芯片使能线CEN，在时钟线CLK对应的时钟信号的升降沿，通过地址线A[m1-1:0]和读数据线Q[n1-1:0]读出第一通道中的数据；通过第一读 写总线组向存储器中的第一通道写入数据，比如，使能芯片使能线CEN，在时钟线CLK对应的时钟信号的升降沿，通过地址线A[m2-1:0]和写数据线D[n3-1:0]将数据写入第一通道中。
或者，处理器使能第一读写总线组为读总线组，比如，将写使能线WEN设置为高电平，以使第一读写总线组作为读总线组；通过第一读总线组和第一读写总线读取存储器中的第一通道的数据，比如，使能芯片使能线CEN，在时钟线CLK对应的时钟信号的升降沿，分别通过地址线A[m1-1:0]和读数据线Q[n3-1:0]、以及地址线A[m2-1:0]和读数据线Q[n2-1:0]读出第一通道中的数据。
在本申请实施例中，存储器中的第一通道对应有第一读总线组和第一读写总线组，在访问该存储器的第一通道时，可以根据数据读写时的读写带宽的需求，适应性地将第一读写总线组作为读总线组或写总线组，进而第一读总线组和第一读写总线组访问该存储器的第一通道，从而实现同一存储器对于不同读写带宽的需求。
比如，当该存储器中的第一通道用于存储业务报文时，处理器可以使能第一读写总线组为写总线组，通过第一读总线组读取存储器中的第一通道的业务报文，以及通过第一读写总线组向存储器中的第一通道写入业务报文。当该存储器中的第一通道用于存储业务表项时，处理器可以使能第一读写总线组为读总线组，通过第一读总线组和第一读写总线组读取存储器中的第一通道的业务表项。
在一种可能的实施例中，该存储器还包括第二通道，第二通道对应第二读写总线组，该方法还包括S302：处理器通过第二读写总线组访问该存储器中的第二通道。
其中，处理器通过第二读写总线组访问该存储器中的第二通道的具体过程与S301中通过第一读写总线组访问该存储器中的第一通道的具体过程类似，具体可以参考S301中的相关描述，本申请实施例在此不再赘述。
在实际应用中，第二通道可以对应一组总线，也可以对应两组总线。比如，当第二通道对应一组总线时，第二通道可以仅对应第二读写总线，即只能通过第二读写总线访问第二通道。当第二通道对应两组总线时，第二通道除了对应第二读写总线，还可以对应第二读总线，即第二通道与第一通道类似，可以对应一组读总线和一组读写总线。
进一步的，第二通道还对应第二读总线组，该方法还包括S303：处理器通过第二读总线组读取第二通道中的数据。
其中，处理器通过第二读总线组访问该存储器中的第二通道的具体过程与S301中通过第一读总线组访问该存储器中的第一通道的具体过程类似，具体可以参考S301中的相关描述，本申请实施例在此不再赘述。
需要说明的是，S301与S302和S303可以不分先后顺序，S302与S303也可以不分先后顺序，图5中以S302和S303位于S301之后，且S302和S303并列执行为例进行说明。
在实际应用中，该网络设备中的存储器可以包括多个通道，比如，该存储器可以是三维堆叠的N个SRAM构成的存储器，若每个SRAM包括两个通道，则该存储器可以包括2N个通道。多个通道中的一个或者多个通道可以与第一通道或第二通道类似，对应设置有一个读总线组和一个读写总线组，从而在访问某一通道时，可以通过 该通道对应的读总线组和读写总线组访问该通道。
需要说明的是，关于S301-S303中的第一读总线组、第一读写总线组、第二读总线组和第二读写总线组的相关描述可以参见上述图3中的相关描述，本申请实施例在此不再赘述。
在本申请实施例提供的数据访问方法中，存储器中的任一通道可以对应一个读总线组和一个读写总线组，处理器在访问存储器时，处理器可以根据数据读写时的读写带宽的需求，适应性地将同一通道对应的读写总线组作为读总线组或写总线组，进而根据这一个读总线组和这一个读写总线组访问该存储器，从而实现同一网络设备对于不同读写带宽的需求。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种存储器，其特征在于，所述存储器包括：
    至少一个通道，所述至少一个通道包括第一通道；
    所述第一通道对应第一读总线组和第一读写总线组，所述第一读总线组用于读取所述第一通道的数据，所述第一读写总线组用于读取所述第一通道的数据或向所述第一通道中写入数据。
  2. 根据权利要求1所述的存储器，其特征在于，所述至少一个通道还包括第二通道，所述第二通道对应第二读写总线组，所述第二读写总线组用于读取所述第二通道的数据或向所述第二通道中写数据。
  3. 根据权利要求2所述的存储器，其特征在于，所述第一读写总线组和所述第二读写总线组的总线位宽不同。
  4. 根据权利要求2或3所述的存储器，其特征在于，所述第一读写总线组和所述第二读写总线组中存在至少一条读写总线的读写功能不同。
  5. 根据权利要求2-4任一项所述的存储器，其特征在于，所述第二通道还对应第二读总线组，所述第二读总线组用于读取所述第二通道的数据。
  6. 根据权利要求5所述的存储器，其特征在于，所述第一读总线组和所述第二读总线组的总线位宽不同。
  7. 根据权利要求5或6所述的存储器，其特征在于，所述第一读总线组和所述第二读总线组存在至少一条读总线的读功能不同。
  8. 根据权利要求1-7任一项所述的存储器，其特征在于，读总线组和读写总线组中均包括控制总线、地址总线和数据总线。
  9. 根据权利要求1-8任一项所述的存储器，其特征在于，所述存储器包括三维堆叠的N个静态随机存储器SRAM，所述N为大于1的整数。
  10. 根据权利要求1-9任一项所述的存储器，其特征在于，所述至少一个通道中的每个通道包括连续的多个存储库，所述连续的多个存储库对应设置有一个读总线组和一个读写总线组。
  11. 一种网络设备，其特征在于，所述网络设备包括处理器和存储器，所述处理器用于访问所述存储器，所述存储器为权利要求1-10任一项所述的存储器。
  12. 根据权利要求11所述的网络设备，其特征在于，所述网络设备为网络交换及转发设备。
  13. 根据权利要求12所述的网络设备，其特征在于，所述网络交换及转发设备包括路由器或者交换器。
  14. 一种数据访问方法，其特征在于，应用于包括处理器和存储器的网络设备中，所述存储器包括第一通道，所述第一通道对应第一读总线组和第一读写总线组，所述方法包括：
    所述处理器通过所述第一读总线组和所述第一读写总线组访问所述存储器中的所述第一通道。
  15. 根据权利要求14所述的方法，其特征在于，所述处理器通过所述第一读总线 组和所述第一读写总线组访问所述存储器中的所述第一通道，包括：
    所述处理器使能所述第一读写总线组为写总线组；
    所述处理器通过所述第一读总线组读取所述存储器中的所述第一通道的数据，以及通过所述第一读写总线组向所述存储器中的所述第一通道写入数据。
  16. 根据权利要求14或15所述的方法，其特征在于，所述处理器通过所述第一读总线组和所述第一读写总线组访问所述存储器的所述第一通道，还包括：
    所述处理器使能所述第一读写总线组为读总线组；
    所述处理器通过所述第一读总线组和所述第一读写总线读取所述存储器中的所述第一通道的数据。
  17. 根据权利要求14-16任一项所述的方法，其特征在于，所述存储器还包括第二通道，所述第二通道对应第二读写总线组，所述方法还包括：
    所述处理器通过所述第二读写总线组访问所述存储器中的所述第二通道。
  18. 根据权利要求17所述的方法，其特征在于，所述第二通道还对应第二读总线组，所述方法还包括：
    所述处理器通过所述第二读总线组读取所述第二通道中的数据。
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