WO2023159479A1 - 显示基板及其检测方法、显示装置 - Google Patents

显示基板及其检测方法、显示装置 Download PDF

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Publication number
WO2023159479A1
WO2023159479A1 PCT/CN2022/077967 CN2022077967W WO2023159479A1 WO 2023159479 A1 WO2023159479 A1 WO 2023159479A1 CN 2022077967 W CN2022077967 W CN 2022077967W WO 2023159479 A1 WO2023159479 A1 WO 2023159479A1
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WIPO (PCT)
Prior art keywords
compensation
display substrate
driving
driving circuit
pattern
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PCT/CN2022/077967
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English (en)
French (fr)
Inventor
徐元杰
龙跃
刘聪
王彬艳
闫卓然
李双
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/077967 priority Critical patent/WO2023159479A1/zh
Priority to CN202280000293.6A priority patent/CN117178317A/zh
Publication of WO2023159479A1 publication Critical patent/WO2023159479A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a detection method thereof, and a display device.
  • Organic Light-Emitting Diode (English: Organic Light-Emitting Diode) display products
  • the camera is generally installed in the under-screen camera area of the display product.
  • a driving circuit for driving the light-emitting elements is arranged around the under-screen imaging area.
  • the purpose of the present disclosure is to provide a display substrate, a detection method thereof, and a display device.
  • a first aspect of the present disclosure provides a display substrate, including a base, the base includes a first area and a second area; the second area includes a plurality of driving circuits, and the plurality of driving circuits includes a plurality of normal driving circuits and a plurality of dummy driving circuits; the normal driving circuits include normal driving transistors, the dummy driving circuits include dummy driving transistors, and part of the normal driving circuits are used to drive the anode pattern of the first region; the plurality of driving The circuit is divided into a plurality of driving circuit columns, each driving circuit column surrounds the first area, and the driving circuit column surrounds a driving circuit column located between the driving circuit column and the first area;
  • the display substrate also includes a plurality of signal lead-out lines and a plurality of test pads, and the signal lead-out lines are coupled to corresponding test pads;
  • At least one electrode of a target dummy driving transistor in the target dummy driving circuit is coupled to at least one signal lead-out line.
  • the plurality of driving circuits are divided into multiple rows of driving circuits, and each row of driving circuits includes at least one driving circuit arranged along the first direction;
  • the display substrate further includes a plurality of signal lines, so The signal line includes at least a portion extending along the first direction, and the signal line is respectively coupled to each driving circuit in the corresponding driving circuit row;
  • the driving circuit row to which the target dummy driving transistor belongs corresponds to a coupled signal line, which is multiplexed as a signal lead-out line coupled to the target dummy driving transistor.
  • the plurality of signal lines include a plurality of gate lines, a plurality of light emission control lines and a plurality of reset lines; each row of driving circuits is coupled to the corresponding gate lines, and the light emission control lines and the reset line;
  • At least one of the gate line, the light emission control line and the reset line coupled to the row of the driving circuit to which the target virtual driving transistor belongs is multiplexed as a signal lead-out line coupled to the target virtual driving transistor.
  • the reset line coupled to the row of the driving circuit to which the target virtual driving transistor belongs is multiplexed as a signal lead-out line coupled to the gate of the target virtual driving transistor;
  • the gate line coupled to the row of the driving circuit to which the target dummy driving transistor belongs is multiplexed as a signal lead-out line coupled to the first pole of the target dummy driving transistor;
  • the row of the driving circuit to which the target dummy driving transistor belongs corresponds to the coupled light emission control line, which is multiplexed as the signal lead-out line coupled to the second pole of the target dummy driving transistor.
  • the row of the driving circuit to which the target dummy driving transistor belongs corresponds to the coupled reset line, and forms an integral structure with the gate of the target dummy driving transistor.
  • the target dummy drive circuit includes a first conductive connection part; the gate line coupled to the row of the drive circuit to which the target dummy drive transistor belongs is connected to the target dummy drive transistor through the first conductive connection part first pole coupling.
  • the target dummy driving circuit includes a second conductive connection part; the row of the driving circuit to which the target dummy driving transistor belongs corresponds to a light emission control line coupled to the target dummy driving circuit through the second conductive connection part.
  • the second pole of the transistor is coupled.
  • the display substrate includes a first source-drain metal layer, and the first conductive connection part and/or the second conductive connection part are made of the first source-drain metal layer.
  • At least some of the driving circuit columns include odd-numbered or even-numbered driving circuit columns.
  • adjacent driving circuit columns are separated by at least one other driving circuit column, and the other driving circuit columns do not include the target virtual driving circuit.
  • the display substrate further includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, and a second gate metal layer, which are sequentially stacked along a direction away from the substrate. , an interlayer insulating layer and a first source-drain metal layer;
  • the first region further includes: a compensation structure using the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the The second gate metal layer, at least one of the interlayer insulating layer and the first source-drain metal layer is fabricated.
  • the compensation structure includes compensation patterns uniformly distributed throughout the first region.
  • the first region includes a plurality of anode patterns
  • the compensation structure includes a plurality of first compensation patterns and a plurality of second compensation patterns
  • the orthographic projection of the first compensation patterns on the substrate is the same as
  • the orthographic projections of the corresponding anode patterns on the substrate at least partially overlap
  • the orthographic projections of the second compensation pattern on the substrate at least partially overlap with the orthographic projections of the corresponding anode patterns on the substrate
  • the first compensation pattern and the second compensation pattern are arranged in different layers.
  • the first compensation pattern includes a plurality of sub-compensation patterns independent of each other, and the orthographic projection of the sub-compensation patterns on the substrate is at least partly the same as the orthographic projection of the corresponding anode pattern on the substrate. overlap.
  • the second compensation pattern includes a plurality of via holes, and the orthographic projection of the via holes on the substrate at least partially overlaps with the corresponding orthographic projection of the anode pattern on the substrate.
  • the orthographic projection of the via hole on the substrate in the second compensation pattern corresponding to the anode pattern is covered by the orthographic projection of the sub-compensation pattern corresponding to the anode pattern on the substrate.
  • the first compensation pattern is made using the active layer
  • the second compensation pattern is made using the interlayer insulating layer.
  • the anode pattern includes a plurality of first anode patterns, a plurality of second anode patterns and a plurality of third anode patterns, the first anode pattern, the second anode pattern and the third anode pattern
  • the colors of the corresponding sub-pixels are different;
  • At least two of the first anode pattern, the second anode pattern and the third anode pattern have different areas of the corresponding first compensation patterns, and different areas of the corresponding second compensation patterns.
  • two of the first anode pattern, the second anode pattern and the third anode pattern have the same area of the corresponding first compensation pattern, and the same area of the corresponding second compensation pattern.
  • the first anode pattern corresponds to blue sub-pixels
  • the second anode pattern corresponds to red sub-pixels
  • the third anode pattern corresponds to green sub-pixels
  • the first compensation pattern corresponding to the first anode pattern The area is greater than the area of the first compensation pattern corresponding to the second anode pattern
  • the number of via holes corresponding to the first anode pattern is greater than the number of via holes corresponding to the second anode pattern.
  • the compensation pattern adopts the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer, the one of the interlayer insulating layer and the first source-drain metal layer.
  • the compensation structure includes a plurality of compensation driving circuits, and the compensation driving circuits have the same circuit structure as the virtual driving circuit or the normal driving circuit.
  • the plurality of compensation drive circuits are divided into at least two columns of compensation drive circuits, the at least two columns of compensation drive circuits are nested in sequence, and the at least two columns of compensation drive circuits are located in the first area the edge of.
  • the plurality of test pads are disposed on a frame area of the display substrate.
  • the first area includes an off-screen camera area
  • the second area includes a transition area
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • the third aspect of the present disclosure provides a detection method for the display substrate, which is used to detect the above-mentioned display substrate, and the detection method includes:
  • the layout of the compensation structure in the display substrate is adjusted according to the characteristics of the target dummy driving transistor.
  • FIG. 1 is a circuit structure of a normal driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a driving timing diagram of a normal driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the position of the test pad provided by the embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a first area and a second area provided by an embodiment of the present disclosure
  • FIG. 5 is a first schematic diagram of a compensation structure provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the position of the target virtual drive circuit provided by the embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of multiplexing signal lines into signal lead-out lines provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a normal driving circuit and a target virtual driving circuit provided by an embodiment of the present disclosure
  • Figure 9a is a schematic layout diagram of the active layer in Figure 8.
  • FIG. 9b is a schematic layout diagram of the first gate metal layer in FIG. 8;
  • FIG. 9c is a schematic layout diagram of the first source-drain metal layer in FIG. 8;
  • Fig. 10 is a schematic cross-sectional view along the B1B2 direction in Fig. 8;
  • Fig. 11 is a schematic cross-sectional view along the C1C2 direction in Fig. 8;
  • Fig. 12 is the second schematic diagram of the compensation structure provided by the embodiment of the present disclosure.
  • FIG. 13 is an enlarged schematic diagram of via holes included in the first compensation pattern and the second compensation pattern corresponding to part A in FIG. 12 .
  • the driving circuit for driving the light-emitting elements is arranged around the under-screen imaging area.
  • the anode pattern in the light-emitting element can be coupled to a corresponding driving circuit through a connection line, and receive a driving signal provided by the driving circuit, so as to realize light emission of the light-emitting element.
  • an embodiment of the present disclosure provides a display substrate, including a base, the base includes a first region 10 and a second region 20; the second region 20 includes multiple A drive circuit 30, the plurality of drive circuits 30 include a plurality of normal drive circuits 301 and a plurality of dummy drive circuits; the normal drive circuit 301 includes a normal drive transistor, and the dummy drive circuit includes a dummy drive transistor, partly described
  • the normal driving circuit 301 is used to drive the anode pattern of the first region 10; the plurality of driving circuits are divided into multiple driving circuit columns, each driving circuit column surrounds the first region 10, and the driving circuit columns enclosing the drive circuit column located between the drive circuit column and the first region 10;
  • the display substrate further includes a plurality of signal lead-out lines 40 and a plurality of test pads 41, and the signal lead-out lines 40 are coupled to corresponding test pads 41;
  • At least one electrode of the target dummy drive transistor 3021 in the target dummy drive circuit 302 is coupled to at least one signal lead-out line 40 in at least some of the drive circuit columns.
  • the display substrate may adopt under-screen camera technology (English: Full Display with Camera, referred to as FDC).
  • a display product mainly includes a first area 10 and a normal display area, and the first area 10 is used for setting In the camera, a plurality of first sub-pixels and a plurality of second sub-pixels are distributed in the normal display area, the first sub-pixels include a normal driving circuit 301, and the second sub-pixels include a normal driving circuit 301 and a dummy driving circuit,
  • the normal drive circuit 301 in the first sub-pixel is used to drive the light-emitting elements in the normal display area, the normal drive circuit 301 included in the second sub-pixel is used to drive the light-emitting elements in the first area 10, and the second sub-pixel includes A pixel includes a dummy drive circuit that is not used to drive a light emitting element.
  • the multiple first sub-pixels are divided into multiple first sub-pixel columns, and the multiple first sub-pixel columns are divided into multiple circuit groups, and each circuit group includes at least one sub-pixel column ;
  • the plurality of second sub-pixels are divided into a plurality of second sub-pixel columns, and the circuit groups and the second sub-pixel columns are arranged alternately along the first direction.
  • the second region 20 is located in the normal display region.
  • the display substrate may adopt AA hole technology, in which a display product mainly includes a first area 10, a first display area and a second display area. At least part of the second display area is located between the first display area and the first area 10 . The pixel density in the second display area is less than the pixel density in the first display area.
  • the second area 20 is located in the second display area.
  • the substrate includes a first region 10 and a second region 20 , and the second region 20 surrounds the first region 10 .
  • the shape of the first region 10 includes circle, square, and irregular shape.
  • the second region 20 includes multiple driving circuits, and the multiple driving circuits include multiple normal driving circuits 301 and multiple dummy driving circuits.
  • the normal driving circuit 301 includes a 7T1C circuit structure, but is not limited thereto.
  • the circuit structure of the virtual driving circuit may be the same as or different from that of the normal driving circuit 301 .
  • a part of the normal driving circuit 301 is used to drive the anode pattern in the first region 10 .
  • Another part of the normal driving circuit 301 is used to drive the anode pattern in the second region 20 .
  • the virtual driving circuit includes some transistors in the normal driving circuit 301, but not limited thereto.
  • the multiple driving circuits are divided into multiple driving circuit columns, and the multiple driving circuit columns are nested in sequence, that is, each driving circuit column surrounds the first region 10, and the driving circuit columns It surrounds other drive circuit columns located between itself and the first region 10 .
  • Each column of driving circuits includes at least one of the normal driving circuit 301 and the dummy driving circuit.
  • each column of driving circuits includes multiple normal driving circuits 301 and multiple virtual driving circuits.
  • the plurality of signal lead lines 40 are coupled to the plurality of test pads 41 in a one-to-one correspondence.
  • the signal leads 40 and the test pads 41 correspondingly coupled thereto form an integral structure.
  • the signal lead-out lines can be made by using a separate conductive material layer; or can be made by using the conductive material layer already used in the display substrate.
  • the signal lead-out line 40 can be an independent signal lead-out line 40 used only for transmitting test signals, or it can be an existing signal line in the multiplexing display substrate.
  • the minimum distances between the normal driving circuits 301 and/or the dummy driving circuits belonging to the same column of driving circuits and the under-screen camera area are equal.
  • the characteristic shift of transistors is substantially the same.
  • the driver circuit column includes at least one dummy driver
  • the at least one dummy driver circuit includes at least one target dummy driver circuit 302
  • the target dummy driver circuit 302 includes a target dummy driver transistor 3021
  • the target dummy driver circuit 302 includes a target dummy driver transistor 3021
  • the target Each electrode included in the dummy driving transistor 3021 is respectively coupled to the corresponding signal lead-out line 40 .
  • the target virtual driving circuit 302 indicates a virtual driving circuit selected from the driving circuit column for testing, and its specific structure may be the same as that of other virtual driving circuits.
  • each electrode included in the target virtual drive transistor 3021 in the target virtual drive circuit 302 is selected to be connected to the corresponding signal lead-out Line 40 is coupled, and signal lead-out line 40 is coupled with corresponding test pad 41;
  • signal lead-out line 40 is coupled with corresponding test pad 41;
  • the compensation scheme so as to overcome the difference between the first area 10 and the second area 20, the characteristics of the driving transistors in the driving circuit around the first area 10 are shifted, which ultimately affects the display effect of the display product.
  • the plurality of driving circuits are divided into multiple rows of driving circuit rows, and each row of driving circuit rows includes at least one of the drive circuits;
  • the display substrate further includes a plurality of signal lines, the signal lines include at least a portion extending along the first direction, and the signal lines are connected to each drive circuit in the corresponding drive circuit row separately coupled;
  • the driving circuit row to which the target dummy driving transistor 3021 belongs corresponds to the coupled signal line, which is multiplexed as the signal lead-out line 40 coupled to the target dummy driving transistor 3021 .
  • the second gate metal layer is not shown in FIG. 8 , and the normal drive circuit 301 includes the second gate metal layer.
  • the second source-drain metal layer can be used to form the second plate of the capacitor, initialize the structure of the signal line, etc. , but not limited to.
  • the second gate metal layer may or may not be provided in the target dummy driving circuit 302 according to actual needs.
  • the display substrate further includes other display areas, the other display areas surround the second area 20, the other display areas include a plurality of sub-pixels distributed in an array, and the sub-pixels include a normal driving circuit 301 and a light emitting element .
  • the multiple driving circuits in the second region 20 are divided into multiple rows of driving circuits, and the driving circuits may be located in the same row as the driving circuits in other display regions, and the driving circuits in the same row share the same Gate line GA, reset line Rst and light emitting control line EM etc.
  • each driving circuit in each row of driving circuits includes a normal driving circuit 301 and a dummy driving circuit.
  • the driving circuit row to which the target dummy driving transistor 3021 belongs corresponds to a coupled signal line, which is multiplexed as the signal lead-out line 40 coupled to the target dummy driving transistor 3021 .
  • the signal lines are used to provide corresponding scanning signals for the display substrate.
  • the signal line is multiplexed as the signal lead-out line 40 for providing a detection signal and collecting signals on each electrode of the target virtual driving transistor 3021 .
  • the extension of the signal line along the first direction means that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, and the main part extends along the first direction.
  • the length of the primary portion extending in the first direction is greater than the length of the secondary portion extending in the other directions.
  • the display substrate provided by the above-mentioned embodiment, by setting the signal line correspondingly coupled to the driving circuit row to which the target virtual driving transistor 3021 belongs, multiplexing the signal lead-out line 40 coupled to the target virtual driving transistor 3021, not only ensuring In addition to the normal display function of the display substrate, it also has a detection function, which effectively reduces the layout difficulty of the display substrate and simplifies the internal structure of the display substrate.
  • the plurality of signal lines include a plurality of gate lines GA, a plurality of light emission control lines EM and a plurality of reset lines Rst; coupling the corresponding gate line GA, the light emission control line EM and the reset line Rst;
  • the driving circuit row to which the target dummy driving transistor 3021 belongs corresponds to the coupled gate line GA, at least one of the light emission control line EM and the reset line Rst, and is multiplexed as the signal lead-out line 40 coupled to the target dummy driving transistor 3021 .
  • the signal line extends to one end of the frame area of the display substrate, and is respectively coupled to the corresponding test pad 41 and the corresponding gate 3021a driving circuit (GOA).
  • GAA gate 3021a driving circuit
  • the gate line GA correspondingly coupled to the driving circuit row to which the target dummy driving transistor 3021 belongs, at least one of the light emission control line EM and the reset line Rst is multiplexed as the target
  • the signal lead-out line 40 coupled to the dummy driving transistor 3021 not only ensures the normal display function of the display substrate, but also has a detection function, which effectively reduces the layout difficulty of the display substrate and simplifies the internal structure of the display substrate.
  • the driving circuit row to which the target dummy driving transistor 3021 belongs is set to correspond to the coupled reset line Rst, which is multiplexed as the target dummy driving transistor 3021
  • the driving circuit row to which the target dummy driving transistor 3021 belongs corresponds to the coupled gate line GA, which is multiplexed as the signal lead-out line 40 coupled to the first pole 3021b of the target dummy driving transistor 3021;
  • the row of the driving circuit to which the target dummy driving transistor 3021 belongs corresponds to the coupled light emission control line EM, which is multiplexed as the signal lead-out line 40 coupled to the second pole 3021c of the target dummy driving transistor 3021 .
  • the first pole 3021b of the target dummy driving transistor 3021 includes a drain
  • the second pole 3021c of the target dummy driving transistor 3021 includes a source
  • the above setting method not only ensures the normal display function of the display substrate, but also has a detection function, which effectively reduces the layout difficulty of the display substrate and simplifies the internal structure of the display substrate.
  • the driving circuit row to which the target dummy driving transistor 3021 belongs corresponds to the coupled reset line Rst, and is connected to the target dummy driving transistor 3021
  • the gate electrode 3021a is formed as an integral structure.
  • both the reset line Rst and the gate 3021a of the target dummy driving transistor 3021 are made of the first gate metal layer.
  • one end of the reset line Rst coupled to the gate 3021a of the target dummy driving transistor 3021 extends out of a corner portion 70, and the corner portion 70 is connected to the gate 3021a of the target dummy driving transistor 3021. form an entity.
  • the corner portion 70 includes an arc or a semicircle. The opening of the corner portion 70 faces the target dummy driving circuit 302 .
  • the reset line Rst which is coupled to the row of the drive circuit to which the target dummy drive transistor 3021 belongs, forms an integral structure with the gate 3021a of the target dummy drive transistor 3021, so that the gate of the target dummy drive transistor 3021 3021a and the reset line Rst can be formed through one patterning process, which not only simplifies the manufacturing process of the display substrate, but also effectively improves the reliability of the electrical connection between the gate 3021a and the reset line Rst.
  • the target dummy driving circuit 302 includes a first conductive connection portion 51; the row of the driving circuit to which the target dummy driving transistor 3021 belongs corresponds to the coupled gate
  • the line GA is coupled to the first pole 3021b of the target dummy driving transistor 3021 through the first conductive connection portion 51 .
  • the substrate 90, the first gate insulating layer GI1 and the second gate insulating layer GI2 are also shown in FIG. 10 and FIG. 11.
  • the first conductive connection part 51 is made of the first source-drain metal layer, and can be formed in the same patterning process as other conductive structures made of the first source-drain metal layer in the display substrate.
  • the orthographic projection of the first conductive connection part 51 on the substrate has an overlapping area with the orthographic projection of the gate line GA on the substrate, and in the overlapping area, the first The conductive connection part 51 is coupled to the gate line GA through a via hole.
  • the orthographic projection of the first conductive connecting portion 51 on the substrate and the orthographic projection of the first pole 3021b of the target dummy driving transistor 3021 on the substrate have an overlapping area, and in the overlapping area, the The first conductive connection portion 51 is coupled to the first pole 3021b of the target dummy driving transistor 3021 through a via hole.
  • the above arrangement of the first conductive connection portion 51 can effectively reduce the distance between the gate line GA correspondingly coupled to the driving circuit row to which the target dummy driving transistor 3021 belongs and the first electrode 3021b of the target dummy driving transistor 3021.
  • the connection difficulty ensures the reliability of the connection.
  • the target dummy driving circuit 302 includes a second conductive connection portion 52;
  • the second conductive connection portion 52 is coupled to the second pole 3021c of the target dummy driving transistor 3021 .
  • the second conductive connection part 52 is made of the first source-drain metal layer, and can be formed in the same patterning process as other conductive structures made of the first source-drain metal layer in the display substrate.
  • the orthographic projection of the second conductive connecting portion 52 on the substrate has an overlapping area with the orthographic projection of the emission control line EM on the substrate, and in the overlapping area, the first The two conductive connection parts 52 are coupled to the light emission control line EM through via holes.
  • the orthographic projection of the first conductive connecting portion 51 on the substrate and the orthographic projection of the second pole 3021c of the target dummy driving transistor 3021 on the substrate have an overlapping area, and in the overlapping area, the The second conductive connection portion 52 is coupled to the second pole 3021c of the target dummy driving transistor 3021 through a via hole.
  • the above-mentioned setting of the second conductive connection portion 52 can effectively reduce the gap between the light emission control line EM correspondingly coupled to the driving circuit row to which the target dummy driving transistor 3021 belongs and the second pole 3021c of the target dummy driving transistor 3021.
  • the connection difficulty ensures the reliability of the connection.
  • the display substrate includes a first source-drain metal layer, and the first conductive connection part 51 and/or the second conductive connection part 52 are both made of the first source-drain metal layer.
  • the at least some of the driver circuit columns include odd-numbered or even-numbered driver circuit columns.
  • each electrode included in the target dummy driving transistor 3021 in the target dummy driving circuit 302 is respectively coupled to the corresponding signal lead-out line 40 .
  • the electrodes included in the target dummy driving transistor 3021 in the target dummy driving circuit 302 are respectively coupled to corresponding signal lead-out lines 40 .
  • each electrode included in the target dummy driving transistor 3021 in the target dummy driving circuit 302 is respectively coupled to the corresponding signal lead-out line 40 .
  • adjacent driving circuit columns are separated by at least one other driving circuit column, and the other driving circuit columns do not include the target virtual driving circuit.
  • adjacent driving circuit columns are separated by five other driving circuit columns.
  • At least some of the driving circuit columns can be arranged at intervals, and it is not necessary to collect the electrode signals of the virtual driving transistors in each driving circuit column, so that the display substrate can be reduced while meeting the collection requirements. of complexity.
  • the display substrate further includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, and a second gate a metal layer, an interlayer insulating layer and a first source-drain metal layer;
  • the first region 10 further includes: a compensation structure, the compensation structure adopts the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the at least one of the second gate metal layer, the interlayer insulating layer and the first source-drain metal layer.
  • the compensation structure adopts the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer,
  • the specific structure of the compensation structure may be the same as that formed in the second region 20 by the film layer used, but it is not limited thereto.
  • the signal of each electrode of the target dummy drive transistor 3021 is monitored in real time through the signal lead-out line 40 and the test pad 41, so as to obtain the characteristics and threshold voltage drift of the target dummy drive transistor 3021, and according to the target dummy drive transistor 3021 3021’s characteristics and threshold voltage drift, conduct a bad analysis, determine the degree of influence of the first region 10 on the target virtual drive transistor 3021, and implement a corresponding compensation plan for the display substrate according to the determined result, so as to overcome the problem caused by the first region 10
  • the difference between the second area 20 and the second area 10 leads to a shift in the characteristics of the driving transistor in the driving circuit around the first area 10 , which ultimately affects the display effect of the display product.
  • a compensation structure can be set in the first region 10, which can reduce the structural difference between the first region 10 and the second region 20, thereby reducing the The degree of influence on the normal driving transistor and the dummy driving transistor ensures the working performance of the normal driving transistor.
  • the compensation structure includes compensation patterns 60 uniformly distributed throughout the first region 10 .
  • the above setting method can compensate the entire first region 10, effectively reducing the structural difference between the first region 10 and the second region 20, thereby reducing the degree of influence of the first region 10 on the normal driving transistor and the dummy driving transistor. , to ensure the working performance of the normal driving transistor.
  • the first region 10 includes a plurality of anode patterns 80;
  • the compensation structure includes a plurality of first compensation patterns 601 and a plurality of second compensation patterns, the The orthographic projection of the first compensation pattern 601 on the substrate at least partially overlaps the orthographic projection of the corresponding anode pattern 80 on the substrate;
  • the orthographic projection of the second compensation pattern on the substrate is corresponding to The orthographic projection of the anode pattern 80 on the substrate at least partially overlaps; the first compensation pattern 601 and the second compensation pattern are arranged in different layers.
  • the dotted box in FIG. 12 is the outline of the corresponding anode pattern 80 .
  • the orthographic projection of the first compensation pattern 601 on the substrate is covered by the orthographic projection of the corresponding anode pattern 80 on the substrate.
  • the orthographic projection of the second compensation pattern on the substrate is covered by the orthographic projection of the corresponding anode pattern 80 on the substrate.
  • the anode pattern 80 includes a light-transmitting anode pattern or an opaque anode pattern.
  • the above setting method enables the first compensation pattern 601 and the second compensation pattern to be blocked by the anode pattern 80, avoiding the impact of the first compensation pattern 601 and the second compensation pattern on the first area 10 influences the light transmission performance of the first region 10, ensuring the transmittance of the first region 10.
  • the above setting method can compensate the entire first region 10, effectively reducing the structural difference between the first region 10 and the second region 20, thereby reducing the degree of influence of the first region 10 on the normal driving transistor and the dummy driving transistor. , to ensure the working performance of the normal driving transistor.
  • the first compensation pattern 601 includes a plurality of sub-compensation patterns 6011 independent of each other, and the orthographic projection of the sub-compensation patterns 6011 on the base corresponds to the corresponding Orthographic projections of the anode pattern 80 on the substrate are at least partially overlapped.
  • the above arrangement reduces the influence of the first region 10 on the normal driving transistor and the dummy driving transistor while minimizing the influence of the first compensation pattern 601 on the light transmittance of the first region 10 .
  • the second compensation pattern includes a plurality of via holes 602, and the orthographic projection of the via holes 602 on the substrate corresponds to the corresponding anode pattern 80 The orthographic projections on the substrate at least partially overlap.
  • the second compensation pattern includes a body structure and a plurality of via holes disposed on the body structure.
  • the outline of the body structure is substantially the same as the outline of the anode pattern covering it.
  • the boundary of the body structure and the boundary of the first region 10 are approximately coincident.
  • the plurality of via holes included in the second compensation pattern can be completely covered by the anode pattern 80 .
  • the number of via holes included in the second compensation pattern can be set according to actual needs.
  • the orthographic projection of the via hole on the substrate in the second compensation pattern corresponding to the anode pattern is covered by the orthographic projection of the sub-compensation pattern corresponding to the anode pattern on the substrate.
  • the above setting method reduces the impact of the first region 10 on the normal driving transistor and the dummy driving transistor while minimizing the influence of the first compensation pattern 601 and the second compensation pattern on the light transmittance of the first region 10. influence level.
  • the first compensation pattern is fabricated using the active layer, and the second compensation pattern is fabricated using the interlayer insulating layer.
  • the anode pattern 80 includes a plurality of first anode patterns, a plurality of second anode patterns and a plurality of third anode patterns, the first anode pattern, the second anode pattern and the first anode pattern
  • the colors of the sub-pixels corresponding to the three anode patterns are different;
  • At least two of the first anode pattern, the second anode pattern and the third anode pattern have different areas of the corresponding first compensation patterns, and different areas of the corresponding second compensation patterns.
  • the larger the area of the anode pattern the larger the corresponding area of the first compensation pattern.
  • the smaller the area of the anode pattern the smaller the corresponding area of the first compensation pattern.
  • the larger the area of the anode pattern the larger the corresponding area of the second compensation pattern.
  • two of the first anode pattern, the second anode pattern and the third anode pattern have the same area of the corresponding first compensation pattern, and the same area of the corresponding second compensation pattern .
  • the first anode pattern corresponds to the blue sub-pixel
  • the second anode pattern corresponds to the red sub-pixel
  • the third anode pattern corresponds to the green sub-pixel
  • the first anode pattern corresponds to the first
  • the area of the compensation pattern is larger than the area of the first compensation pattern corresponding to the second anode pattern
  • the number of via holes corresponding to the first anode pattern is larger than the number of via holes corresponding to the second anode pattern.
  • the area of the first anode pattern is larger than the area of the second anode pattern.
  • the area of the second anode pattern is approximately the same as the area of the third anode pattern.
  • the compensation pattern 60 adopts the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer, one of the interlayer insulating layer and the first source-drain metal layer is fabricated.
  • the compensation pattern 60 is made by using the active layer.
  • the compensation structure includes a plurality of compensation driving circuits 61 , and the compensation driving circuits 61 have the same circuit structure as the virtual driving circuit or the normal driving circuit 301 .
  • the signal of each electrode of the target dummy drive transistor 3021 is monitored in real time through the signal lead-out line 40 and the test pad 41, so as to obtain the characteristics and threshold voltage drift of the target dummy drive transistor 3021, and according to the target dummy drive transistor 3021 3021’s characteristics and threshold voltage drift, conduct a bad analysis, determine the degree of influence of the first region 10 on the target virtual drive transistor 3021, and implement a corresponding compensation plan for the display substrate according to the determined result, so as to overcome the problem caused by the first region 10
  • the difference between the second area 20 and the second area 10 leads to a shift in the characteristics of the driving transistor in the driving circuit around the first area 10 , which ultimately affects the display effect of the display product.
  • a plurality of compensation driving circuits 61 can be set in the first region 10, and the compensation driving circuits 61 can reduce the structural difference between the first region 10 and the second region 20, Therefore, the degree of influence of the first region 10 on the normal driving transistor and the dummy driving transistor is reduced, and the working performance of the normal driving transistor is ensured.
  • the plurality of compensation drive circuits 61 are divided into at least two columns of compensation drive circuits 61 columns, and the at least two columns of compensation drive circuits 61 columns are nested in sequence, and the at least two columns
  • the column compensation driving circuit 61 is located at the edge of the first region 10 .
  • the at least two columns of compensation driving circuits 61 include two columns of compensation driving circuits 61 , or include four columns of compensation driving circuits 61 .
  • the above setting of the at least two columns of compensation driving circuits 61 is located at the edge of the first region 10, so that the at least two columns of compensation driving circuits 61 are close to the second region 20, so that the first region 10 can be effectively reduced.
  • the structural difference between the edge and the second region 20 reduces the degree of influence of the first region 10 on the normal driving transistor and the dummy driving transistor, thereby ensuring the working performance of the normal driving transistor.
  • the display substrate provided by the above embodiments, it is also possible to verify whether some current compensation structure design schemes are effective according to the monitoring results, and to verify the most effective compensation structure design scheme.
  • different target virtual driving circuits 302 that are affected can be differentiated according to the monitoring results, and the compensation design can be realized with a gradient.
  • the above detection scheme can provide data support for how to improve after a problem occurs.
  • the plurality of test pads 41 are disposed on a frame area of the display substrate.
  • the plurality of test pads 41 are disposed on the left frame area or the right frame area of the display substrate.
  • a signal can be input to the test pad 41 or a signal on the test pad 41 can be collected.
  • the first area 10 includes an off-screen camera area
  • the second area 20 includes a transition area
  • the display substrate further includes multiple reset lines Rst, multiple data lines DA, multiple gate lines GA, multiple light emission control lines EM, and multiple power lines VDD, a plurality of first initialization signal lines Vinit1 and a plurality of second initialization signal lines Vinit2.
  • the normal drive circuit 301 includes a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a data write transistor T4, a power control transistor T5, a light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst.
  • the gate of the first reset transistor T1 is coupled to the corresponding reset line Rst
  • the first pole of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1
  • the gate of the first reset transistor T1 The second pole is coupled to the gate of the driving transistor T3.
  • the gate of the compensation transistor T2 is coupled to the corresponding gate line GA, the first pole of the compensation transistor T2 is coupled to the second pole of the driving transistor T3, the second pole of the compensation transistor T2 is coupled to the The gate of the driving transistor T3 is coupled.
  • the gate of the data writing transistor T4 is coupled to the corresponding gate line GA, the first pole of the data writing transistor T4 is coupled to the corresponding data line DA, and the second pole of the data writing transistor T4 coupled with the first pole of the driving transistor T3;
  • the gate of the power control transistor T5 is coupled to the corresponding light emission control signal line, the first pole of the power control transistor T5 is coupled to the power line VDD, the second pole of the power control transistor T5 is coupled to the drive The first pole of the transistor T3 is coupled;
  • the gate of the light emission control transistor T6 is coupled to the corresponding light emission control signal line, the first electrode of the light emission control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emission control transistor T6
  • the diode is coupled to the light emitting element EL included in the sub-pixel; the cathode of the light emitting element EL receives the negative power supply signal VSS.
  • the gate of the second reset transistor T7 is coupled to the same reset line Rst′ as the gate of the first reset transistor T1 in the driving circuit adjacent along the second direction.
  • the first pole of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and the second pole of the second reset transistor T7 is coupled to the anode of the light emitting element EL.
  • the second reset transistor T7 is used to reset the anode of the light emitting element EL.
  • each working cycle includes a first reset period P1 , a writing compensation period P2 , a second reset period P3 and a light emitting period P4 .
  • the reset signal input by the reset line Rst is at an active level
  • the first reset transistor T1 is turned on
  • the first initialization signal transmitted by the first initialization signal line Vinit1 is input to the gate of the driving transistor T3 T3-g, so that the gate-source voltage Vgs held on the driving transistor T3 in the previous frame is cleared, and the gate T3-g of the driving transistor T3 is reset.
  • the reset signal is at an inactive level
  • the first reset transistor T1 is turned off
  • the gate scanning signal input from the gate line GA is at an active level
  • the control compensation transistor T2 and the data writing transistor T4 are turned on
  • the data signal is written into the data line DA, and transmitted to the first pole of the driving transistor T3 through the data writing transistor T4, and at the same time, the compensation transistor T2 and the data writing transistor T4 are turned on, so that the driving transistor T3 is formed into a diode structure , so the compensation transistor T2, the driving transistor T3 and the data writing transistor T4 work together to realize the threshold voltage compensation of the driving transistor T3.
  • the gate T3-g potential of the driving transistor T3 can be controlled to finally Vdata+Vth is reached, wherein Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the driving transistor T3.
  • the gate scan signal is at an inactive level
  • the compensation transistor T2 and the data writing transistor T4 are both turned off
  • the reset signal input from the reset line Rst' coupled to the adjacent next row of sub-pixels is at
  • the active level controls the second reset transistor T7 to turn on, and the initialization signal input by the second initialization signal line Vinit2 is input to the anode of the light emitting element EL to control the light emitting element EL not to emit light.
  • the cathode of the light emitting element EL is connected to the negative power supply signal VSS.
  • the light-emitting control signal written in the light-emitting control line EM is at an active level, and the power control transistor T5 and the light-emitting control transistor T6 are controlled to be turned on, so that the power signal transmitted by the power line VDD is input to the first drive transistor T3.
  • the driving transistor T3 since the gate T3-g of the driving transistor T3 is kept at Vdata+Vth, the driving transistor T3 is turned on, and the gate-source voltage corresponding to the driving transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power supply signal , the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a watch, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and backplane etc.
  • each electrode included in the target virtual driving transistor 3021 in the selected target virtual driving circuit 302 is respectively coupled to the corresponding signal lead-out line 40, and the signal lead-out line 40 is connected to the corresponding signal lead-out line 40.
  • the corresponding test pad 41 is coupled; in this way, the signal of each electrode of the target virtual drive transistor 3021 can be monitored in real time through the signal lead-out line 40 and the test pad 41, thereby obtaining the characteristics and the threshold voltage drift situation of the target virtual drive transistor 3021, according to the target virtual drive transistor 3021.
  • the characteristics and threshold voltage drift of the transistor 3021 are analyzed to determine the degree of influence of the first region 10 on the target virtual driving transistor 3021, and a corresponding compensation scheme is performed on the display substrate according to the determined result, so as to overcome the problem caused by the first region 10.
  • the difference between 10 and the second region 20 leads to a shift in the characteristics of the driving transistor in the driving circuit around the first region 10 , which ultimately affects the display effect of the display product.
  • the display substrate provided by the above-mentioned embodiment, by setting the signal line correspondingly coupled to the driving circuit row to which the target virtual driving transistor 3021 belongs, multiplexing the signal lead-out line 40 coupled to the target virtual driving transistor 3021, not only ensuring In addition to the normal display function of the display substrate, it also has a detection function, which effectively reduces the layout difficulty of the display substrate and simplifies the internal structure of the display substrate.
  • the reset line correspondingly coupled to the row of the driving circuit to which the target dummy driving transistor 3021 belongs is set to form an integral structure with the gate of the target dummy driving transistor 3021, so that the target dummy driving transistor 3021
  • the gate of the driving transistor 3021 can be formed with the reset line through one patterning process, which not only simplifies the manufacturing process of the display substrate, but also effectively improves the reliability of the electrical connection between the gate and the reset line.
  • the provision of the first conductive connection portion 51 can effectively reduce the connection between the gate line corresponding to the driving circuit row to which the target dummy driving transistor 3021 belongs and the target dummy driving transistor 3021.
  • connection difficulty between the first poles ensures the reliability of the connection.
  • the second conductive connection part 52 is provided, which can effectively reduce the light emission control line coupled to the driving circuit row to which the target dummy drive transistor 3021 belongs, and the target dummy drive transistor 3021.
  • the connection difficulty between the second poles ensures the reliability of the connection.
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • An embodiment of the present disclosure also provides a detection method for a display substrate, which is used to detect the display substrate provided in the above embodiment, and the detection method includes:
  • the layout of the compensation structure in the display substrate is adjusted.
  • a 0V voltage signal is input to the drain of the target dummy driving transistor 3021 .
  • a gradually changing voltage signal is input to the source and gate of the target dummy driving transistor 3021 .
  • test pad 41 is used to collect the signals of the electrodes of the target virtual driving transistor 3021 in the target virtual driving circuit 302 to obtain the characteristic curve of the target virtual driving transistor 3021 .
  • the layout of the compensation structure in the display substrate is adjusted.
  • each electrode included in the target virtual drive transistor 3021 in the target virtual drive circuit 302 is selected to correspond to The signal lead-out line 40 is coupled, and the signal lead-out line 40 is coupled with the corresponding test pad 41; Through the signal lead-out line 40 and the test pad 41, the signals of each electrode of the target virtual drive transistor 3021 are monitored in real time, thereby obtaining the target virtual drive transistor 3021.
  • the corresponding compensation scheme overcomes the problem that due to the difference between the first region 10 and the second region 20, the characteristics of the driving transistor in the driving circuit around the first region 10 are shifted, which ultimately affects the display effect of the display product .
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

一种显示基板及其检测方法、显示装置。显示基板包括基底，基底包括第一区域（10）和第二区域（20）；第二区域（20）包括多个驱动电路，多个驱动电路包括多个正常驱动电路（301）和多个虚拟驱动电路；正常驱动电路（301）包括正常驱动晶体管，虚拟驱动电路包括虚拟驱动晶体管，部分正常驱动电路（301）用于驱动第一区域（10）的阳极图形；多个驱动电路划分为多列驱动电路列，多列驱动电路列依次嵌套设置，每列驱动电路列均包围第一区域（10）；显示基板还包括多条信号引出线（40）和多个测试垫（41），信号引出线（40）与对应的测试垫（41）耦接；至少部分驱动电路列中，选取目标虚拟驱动电路（302）中的目标虚拟驱动晶体管（3021）包括的各个电极分别与对应的信号引出线（40）耦接。这样能实时监控目标虚拟驱动晶体管（3021）各个电极的信号，从而得到目标虚拟驱动晶体管（3021）的特性和阈值电压漂移情况。

Description

显示基板及其检测方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其检测方法、显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode)显示产品中，为了实现窄边框和全面屏显示，一般会将摄像头设置于显示产品的屏下摄像区域。屏下摄像区域一般仅设置发光元件，用于驱动该发光元件的驱动电路被设置于屏下摄像区域的周边。
发明内容
本公开的目的在于提供一种显示基板及其检测方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括基底，所述基底包括第一区域和第二区域；所述第二区域包括多个驱动电路，所述多个驱动电路包括多个正常驱动电路和多个虚拟驱动电路；所述正常驱动电路包括正常驱动晶体管，所述虚拟驱动电路包括虚拟驱动晶体管，部分所述正常驱动电路用于驱动所述第一区域的阳极图形；所述多个驱动电路划分为多列驱动电路列，每列驱动电路列均包围所述第一区域，所述驱动电路列包围位于该驱动电路列与所述第一区域之间的驱动电路列；
所述显示基板还包括多条信号引出线和多个测试垫，所述信号引出线与对应的测试垫耦接；
至少部分驱动电路列中，目标虚拟驱动电路中的目标虚拟驱动晶体管的至少一个电极与至少一个信号引出线耦接。
可选的，所述多个驱动电路划分为多行驱动电路行，每行驱动电路行均包括沿第一方向排列的至少一个所述驱动电路；所述显示基板还包括多条信号线，所述信号线包括沿所述第一方向延伸的至少部分，所述信号线与对应 的驱动电路行中的各驱动电路分别耦接；
所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的信号线，复用为所述目标虚拟驱动晶体管耦接的信号引出线。
可选的，所述多条信号线包括多条栅线，多条发光控制线和多条复位线；每行驱动电路行均耦接对应的所述栅线，所述发光控制线和所述复位线；
所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的栅线，发光控制线和复位线中的至少一条，复用为所述目标虚拟驱动晶体管耦接的信号引出线。
可选的，所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的复位线，复用为所述目标虚拟驱动晶体管的栅极耦接的信号引出线；
所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的栅线，复用为所述目标虚拟驱动晶体管的第一极耦接的信号引出线；
所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的发光控制线，复用为所述目标虚拟驱动晶体管的第二极耦接的信号引出线。
可选的，所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的复位线，与所述目标虚拟驱动晶体管的栅极形成为一体结构。
可选的，所述目标虚拟驱动电路包括第一导电连接部；所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的栅线，通过所述第一导电连接部与所述目标虚拟驱动晶体管的第一极耦接。
可选的，所述目标虚拟驱动电路包括第二导电连接部；所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的发光控制线，通过所述第二导电连接部与所述目标虚拟驱动晶体管的第二极耦接。
可选的，所述显示基板包括第一源漏金属层，所述第一导电连接部和/或所述第二导电连接部均采用所述第一源漏金属层制作。
可选的，所述至少部分驱动电路列包括奇数列驱动电路列或偶数列驱动电路列。
可选的，所述至少部分驱动电路列中，相邻的驱动电路列之间间隔至少一列其他驱动电路列，所述其他驱动电路列中不包括所述目标虚拟驱动电路。
可选的，所述显示基板还包括沿远离所述基底的方向依次层叠设置的有 源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层和第一源漏金属层；
所述第一区域还包括：补偿结构，所述补偿结构采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅金属层，所述层间绝缘层和所述第一源漏金属层中的至少一层制作。
可选的，所述补偿结构包括均匀分布在整个所述第一区域的补偿图形。
可选的，所述第一区域包括多个阳极图形；所述补偿结构包括多个第一补偿图形和多个第二补偿图形，所述第一补偿图形在所述基底上的正投影，与对应的阳极图形在所述基底上的正投影至少部分交叠；所述第二补偿图形在所述基底上的正投影，与对应的阳极图形在所述基底上的正投影至少部分交叠；所述第一补偿图形与所述第二补偿图形异层设置。
可选的，所述第一补偿图形包括相互独立的多个子补偿图形，所述子补偿图形在所述基底上的正投影，与对应的所述阳极图形在所述基底上的正投影至少部分交叠。
可选的，所述第二补偿图形包括多个过孔，所述过孔在所述基底上的正投影，与对应的所述阳极图形在所述基底上的正投影至少部分交叠。
可选的，所述阳极图形对应的第二补偿图形中的所述过孔在所述基底上的正投影，被该阳极图形对应的子补偿图形在所述基底上的正投影覆盖。
可选的，所述第一补偿图形采用所述有源层制作，所述第二补偿图形采用所述层间绝缘层制作。
可选的，所述阳极图形包括多个第一阳极图形，多个第二阳极图形和多个第三阳极图形，所述第一阳极图形，所述第二阳极图形和所述第三阳极图形对应的子像素的颜色不同；
所述第一阳极图形，所述第二阳极图形和所述第三阳极图形中的至少两个，对应的第一补偿图形的面积不同，对应的第二补偿图形的面积不同。
可选的，所述第一阳极图形，所述第二阳极图形和所述第三阳极图形中的两个，对应的第一补偿图形的面积相同，对应的第二补偿图形的面积相同。
可选的，所述第一阳极图形对应蓝色子像素，所述第二阳极图形对应红色子像素，所述第三阳极图形对应绿色子像素；所述第一阳极图形对应的第 一补偿图形的面积大于所述第二阳极图形对应的第一补偿图形的面积；所述第一阳极图形对应的过孔的数量大于所述第二阳极图形对应的过孔的数量。
可选的，所述补偿图形采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅金属层，所述层间绝缘层和所述第一源漏金属层中的一层制作。
可选的，所述补偿结构包括多个补偿驱动电路，所述补偿驱动电路与所述虚拟驱动电路或所述正常驱动电路的电路结构相同。
可选的，所述多个补偿驱动电路划分为至少两列补偿驱动电路列，所述至少两列补偿驱动电路列依次嵌套设置，所述至少两列补偿驱动电路列位于所述第一区域的边缘。
可选的，所述多个测试垫设置于所述显示基板的边框区域。
可选的，所述第一区域包括屏下摄像区域，所述第二区域包括过渡区域。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的检测方法，用于检测上述显示基板，所述检测方法包括：
向所述显示基板中的测试垫输入相应的测试信号；
通过所述测试垫采集目标虚拟驱动电路中的目标虚拟驱动晶体管的各个电极的信号；
根据采集到的信号，确定所述目标虚拟驱动晶体管的特性；
根据所示目标虚拟驱动晶体管的特性，调整所述显示基板中的补偿结构的布局。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的正常驱动电路的电路结构；
图2为本公开实施例提供的正常驱动电路的驱动时序图；
图3为本公开实施例提供的测试垫位置示意图；
图4为本公开实施例提供的第一区域和第二区域的示意图；
图5为本公开实施例提供的补偿结构第一示意图；
图6为本公开实施例提供的目标虚拟驱动电路的位置示意图；
图7为本公开实施例提供的信号线复用为信号引出线的示意图；
图8为本公开实施例提供的正常驱动电路和目标虚拟驱动电路的示意图；
图9a为图8中有源层的布局示意图；
图9b为图8中第一栅金属层的布局示意图；
图9c为图8中第一源漏金属层的布局示意图；
图10为图8中沿B1B2方向的截面示意图；
图11为图8中沿C1C2方向的截面示意图；
图12本公开实施例提供的补偿结构第二示意图；
图13为图12中A部分对应的第一补偿图形和第二补偿图形包括的过孔的放大示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其检测方法、显示装置，下面结合说明书附图进行详细描述。
在将摄像头设置于显示产品的屏下摄像区域时，为了保证摄像效果，屏下摄像区域中仅设置发光元件，用于驱动发光元件的驱动电路设置于屏下摄像区域的周边。所述发光元件中的阳极图形可以通过连接线与对应的驱动电路耦接，接收该驱动电路提供的驱动信号，从而实现发光元件的发光。
由于屏下摄像区域的周边设置有驱动电路，因此周边的膜层较多，膜层密度较大，与屏下摄像区域的差异较大。这种差异会造成屏下摄像区域周边的驱动电路中驱动晶体管的特性产生偏移，尤其是靠近屏下摄像区域的驱动电路中驱动晶体管的特性会产生较大偏移，会造成屏下摄像区域周边的显示亮度异常，造成肉眼可见的屏下摄像区域周边亮环，最终影响显示产品的显 示效果。
请参阅图3，图4，图5和图6，本公开实施例提供了一种显示基板，包括基底，所述基底包括第一区域10和第二区域20；所述第二区域20包括多个驱动电路30，所述多个驱动电路30包括多个正常驱动电路301和多个虚拟驱动电路；所述正常驱动电路301包括正常驱动晶体管，所述虚拟驱动电路包括虚拟驱动晶体管，部分所述正常驱动电路301用于驱动所述第一区域10的阳极图形；所述多个驱动电路划分为多列驱动电路列，每列驱动电路列均包围所述第一区域10，所述驱动电路列包围位于该驱动电路列与所述第一区域10之间的驱动电路列；
如图3和图7所示，所述显示基板还包括多条信号引出线40和多个测试垫41，所述信号引出线40与对应的测试垫41耦接；
如图8所示，至少部分驱动电路列中，目标虚拟驱动电路302中的目标虚拟驱动晶体管3021的至少一个电极与至少一个信号引出线40耦接。
示例性的，所述显示基板可以采用屏下摄像头技术(英文：Full Display with Camera，简称FDC)，这种技术中显示产品主要包括第一区域10和正常显示区域，第一区域10用于设置摄像头，正常显示区域中分布有多个第一子像素和多个第二子像素，所述第一子像素包括正常驱动电路301，所述第二子像素包括正常驱动电路301和虚拟驱动电路，第一子像素中的正常驱动电路301用于驱动正常显示区中的发光元件，所述第二子像素包括的正常驱动电路301用于驱动第一区域10中的发光元件，所述第二子像素包括的虚拟驱动电路不用于驱动发光元件。在所述正常显示区域中，多个第一子像素划分为多列第一子像素列，所述多列第一子像素列划分为多组电路组，每组电路组包括至少一列子像素列；所述多个第二子像素划分为多列第二子像素列，所述电路组与所述第二子像素列沿第一方向交替排列。
示例性的，当所述显示基板采用FDC技术时，所述第二区域20位于所述正常显示区域中。
示例性的，所述显示基板可以采用AA hole技术，这种技术中显示产品主要包括第一区域10，第一显示区域和第二显示区域。所述第二显示区域的至少部分位于所述第一显示区域和所述第一区域10之间。所述第二显示区域 中的像素密度小于所述第一显示区域中的像素密度。当所述显示基板采用AA hole技术时，所述第二区域20位于所述第二显示区。
示例性的，所述基底包括第一区域10和第二区域20，所述第二区域20包围所述第一区域10。所述第一区域10的形状包括圆形，方形，以及不规则形状等。
示例性的，所述第二区域20包括多个驱动电路，所述多个驱动电路包括多个正常驱动电路301和多个虚拟驱动电路。所述正常驱动电路301包括7T1C电路结构，但不仅限于此。所述虚拟驱动电路可以与所述正常驱动电路301的电路结构相同或不同。所述正常驱动电路301中的一部分用于驱动所述第一区域10中的阳极图形。所述正常驱动电路301中的另一部分用于驱动所述第二区域20中的阳极图形。
示例性的，所述虚拟驱动电路包括所述正常驱动电路301中的部分晶体管，但不仅限于此。
示例性的，所述多个驱动电路划分为多列驱动电路列，所述多列驱动电路列依次嵌套设置，即每列驱动电路列均包围所述第一区域10，所述驱动电路列包围位于其自身与所述第一区域10之间的其它驱动电路列。每列驱动电路列中包括所述正常驱动电路301和所述虚拟驱动电路中的至少一种。
示例性的，每列驱动电路列中同时包括多个所述正常驱动电路301和多个所述虚拟驱动电路。
示例性的，所述多条信号引出线40和所述多个测试垫41一一对应耦接。所述信号引出线40与其对应耦接的所述测试垫41形成为一体结构。
示例性的，所述信号线引出线可以采用单独的一层导电材料层制作；或者可以采用显示基板中已用的导电材料层制作。所述信号引出线40可以是独立的，仅用于传输测试信号的信号引出线40，也可以是复用显示基板中现有的信号线。
示例性的，属于同一列驱动电路列的所述正常驱动电路301和/或所述虚拟驱动电路与所述屏下摄像头区之间的最小距离相等。属于同一列驱动电路列的所述正常驱动电路301和/或所述虚拟驱动电路中，晶体管的特性偏移大致相同。
示例性的，至少部分驱动电路列中包括至少一个虚拟驱动驱动，所述至少一个虚拟驱动电路中包括至少一个目标虚拟驱动电路302，所述目标虚拟驱动电路302中包括目标虚拟驱动晶体管3021，目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接。需要说明，上述目标虚拟驱动电路302指示从所述驱动电路列中选出的，用于测试的虚拟驱动电路，其具体结构可以与其他虚拟驱动电路相同。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，在至少部分驱动电路列中，选取目标虚拟驱动电路302中的目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接，信号引出线40与对应的测试垫41耦接；这样可以通过信号引出线40和测试垫41实时监控目标虚拟驱动晶体管3021各个电极的信号，从而得到目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，根据目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，进行不良分析，确定第一区域10对目标虚拟驱动晶体管3021的影响程度，根据确定的结果对所述显示基板进行相应的补偿方案，从而克服由于第一区域10与第二区域20之间的差异，导致的第一区域10周边的驱动电路中驱动晶体管的特性产生偏移，最终影响显示产品的显示效果的问题。
如图3，图7和图8，图9a至图9c所示，在一些实施例中，所述多个驱动电路划分为多行驱动电路行，每行驱动电路行均包括沿第一方向排列的至少一个所述驱动电路；所述显示基板还包括多条信号线，所述信号线包括沿所述第一方向延伸的至少部分，所述信号线与对应的驱动电路行中的各驱动电路分别耦接；
所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的信号线，复用为所述目标虚拟驱动晶体管3021耦接的信号引出线40。
值得注意，图8中未示意第二栅金属层，正常驱动电路301中包括第二栅金属层，所述第二源漏金属层可以用于形成电容的第二极板，初始化信号线等结构，但不仅限于此。目标虚拟驱动电路302中可以根据实际需要设置或者不设置第二栅金属层。
示例性的，所述显示基板还包括其他显示区域，所述其他显示区域包围 所述第二区域20，所述其他显示区域包括阵列分布的多个子像素，子像素包括正常驱动电路301和发光元件。
示例性的，所述第二区域20的多个驱动电路划分为多行驱动电路行，该驱动电路行可以与其他显示区域中的驱动电路行位于同一行，位于同一行的驱动电路共用相同的栅线GA，复位线Rst和发光控制线EM等。
示例性的，每行驱动电路行中的各驱动电路包括正常驱动电路301和虚拟驱动电路。
示例性的，所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的信号线，复用为所述目标虚拟驱动晶体管3021耦接的信号引出线40。在正常显示时段，所述信号线用于为显示基板提供相应的扫描信号。在检测时段，所述信号线复用为所述信号引出线40，用于提供检测信号，以及采集目标虚拟驱动晶体管3021上各电极上的信号。
需要说明，信号线沿第一方向延伸是指：信号线包括主要部分和与所述主要部分连接的次要部分，所述主要部分是线、线段或条形状体，所述主要部分沿第一方向延展，且所述主要部分沿第一方向延展的长度大于次要部分沿其它方向伸展的长度。
上述实施例提供的显示基板中，通过设置所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的信号线，复用为所述目标虚拟驱动晶体管3021耦接的信号引出线40，不仅保证了显示基板的正常显示功能，同时还兼备了检测功能，有效降低了显示基板的布局难度，简化了显示基板的内部结构。
如图3，图7和图8所示，在一些实施例中，所述多条信号线包括多条栅线GA，多条发光控制线EM和多条复位线Rst；每行驱动电路行均耦接对应的所述栅线GA，所述发光控制线EM和所述复位线Rst；
所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的栅线GA，发光控制线EM和复位线Rst中的至少一条，复用为所述目标虚拟驱动晶体管3021耦接的信号引出线40。
示例性的，所述信号线延伸至所述显示基板的边框区域的一端，分别与对应的测试垫41和对应的栅极3021a驱动电路(GOA)耦接。
上述实施例提供的显示基板中，通过设置所述目标虚拟驱动晶体管3021 所属的驱动电路行对应耦接的栅线GA，发光控制线EM和复位线Rst中的至少一条，复用为所述目标虚拟驱动晶体管3021耦接的信号引出线40，不仅保证了显示基板的正常显示功能，同时还兼备了检测功能，有效降低了显示基板的布局难度，简化了显示基板的内部结构。
如图3，图7和图8所示，在一些实施例中，设置所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的复位线Rst，复用为所述目标虚拟驱动晶体管3021的栅极3021a耦接的信号引出线40；
所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的栅线GA，复用为所述目标虚拟驱动晶体管3021的第一极3021b耦接的信号引出线40；
所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的发光控制线EM，复用为所述目标虚拟驱动晶体管3021的第二极3021c耦接的信号引出线40。
示例性的，所述目标虚拟驱动晶体管3021的第一极3021b包括漏极，所述目标虚拟驱动晶体管3021的第二极3021c包括源极。
上述设置方式不仅保证了显示基板的正常显示功能，同时还兼备了检测功能，有效降低了显示基板的布局难度，简化了显示基板的内部结构。
如图3，图6，图7和图8所示，在一些实施例中，所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的复位线Rst，与所述目标虚拟驱动晶体管3021的栅极3021a形成为一体结构。
示例性的，所述复位线Rst和所述目标虚拟驱动晶体管3021的栅极3021a均采用第一栅金属层制作。
示例性的，所述复位线Rst与所述目标虚拟驱动晶体管3021的栅极3021a耦接的一端，会延伸出拐角部分70，所述拐角部分70与所述目标虚拟驱动晶体管3021的栅极3021a形成为一体机构。示例性的，所述拐角部分70包括弧形或半圆形等。所述拐角部分70的开口朝向所述目标虚拟驱动电路302。
上述设置所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的复位线Rst，与所述目标虚拟驱动晶体管3021的栅极3021a形成为一体结构，使得所述目标虚拟驱动晶体管3021的栅极3021a能够与所述复位线Rst通过一次构图工艺形成，这样不仅简化了显示基板的制作工艺流程，也有效提升 了栅极3021a与复位线Rst之间电连接的信赖性。
如图8，图10和图11所示，在一些实施例中，所述目标虚拟驱动电路302包括第一导电连接部51；所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的栅线GA，通过所述第一导电连接部51与所述目标虚拟驱动晶体管3021的第一极3021b耦接。
需要说明，图10和图11中还示意了基底90，第一栅极绝缘层GI1和第二栅极绝缘层GI2.
示例性的，所述第一导电连接部51采用第一源漏金属层制作，能够与所述显示基板中采用第一源漏金属层制作的其它导电结构在同一次构图工艺中形成。
示例性的，所述第一导电连接部51在所述基底上的正投影，与所述栅线GA在所述基底上的正投影具有交叠区域，在该交叠区域，所述第一导电连接部51通过过孔与所述栅线GA耦接。所述第一导电连接部51在所述基底上的正投影，与所述目标虚拟驱动晶体管3021的第一极3021b在所述基底上的正投影具有交叠区域，在该交叠区域，所述第一导电连接部51通过过孔与所述目标虚拟驱动晶体管3021的第一极3021b耦接。
上述设置所述第一导电连接部51，能够有效降低所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的栅线GA，与所述目标虚拟驱动晶体管3021的第一极3021b之间的连接难度，保证了连接的信赖性。
如图8所示，在一些实施例中，所述目标虚拟驱动电路302包括第二导电连接部52；所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的发光控制线EM，通过所述第二导电连接部52与所述目标虚拟驱动晶体管3021的第二极3021c耦接。
示例性的，所述第二导电连接部52采用第一源漏金属层制作，能够与所述显示基板中采用第一源漏金属层制作的其它导电结构在同一次构图工艺中形成。
示例性的，所述第二导电连接部52在所述基底上的正投影，与所述发光控制线EM在所述基底上的正投影具有交叠区域，在该交叠区域，所述第二导电连接部52通过过孔与所述发光控制线EM耦接。所述第一导电连接部51在 所述基底上的正投影，与所述目标虚拟驱动晶体管3021的第二极3021c在所述基底上的正投影具有交叠区域，在该交叠区域，所述第二导电连接部52通过过孔与所述目标虚拟驱动晶体管3021的第二极3021c耦接。
上述设置所述第二导电连接部52，能够有效降低所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的发光控制线EM，与所述目标虚拟驱动晶体管3021的第二极3021c之间的连接难度，保证了连接的信赖性。
在一些实施例中，所述显示基板包括第一源漏金属层，所述第一导电连接部51和/或所述第二导电连接部52均采用所述第一源漏金属层制作。
在一些实施例中，所述至少部分驱动电路列包括奇数列驱动电路列或偶数列驱动电路列。
示例性的，所述至少部分驱动电路列中，目标虚拟驱动电路302中的目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接。
示例性的，奇数列驱动电路列中，目标虚拟驱动电路302中的目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接。
示例性的，偶数列驱动电路列中，目标虚拟驱动电路302中的目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接。
在一些实施例中，所述至少部分驱动电路列中，相邻的驱动电路列之间间隔至少一列其他驱动电路列，所述其他驱动电路列中不包括所述目标虚拟驱动电路。
示例性的，所述至少部分驱动电路列中，相邻的驱动电路列之间间隔五列其他驱动电路列。
上述实施例提供的显示基板中，所述至少部分驱动电路列可以间隔设置，不必对每一列驱动电路列中的虚拟驱动晶体管的电极信号进行采集，这样能够在满足采集需要的同时，降低显示基板的复杂程度。
在一些实施例中，所述显示基板还包括沿远离所述基底的方向依次层叠设置的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层和第一源漏金属层；
所述第一区域10还包括：补偿结构，所述补偿结构采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅 金属层，所述层间绝缘层和所述第一源漏金属层中的至少一层制作。
示例性的，所述补偿结构在采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅金属层，所述层间绝缘层和所述第一源漏金属层中的至少一层制作时，补偿结构的具体结构可以与其采用的制作膜层在第二区域20形成的结构相同，但不仅限于此。
上述实施例提供的显示基板中，通过信号引出线40和测试垫41实时监控目标虚拟驱动晶体管3021各个电极的信号，从而得到目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，根据目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，进行不良分析，确定第一区域10对目标虚拟驱动晶体管3021的影响程度，根据确定的结果对所述显示基板进行相应的补偿方案，从而克服由于第一区域10与第二区域20之间的差异，导致的第一区域10周边的驱动电路中驱动晶体管的特性产生偏移，最终影响显示产品的显示效果的问题。
基于上述思想，在获取到确定的结果后，可以在所述第一区域10设置补偿结构，该补偿结构可以降低第一区域10与第二区域20之间的结构差异，从而降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响程度，保证所述正常驱动晶体管的工作性能。
如图5所示，在一些实施例中，设置所述补偿结构包括均匀分布在整个所述第一区域10的补偿图形60。
上述设置方式能够对整个所述第一区域10进行补偿，有效降低了第一区域10与第二区域20之间的结构差异，从而降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响程度，保证所述正常驱动晶体管的工作性能。
如图12和图13所示，在一些实施例中，所述第一区域10包括多个阳极图形80；所述补偿结构包括多个第一补偿图形601和多个第二补偿图形，所述第一补偿图形601在所述基底上的正投影，与对应的阳极图形80在所述基底上的正投影至少部分交叠；所述第二补偿图形在所述基底上的正投影，与对应的阳极图形80在所述基底上的正投影至少部分交叠；所述第一补偿图形601与所述第二补偿图形异层设置。
示例性的，图12中虚线框为对应的阳极图形80的轮廓。
示例性的，所述第一补偿图形601在所述基底上的正投影，被对应的阳极图形80在所述基底上的正投影覆盖。
示例性的，所述第二补偿图形在所述基底上的正投影，被对应的阳极图形80在所述基底上的正投影覆盖。
示例性的，上述阳极图形80包括透光的阳极图形或者不透光的阳极图形。
上述设置方式使得所述第一补偿图形601和所述第二补偿图形能够被所述阳极图形80遮挡，避免了所述第一补偿图形601和所述第二补偿图形对所述第一区域10的透光性能产生影响，保证了所述第一区域10的透过率。
上述设置方式能够对整个所述第一区域10进行补偿，有效降低了第一区域10与第二区域20之间的结构差异，从而降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响程度，保证所述正常驱动晶体管的工作性能。
如图12和图13所示，在一些实施例中，所述第一补偿图形601包括相互独立的多个子补偿图形6011，所述子补偿图形6011在所述基底上的正投影，与对应的所述阳极图形80在所述基底上的正投影至少部分交叠。
上述设置方式在降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响的同时，最大限度降低了所述第一补偿图形601对所述第一区域10的透光率的影响程度。
如图12和图13所示，在一些实施例中，所述第二补偿图形包括多个过孔602，所述过孔602在所述基底上的正投影，与对应的所述阳极图形80在所述基底上的正投影至少部分交叠。
示例性的，所述第二补偿图形包括本体结构，以及设置于所述本体结构上的多个过孔。
示例性的，所述本体结构的轮廓与覆盖其的阳极图形的轮廓大致相同。
示例性的，所述本体结构的边界与所述第一区域10的边界大致贴合。
示例性的，所述第二补偿图形包括的多个过孔能够被所述阳极图形80完全覆盖。
示例性的，所述第二补偿图形包括的过孔的数量可以根据实际需要设置。
在一些实施例中，所述阳极图形对应的第二补偿图形中的所述过孔在所 述基底上的正投影，被该阳极图形对应的子补偿图形在所述基底上的正投影覆盖。
上述设置方式在降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响的同时，最大限度降低了所述第一补偿图形601和第二补偿图形对所述第一区域10的透光率的影响程度。
在一些实施例中，所述第一补偿图形采用所述有源层制作，所述第二补偿图形采用所述层间绝缘层制作。
在一些实施例中，所述阳极图形80包括多个第一阳极图形，多个第二阳极图形和多个第三阳极图形，所述第一阳极图形，所述第二阳极图形和所述第三阳极图形对应的子像素的颜色不同；
所述第一阳极图形，所述第二阳极图形和所述第三阳极图形中的至少两个，对应的第一补偿图形的面积不同，对应的第二补偿图形的面积不同。
示例性的，所述阳极图形的面积越大，其对应的所述第一补偿图形的面积越大。所述阳极图形的面积越小，其对应的第一补偿图形的面积越小。
示例性的，所述阳极图形的面积越大，其对应的所述第二补偿图形的面积越大。所述阳极图形的面积越小，其对应的第二补偿图形的面积越小。
在一些实施例中，所述第一阳极图形，所述第二阳极图形和所述第三阳极图形中的两个，对应的第一补偿图形的面积相同，对应的第二补偿图形的面积相同。
在一些实施例中，所述第一阳极图形对应蓝色子像素，所述第二阳极图形对应红色子像素，所述第三阳极图形对应绿色子像素；所述第一阳极图形对应的第一补偿图形的面积大于所述第二阳极图形对应的第一补偿图形的面积；所述第一阳极图形对应的过孔的数量大于所述第二阳极图形对应的过孔的数量。
示例性的，所述第一阳极图形的面积大于所述第二阳极图形的面积。所述第二阳极图形的面积与所述第三阳极图形的面积大致相同。
在一些实施例中，所述补偿图形60采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅金属层，所述层间绝缘层和所述第一源漏金属层中的一层制作。
示例性的，所述补偿图形60采用所述有源层制作。
如图5所示，在一些实施例中，所述补偿结构包括多个补偿驱动电路61，所述补偿驱动电路61与所述虚拟驱动电路或所述正常驱动电路301的电路结构相同。
上述实施例提供的显示基板中，通过信号引出线40和测试垫41实时监控目标虚拟驱动晶体管3021各个电极的信号，从而得到目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，根据目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，进行不良分析，确定第一区域10对目标虚拟驱动晶体管3021的影响程度，根据确定的结果对所述显示基板进行相应的补偿方案，从而克服由于第一区域10与第二区域20之间的差异，导致的第一区域10周边的驱动电路中驱动晶体管的特性产生偏移，最终影响显示产品的显示效果的问题。
基于上述思想，在获取到确定的结果后，可以在所述第一区域10设置多个补偿驱动电路61，该补偿驱动电路61可以降低第一区域10与第二区域20之间的结构差异，从而降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响程度，保证所述正常驱动晶体管的工作性能。
如图5所示，在一些实施例中，所述多个补偿驱动电路61划分为至少两列补偿驱动电路61列，所述至少两列补偿驱动电路61列依次嵌套设置，所述至少两列补偿驱动电路61列位于所述第一区域10的边缘。
示例性的，所述至少两列补偿驱动电路61列包括两列补偿驱动电路61列，或者包括四列补偿驱动电路61列。
上述设置所述至少两列补偿驱动电路61列位于所述第一区域10的边缘，使得所述至少两列补偿驱动电路61列靠近所述第二区域20，从能够有效降低第一区域10的边缘与第二区域20之间的结构差异，从而降低第一区域10对正常驱动晶体管和虚拟驱动晶体管的影响程度，保证所述正常驱动晶体管的工作性能。
上述实施例提供的显示基板中，还可以根据监控的结果，验证目前的一些补偿结构设计方案是否有效，并能够验证出最有效的补偿结构设计方案。同时，可以根据监控结果对受到影响不同的目标虚拟驱动电路302进行区别 化，有梯度的实现补偿设计。上述检测方案能够为在出现问题后，对于如何改善，提供数据支撑。
在一些实施例中，所述多个测试垫41设置于所述显示基板的边框区域。
示例性的，所述多个测试垫41设置于所述显示基板的左侧边框区域或者右侧边框区域。
示例性的，通过对所述测试垫41扎针，能够向所述测试垫41输入信号，或者采集所述测试垫41上的信号。
在一些实施例中，所述第一区域10包括屏下摄像区域，所述第二区域20包括过渡区域。
如图1和图2所示，在一些实施例中，所述显示基板还包括多条复位线Rst，多条数据线DA，多条栅线GA，多条发光控制线EM，多条电源线VDD，多条第一初始化信号线Vinit1和多条第二初始化信号线Vinit2。
所述正常驱动电路301包括第一复位晶体管T1，补偿晶体管T2，驱动晶体管T3，数据写入晶体管T4，电源控制晶体管T5，发光控制晶体管T6，第二复位晶体管T7和存储电容Cst。
所述第一复位晶体管T1的栅极与对应的复位线Rst耦接，所述第一复位晶体管T1的第一极与对应的第一初始化信号线Vinit1耦接，所述第一复位晶体管T1的第二极与所述驱动晶体管T3的栅极耦接。
所述补偿晶体管T2的栅极与对应的栅线GA耦接，所述补偿晶体管T2的第一极与所述驱动晶体管T3的第二极耦接，所述补偿晶体管T2的第二极与所述驱动晶体管T3的栅极耦接。
所述数据写入晶体管T4的栅极与对应的栅线GA耦接，所述数据写入晶体管T4的第一极与对应的数据线DA耦接，所述数据写入晶体管T4的第二极与所述驱动晶体管T3的第一极耦接；
所述电源控制晶体管T5的栅极与对应的发光控制信号线耦接，所述电源控制晶体管T5的第一极与电源线VDD耦接，所述电源控制晶体管T5的第二极与所述驱动晶体管T3的第一极耦接；
所述发光控制晶体管T6的栅极与对应的发光控制信号线耦接，所述发光控制晶体管T6的第一极与所述驱动晶体管T3的第二极耦接，所述发光控制 晶体管T6的第二极与子像素包括的发光元件EL耦接；所述发光元件EL的阴极接收负电源信号VSS。
所述第二复位晶体管T7的栅极与沿所述第二方向相邻的驱动电路中的第一复位晶体管T1的栅极耦接同一条复位线Rst'。所述第二复位晶体管T7的第一极与对应的第二初始化信号线Vinit2耦接，所述第二复位晶体管T7的第二极与所述发光元件EL的阳极耦接。所述第二复位晶体管T7用于对发光元件EL的阳极进行复位。
如图1和图2所示，上述结构的正常驱动电路301在工作时，每个工作周期均包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在所述第一复位时段P1，复位线Rst输入的复位信号处于有效电平，第一复位晶体管T1导通，由第一初始化信号线Vinit1传输的第一初始化信号输入至驱动晶体管T3的栅极T3-g，使得前一帧保持在驱动晶体管T3上的栅源电压Vgs被清零，实现对驱动晶体管T3的栅极T3-g复位。
在写入补偿时段P2，所述复位信号处于非有效电平，第一复位晶体管T1截止，栅线GA输入的栅极扫描信号处于有效电平，控制补偿晶体管T2和数据写入晶体管T4导通，数据线DA写入数据信号，并经所述数据写入晶体管T4传输至驱动晶体管T3的第一极，同时，补偿晶体管T2和数据写入晶体管T4导通，使得驱动晶体管T3形成为二极管结构，因此通过补偿晶体管T2、驱动晶体管T3和数据写入晶体管T4配合工作，实现对驱动晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制驱动晶体管T3的栅极T3-g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表驱动晶体管T3的阈值电压。
在第二复位时段P3，所述栅极扫描信号处于非有效电平，补偿晶体管T2和数据写入晶体管T4均截止，相邻的下一行子像素耦接的复位线Rst’输入的复位信号处于有效电平，控制第二复位晶体管T7导通，将所述第二初始化信号线Vinit2输入的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发光。发光元件EL的阴极接入负电源信号VSS。
在发光时段P4，发光控制线EM写入的发光控制信号处于有效电平，控制电源控制晶体管T5和发光控制晶体管T6导通，使得由电源线VDD传输的电源信号输入至驱动晶体管T3的第一极，同时由于驱动晶体管T3的栅极T3-g保持在Vdata+Vth，使得驱动晶体管T3导通，驱动晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、手表、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
上述实施例提供的显示基板中，在至少部分驱动电路列中，选取目标虚拟驱动电路302中的目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接，信号引出线40与对应的测试垫41耦接；这样可以通过信号引出线40和测试垫41实时监控目标虚拟驱动晶体管3021各个电极的信号，从而得到目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，根据目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，进行不良分析，确定第一区域10对目标虚拟驱动晶体管3021的影响程度，根据确定的结果对所述显示基板进行相应的补偿方案，从而克服由于第一区域10与第二区域20之间的差异，导致的第一区域10周边的驱动电路中驱动晶体管的特性产生偏移，最终影响显示产品的显示效果的问题。
上述实施例提供的显示基板中，通过设置所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的信号线，复用为所述目标虚拟驱动晶体管3021耦接的信号引出线40，不仅保证了显示基板的正常显示功能，同时还兼备了检测功能，有效降低了显示基板的布局难度，简化了显示基板的内部结构。上述实施例提供的显示基板中，设置所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的复位线，与所述目标虚拟驱动晶体管3021的栅极形成为一体结构，使得所述目标虚拟驱动晶体管3021的栅极能够与所述复位线通过一次构图工艺形成，这样不仅简化了显示基板的制作工艺流程，也有效提升了栅极与复位线之间电连接的信赖性。上述实施例提供的显示基板中，设置 所述第一导电连接部51，能够有效降低所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的栅线，与所述目标虚拟驱动晶体管3021的第一极之间的连接难度，保证了连接的信赖性。上述实施例提供的显示基板中，设置所述第二导电连接部52，能够有效降低所述目标虚拟驱动晶体管3021所属的驱动电路行对应耦接的发光控制线，与所述目标虚拟驱动晶体管3021的第二极之间的连接难度，保证了连接的信赖性。
本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
本公开实施例还提供了一种显示基板的检测方法，用于检测上述实施例提供的显示基板，所述检测方法包括：
向所述显示基板中的测试垫41输入相应的测试信号；
通过所述测试垫41采集目标虚拟驱动电路302中的目标虚拟驱动晶体管3021的各个电极的信号；
根据采集到的信号，确定所述目标虚拟驱动晶体管3021的特性；
根据所示目标虚拟驱动晶体管3021的特性，调整所述显示基板中的补偿结构的布局。
示例性的，为所述目标虚拟驱动晶体管3021的漏极输入0V电压信号。为所述目标虚拟驱动晶体管3021的源极和栅极输入渐变的电压信号。
示例性的，通过所述测试垫41采集目标虚拟驱动电路302中的目标虚拟驱动晶体管3021的各个电极的信号，获取所述目标虚拟驱动晶体管3021的特性曲线。
示例性的，根据所示目标虚拟驱动晶体管3021的特性曲线，调整所述显示基板中的补偿结构的布局。
采用本公开实施例提供的检测方法检测上述实施例提供的显示基板时，在显示基板的至少部分驱动电路列中，选取目标虚拟驱动电路302中的目标虚拟驱动晶体管3021包括的各个电极分别与对应的信号引出线40耦接，信号引出线40与对应的测试垫41耦接；通过信号引出线40和测试垫41实时监控目标虚拟驱动晶体管3021各个电极的信号，从而得到目标虚拟驱动晶体管3021的特性和阈值电压漂移情况，根据目标虚拟驱动晶体管3021的特性 和阈值电压漂移情况，进行不良分析，确定第一区域10对目标虚拟驱动晶体管3021的影响程度，根据确定的结果对所述显示基板进行相应的补偿方案，从而克服由于第一区域10与第二区域20之间的差异，导致的第一区域10周边的驱动电路中驱动晶体管的特性产生偏移，最终影响显示产品的显示效果的问题。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或 者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种显示基板，包括基底，所述基底包括第一区域和第二区域；所述第二区域包括多个驱动电路，所述多个驱动电路包括多个正常驱动电路和多个虚拟驱动电路；所述正常驱动电路包括正常驱动晶体管，所述虚拟驱动电路包括虚拟驱动晶体管，部分所述正常驱动电路用于驱动所述第一区域的阳极图形；所述多个驱动电路划分为多列驱动电路列，每列驱动电路列均包围所述第一区域，所述驱动电路列包围位于该驱动电路列与所述第一区域之间的驱动电路列；
    所述显示基板还包括多条信号引出线和多个测试垫，所述信号引出线与对应的测试垫耦接；
    至少部分驱动电路列中，目标虚拟驱动电路中的目标虚拟驱动晶体管的至少一个电极与至少一个信号引出线耦接。
  2. 根据权利要求1所述的显示基板，其中，所述多个驱动电路划分为多行驱动电路行，每行驱动电路行均包括沿第一方向排列的至少一个所述驱动电路；所述显示基板还包括多条信号线，所述信号线包括沿所述第一方向延伸的至少部分，所述信号线与对应的驱动电路行中的各驱动电路分别耦接；
    所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的信号线，复用为所述目标虚拟驱动晶体管耦接的信号引出线。
  3. 根据权利要求2所述的显示基板，其中，所述多条信号线包括多条栅线，多条发光控制线和多条复位线；每行驱动电路行均耦接对应的所述栅线，所述发光控制线和所述复位线；
    所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的栅线，发光控制线和复位线中的至少一条，复用为所述目标虚拟驱动晶体管耦接的信号引出线。
  4. 根据权利要求3所述的显示基板，其中，
    所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的复位线，复用为所述目标虚拟驱动晶体管的栅极耦接的信号引出线；
    所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的栅线，复用为所 述目标虚拟驱动晶体管的第一极耦接的信号引出线；
    所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的发光控制线，复用为所述目标虚拟驱动晶体管的第二极耦接的信号引出线。
  5. 根据权利要求4所述的显示基板，其中，所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的复位线，与所述目标虚拟驱动晶体管的栅极形成为一体结构。
  6. 根据权利要求4所述的显示基板，其中，所述目标虚拟驱动电路包括第一导电连接部；所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的栅线，通过所述第一导电连接部与所述目标虚拟驱动晶体管的第一极耦接。
  7. 根据权利要求6所述的显示基板，其中，所述目标虚拟驱动电路包括第二导电连接部；所述目标虚拟驱动晶体管所属的驱动电路行对应耦接的发光控制线，通过所述第二导电连接部与所述目标虚拟驱动晶体管的第二极耦接。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板包括第一源漏金属层，所述第一导电连接部和/或所述第二导电连接部均采用所述第一源漏金属层制作。
  9. 根据权利要求1所述的显示基板，其中，所述至少部分驱动电路列包括奇数列驱动电路列或偶数列驱动电路列。
  10. 根据权利要求1所述的显示基板，其中，所述至少部分驱动电路列中，相邻的驱动电路列之间间隔至少一列其他驱动电路列，所述其他驱动电路列中不包括所述目标虚拟驱动电路。
  11. 根据权利要求1所述的显示基板，其中，所述显示基板还包括沿远离所述基底的方向依次层叠设置的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层和第一源漏金属层；
    所述第一区域还包括：补偿结构，所述补偿结构采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅金属层，所述层间绝缘层和所述第一源漏金属层中的至少一层制作。
  12. 根据权利要求11所述的显示基板，其中，所述补偿结构包括均匀分布在整个所述第一区域的补偿图形。
  13. 根据权利要求11所述的显示基板，其中，所述第一区域包括多个阳极图形；所述补偿结构包括多个第一补偿图形和多个第二补偿图形，所述第一补偿图形在所述基底上的正投影，与对应的阳极图形在所述基底上的正投影至少部分交叠；所述第二补偿图形在所述基底上的正投影，与对应的阳极图形在所述基底上的正投影至少部分交叠；所述第一补偿图形与所述第二补偿图形异层设置。
  14. 根据权利要求13所述的显示基板，其中，所述第一补偿图形包括相互独立的多个子补偿图形，所述子补偿图形在所述基底上的正投影，与对应的所述阳极图形在所述基底上的正投影至少部分交叠。
  15. 根据权利要求14所述的显示基板，其中，所述第二补偿图形包括多个过孔，所述过孔在所述基底上的正投影，与对应的所述阳极图形在所述基底上的正投影至少部分交叠。
  16. 根据权利要求15所述的显示基板，其中，所述阳极图形对应的第二补偿图形中的所述过孔在所述基底上的正投影，被该阳极图形对应的子补偿图形在所述基底上的正投影覆盖。
  17. 根据权利要求13所述的显示基板，其中，所述第一补偿图形采用所述有源层制作，所述第二补偿图形采用所述层间绝缘层制作。
  18. 根据权利要求13所述的显示基板，其中，所述阳极图形包括多个第一阳极图形，多个第二阳极图形和多个第三阳极图形，所述第一阳极图形，所述第二阳极图形和所述第三阳极图形对应的子像素的颜色不同；
    所述第一阳极图形，所述第二阳极图形和所述第三阳极图形中的至少两个，对应的第一补偿图形的面积不同，对应的第二补偿图形的面积不同。
  19. 根据权利要求18所述的显示基板，其中，所述第一阳极图形，所述第二阳极图形和所述第三阳极图形中的两个，对应的第一补偿图形的面积相同，对应的第二补偿图形的面积相同。
  20. 根据权利要求19所述的显示基板，其中，所述第一阳极图形对应蓝色子像素，所述第二阳极图形对应红色子像素，所述第三阳极图形对应绿色子像素；所述第一阳极图形对应的第一补偿图形的面积大于所述第二阳极图形对应的第一补偿图形的面积；所述第一阳极图形对应的过孔的数量大于所 述第二阳极图形对应的过孔的数量。
  21. 根据权利要求12所述的显示基板，其中，所述补偿图形采用所述有源层，所述第一栅极绝缘层，所述第一栅金属层，所述第二栅极绝缘层，所述第二栅金属层，所述层间绝缘层和所述第一源漏金属层中的一层制作。
  22. 根据权利要求11所述的显示基板，其中，所述补偿结构包括多个补偿驱动电路，所述补偿驱动电路与所述虚拟驱动电路或所述正常驱动电路的电路结构相同。
  23. 根据权利要求22所述的显示基板，其中，所述多个补偿驱动电路划分为至少两列补偿驱动电路列，所述至少两列补偿驱动电路列依次嵌套设置，所述至少两列补偿驱动电路列位于所述第一区域的边缘。
  24. 根据权利要求1所述的显示基板，其中，所述多个测试垫设置于所述显示基板的边框区域。
  25. 根据权利要求1所述的显示基板，其中，所述第一区域包括屏下摄像区域，所述第二区域包括过渡区域。
  26. 一种显示装置，包括如权利要求1～25中任一项所述的显示基板。
  27. 一种显示基板的检测方法，用于检测如权利要求1～25中任一项所述的显示基板，所述检测方法包括：
    向所述显示基板中的测试垫输入相应的测试信号；
    通过所述测试垫采集目标虚拟驱动电路中的目标虚拟驱动晶体管的各个电极的信号；
    根据采集到的信号，确定所述目标虚拟驱动晶体管的特性；
    根据所示目标虚拟驱动晶体管的特性，调整所述显示基板中的补偿结构的布局。
PCT/CN2022/077967 2022-02-25 2022-02-25 显示基板及其检测方法、显示装置 WO2023159479A1 (zh)

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