WO2023142404A1 - 显示面板及显示设备 - Google Patents

显示面板及显示设备 Download PDF

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Publication number
WO2023142404A1
WO2023142404A1 PCT/CN2022/107403 CN2022107403W WO2023142404A1 WO 2023142404 A1 WO2023142404 A1 WO 2023142404A1 CN 2022107403 W CN2022107403 W CN 2022107403W WO 2023142404 A1 WO2023142404 A1 WO 2023142404A1
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WIPO (PCT)
Prior art keywords
pixel circuit
circuit units
display panel
pixel
units
Prior art date
Application number
PCT/CN2022/107403
Other languages
English (en)
French (fr)
Inventor
刘雨生
王刚
丁立薇
米磊
Original Assignee
昆山国显光电有限公司
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Filing date
Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to EP22923212.9A priority Critical patent/EP4318588A4/en
Priority to KR1020237037278A priority patent/KR20230157517A/ko
Priority to JP2023566913A priority patent/JP2024517197A/ja
Publication of WO2023142404A1 publication Critical patent/WO2023142404A1/zh
Priority to US18/486,408 priority patent/US20240040832A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • the frame of the screen cannot be further reduced. Therefore, it is proposed to arrange part of the driving circuit in the display area on the market. In order to reduce the size of the border technology, but this has caused the change of the pixel circuit in the display area, which in turn affects the display stability of the screen.
  • a display panel including a substrate, a plurality of light emitting units arranged in an array, a plurality of first pixel circuit units, and a plurality of second pixel circuit units.
  • the substrate includes a display area and a frame area at least partially surrounding the display area.
  • the plurality of light emitting units are arranged in the display area.
  • Each light emitting unit includes a first electrode.
  • the plurality of first pixel circuit units are arranged in an array and arranged in the display area.
  • Each first pixel circuit unit includes a plurality of first pixel circuits.
  • the plurality of first pixel circuits are arranged in an array, and at least one first pixel circuit is electrically connected to a first electrode of a corresponding light emitting unit.
  • the plurality of second pixel circuit units are arranged in the display area.
  • Each second pixel circuit unit includes a plurality of second pixel circuits.
  • the plurality of second pixel circuits are arranged in an array, and at least one second pixel circuit is electrically connected to the first electrode of a corresponding light emitting unit.
  • a first placement gap is formed between any two adjacent first pixel circuit units.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of the front structure of a display panel in an embodiment of the present application.
  • FIG. 2 is a schematic front view of a partial structure of a display panel in an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of a partial structure of a display panel in an embodiment of the present application.
  • FIG. 4 is a schematic plan view of the connection between the light emitting unit and the pixel circuit unit of the display panel in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of some wires in a display panel according to an embodiment of the present application.
  • the direction perpendicular to the display surface of the display panel is defined as the third direction, and the two directions parallel to and intersecting the display surface are defined as the first direction and the second direction.
  • the third direction is also the thickness direction of the display panel and its substrate, and the direction from the substrate to the light emitting unit.
  • part of the driving circuit originally located in the frame area of the display panel can be arranged in the display area.
  • the pixel circuit is electrically connected to the light emitting unit for making the light emitting unit emit light.
  • the driving circuit in the display area without affecting the size of the display area, the size of the original pixel circuit can be reduced while maintaining the size of the original light-emitting unit, and then the driving circuit can be placed under the area close to the frame area. space, thereby reducing the size of the border area.
  • the inventor found that although the space of the display area obtained by reducing the size of the pixel circuit can meet the requirements for placing the driving circuit in the display area, the distance between the corresponding two adjacent pixel circuits Increased, which has a certain impact on the stability of the display.
  • the distance between the corresponding two adjacent pixel circuits Increased, which has a certain impact on the stability of the display.
  • the distance between two adjacent pixel circuits increases, the increased distance is not enough for arranging other materials or components, thus failing to improve the display stability.
  • a display panel 100 in at least one embodiment of the present application includes a substrate 10 , a plurality of light emitting units 20 , a plurality of first pixel circuit units 30 and a plurality of second pixel circuit units 40 .
  • the substrate 10 includes a display area AA and a frame area FA at least partially surrounding the display area.
  • the display panel 100 When the display panel 100 is displaying, it can display images in the display area AA, but not display images in the frame area FA.
  • a plurality of light emitting units 20 are arranged in an array and located in the display area AA.
  • Each light emitting unit 20 includes a first electrode 21 .
  • each light emitting unit 20 further includes a light emitting portion 22 and a second electrode 23 .
  • the first electrode 21 is an anode
  • the second electrode 23 is a cathode.
  • the light emitting part 22 may include at least an organic light emitting layer.
  • the plurality of light emitting units 20 are arranged in rows along the first direction, and arranged in columns along the second direction. In one embodiment, the first direction is perpendicular to the second direction.
  • a plurality of first pixel circuit units 30 are arranged in an array and located in the display area AA.
  • Each first pixel circuit unit 30 includes a plurality of first pixel circuits 31 .
  • a plurality of first pixel circuits 31 are arranged in an array, arranged in rows along the first direction, and arranged in columns along the second direction, and each first pixel circuit 31 is electrically connected to a light emitting unit 20, so that the The light emitting unit 20 emits light.
  • at least one first pixel circuit 31 is electrically connected to the first electrode 21 of the corresponding light emitting unit 20 .
  • a plurality of second pixel circuit units 40 are disposed in the display area AA.
  • Each second pixel circuit unit 40 includes a plurality of second pixel circuits 41 .
  • the plurality of second pixel circuits 41 are arranged in an array, arranged in rows along the first direction, and arranged in columns along the second direction. At least one second pixel circuit 41 is configured to be electrically connected to a light emitting unit 20 to make the light emitting unit 20 emit light. Specifically, at least one second pixel circuit 41 is electrically connected to the first electrode 21 of the corresponding light emitting unit 20 . In some embodiments, any light emitting unit 20 among the plurality of light emitting units 20 in the display panel 100 is configured to be electrically connected to a first pixel circuit 31 or a second pixel circuit 41 .
  • the first pixel circuit unit 30 and the second pixel circuit 41 are arranged side by side on the same plane perpendicular to the third direction, and the plurality of light-emitting units 20 are entirely located between the first pixel circuit unit 30 and the second pixel circuit 41 above.
  • both the first pixel circuit 31 and the second pixel circuit 41 include thin film transistors.
  • the thin film transistor has a current output terminal, and the current output terminal is electrically connected to the first electrode 21 of the light emitting unit 20 .
  • the TFTs in the first pixel circuit 31 and the second pixel circuit 41 both include a source 311 , a drain 312 , a gate 313 and a semiconductor layer 314 .
  • the source 311 and the drain 312 are arranged at intervals, and are electrically connected to the semiconductor layer 314 respectively.
  • the gate 312 is disposed opposite to the semiconductor layer 314 in the third direction and is electrically insulated.
  • the thin film transistor is a P-type transistor, and the first electrode 21 of the light emitting unit 20 is connected to the drain 312 . In other embodiments, the thin film transistor is an N-type transistor, and the first electrode 21 of the light emitting unit 20 is connected to the source 311 .
  • the display panel 100 further includes a plurality of gate lines 50 and a plurality of data lines 60 disposed on the substrate 10 .
  • Each gate line 50 extends along the first direction, and a plurality of gate lines 50 are arranged at intervals along the second direction.
  • Each data line 60 extends along the second direction, and a plurality of data lines 60 are arranged at intervals along the first direction.
  • a plurality of gate lines 50 intersect with a plurality of data lines 60 to define and form a plurality of pixel regions.
  • Both the first direction and the second direction are parallel to the base 10 .
  • the first direction is perpendicular to the second direction.
  • each first pixel circuit 31 is correspondingly disposed in a pixel area.
  • Each second pixel circuit 41 is correspondingly disposed in another pixel region.
  • the plurality of first pixel circuit units 30 in the embodiment of the present application are arranged in an array, between any two adjacent rows of first pixel circuit units 30 and/or between any adjacent two columns of first pixel circuit units 30 A first placement gap CC1 is formed.
  • the plurality of first pixel circuit units 30 are arranged in rows along the first direction, and arranged in columns along the second direction.
  • the distance between the orthographic projections of any two adjacent first pixel circuits 31 on the substrate 10 is smaller than the size of the first placement gap CC1 . In this way, it is beneficial to make the display panel 100 have a larger size of the first placement gap CC1.
  • the size of the placement gap between the two pixel circuits is the size of the placement gap in the first direction.
  • the size of the placement gap between the two pixel circuits is the size of the placement gap in the second direction. That is to say, not all pixel circuits in the display panel 100 are arranged at equal intervals, and the distance between two adjacent first pixel circuits 31 located in different first pixel circuit units 30 is greater than that in the same first pixel circuit unit 30 . The distance between two adjacent first pixel circuits 31.
  • all the first pixel circuits 31 located in the same first pixel circuit unit 30 are equally spaced.
  • a regular arrangement of a plurality of first pixel circuit units 30 is planned, so that two adjacent first pixel circuit units 30 in each first pixel circuit unit 30
  • the spacing between a pixel circuit 31 is reduced, and the spacing between any two adjacent rows and/or two columns of first pixel circuit units 30 (ie, the first placement gap CC1) is correspondingly increased.
  • the increased spacing It can be used to set other materials or elements, such as virtual pixel circuits, etc., thereby improving the display stability of the display panel 100 .
  • the orthographic projection of each first pixel circuit unit 30 on the substrate 10 forms a first projected area BB1
  • the first electrodes 21 of the plurality of light emitting units 20 corresponding to the first pixel circuit unit 30 are in the
  • the orthographic projection of the substrate 10 forms a second projected area, and the second projected area is located within the first projected area BB1.
  • the first projection area BB1 includes the orthographic projection area of the gap between two adjacent first pixel circuits 31 on the substrate 10 .
  • the orthographic projection of each second pixel circuit unit 40 on the substrate 10 forms a third projection area BB2, and the orthographic projection of the first electrodes 21 of the plurality of light emitting units 20 corresponding to the second pixel circuit unit 40 on the substrate 10 forms a fourth projection area BB2.
  • the fourth projection area does not overlap or only partially overlaps with the third projection area BB2.
  • the third projection area BB2 includes the orthographic projection area of the gap between two adjacent second pixel circuits 41 on the substrate 10 .
  • connection lines between it and the corresponding light-emitting unit are changed.
  • the line process may become complicated and may affect the stability of the display.
  • the first pixel circuit 31 in the first pixel circuit unit 30 and the corresponding light emitting unit 20 can basically keep the size of the first pixel circuit 31
  • the relative position with the light emitting unit 20 when not reduced does not need to change the connection line.
  • the position of the first pixel circuit 31 may substantially correspond to the position of the light emitting unit 20 electrically connected to it in the third direction.
  • the orthographic projections of the substrate 10 are at least partially overlapping.
  • the fourth projection area and the third projection area BB2 only partially overlap or do not overlap, so the second pixel circuit 41 of the second pixel circuit unit 40 and the corresponding light emitting unit 20 do not maintain the size of the second pixel circuit 41 without reducing
  • the relative position of the light-emitting unit 20 and the connection line are also changed accordingly, so as to meet the requirement of reducing the size of the pixel circuit due to the narrow frame.
  • the positions of at least part of the second pixel circuits 41 do not correspond to the positions of the light emitting units 20 electrically connected to them in the third direction, for example, at least part of the plurality of second pixel circuits 41 are projected on the substrate 10 There is no overlap with the orthographic projection of the corresponding light emitting unit 20 on the substrate 10 at all.
  • the pixel circuit is reduced. The number of connection lines that need to be changed simplifies the line process, thereby improving the stability of the display.
  • each first pixel circuit 31 Since the size of each first pixel circuit 31 is reduced, in order to gather a plurality of first pixel circuits 31 to form the first pixel circuit unit 30 , the distance between two adjacent first pixel circuits 31 must be shortened. Therefore, when two adjacent first pixel circuits 31 with reduced sizes are brought close to each other, there will be a slight deviation in the third direction between the position of at least part or all of the first pixel circuits 31 and the position of the corresponding light emitting unit 20 , but the slight deviation is within the controllable range.
  • the display panel 100 further includes a transfer metal layer 65 , and the transfer metal layer 65 is located between the plurality of second pixel circuits 41 and the corresponding first electrodes 21 of the plurality of light emitting units 20 . At least part of the second pixel circuits 41 are electrically connected to the first electrodes 21 of the corresponding light emitting units 20 through the transfer metal layer 65 .
  • the transfer metal layer 65 is located between the planarization layer 78 and the source-drain layer 73 . More specifically, the transfer metal layer 65 is connected to the source-drain layer 73 through the via hole opened in the passivation layer 76 .
  • the display area AA includes a first display area AA1 and a second display area AA2 located between the first display area AA1 and the frame area FA.
  • a plurality of first pixel circuit units 30 are disposed in the first display area AA1
  • a plurality of second pixel circuit units 40 are disposed in the second display area AA2 .
  • the driving circuit 55 is partially disposed in the display area, such as the second display area AA2, and is located at the edge of the display area AA. Setting the position of the second pixel circuit unit 40 closer to the frame area FA than the position of the first pixel circuit unit 30 can limit the relative position change between the pixel circuit and the light emitting unit 20 to the second pixel circuit as much as possible.
  • the units 40 can further form the first placement spaces CC1 regularly between the first pixel circuit units 30 .
  • the display panel 100 includes a driving circuit 55 .
  • the driving circuit 55 is disposed on the substrate 10 , and at least part of the driving circuit 55 is disposed in the display area AA, such as the second display area AA2 .
  • the driving circuit 55 can be electrically connected with the first pixel circuit 31 and the second pixel circuit 41 to provide a driving signal.
  • the drive circuit 55 includes a switch circuit, a gate drive circuit and a light emission control circuit.
  • the switch circuit is electrically connected to the first pixel circuit 31 and the second pixel circuit 41 through the data line 60 .
  • each data line 60 is electrically connected to all first pixel circuits 31 or all second pixel circuits 41 corresponding to the same column.
  • the gate drive circuit is electrically connected to the first pixel circuit 31 and the second pixel circuit 41 through the scan lines of the gate lines 50 for providing gate drive signals.
  • each gate line 50 is electrically connected to all first pixel circuits 31 or all second pixel circuits 41 corresponding to the same row.
  • the light emission control circuit may also be electrically connected to the first pixel circuit 31 and the second pixel circuit 41 through the light emission control line in the gate line 50 for providing a light emission signal.
  • the light emission control circuit and the gate driving circuit are distributed on opposite sides of the gate line 50 along the second direction.
  • the pixel circuit is used to provide the data signal from the data line 60 to the light emitting unit 20 in response to the gate driving signal from the gate line 50, so as to control the light emission of each light emitting unit 20, or control the brightness of each light emitting unit 20 .
  • the orthographic projection of the driving circuit 55 disposed in the display area AA on the substrate 10 forms a fifth projection area
  • the fifth projection area is located on the side of the third projection area BB2 away from the first projection area BB1
  • the four projection areas partially overlap.
  • the driving circuit 55 can be closed under the light-emitting unit 20 of the display area AA near the edge of the frame area FA, thereby reducing the size of the frame.
  • the display panel 100 further includes a power line electrically connected to at least one of the first pixel circuit 31 , the second pixel circuit 41 and the light emitting unit 20 to provide a voltage signal.
  • the power line of the present application can be arranged in the display area AA or the frame area FA.
  • the power cord may include at least one of a first power cord, a second power cord, and a third power cord.
  • the first power line is used to provide a low voltage signal (VDD)
  • the second power line is used to provide a high voltage signal (VSS)
  • the third power line is used to provide a reference voltage signal (Vref).
  • the first power line VDD is electrically connected to the first pixel circuit 31 and the second pixel circuit 41 in the display area AA to apply a voltage to the first electrode 21 of the light emitting unit 20 .
  • the second power line VSS is electrically connected to the second electrode 23 of the light emitting unit 20 in the frame area FA to apply a voltage to the second electrode 23 .
  • the third power line Vref is electrically connected to the first pixel circuit 31 and the second pixel circuit 41 in the display area AA.
  • the display panel 100 further includes a first dummy pixel circuit 68, the first dummy pixel circuit 68 is set in the display area AA, and specifically in the first placement gap CC1, and The first pixel circuit unit 30 and the second pixel circuit unit 40 are arranged in the same layer.
  • the first dummy pixel circuit 68 is electrically connected to the power line.
  • the first dummy pixel circuit 68 may be electrically connected to at least one or any combination of the first power line VDD, the second power line VSS and the third power line Vref among the power lines. When electrically connected with any combination thereof, the connections can be made according to certain rules.
  • the obvious voltage drop (IR Drop) generated on the longer power supply line can be compensated by increasing the transmission line, so that the plurality of first pixel circuits 31 and The voltages obtained by the second pixel circuits 41 are the same, and the driving currents provided to the respective light emitting units 20 are consistent, so that the luminous brightness of the display panel 100 is uniform, and the display uniformity of the display panel 100 is improved.
  • the first dummy pixel circuit 68 can be concentratedly placed in the first placement gap CC1 , which can simplify the connection between the first dummy pixel circuit 68 and the power line.
  • a plurality of light-emitting units 20 are arranged in four rows and two columns according to small squares of the same size, and a plurality of first pixel circuits 31 in the corresponding first pixel circuit unit 30 also use small squares of the same size.
  • the grid is arranged in 5 rows and 2.5 columns, therefore, the extra row and 0.5 column in the first pixel circuit unit 30 is the area where the first dummy pixel circuit 68 can be placed.
  • the first dummy pixel circuit 68 includes a plurality of first sub-dummy pixel circuits 681 connected to each other.
  • the pattern and shape of the first sub-dummy pixel circuits 681 are similar to those of the first pixel circuit 31 or
  • the patterns and shapes of the second pixel circuits 41 are the same.
  • the first sub-dummy pixel circuit 681 can be formed synchronously with the first pixel circuit 31 or the second pixel circuit 41 , thus reducing the manufacturing difficulty of the first dummy pixel circuit 68 and simplifying the process flow of the display panel 100 .
  • the display area AA can also avoid problems such as display bright marks or dark marks (mura) and poor optical fringes caused by differences in circuit design.
  • the first sub-dummy pixel circuit 681 may include a non-metal layer 6811 , a first metal layer 6812 and a second metal layer 6813 stacked along the third direction.
  • the display panel 100 may include an array layer 70 , a passivation layer 76 , a planarization layer 78 and a light emitting element layer 80 sequentially stacked on the substrate 10 along the third direction.
  • the array layer 70 includes an active layer 71 , a gate layer 72 and a source-drain layer 73 .
  • the array layer 70 further includes a first insulating layer 74 disposed between the active layer 71 and the gate layer 72 , and a second insulating layer 75 disposed between the gate layer 72 and the source-drain layer 73 .
  • the light emitting device layer 80 includes a first electrode layer 81 , a light emitting layer 82 and a second electrode layer 83 .
  • the source-drain layer 73 is formed with the source 311 and the drain 312 of the thin film transistors of the first pixel circuit 31 and the second pixel circuit 41
  • the active layer 71 is formed with the electrodes of the first pixel circuit 31 and the second pixel circuit 41
  • the semiconductor layer 314 of the thin film transistor, the gate layer 72 is formed with the gate 313 of the thin film transistor of the first pixel circuit 31 and the second pixel circuit 41 .
  • the first electrode layer 81 forms the first electrode 21 of the light emitting unit 20
  • the light emitting layer 82 forms the light emitting portion 22 of the light emitting unit 20
  • the second electrode layer 83 forms the second electrode 23 of the light emitting unit 20 .
  • the non-metal layer 6811 is disposed on the same layer as the active layer 71 , and the pattern and shape of the non-metal layer 6811 are the same as those of the first pixel circuit 31 or the second pixel circuit 41 in the active layer 71 .
  • the non-metallic layer 6811 includes a dummy semiconductor layer, which is arranged in the same layer as the semiconductor layer 314 of the thin film transistors of the first pixel circuit 31 and the second pixel circuit 41 and has the same pattern and shape respectively.
  • the first metal layer 6812 is provided on the same layer as the gate layer 72 , and the pattern and shape of the first metal layer 6812 are the same as those of the first pixel circuit 31 and the second pixel circuit 41 on the gate layer 72 respectively.
  • the first metal layer 6812 includes a dummy gate, which is arranged on the same layer as the gates 313 of the thin film transistors of the first pixel circuit 31 and the second pixel circuit 41 and has the same pattern and shape.
  • the second metal layer 6813 is provided on the same layer as the source and drain layer 73 , and the pattern and shape of the second metal layer 6813 are the same as those of the first pixel circuit 31 and the second pixel circuit 41 in the source and drain layer 73 respectively.
  • the second metal layer 6813 may include a dummy source and a dummy drain, which are respectively arranged on the same layer as the source 311 and drain 312 of the thin film transistors of the first pixel circuit 31 and the second pixel circuit 41 and patterned The same as the shape respectively.
  • the non-metal layer 6811 , the first metal layer 6812 and the second metal layer 6813 are connected to each other along the third direction. Specifically, via holes can be opened on the first insulating layer 74 and the second insulating layer 75 to connect the three.
  • the non-metal layer 6811 may also be connected to the first metal layer 6812 , or the first metal layer 6812 may be connected to the second metal layer 6813 , or the non-metal layer 6811 may be connected to the second metal layer 6813 .
  • the first sub-dummy pixel circuit 681 may also include only one of the non-metallic layer 6811 , the first metal layer 6812 and the second metal layer 6813 or any combination thereof, which is not limited here.
  • the first dummy pixel circuit 681 is not electrically connected to any light emitting unit 20 .
  • an isolation can be made on the non-metal layer 6811 to separate it into two independent and mutually insulated parts, for example, to separate the dummy semiconductor layer into two independent and mutually insulated parts.
  • the two independent and mutually insulated parts can be respectively connected to the virtual source and the virtual drain of the second metal layer 6813 through via holes in the first insulating layer 74 and the second insulating layer 75 .
  • At least one of the dummy source and dummy drain of the second metal layer 6813 may not be connected to the non-metal layer 6811, specifically, by canceling the first insulating layer 74 and the second insulating layer 74 The corresponding via implementation of layer 75 .
  • the wiring of the first dummy pixel circuits 68 is in a grid shape.
  • the wiring shape of at least part of the first dummy pixel circuits 68 matches the wiring shape of the plurality of gate lines 50 and the plurality of data lines 60 .
  • the first dummy pixel circuit 68 includes multiple first metal wires 682 parallel to the gate lines 50 and multiple second metal wires 683 parallel to the data lines 60, and the multiple first metal wires 682 and A plurality of second metal traces 683 intersect to form a grid structure. More specifically, the first metal trace 682 is parallel to the second direction, and the second metal trace 683 is parallel to the first direction.
  • the extending direction of the first metal wire 682 is the same as that of the gate line 50
  • the extending direction of the second metal wire 683 is the same as that of the data line 60 . Since the first metal wiring 682 and the second metal wiring 683 are to be electrically connected to the power supply line, which are different from the signal sources of the gate line 50 and the data line 60, therefore, in order to distinguish the two, the first metal wiring 682 and the second metal wiring 683 can be provided.
  • the second metal wiring 683 is in a different layer from the gate line 50 and the data line 60 .
  • the first metal trace 682 includes one of the first metal layer 6812 and the second metal layer 6813
  • the second metal trace 683 includes the other of the first metal layer 6812 and the second metal layer 6813.
  • each first metal trace 682 may be formed by sequentially connecting one of a plurality of first metal layers 6812 and a plurality of second metal layers 6813 arranged in rows along the first direction
  • each second metal trace 683 It may be formed by sequentially connecting the other of the plurality of first metal layers 6812 and the plurality of second metal layers 6813 arranged along the second direction.
  • the first placement gap CC1 of the display panel 100 includes a first sub-placement gap located between two first pixel circuit units 30 adjacent along the first direction, and a first sub-placement gap located between two adjacent first pixel circuit units 30 along the second direction.
  • the second sub-placement gap between the first pixel circuit units 30.
  • the size of the first sub-placing gap is different from the size of the second sub-placing gap. Different gaps with different settings can meet routing requirements of different sizes, quantities, or shapes.
  • a second placement gap CC2 is formed between adjacent first pixel circuit units 30 and second pixel circuit units 40 .
  • the size CC1 of the first placement gap is equal to the size of the second placement gap CC2. In this way, the size of the gap between the pixel circuit units in the entire display panel can be kept consistent, which is beneficial to optimize the display effect of the screen.
  • the display panel 100 further includes a second dummy pixel circuit, the second dummy pixel circuit is arranged between two adjacent second pixel circuit units 40, and is electrically connected to the power line .
  • the plurality of second pixel circuit units 40 are located on one side of the plurality of first pixel circuit units 30 in the first direction, and the plurality of second pixel circuit units 40 are arranged in a row along the second direction.
  • a third placement gap CC3 is formed between any two adjacent second pixel circuit units 40 in the second direction. All the first placement gaps CC1 between any two adjacent columns of the first pixel circuit units 30 communicate with each other, and communicate with each other with the corresponding third placement gaps CC3 . Further, the second dummy pixel circuit is disposed in the third placement gap CC3.
  • the plurality of second pixel circuit units 40 are located on one side of the plurality of first pixel circuit units 30 in the second direction, and the plurality of second pixel circuit units 40 are arranged in rows along the first direction .
  • a fourth placement gap is formed between any two adjacent second pixel circuit units 40 in the first direction. All the first placement gaps CC1 between any two adjacent rows of first pixel circuit units 30 communicate with each other, and communicate with each other along the corresponding fourth placement gaps. Further, the second dummy pixel circuit is disposed in the fourth placement gap CC4.
  • the arrangement of the plurality of second pixel circuit units 40 may also be a combination of the above two methods, and the display panel 100 includes a plurality of second pixel circuit units arranged in columns along the second direction. 40, also includes a plurality of second pixel circuit units 40 arranged in rows along the first direction, which is not limited here. In this way, it can be avoided that the connection relationship between the first placement gap CC1, the third placement gap CC3, and the fourth placement gap is complicated, resulting in a complicated connection relationship between the first dummy pixel circuit 68 and the second dummy pixel circuit, resulting in wiring complex.
  • a plurality of second pixel circuit units 40 may also be arranged in a row, and the third placement gap CC3 or the fourth placement gap formed between two adjacent second pixel circuit units 40 is cancelled. No limitation is imposed here.
  • the distance between the orthographic projections of any two adjacent second pixel circuits 41 on the substrate 10 is smaller than the size of the third placement gap CC3 or the fourth placement gap.
  • first dummy pixel circuit 68 and the second dummy pixel circuit may be connected at the connection between the first placement gap CC1 and the third placement gap CC3 or the fourth placement gap.
  • the wiring end of the power line is the binding area of the frame area FA
  • two adjacent second pixel circuits A third placement gap CC3 or a fourth placement gap is formed between the circuit units 40, and the second dummy pixel circuit and the first dummy pixel circuit are connected at the connection between the third placement gap CC3 or the fourth placement gap and the first placement gap CC1.
  • the circuit 68 is electrically connected, therefore, the second dummy pixel circuit does not need to bypass the concentrated second pixel circuit unit 40 to the frame area FA, which simplifies the wiring path.
  • the second dummy pixel circuit includes a plurality of second sub-dummy pixel circuits connected to each other, and the structural form, arrangement of film layers, and connection relationship with other components of the second sub-dummy pixel circuit can all be the same as those of the first sub-dummy pixel circuit.
  • a dummy pixel circuit is the same and will not be repeated here.
  • an embodiment of the present application further provides a display device, including the above-mentioned display panel 100 .
  • the display device can be applied to fields such as mobile phone terminals, bionic electronics, electronic skins, wearable devices, vehicle-mounted devices, Internet of Things devices, and artificial intelligence devices.
  • the display terminal may be a digital device such as a mobile phone, a tablet, a handheld computer, an ipod, or a smart watch.

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Abstract

本申请涉及一种显示面板及显示设备，显示面板包括基底、阵列排布的多个发光单元、多个第一像素电路单元以及多个第二像素电路单元。所述基底包括显示区和至少部分围绕显示区的边框区。所述多个发光单元设于显示区。每一发光单元包括第一电极。所述多个第一像素电路单元呈阵列排布并设于显示区。每一第一像素电路单元包括多个第一像素电路。所述多个第一像素电路呈阵列排布，且至少一个第一像素电路与一对应的发光单元的第一电极电连接。所述多个第二像素电路单元设于显示区。每一第二像素电路单元包括多个第二像素电路。所述多个第二像素电路呈阵列排布，且至少一个第二像素电路与一对应的发光单元的第一电极电连接。任意相邻的两个第一像素电路单元之间形成第一放置间隙。

Description

显示面板及显示设备
相关申请
本申请要求2022年1月28日申请的，申请号为202210108272.8，名称为“显示面板及显示设备”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示面板及显示设备。
背景技术
随着显示屏技术的发展，为了在有限空间最大化显示区域，提出了窄边框显示技术。
通常，受限于边框区的驱动电路的布置要求，并且柔性屏可能还受到折弯工艺的限制，导致屏体的边框无法进一步地做小，故市面上提出了将部分驱动电路设置于显示区内以减小边框尺寸的技术，但这造成了显示区内像素电路的改变，进而影响了屏体的显示稳定性。
发明内容
基于此，有必要提供一种显示面板及显示设备。
根据本申请的一个方面，提供一种显示面板，包括基底、阵列排布的多个发光单元、多个第一像素电路单元以及多个第二像素电路单元。所述基底包括显示区和至少部分围绕显示区的边框区。所述多个发光单元设于显示区。每一发光单元包括第一电极。所述多个第一像素电路单元呈阵列排布并设于显示区。每一第一像素电路单元包括多个第一像素电路。所述多个第一像素电路呈阵列排布，且至少一个第一像素电路与一对应的发光单元的第一电极电连接。所述多个第二像素电路单元设于显示区。每一第二像素电路单元包括多个第二像素电路。所述多个第二像素电路呈阵列排布，且至少一个第二像素电路与一对应的发光单元的第一电极电连接。任意相邻的两个第一像素电路单元之间形成第一放置间隙。
根据本申请的又一方面，提供一种显示设备，包括上述的显示面板。
上述显示设备，通过对多个第一像素电路进行布置，以规划出具有规律的多个第一像素电路单元的排布，使得每一第一像素电路单元中的相邻两个第一像素电路之间的间距减小，而任意相邻两个第一像素电路单元之间的间距对应增大，故该增大的间距，能够满足添加其他材料的要求，进而提升了显示面板的显示稳定性。
附图说明
图1为本申请一实施例中的显示面板的正面结构示意图。
图2为本申请一实施例中的显示面板中的部分结构的正面结构示意图。
图3为本申请一实施例中的显示面板的部分结构的截面结构示意图。
图4为本申请一实施例中的显示面板的发光单元与像素电路单元连接的平面示意图。
图5为本申请一实施例中的显示面板中的部分走线的示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
本申请中将垂直于显示面板的显示面的方向定义为第三方向，将平行于显示面且相交的两个方向定义为第一方向与第二方向。第三方向同时也是显示面板及其基底的厚度方向，以及由基底指向发光单元的方向。
为了减小边框尺寸，可以将原本位于显示面板的边框区的驱动电路部分设置于显示区内。
显示面板的显示区中，像素电路与发光单元电连接，用于使发光单元发光。像素电路与发光单元之间通常在垂直于显示面板的显示面的方向即第三方向上一一对应。为了使驱动电路设置在显示区内，而又不影响显示区的尺寸，可以在维持原来发光单元的尺寸的同时缩小原来像素电路的尺寸，进而能够在靠近边框区的区域下方留出放置驱动电路的空间，从而可以减小边框区的尺寸。
在此基础上，经发明人研究发现，虽然缩小像素电路尺寸所获得的显示区的空间能够满足在显示区内的放置驱动电路的需求，但使得对应的相邻两个像素电路之间的间距增大，从而对显示的稳定性造成了一定影响。当显示区内所有像素电路均等间隔设置，相邻的两个像素电路之间的间距虽然增大，但该增大的间距却不足以用于设置其他材料或元件，进而无法提升显示稳定性。
因此，有必要提供一种能够提升显示稳定性的显示面板及显示设备。参阅图1至图4，本申请至少一实施例中的显示面板100，包括基底10、多个发光单元20、多个第一像素电路单元30及多个第二像素电路单元40。基底10包括显示区AA和至少部分围绕显示区的边框区FA，显示面板100在显示过程中，其可在显示区AA内进行图像显示，而在边框区 FA内不显示图像。
多个发光单元20呈阵列排布，并设于显示区AA。每一发光单元20包括第一电极21。进一步地，每一发光单元20还包括发光部22及第二电极23。在本申请的实施例中，第一电极21为阳极，第二电极23为阴极。发光部22可以至少包括有机发光层。在一实施例中，多个发光单元20沿第一方向排布呈行，且沿第二方向排布呈列。在一实施例中，第一方向与第二方向垂直。
多个第一像素电路单元30呈阵列排布，并设于显示区AA。每一第一像素电路单元30包括多个第一像素电路31。多个第一像素电路31呈阵列排布，沿第一方向排布呈行，且沿第二方向排布呈列，且每一第一像素电路31与一发光单元20电连接，以使该发光单元20发光。具体的，至少一个第一像素电路31与其对应的发光单元20的第一电极21电连接。多个第二像素电路单元40设于显示区AA。每一第二像素电路单元40包括多个第二像素电路41。多个第二像素电路41呈阵列排布，沿第一方向排布呈行，且沿第二方向排布呈列。至少一个第二像素电路41被配置为与一发光单元20电连接，以使该发光单元20发光。具体的，至少一个第二像素电路41与其对应的发光单元20的第一电极21电连接。在一些实施例中，显示面板100中的多个发光单元20中的任一发光单元20被配置为与一个第一像素电路31或一个第二像素电路41电连接。在一些实施例中，第一像素电路单元30及第二像素电路41并列设置在垂直于第三方向的同一平面，多个发光单元20整体位于第一像素电路单元30及第二像素电路41的上方。
具体地，第一像素电路31和第二像素电路41均包括薄膜晶体管。薄膜晶体管具有电流输出端，该电流输出端与发光单元20的第一电极21电连接。更具体地，第一像素电路31和第二像素电路41中的薄膜晶体管均包括源极311、漏极312、栅极313及半导体层314。源极311和漏极312间隔设置，并分别与半导体层314电连接。栅极312与半导体层314在第三方向相对设置并电绝缘。在一些实施方式中，薄膜晶体管为P型晶体管，发光单元20的第一电极21与漏极312相连。在另一些实施方式中，薄膜晶体管为N型晶体管，发光单元20的第一电极21与源极311相连。
请一并参阅图5，在本申请的实施例中，显示面板100还包括设于基底10上的多根栅线50和多根数据线60。每一栅线50沿第一方向延伸，且多根栅线50沿第二方向间隔排布。每一数据线60沿第二方向延伸，且多根数据线60沿第一方向间隔排布。多根栅线50与多根数据线60交叉以界定形成多个像素区域。第一方向及第二方向均平行于基底10设置。在一实施例中，第一方向与第二方向垂直。请一并参阅图2至图5，每一第一像素电路31对应设于一像素区域内。每一第二像素电路41对应设于另一像素区域内。
本申请实施例中的多个第一像素电路单元30呈阵列排布，任意相邻的两行第一像素电路单元30之间和/或任意相邻的两列第一像素电路单元30之间形成第一放置间隙CC1。在一实施例中，多个第一像素电路单元30沿第一方向排布呈行，且沿第二方向排布呈列。
在本申请的实施例中，在同一第一像素电路单元30中，任意相邻的两个第一像素电路31在基底10的正投影之间的间距，小于第一放置间隙CC1的尺寸。如此，可有利于使显示面板100具有较大的第一放置间隙CC1的尺寸。
可以理解，当两个像素电路在第一方向上相邻，位于该两个像素电路之间的放置间隙的尺寸为该放置间隙在第一方向上的尺寸。当两个像素电路在第二方向上相邻，位于该两个像素电路之间的放置间隙的尺寸为该放置间隙在第二方向上的尺寸。也就是说，显示面板100中的像素电路并非全部等间隔设置，分别位于不同的第一像素电路单元30的两个相邻的第一像素电路31的间距大于位于同一第一像素电路单元30中的两个相邻的第一像素电路31的间距。
在一些实施例中，位于同一第一像素电路单元30中的所有第一像素电路31为等间隔分布。
本申请实施例通过对多个第一像素电路31进行布置，以规划出具有规律的多个第一像素电路单元30的排布，使得每一第一像素电路单元30中的相邻两个第一像素电路31之间的间距减小，而任意相邻两行和/或两列第一像素电路单元30之间的间距(即第一放置间隙CC1)对应增大，该增大的间距，能够用于设置其他材料或元件，如虚拟的像素电路等，进而提升了显示面板100的显示稳定性。
在本申请的实施例中，每一第一像素电路单元30在基底10的正投影形成第一投影区域BB1，与该第一像素电路单元30对应的多个发光单元20的第一电极21在基底10的正投影形成第二投影区域，第二投影区域位于第一投影区域BB1内。第一投影区域BB1包括相邻两个第一像素电路31之间的间隙在基底10的正投影区域。
每一第二像素电路单元40在基底10的正投影形成第三投影区域BB2，与该第二像素电路单元40对应的多个发光单元20的第一电极21在基底10的正投影形成第四投影区域，第四投影区域与第三投影区域BB2不重叠或者仅部分重叠。第三投影区域BB2包括相邻两个第二像素电路41之间的间隙在基底10的正投影区域。
当像素电路的尺寸缩小时，其与对应的发光单元之间的连接线路发生改变，当大量的连接线路均发生改变时，可能使线路工艺变得复杂，并可能对显示的稳定性造成影响。
本申请实施例中，由于第二投影区域位于第一投影区域BB1内，故第一像素电路单元30内的第一像素电路31可与对应的发光单元20之间基本保持第一像素电路31尺寸未减 小时与发光单元20的相对位置，无需改变连接线路。在一些实施例中，第一像素电路31的位置可与其电连接的发光单元20的位置在第三方向上基本对应，例如，第一像素电路31在基底10的正投影与对应的发光单元20在基底10的正投影至少部分重叠。而第四投影区域与第三投影区域BB2仅部分重叠或者不重叠，故第二像素电路单元40的第二像素电路41与对应的发光单元20之间没有维持第二像素电路41尺寸未减小时与发光单元20的相对位置，连接线路也因此发生改变，以满足因窄边框带来的像素电路尺寸缩小的需求。在一些实施例中，至少部分第二像素电路41的位置与其电连接的发光单元20的位置在第三方向上不对应，例如，多个第二像素电路41中的至少部分在基底10的正投影与对应的发光单元20在基底10的正投影完全不重叠。本申请实施例的显示面板100，通过将像素电路划分成第一像素电路单元30和第二像素电路单元40，并将需要改变连接线路的像素电路限制在第二像素电路单元40，减小了需作改变的连接线路的数量，简化了线路工艺，进而提高了显示的稳定性。
由于每一第一像素电路31的尺寸减小，故为了集中多个第一像素电路31形成第一像素电路单元30，必然会拉近相邻的两个第一像素电路31之间的距离。故在使相邻的两个尺寸减小的第一像素电路31相互靠近的同时会使至少部分或者全部的第一像素电路31的位置与对应的发光单元20的位置在第三方向上存在少许偏差，但该少许偏差在可控范围内。
请再次参阅图3，在一些实施例中，由于在减小像素电路尺寸并改变相邻像素电路间距的同时，发光单元20的尺寸及排布方式不发生变化，故发光单元20与第二像素电路41的电流输出端在第三方向上存在错位。在一些实施例中，显示面板100还包括转接金属层65，转接金属层65位于多个第二像素电路41与对应的多个发光单元20的第一电极21之间。至少部分第二像素电路41通过转接金属层65与对应的发光单元20的第一电极21电连接。具体地，转接金属层65位于平坦化层78与源漏极层73之间。更具体地，转接金属层65与源漏极层73通过开设于钝化层76中的过孔连接。
在一实施例中，显示区AA包括第一显示区AA1和位于第一显示区AA1和边框区FA之间的第二显示区AA2。多个第一像素电路单元30设于第一显示区AA1，多个第二像素电路单元40设于第二显示区AA2。为减小边框尺寸，驱动电路55部分设置于显示区，如第二显示区AA2，并位于显示区AA的边缘。使第二像素电路单元40的位置相较第一像素电路单元30的位置更靠近边框区FA设置，能够将由此引起的像素电路与发光单元20相对位置的改变尽可能的局限于第二像素电路单元40，进而可以在第一像素电路单元30之间呈规律地形成第一放置空间CC1。
进一步地，显示面板100包括驱动电路55。驱动电路55设于基板10上，且至少部分驱动电路55设于显示区AA，如第二显示区AA2。驱动电路55能够与第一像素电路31和第二像素电路41电连接，以提供驱动信号。具体地，驱动电路55包括开关电路、栅极驱动电路和发光控制电路。
其中，开关电路通过数据线60与第一像素电路31和第二像素电路41电连接。具体地，每一数据线60与对应同一列的所有第一像素电路31或者所有第二像素电路41电连接。
栅极驱动电路通过栅线50中的扫描线与第一像素电路31和第二像素电路41电连接，用于提供栅极驱动信号。具体地，每一栅线50与对应同一行的所有第一像素电路31或者所有第二像素电路41电连接。
发光控制电路也可通过栅线50中的发光控制线与第一像素电路31和第二像素电路41电连接，用于提供发光信号。具体地，发光控制电路与栅极驱动电路沿第二方向分布于栅线50相对的两侧。
像素电路用于响应于来自栅线50的栅极驱动信号，将来自数据线60的数据信号提供至发光单元20，以控制每个发光单元20的发光，或者可以控制每个发光单元20的亮度。
在一些实施方式中，设于显示区AA的驱动电路55在基底10的正投影形成第五投影区域，第五投影区域位于第三投影区域BB2远离第一投影区域BB1的一侧，且与第四投影区域部分重叠。如此，可使得驱动电路55收至靠近边框区FA边缘的显示区AA的发光单元20的下方，进而缩小边框尺寸。
在一些实施例中，显示面板100还包括电源线，电源线与第一像素电路31、第二像素电路41及发光单元20中的至少一者电连接，以提供电压信号。
本申请的电源线可设于显示区AA或者边框区FA。在一些实施例中，电源线可以包括第一电源线、第二电源线和第三电源线中的至少一者。第一电源线用于提供低电压信号(VDD)，第二电源线用于提供高电压电压信号(VSS)，第三电源线用于提供参考电压信号(Vref)。具体地，第一电源线VDD与第一像素电路31及第二像素电路41在显示区AA内电连接，以施加电压至发光单元20的第一电极21。第二电源线VSS与发光单元20的第二电极23在边框区FA内电连接，以施加电压至第二电极23。第三电源线Vref与第一像素电路31及第二像素电路41在显示区AA内电连接。
请再次参阅图2和图3，在一些实施例中，显示面板100还包括第一虚拟像素电路68，第一虚拟像素电路68设于显示区AA，并具体设于第一放置间隙CC1，与第一像素电路单元30及第二像素电路单元40同层设置。第一虚拟像素电路68与电源线电连接。具体地， 第一虚拟像素电路68可与电源线中的第一电源线VDD、第二电源线VSS和第三电源线Vref中的至少一者或任意组合电连接。当与其中任意组合电连接时，可按照一定规律进行连接。
如此，通过设置与电源线连接的第一虚拟像素电路68，以增加输送线路的方式，弥补较长的电源线上产生的明显的电压降(IR Drop)，使得多个第一像素电路31和第二像素电路41获得的电压一致，而对各自的发光单元20提供的驱动电流一致，进而使得显示面板100的发光亮度均匀，提升了显示面板100的显示均一性。另外，第一虚拟像素电路68能够集中放置在第一放置间隙CC1，可使其与电源线之间的连接线路变得简单。
如图4所示，多个发光单元20按照同尺寸的小方格排列成4行2列，而对应的第一像素电路单元30中的多个第一像素电路31也使用相同尺寸的小方格排列成5行2.5列，因此，第一像素电路单元30中多出的1行和0.5列即为能够放置第一虚拟像素电路68的区域。
请再次参阅图3，在一些实施例中，第一虚拟像素电路68包括多个彼此相连的第一子虚拟像素电路681，第一子虚拟像素电路681的图案和形状与第一像素电路31或者第二像素电路41的图案和形状相同。如此，第一子虚拟像素电路681可与第一像素电路31或者第二像素电路41同步成形，故降低第一虚拟像素电路68的制作难度，简化了显示面板100的工艺流程。另外，也可使得显示区AA避免出现因电路设计差异导致的显示亮痕或暗痕(Mura)和光学条纹不良等问题。
具体地，第一子虚拟像素电路681可包括沿第三方向层叠设置的非金属层6811、第一金属层6812及第二金属层6813。
更具体地，显示面板100可包括沿第三方向依次层叠设置于基底10上的阵列层70、钝化层76、平坦化层78及发光元件层80。阵列层70包括有源层71、栅极层72和源漏极层73。阵列层70还包括设于有源层71与栅极层72之间的第一绝缘层74，以及设于栅极层72与源漏极层73之间的第二绝缘层75。发光元件层80包括第一电极层81、发光层82及第二电极层83。其中，源漏极层73形成有第一像素电路31和第二像素电路41的薄膜晶体管的源极311及漏极312，有源层71形成有第一像素电路31和第二像素电路41的薄膜晶体管的半导体层314，栅极层72形成有第一像素电路31和第二像素电路41的薄膜晶体管的栅极313。第一电极层81形成发光单元20的第一电极21，发光层82形成发光单元20的发光部22，第二电极层83形成发光单元20的第二电极23。
非金属层6811与有源层71同层设置，且非金属层6811的图案和形状与第一像素电路31或者第二像素电路41在有源层71的图案和形状分别相同。在一些实施例中，非金属层 6811包括虚拟半导体层，与第一像素电路31和第二像素电路41的薄膜晶体管的半导体层314同层设置且图案和形状分别相同。第一金属层6812与栅极层72同层设置，且第一金属层6812的图案和形状与第一像素电路31和第二像素电路41在栅极层72的图案和形状分别相同。在一些实施例中，第一金属层6812包括虚拟栅极，与第一像素电路31和第二像素电路41的薄膜晶体管的栅极313同层设置且图案和形状分别相同。第二金属层6813与源漏极层73同层设置，且第二金属层6813的图案和形状与第一像素电路31和第二像素电路41在源漏极层73的图案和形状分别相同。在一些实施例中，第二金属层6813可包括虚拟源极和虚拟漏极，分别与第一像素电路31和第二像素电路41的薄膜晶体管的源极311和漏极312同层设置且图案和形状分别相同。
在一些实施例中，非金属层6811、第一金属层6812及第二金属层6813之间沿第三方向彼此相连。具体地，可在第一绝缘层74和第二绝缘层75上开设过孔，以使三者相连。在其他实施方式中，也可以是非金属层6811与第一金属层6812相连，或者第一金属层6812与第二金属层6813相连，或者非金属层6811与第二金属层6813相连。
在一些实施例中，第一子虚拟像素电路681也可仅包括非金属层6811、第一金属层6812及第二金属层6813中的一者或者任意两者的组合，在此不作限制。
由于第一虚拟像素电路68不需要具有驱动发光单元20的功能，因此，第一虚拟像素电路681不与任何发光单元20电连接。在一些实施例中，可在非金属层6811上作隔断，以使其分隔成两个独立的且相互绝缘的部分，例如将虚拟半导体层分隔成两个独立的且相互绝缘的部分。该两个独立的且相互绝缘的部分可分别与第二金属层6813的虚拟源极和虚拟漏极通过第一绝缘层74和第二绝缘层75中的过孔相连。
在另一些实施例中，也可使第二金属层6813的虚拟源极和虚拟漏极中的至少一个不与非金属层6811相连，具体地，可通过取消第一绝缘层74和第二绝缘层75的对应的过孔实现。
如图5所示，在一些实施例中，至少部分第一虚拟像素电路68的布线形状呈网格状。具体地，至少部分第一虚拟像素电路68的布线形状与多条栅线50及多条数据线60的布线形状相吻合。如此，可达到降低电压降的效果，且能优化屏体显示效果。具体地，第一虚拟像素电路68包括与栅线50平行的多条第一金属走线682和与数据线60平行的多条第二金属走线683，且多条第一金属走线682与多条第二金属走线683相交以形成网格结构。更具体地，第一金属走线682与第二方向平行，第二金属走线683与第一方向平行。
在一实施方式中，第一金属走线682的延伸方向与栅线50的延伸方向相同，第二金属走线683的延伸方向与数据线60的延伸方向相同。由于第一金属走线682、第二金属走 线683要与电源线电连接，与栅线50及数据线60的信号源不同，因此，为了区分两者，可设置第一金属走线682及第二金属走线683与栅线50及数据线60不同层。
在一些实施例中，第一金属走线682包括第一金属层6812及第二金属层6813其中之一，第二金属走线683包括第一金属层6812及第二金属层6813其中之另一。具体地，每一第一金属走线682可由沿第一方向排列呈行的多个第一金属层6812及多个第二金属层6813其中之一依次相连形成，每一第二金属走线683可由沿第二方向排布呈列的多个第一金属层6812及多个第二金属层6813其中之另一依次相连形成。
一些实施例中，显示面板100的第一放置间隙CC1包括位于沿第一方向相邻的两个第一像素电路单元30之间的第一子放置间隙，以及位于沿第二方向相邻的两个第一像素电路单元30之间的第二子放置间隙。第一子放置间隙的尺寸与第二子放置间隙的尺寸相异。相异设置的不同的间隙能够满足不同尺寸、数量或形态等的走线需求。
一些实施例中，相邻的第一像素电路单元30与第二像素电路单元40之间形成有第二放置间隙CC2。通过设置第二放置间隙CC2，能够使第一像素电路单元30与第二像素电路单元40之间也能够用于设置其他材料，进而提升了显示面板100的显示稳定性。在一实施例中，第一放置间隙的尺寸CC1等于第二放置间隙CC2的尺寸。如此，可使得整个显示面板中的各像素电路单元之间的间隙尺寸保持一致，有利于优化屏体显示效果。
请再次参阅图2，在一些实施例中，显示面板100还包括第二虚拟像素电路，第二虚拟像素电路设于相邻的两个第二像素电路单元40之间，且与电源线电连接。
在一实施例中，多个第二像素电路单元40位于多个第一像素电路单元30在第一方向上的一侧，且多个第二像素电路单元40沿第二方向排布呈列。在第二方向上任意相邻两个第二像素电路单元40之间形成第三放置间隙CC3。任意相邻的两列第一像素电路单元30之间的所有第一放置间隙CC1彼此连通，且与对应的第三放置间隙CC3彼此连通。进一步地，第二虚拟像素电路设于第三放置间隙CC3内。
在另一些实施例中，多个第二像素电路单元40位于多个第一像素电路单元30在第二方向上的一侧，且多个第二像素电路单元40沿第一方向排布呈行。在第一方向上任意相邻两个第二像素电路单元40之间形成第四放置间隙。任意相邻的两行第一像素电路单元30之间的所有第一放置间隙CC1彼此连通，且与对应的第四放置间隙沿彼此连通。进一步地，第二虚拟像素电路设于第四放置间隙CC4内。
在其他实施例中，多个第二像素电路单元40的排布方式也可以是上述两种方式的组合形式，显示面板100既包括沿第二方向排布呈列的多个第二像素电路单元40，也包括沿第一方向排布呈行的多个第二像素电路单元40，在此不作限制。如此，可避免第一放置间 隙CC1与第三放置间隙CC3和第四放置间隙之间连通关系复杂，而造成第一虚拟像素电路68与第二虚拟像素电路之间的连接关系复杂，造成走线复杂。
当然，在其他实施例中，也可设置多个第二像素电路单元40连续排布，而取消相邻两个第二像素电路单元40之间形成的第三放置间隙CC3或者第四放置间隙，在此不作限制。
在同一第二像素电路单元40中，任意相邻的两个第二像素电路41在基底10的正投影之间的间距，小于第三放置间隙CC3或者第四放置间隙的尺寸。
更进一步地，第一虚拟像素电路68与第二虚拟像素电路可在第一放置间隙CC1与第三放置间隙CC3或者第四放置间隙的连通处相连。如此，由于电源线的走线末端是边框区FA的绑定区，故为了避免第一虚拟像素电路68的走线受到集中的第二像素电路单元40的干扰，在相邻两个第二像素电路单元40之间形成第三放置间隙CC3或第四放置间隙，并在该第三放置间隙CC3或第四放置间隙与第一放置间隙CC1的连通处将第二虚拟像素电路与第一虚拟像素电路68电连接，因此，第二虚拟像素电路不用绕过集中的第二像素电路单元40至边框区FA，简化了走线路径。
在一些实施例中，第二虚拟像素电路包括多个彼此连接的第二子虚拟像素电路，第二子虚拟像素电路的结构形式、布置膜层及与其他部件之间的连接关系均可与第一虚拟像素电路相同，在此不再赘述。
基于同样的发明构思，本申请实施例还提供一种显示设备，包括上述的显示面板100。
具体地，显示设备可以应用于手机终端、仿生电子、电子皮肤、可穿戴设备、车载设备、物联网设备及人工智能设备等领域。显示终端具体可为手机、平板、掌上电脑、ipod、智能手表等数码设备。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。

Claims (18)

  1. 一种显示面板，其特征在于，包括：
    基底，包括显示区和至少部分围绕所述显示区的边框区；
    阵列排布的多个发光单元，设于所述显示区，每一所述发光单元包括第一电极；
    呈阵列排布的多个第一像素电路单元，设于所述显示区，每一所述第一像素电路单元包括多个第一像素电路，所述多个第一像素电路呈阵列排布，且至少一个所述第一像素电路与一对应的发光单元的所述第一电极电连接；以及
    多个第二像素电路单元，设于所述显示区，每一所述第二像素电路单元包括多个第二像素电路，所述多个第二像素电路呈阵列排布，且至少一个所述第二像素电路与一对应的发光单元的所述第一电极电连接；
    其中，任意相邻的两个第一像素电路单元之间形成第一放置间隙。
  2. 根据权利要求1所述的显示面板，其特征在于，在同一所述第一像素电路单元中，任意相邻的两个所述第一像素电路在所述基底的正投影之间的间距，小于所述第一放置间隙的尺寸。
  3. 根据权利要求1所述的显示面板，其特征在于，相邻的所述第一像素电路单元与所述第二像素电路单元之间形成有第二放置间隙，所述第一放置间隙的尺寸等于所述第二放置间隙的尺寸。
  4. 根据权利要求1所述的显示面板，其特征在于，所述多个第一像素电路单元沿第一方向排布呈行，且沿第二方向排布呈列；
    所述显示面板的所述第一放置间隙包括位于沿第一方向相邻的两列所述第一像素电路单元之间的第一子放置间隙，以及位于沿第二方向相邻的两行所述第一像素电路单元之间的第二子放置间隙；
    所述第一子放置间隙的尺寸，与所述第二子放置间隙的尺寸相异；
    其中，所述第一方向及所述第二方向均平行于所述基底的显示面，且所述第一方向和所述第二方向相垂直。
  5. 根据权利要求1所述的显示面板，其特征在于，所述显示区包括第一显示区和位于所述第一显示区和所述边框区之间的第二显示区；
    所述多个第一像素电路单元设于所述第一显示区，所述多个第二像素电路单元设于所述第二显示区。
  6. 根据权利要求1所述的显示面板，其特征在于，每一所述第一像素电路单元在所 述基底的正投影形成第一投影区域，与该所述第一像素电路单元对应的多个所述发光单元的所述第一电极在所述基底的正投影形成第二投影区域；所述第二投影区域位于所述第一投影区域内。
  7. 根据权利要求6所述的显示面板，其特征在于，每一所述第二像素电路单元在所述基底的正投影形成第三投影区域，与该所述第二像素电路单元对应的多个所述发光单元的所述第一电极在所述基底的正投影形成第四投影区域，所述第四投影区域与所述第三投影区域部分重叠或者不重叠。
  8. 根据权利要求7所述的显示面板，其特征在于，所述显示面板还包括驱动电路，所述驱动电路设于所述基底上，且至少部分位于所述显示区，所述驱动电路与所述多个第一像素电路及所述多个第二像素电路电连接，以提供驱动信号；
    其中，设于所述显示区的所述驱动电路在所述基底的正投影形成第五投影区域，所述第五投影区域与所述第四投影区域部分重叠。
  9. 根据权利要求7所述的显示面板，其特征在于，所述显示面板还包括转接金属层，所述转接金属层位于所述多个第二像素电路与所述多个第二像素电路对应的多个所述发光单元的所述第一电极之间，至少部分所述第二像素电路通过所述转接金属层与对应的所述发光单元的所述第一电极电连接。
  10. 根据权利要求1所述的显示面板，其特征在于，所述多个第一像素电路单元沿第一方向排布呈行，且沿第二方向排布呈列；
    所述多个第二像素电路单元位于所述多个第一像素电路单元在所述第一方向上的一侧，且所述多个第二像素电路单元沿所述第二方向排布呈列，在所述第二方向上任意相邻的两个第二像素电路单元之间形成第三放置间隙，任意相邻的两列第一像素电路单元之间的所有所述第一放置间隙彼此连通，且与对应的所述第三放置间隙彼此连通；
    其中，所述第一方向及所述第二方向均平行于所述基底的显示面，且所述第一方向与所述第二方向相垂直。
  11. 根据权利要求1所述的显示面板，其特征在于，所述多个第一像素电路单元沿第一方向排布呈行，且沿第二方向排布呈列；
    所述多个第二像素电路单元位于所述多个第一像素电路单元在所述第二方向上的一侧，且所述多个第二像素电路单元沿所述第一方向排布呈行，在所述第一方向上任意相邻两个第二像素电路单元之间形成第四放置间隙，任意相邻的两行第一像素电路单元之间的所有所述第一放置间隙彼此连通，且与对应的所述第四放置间隙彼此连通；
    其中，所述第一方向及所述第二方向均平行于所述基底的显示面，且所述第一方向与 所述第二方向相垂直。
  12. 根据权利要求1所述的显示面板，其特征在于，所述多个第一像素电路单元沿第一方向排布呈行，且沿第二方向排布呈列；
    所述多个第二像素电路单元位于所述多个第一像素电路单元在第一方向上的一侧，且所述多个第二像素电路单元沿所述第二方向排布呈列，在所述第二方向上任意相邻两个第二像素电路单元之间形成第三放置间隙，任意相邻的两列第一像素电路单元之间的所有所述第一放置间隙彼此连通，且与对应的所述第三放置间隙彼此连通；和
    所述多个第二像素电路单元位于所述多个第一像素电路单元在所述第二方向上的一侧，且所述多个第二像素电路单元沿所述第一方向排布呈行，在所述第一方向上任意相邻两个第二像素电路单元之间形成第四放置间隙，任意相邻的两行第一像素电路单元之间的所有所述第一放置间隙彼此连通，且与对应的所述第四放置间隙彼此连通；
    其中，所述第一方向及所述第二方向均平行于所述基底的显示面，且所述第一方向与所述第二方向相垂直。
  13. 根据权利要求1～12任一项所述的显示面板，其特征在于，所述显示面板还包括电源线及第一虚拟像素电路，所述电源线与所述第一像素电路、所述第二像素电路及所述发光单元中的至少一者电连接，以提供电压信号，所述第一虚拟像素电路设于所述第一放置间隙，且与所述电源线电连接。
  14. 根据权利要求13所述的显示面板，其特征在于，至少部分所述第一虚拟像素电路的布线形状呈网格状。
  15. 根据权利要求13所述的显示面板，其特征在于，所述电源线能够接入低电压信号、高电压信号或者参考电压信号中的至少一者。
  16. 根据权利要求13所述的显示面板，其特征在于，所述第一虚拟像素电路包括多个彼此相连的第一子虚拟像素电路，所述第一子虚拟像素电路的图案和形状与所述第一像素电路或者所述第二像素电路的图案和形状相同。
  17. 根据权利要求16所述的显示面板，其特征在于，所述第一子虚拟像素电路包括多个沿第三方向层叠设置的非金属层、第一金属层及第二金属层，所述非金属层、所述第一金属层及所述第二金属层中的至少两者之间沿第三方向彼此相连；
    其中，所述第三方向为所述基底指向所述多个发光单元的方向。
  18. 一种显示设备，其特征在于，包括如权利要求1～17任一项所述的显示面板。
PCT/CN2022/107403 2022-01-28 2022-07-22 显示面板及显示设备 WO2023142404A1 (zh)

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