WO2023138228A1 - 一种半导体结构及其制备方法 - Google Patents

一种半导体结构及其制备方法 Download PDF

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WO2023138228A1
WO2023138228A1 PCT/CN2022/136132 CN2022136132W WO2023138228A1 WO 2023138228 A1 WO2023138228 A1 WO 2023138228A1 CN 2022136132 W CN2022136132 W CN 2022136132W WO 2023138228 A1 WO2023138228 A1 WO 2023138228A1
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layer
substrate
isolation
groove structure
filling
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PCT/CN2022/136132
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English (en)
French (fr)
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赵文礼
白杰
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • Embodiments of the present application relate to but are not limited to a semiconductor structure and a manufacturing method thereof.
  • An embodiment of the present disclosure provides a method for preparing a semiconductor structure, including:
  • a first isolation layer, a second isolation layer, and a third isolation layer are sequentially formed on the bottom and side walls of the groove structure, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate to form a side ditch;
  • a filling layer is formed to fill the gutter, the upper surface of the filling layer is flush with the upper surface of the protection layer.
  • the forming the filling layer filling the gutter includes:
  • the filling layer is planarized such that the upper surface of the filling layer is flush with the upper surface of the protection layer.
  • a protective layer on the surface of the substrate located on both sides of the groove structure it further includes;
  • the material of the filling layer is the same as that of the second isolation layer.
  • the filling layer to fill the gutter after forming the filling layer to fill the gutter, it further includes:
  • a silicon germanium layer is formed on the surface of the substrate on one side of the groove structure.
  • a silicon germanium layer on the surface of the substrate on one side of the groove structure further comprising:
  • a first gate stack is formed over the high-K dielectric layer on one side of the groove structure where the silicon germanium layer is formed, and a second gate stack is formed on the other side of the groove structure over the high-K dielectric layer, the materials of the first gate stack and the second gate stack are different.
  • the preparation method includes:
  • the first gate stack includes a stacked structure of titanium nitride, aluminum oxide and titanium nitride
  • the second gate stack includes a stacked structure of lanthanum oxide and titanium nitride.
  • a high-K dielectric layer on the substrate before depositing a high-K dielectric layer on the substrate, further comprising:
  • An interface layer is formed on the surface of the silicon germanium layer and the surface of the substrate on the other side of the groove structure.
  • a PMOS is formed on one side of the groove structure where the silicon germanium layer is formed, and an NMOS is formed on the other side of the groove structure.
  • the sequentially forming a first isolation layer, a second isolation layer and a third isolation layer on the bottom and sidewalls of the groove structure includes:
  • the first isolation layer, the second isolation layer and the third isolation layer are planarized using the surface of the substrate as a stop layer.
  • planarizing the filling layer so that the upper surface of the filling layer is flush with the upper surface of the protective layer includes:
  • the filling layer is etched by a wet etching process, and a wet etchant of the wet etching process includes phosphoric acid.
  • the temperature of the wet etching process is controlled at 155°C to 165°C.
  • An embodiment of the present disclosure also provides a semiconductor structure, including:
  • a substrate comprising a grooved structure
  • An isolation dielectric the isolation dielectric is filled in the groove structure, and the isolation dielectric includes a first isolation layer, a second isolation layer, and a third isolation layer covering the bottom surface and the sidewall of the groove structure in sequence, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate to form a side ditch;
  • the filling layer fills the side ditch, the upper surface of the filling layer is flush with the upper surface of the second isolation layer and the upper surface of the third isolation layer, and the upper surface of the filling layer is higher than the upper surface of the substrate.
  • the semiconductor structure also includes:
  • a silicon germanium layer, the silicon germanium layer is located on the surface of the substrate on one side of the groove structure, and the upper surface of the silicon germanium layer is higher than the upper surface of the filling layer.
  • the semiconductor structure also includes:
  • An interface layer includes a first interface layer and a second interface layer, the first interface layer is located on the surface of the silicon germanium layer, and the second interface layer is located on the surface of the substrate on the other side of the groove structure.
  • the thickness of the second interface layer is not smaller than the thickness of the first interface layer, and the upper surface of the second interface layer is flush with the upper surface of the filling layer.
  • the semiconductor structure also includes:
  • the PMOS is located on one side of the groove structure, and the channel of the PMOS includes a silicon germanium layer;
  • the NMOS is located on the other side of the groove structure.
  • the POMS further includes a high-K dielectric layer and a laminated structure of titanium nitride, aluminum oxide and titanium nitride;
  • the NOMS further includes a high-K dielectric layer and a laminated structure of lanthanum oxide and titanium nitride.
  • the substrate is first protected by a protective layer, and then a filling layer is formed to fill the side ditch, which eliminates the side ditch, prevents the side ditch from affecting the electrical characteristics of the device, and reduces the process difficulty of subsequent metal wiring and film deposition.
  • FIG. 1 is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure
  • 2a-2l are structural schematic diagrams of a semiconductor structure during the preparation process according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure.
  • STI shallow trench isolation
  • an embodiment of the present disclosure provides a method for preparing a semiconductor structure. Referring to FIG. 1 , the method includes:
  • Step 101 providing a substrate, the substrate including a groove structure.
  • Step 102 sequentially forming a first isolation layer, a second isolation layer and a third isolation layer on the bottom and sidewalls of the groove structure, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate to form a side ditch.
  • Step 103 forming a protection layer on the surface of the substrate located on both sides of the groove structure.
  • Step 104 forming a filling layer to fill the gutter, the upper surface of the filling layer being flush with the upper surface of the protection layer.
  • the substrate is first protected by a protective layer, and then a filling layer is formed to fill the side ditch, so as to prevent the side ditch from affecting the electrical characteristics of the device, and at the same time reduce the process difficulty of subsequent metal wiring and film layer deposition.
  • step 101 is performed, as shown in FIG. 2 a , a substrate 201 is provided, and the substrate includes a groove structure 203 .
  • the substrate 201 includes but not limited to silicon, silicon germanium, germanium, silicon on insulator (SOI), silicon on insulator (SSOI) or other suitable semiconductor substrates.
  • the groove structure 203 can be formed by basically isolating the device active region through photolithography and etching processes, for example.
  • the sidewall and the bottom surface of the groove structure are rounded corners, which help to improve the filling quality and the electrical characteristics of the isolation structure.
  • step 102 is performed, referring to the accompanying drawings 2b-2e, forming a first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 sequentially on the bottom and sidewalls of the groove structure 203, wherein the upper surface of the first isolation layer 205 is lower than the upper surface of the second isolation layer 207 and the substrate 201 to form a side ditch 211.
  • sequentially forming a first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 on the bottom and sidewalls of the groove structure includes: sequentially depositing the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 above the substrate; and planarizing the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 using the surface of the substrate as a stop layer.
  • a first isolation layer 205 , a second isolation layer 207 and a third isolation layer 209 are sequentially deposited on the substrate.
  • the material of the first isolation layer 205 may be an oxide material, for example, silicon oxide.
  • the oxidation process can be used to make the substrate into the high-temperature oxidation equipment, and a layer of oxide is grown by the principle of thermal oxidation.
  • the first isolation layer 205 mainly plays the role of directly protecting the active region, and at the same time repairs the damage of the etching surface of the substrate groove.
  • the material of the second isolation layer 207 may be a nitride material, for example, silicon nitride.
  • a Low Pressure Chemical Vapor Deposition (LPCVD) method may be used to feed ammonia gas and silicon tetrachloride to form a layer of silicon nitride on the first isolation layer 205 .
  • the material of the third isolation layer 209 may be insulating dielectric, for example, oxide. In actual operation, it can be formed by wet oxidation process, dry oxidation process or spin-on dielectric (Spin-on Dielectrics, SOD) process.
  • the spin-on dielectric (Spin-on Dielectrics, SOD) process has the advantages of good insulation performance and strong hole filling ability. Using SOD to fill the grooves between microelectronic circuits can reduce the space occupied by the isolation area while maintaining the same device performance, realize the technical process of high-density circuits, and improve circuit efficiency.
  • the planarization treatment may be, for example, chemical mechanical polishing (CMP), where the substrate plane may serve as a stop layer for the chemical mechanical polishing process.
  • CMP chemical mechanical polishing
  • the first isolation layer, the second isolation layer and the third isolation layer after forming the first isolation layer, the second isolation layer and the third isolation layer, it also includes: forming a mask layer above the substrate, the mask layer comprising a stacked structure of a first oxide layer 213, a silicon nitride layer 214 and a second oxide layer 215.
  • the mask is used to protect other areas of the substrate, for example, in a semiconductor storage device including a core area and a peripheral area, to prevent subsequent processes in the peripheral area from affecting elements in the core area.
  • the step of forming the first oxide layer 213 , the silicon nitride layer 214 and the second oxide layer 215 is performed before the process of growing a gate in the peripheral region.
  • the mask layer is removed to expose the substrate surface.
  • the process of removing the mask layer includes but not limited to wet etching, dry etching, chemical mechanical polishing or a combination thereof.
  • the first isolation layer 205 will be over-etched, causing the lower surface of the first isolation layer 205 to sink, resulting in side grooves 211 (as shown in FIG. 2e).
  • step 103 is performed, as shown in FIG. 2f , forming a protection layer 221 on the surface of the substrate located on both sides of the groove structure.
  • the material of the protection layer may be an oxide material, for example, silicon oxide.
  • the substrate can be put into thermal oxidation equipment, a certain amount of pure oxygen can be passed through, and a thermal oxidation layer is formed on the surface of the substrate on both sides of the groove structure by high temperature oxidation.
  • the thickness of the thermal oxidation layer can be, for example, 2-3 nm.
  • the protection layer is used to protect the surface of the substrate and as a stress buffer layer. Prevent the subsequent deposition of the filling layer from contaminating the substrate, and relieve the stress between the filling layer and the substrate.
  • the method before forming the protection layer on the surface of the substrate located on both sides of the groove structure, the method further includes: etching part of the first isolation layer. While increasing the depth of the side ditch, it makes the side ditch more regular and smooth, which is conducive to the filling of the subsequent filling layer.
  • step 104 is executed, as shown in Figures 2g-2h, a filling layer 218 filling the side ditch 211 is formed, the upper surface of the filling layer 218 is flush with the upper surface of the protection layer 221 .
  • the material of the filling layer 218 includes but not limited to oxide, nitride or other suitable insulating dielectrics.
  • the formation process of the filling layer includes but not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof. In actual operation, the material of the filling layer 218 is the same as that of the second isolation layer 207 .
  • a filling material is deposited above the substrate by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the atomic layer deposition process has excellent filling ability, and has inherent advantages such as low temperature deposition, film purity and excellent coverage.
  • the filling material is planarized so that the upper surface of the filling layer 218 is flush with the upper surface of the protection layer 221 .
  • the planarization process includes but not limited to wet etching, dry etching, chemical mechanical polishing or a combination thereof.
  • the filling layer is etched using a wet etching process, and a wet etchant in the wet etching process includes phosphoric acid. The wet etching process is easy to operate, has low requirements on equipment, and is easy to realize mass production.
  • the temperature of the wet etching process is controlled at 155°C to 165°C, for example, 157°C, 160°C, 162°C. If the temperature of the wet etching process is too low, the etching efficiency will be reduced or the filling layer will not be completely removed, and if the temperature of the wet etching process is too high, it may lead to over-etching.
  • the filling layer to fill the side trench further includes: removing the protective layer 221 to expose the substrate 201; forming a silicon germanium layer 217 on the surface of the substrate located on one side of the groove structure.
  • the protection layer 221 is removed to expose the substrate 201 .
  • the protective layer is removed to expose the substrate and prepare for the subsequent deposition of silicon germanium layer, high-K dielectric layer and gate stack.
  • a hydrofluoric acid solution may be used to remove the protective layer. Hydrofluoric acid has good uniformity and high etching selectivity for the oxide protection layer.
  • the upper surface of the filling layer 218 is flush with the upper surface of the substrate; in some specific embodiments, the upper surface of the filling layer 218 is flush with the upper surfaces of the substrate 201, the first isolation layer 205, the second isolation layer 207 and the third isolation layer 209.
  • only the protective layer 221 on the upper surface of the substrate can be removed to keep the filling layer 218 and the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 from being etched.
  • the upper surface of the filling layer 218 can be higher than the upper surface of the substrate.
  • a silicon germanium layer 217 is formed on the surface of the substrate at one side of the groove structure.
  • the silicon germanium layer is used to form a PMOS channel, and the stress mechanism of the silicon germanium layer can greatly improve the driving current, and the silicon germanium layer can increase the mobility of channel carriers due to stress, which is beneficial to adjust the threshold voltage.
  • the silicon germanium layer 217 may be deposited by chemical vapor phase epitaxy (CVD), selective vapor phase epitaxy and other techniques.
  • a third oxide layer (not shown in the figure) is formed on the substrate surface on both sides of the groove structure.
  • a third oxide layer may be formed over the substrate, for example by a thermal oxidation process.
  • the thickness of the third oxide layer is relatively thick, such as 30-60 nm, for example, 32 nm, 42 nm, 55 nm, 58 nm, etc.
  • the silicon germanium layer can be deposited by chemical vapor phase epitaxy (CVD), selective vapor phase epitaxy and other technologies.
  • the third oxide layer on the surface of the substrate on the other side of the groove structure is etched and removed to expose the substrate and prepare for subsequent deposition of a high-K dielectric layer and a gate stack.
  • the side ditch is filled with the filling layer 218 before forming the silicon germanium layer. Since the material of the filling layer is etched relatively larger than that of the third oxide layer, no side ditch will be generated after removing the third oxide layer.
  • the filling layer for filling the side ditch after forming the filling layer for filling the side ditch, it also includes: removing the protective layer on the surface of the substrate on one side of the groove structure to expose the substrate; forming a silicon germanium (SiGe) layer on the surface of the substrate on one side of the groove structure; removing the protective layer on the other side of the groove structure.
  • SiGe silicon germanium
  • the material of the high-K dielectric layer 225 may include but not limited to BaZrO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO 3 (BST), Al 2 O 3 , La 2 O 3 , Si 3 N 4 , oxynitride or other suitable materials.
  • the high-K dielectric layer 225 can be formed by a suitable process such as CVD, ALD or PVD.
  • the thickness of the high-K dielectric layer 225 may range from 2 nm to 10 nm.
  • the first gate stack 233 includes a stack structure of titanium nitride 227 , aluminum oxide 229 and titanium nitride 227
  • the second gate stack 235 includes a stack structure of lanthanum oxide 231 and titanium nitride 227 .
  • a second gate stack may be deposited on the high-K dielectric layer, and then etched through a mask to remove the second gate stack above the high-K dielectric layer on the side where the silicon germanium layer is formed in the groove structure, and then the first gate stack may be deposited.
  • one side can be covered with a patterned first mask layer, titanium nitride and aluminum oxide are sequentially deposited on the high-K dielectric layer on the side where the SiGe layer is formed, and then the first mask layer is removed, a second mask layer is formed on the aluminum oxide stack, lanthanum oxide is formed on the high-K dielectric layer on the other side of the groove structure, the second mask layer is removed, and titanium nitride is simultaneously deposited on the aluminum oxide and lanthanum oxide to form the first gate stack and the second gate stack.
  • the work function value of the gate material can be freely set and adjusted to fully control the threshold voltage.
  • the high-K dielectric layer 225 before depositing the high-K dielectric layer 225 on the substrate, it further includes: forming an interface layer 223 (interface layer, IL) on the surface of the silicon germanium layer 217 and the surface of the substrate on the other side of the groove structure.
  • the interface layer 223 may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer or other suitable thin film layers.
  • the interface layer can be formed by suitable processes such as CVD, ALD or PVD, for example, the interface layer can be formed by high temperature pure oxygen thermal oxidation.
  • the thickness of the interface layer may range from 0.8 nm to 1.5 nm, for example, 1 nm.
  • the interfacial layer can increase the adhesion between the high-K dielectric layer and the substrate or silicon germanium layer, and has the function of preventing electric leakage.
  • the interface layer includes a first interface layer and a second interface layer, the first interface layer is located on the surface of the silicon germanium layer, and the second interface layer is located on the surface of the substrate on the other side of the groove structure; the thickness of the second interface layer is greater than or equal to the thickness of the first interface layer, and the upper surface of the second interface layer is flush with the upper surface of the filling layer 218.
  • the upper surface of the second interface layer is flush with the upper surface of the filling layer, which can further reduce the process difficulty of depositing metal wiring and film deposition, so that the performance of the device is more stable.
  • a PMOS P-type metal oxide semiconductor
  • an NMOS N-type metal oxide semiconductor
  • the PMOS can be formed first and then the NMOS, or the NMOS can be formed first and then the PMOS can be formed.
  • a CMOS Complementary Metal Oxide Semiconductor
  • the metal atoms in PMOS form dipoles at the interface between the high-K dielectric layer and IL, and the combined SiGe structure acts as a channel to effectively adjust the threshold voltage of PMOS.
  • due to the elimination of side trenches there will be no discontinuous breaks and damage to the channel surface of the device during the subsequent growth of high-K dielectric layers and work function metals, avoiding drift and instability of CMOS performance.
  • the semiconductor structure includes: a substrate 201, the substrate includes a groove structure 203; an isolation dielectric 204, the isolation dielectric 204 is filled in the groove structure, and the isolation dielectric 204 includes a first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 that cover the bottom and side walls of the groove structure 203 in sequence; wherein, the upper surface of the first isolation layer 205 is lower than the second isolation layer 207 and the substrate.
  • the upper surface of 201 constitutes the side ditch 211; the filling layer 218, the filling layer 218 fills the side ditch 211, the upper surface of the filling layer is flush with the upper surface of the second isolation layer and the upper surface of the third isolation layer, and the upper surface of the filling layer 218 is higher than the upper surface of the substrate 201. Since the filling layer 218 fills the side ditch 211 , the side ditch is prevented from affecting the electrical characteristics of the device, and at the same time, the difficulty of subsequent processes, such as cleaning, metal wiring, and film deposition, is reduced.
  • the semiconductor structure further includes: a silicon germanium layer 217, the silicon germanium layer 217 is located on the surface of the substrate on one side of the groove structure 203, and the upper surface of the silicon germanium layer 217 is higher than the upper surface of the filling layer 218.
  • the silicon germanium layer is used to form a PMOS channel, and the stress mechanism of the silicon germanium layer can greatly improve the driving current, and the silicon germanium layer can increase the mobility of channel carriers due to stress, which is beneficial to adjust the threshold voltage.
  • the silicon germanium layer 217 may be deposited by chemical vapor phase epitaxy (CVD), selective vapor phase epitaxy and other techniques.
  • the semiconductor structure further includes: an interface layer 223, the interface layer 223 includes a first interface layer and a second interface layer, the first interface layer is located on the surface of the silicon germanium layer, and the second interface layer is located on the surface of the substrate on the other side of the groove structure.
  • the interface layer 223 may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer or other suitable thin film layers.
  • the interface layer can be formed by suitable processes such as CVD, ALD or PVD, for example, the interface layer can be formed by high temperature pure oxygen thermal oxidation.
  • the thickness of the interface layer may range from 0.8 nm to 1.5 nm, for example, 1 nm.
  • the interface layer can increase the adhesion between the high-K dielectric layer and the substrate or silicon germanium layer, and has the function of preventing electric leakage.
  • the thickness of the second interface layer is not smaller than the thickness of the first interface layer, and the upper surface of the second interface layer is flush with the upper surface of the filling layer 218 .
  • the upper surface of the second interface layer is flush with the upper surface of the filling layer, which can further reduce the process difficulty of depositing metal wiring and film deposition, so that the performance of the device is more stable.
  • the semiconductor structure further includes: PMOS, the PMOS is located on one side of the groove structure, and the channel of the PMOS includes a silicon germanium layer; NMOS, the NMOS is located on the other side of the groove structure.
  • CMOS Complementary Metal Oxide Semiconductor
  • the metal atoms in PMOS form dipoles at the interface between the high-K dielectric layer and IL, and the combined SiGe structure acts as a channel to effectively adjust the threshold voltage of PMOS.
  • the POMS also includes a high-K dielectric layer and a laminated structure of titanium nitride, aluminum oxide and titanium nitride;
  • the NOMS also includes a high-K dielectric layer and a laminated structure of lanthanum oxide and titanium nitride.
  • the substrate is first protected by a protective layer, and then a filling layer is formed to fill the side ditch, which eliminates the side ditch, prevents the side ditch from affecting the electrical characteristics of the device, and reduces the process difficulty of subsequent metal wiring and film layer deposition.
  • the semiconductor structure provided by the embodiments of the present disclosure and the method for forming the same can be applied to any integrated circuit including the structure.
  • the technical features in the technical solutions described in each embodiment can be combined arbitrarily under the condition that there is no conflict.
  • Those skilled in the art can change the order of the steps of the above forming method without departing from the protection scope of the present disclosure.
  • the steps in the embodiments of the present disclosure can be executed at the same time, or in sequence, if there is no conflict.
  • An embodiment of the present disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including a groove structure; sequentially forming a first isolation layer, a second isolation layer, and a third isolation layer on the bottom and sidewalls of the groove structure, wherein the upper surface of the first isolation layer is lower than the second isolation layer and the upper surface of the substrate to form a side ditch; forming a protective layer on the surface of the substrate located on both sides of the groove structure; forming a filling layer to fill the side groove, the upper surface of the filling layer is flush with the upper surface of the protection layer.
  • the substrate is first protected by a protective layer, and then a filling layer is formed to fill the side ditch, which eliminates the side ditch, prevents the side ditch from affecting the electrical characteristics of the device, and reduces the process difficulty of subsequent metal wiring and film deposition.

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Abstract

本公开实施例提供了一种半导体结构的制备方法，所述制备方法包括：提供衬底，所述衬底包括凹槽结构；在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟；在位于所述凹槽结构两侧的所述衬底表面上形成保护层；形成填充所述边沟的填充层，所述填充层的上表面与所述保护层的上表面齐平。

Description

一种半导体结构及其制备方法
相关申请的交叉引用
本申请要求在2022年1月24日提交中国专利局、申请号为202210081376.4、申请名称为“一种半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种半导体结构及其制备方法。
背景技术
在集成电路的制造中，数以万计的有源器件(例如PMOS与NMOS)同时集成在衬底材料上。为了让器件之间不要互相影响，需要采用隔离技术将各有源器件彼此隔离。
然而目前的隔离技术仍存在不足，如何优化隔离部件为现阶段亟需解决的技术问题。
发明内容
本公开实施例提供了一种半导体结构的制备方法，包括：
提供衬底，所述衬底包括凹槽结构；
在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟；
在位于所述凹槽结构两侧的所述衬底表面上形成保护层；
形成填充所述边沟的填充层，所述填充层的上表面与所述保护层的上表面齐平。
在一些实施例中，所述形成填充所述边沟的填充层，包括：
采用原子层沉积工艺在所述衬底的上方沉积填充层；
平面化所述填充层使得所述填充层的上表面与所述保护层的上表面齐平。
在一些实施例中，在位于所述凹槽结构两侧的所述衬底表面上形成保护层之前，还包括；
刻蚀部分所述第一隔离层。
在一些实施例中，所述填充层的材料与所述第二隔离层的材料相同。
在一些实施例中，形成填充所述边沟的填充层后，还包括：
去除所述保护层，暴露出衬底；
在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层。
在一些实施例中，在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层之后，还包括：
在所述衬底的上方沉积高K介电层；
在位于凹槽结构形成硅锗层的一侧的高K介电层上方形成第一栅极堆叠，在位于凹槽结构另一侧的高K介电层上方形成第二栅极堆叠，所述第一栅极堆叠和所述第二栅极堆叠的材料不同。
在一些实施例中，所述制备方法包括：
所述第一栅极堆叠包括氮化钛、氧化铝和氮化钛的叠层结构，所述第二栅极堆叠包括氧化镧和氮化钛的叠层结构。
在一些实施例中，在所述衬底的上方沉积高K介电层之前，还包括：
在所述硅锗层的表面和位于所述凹槽结构另一侧的所述衬底的表面上形成界面层。
在一些实施例中，在位于所述凹槽结构形成硅锗层的一侧形成PMOS，在位于所述凹槽结构的另一侧形成NMOS。
在一些实施例中，所述在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，包括：
在所述衬底的上方依次沉积第一隔离层、第二隔离层和第三隔离层；
以衬底的表面为停止层平坦化所述第一隔离层、第二隔离层和第三隔离层。
在一些实施例中，平面化所述填充层使得所述填充层的上表面与所述保护层的上表面齐平，包括：
采用湿法刻蚀工艺刻蚀所述填充层，所述湿法刻蚀工艺的湿法刻蚀剂包括磷酸。
在一些实施例中，所述湿法刻蚀工艺的温度控制在155摄氏度至165摄氏度。
本公开实施例还提供了一种半导体结构，包括：
衬底，所述衬底包括凹槽结构；
隔离电介质，所述隔离电介质填充于所述凹槽结构中，所述隔离电介质包括依次覆盖在所述凹槽结构底面和侧壁的第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟；
填充层，所述填充层填充所述边沟，所述填充层的上表面与所述第二隔离层的上表面以及所述第三隔离层的上表面齐平，且所述填充层的上表面高于所述衬底的上表面。
在一些实施例中，所述半导体结构还包括：
硅锗层，所述硅锗层位于所述凹槽结构一侧的所述衬底的表面上，且所述锗硅层的上表面高于所述填充层的上表面。
在一些实施例中，所述半导体结构还包括：
界面层，所述界面层包括第一界面层和第二界面层，所述第一界面层位于所述锗硅层的表面上，所述第二界面层位于所述凹槽结构的另一侧的衬底的表面上。
在一些实施例中，所述第二界面层的厚度不小于所述第一界面层的厚度，且所述第二界面层的上表面与所述填充层的上表面齐平。
在一些实施例中，所述半导体结构还包括：
PMOS，所述PMOS位于所述凹槽结构的一侧，所述PMOS的沟道包括硅锗层；
NMOS，所述NMOS位于所述凹槽结构的另一侧。
在一些实施例中，所述POMS还包括高K介电层以及氮化钛、氧化铝和氮化钛的叠层结构；所述NOMS还包括高K介电层以及氧化镧和氮化钛的叠层结构。
本公开首先通过保护层保护衬底，再形成填充所述边沟的填充层，消除了边沟，避免边沟影响器件的电学特性，同时降低了后续金属布线和膜层沉积的工艺难度。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例的半导体结构的制备方法的流程图；
图2a-2l为本公开一实施例的半导体结构在制备过程中的结构示意图；
图3为本公开一实施例的半导体结构的剖面示意图。
201-衬底；203-凹槽结构；204-隔离电介质；205-第一隔离层；207-第二隔离层；209-第三隔离层；211-边沟；213-第一氧化物层；214-氮化硅层；215-第二氧化物层；217-硅锗层；218-填充层；221-保护层；223-界面层；225-高K介电层；227-氮化钛；229-氧化铝；231-氧化镧；233-第一栅极堆叠；235-第二栅极堆叠。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开， 而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在 该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
随着摩尔定律的发展，浅沟槽隔离(STI)技术制作有源区域之间的绝缘结构已逐渐被普遍采用。由于工艺局限，STI结构与有源区相邻的区域容易向下凹陷形成边沟，在形成有边沟的衬底上形成半导体器件容易产生寄生的电流，从而影响半导体器件的电学特性，且边沟的存在会导致形成半导体器件的后续工艺难度增加，例如沉积的导电层发生断裂，导致半导体器件失效。
基于此，本公开实施例提供了一种半导体结构的制备方法，参考附图1，所述方法包括：
步骤101：提供衬底，所述衬底包括凹槽结构。
步骤102：在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟。
步骤103：在位于所述凹槽结构两侧的所述衬底表面上形成保护层。
步骤104：形成填充所述边沟的填充层，所述填充层的上表面与所述保护层的上表面齐平。
在本公开实施例中，首先通过保护层保护衬底，再形成填充所述边沟的填充层，避免边沟影响器件的电学特性，同时降低了后续金属布线和膜层沉积的工艺难度。
下面结合附图2a-2l对本发明实施例提供的半导体结构的制备方法进行具体说明。
首先，执行步骤101，如附图2a所示，提供衬底201，所述衬底包括凹槽结构203。所述衬底201包括但不限于硅、硅锗、锗、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)或其他合适的半导体衬底。所述凹槽结构203例如可以经过光刻和蚀刻工艺对器件有源区进行基础隔离形成凹槽结构。在一些实施例中，所述凹槽结构的侧壁与底表面为圆滑的转角，有助于提高填充的质量和隔 离结构的电学特性。
接着，执行步骤102，参考附图2b-2e，在所述凹槽结构203的底部与侧壁上依次形成第一隔离层205、第二隔离层207和第三隔离层209，其中，所述第一隔离层205的上表面低于所述第二隔离层207和所述衬底201的上表面从而构成边沟211。
在一些实施例中，参见附图2b-2c，在所述凹槽结构的底部与侧壁上依次形成第一隔离层205、第二隔离层207和第三隔离层209，包括：在所述衬底的上方依次沉积第一隔离层205、第二隔离层207和第三隔离层209；以衬底的表面为停止层平坦化所述第一隔离层205、第二隔离层207和第三隔离层209。
具体的，首先，如附图2b所示，在所述衬底的上方依次沉积第一隔离层205、第二隔离层207和第三隔离层209。所述第一隔离层205的材料可以为氧化物材料，示例性的，例如氧化硅。在实际操作中，可以利用氧化工艺制作，将衬底进入高温氧化设备，采用热氧化的原理生长一层氧化物。所述第一隔离层205主要起到直接保护有源区的作用，同时修复衬底凹槽的蚀刻面的损伤。所述第二隔离层207的材料可以为氮化物材料，示例性的，例如氮化硅。在实际操作中，可以采用低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)的方法，通入氨气和四氯化硅，在第一隔离层205上方形成一层氮化硅。所述第三隔离层209的材料可以为绝缘电介质，示例性的，例如氧化物。在实际操作中，可以采用湿氧化工艺、干氧化工艺或旋涂绝缘介质(Spin-on Dielectrics，SOD)等工艺形成，旋涂绝缘介质(Spin-on Dielectrics，SOD)工艺具有绝缘性能好，填洞能力强等优点，采用SOD填充微电子电路之间的沟槽，能够在器件性能保持不变的前提下，缩小隔离区所占空间，实现高密电路的技术工艺，提升电路效率。
接着，如附图2c所示，平面化所述第一隔离层205、第二隔离层207和第三隔离层209。所述平面化处理例如可以为化学机械研磨(Chemical Mechanical Polishing，CMP)，这里，衬底平面可以作为化学机械研磨过程的停止层。
接下来，如附图2d所示，在形成第一隔离层、第二隔离层和第三隔离层之 后，还包括：在所述衬底的上方形成掩膜层，所述掩膜层包括第一氧化物层213、氮化硅层214和第二氧化物层215的叠层结构。所述掩膜用于保护衬底的其它区域，例如在包含核心区域和外围区域的半导体存储器件中，避免外围区域的后续工艺影响核心区域的元件。具体的，形成所述第一氧化物层213、氮化硅层214和第二氧化物层215的步骤在外围区域生长栅极(gate)的工艺之前进行。
然后，如附图2e所示，去除所述掩膜层，暴露出衬底表面。这里，去除所述掩膜层的工艺包括但不限于湿法刻蚀、干法蚀刻、化学机械研磨或其组合。
在以上的工艺中，平坦化所述第一隔离层205、第二隔离层207和第三隔离层209的步骤(参见图2c)，去除掩膜层的步骤(参见附图2e)的过程中，会对第一隔离层205产生过刻蚀，导致第一隔离层205的下表面下陷，产生边沟211(如图2e所示)。
接着，执行步骤103，如附图2f所示，在位于所述凹槽结构两侧的所述衬底表面上形成保护层221。所述保护层的材料可以为氧化物材料，示例性的，例如氧化硅。在实际操作中，可以将衬底进入热氧化设备，通入一定的纯氧，采用高温氧化在所述凹槽结构两侧的所述衬底的表面上形成热氧化层，所述热氧化层的厚度例如可以为2～3nm。所述保护层用于保护衬底表面和作为应力缓冲层。防止后续沉积填充层污染衬底，以及缓减填充层与衬底之间的应力。
在一些实施例中，在位于所述凹槽结构两侧的所述衬底表面上形成保护层之前，还包括；刻蚀部分所述第一隔离层。增加边沟深度的同时，使得边沟更加规则平整，有利于后续填充层的填充。
最后，执行步骤104，如附图2g-2h所示，形成填充所述边沟211的填充层218，所述填充层218的上表面与所述保护层221的上表面齐平。所述填充层218的材料包括但不限于氧化物、氮化物或其他合适的绝缘电介质。所述填充层的形成工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。在实际操作中，所述填充层218的材料与所述第二隔离层207的材料相同。应用相同的材料可 以避免材料间分层，较好的兼容性可以提高填充效果。在后续平面化填充材料过程中，由于所述填充层和所述第二隔离层的刻蚀速率或抛光速率相同，所述填充层与所述第二隔离层的表面可以较为平整。
具体的，首先，参见附图2g，采用原子层沉积工艺(ALD)在所述衬底的上方沉积填充材料。原子层沉积工艺填充能力优异，具有低温沉积、薄膜纯度以及绝佳覆盖率等固有优点。
接着，如附图2h所示，平面化所述填充材料使得所述填充层218的上表面与所述保护层221的上表面齐平。如此，形成填充所述边沟的填充层218，消除了边沟。所述平面化工艺包括但不限于湿法刻蚀、干法蚀刻、化学机械研磨或其组合。在一些实施例中，采用湿法刻蚀工艺刻蚀所述填充层，所述湿法刻蚀工艺的湿法刻蚀剂包括磷酸。湿法刻蚀工艺操作简便，对设备要求低，易于实现大批量生产。示例性的，所述填充层为氮化硅时，利用磷酸对于填充层具有良好的均匀性和较高的刻蚀选择比，平面化所述填充层时，对衬底表面和第三隔离层的影响较小。在实际操作中，所述湿法刻蚀工艺的温度控制在155摄氏度至165摄氏度，示例性的，例如157摄氏度、160摄氏度、162摄氏度。湿法刻蚀工艺的温度过低会导致刻蚀效率降低或者导致填充层去除不完全，湿法刻蚀工艺的过高可能会导致过刻蚀。
在一些实施例中，如附图2i-2j所示，形成填充所述边沟的填充层后，还包括：去除所述保护层221，暴露出衬底201；在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层217。
具体的，参考附图2i，首先，去除所述保护层221，暴露出衬底201。去除保护层，暴露出衬底，为后续沉积硅锗层、高K介电层和栅极堆叠做准备。在实际操作中，可以采用氢氟酸溶液去除所述保护层。氢氟酸对于氧化物保护层具有良好的均匀性和较高的刻蚀选择比。在该实施例中，所述填充层218的上表面与衬底的上表面齐平；在一些具体实施例中，所述填充层218的上表面与衬底201、第一隔离层205、第二隔离层207和第三隔离层209的上表面齐平。在一些其他实施例中，可以只去除衬底上表面的保护层221，保持填充层218 和第一隔离层205、第二隔离层207、第三隔离层209不被刻蚀，在该实施例中，填充层218的上表面可以高于衬底的上表面。
接着，参考附图2j，在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层217。所述硅锗层用于形成PMOS的沟道，硅锗层应力机制对驱动电流有较大的改善作用，硅锗层由于应力作用可提高沟道载流子的迁移率，有利于调节阈值电压。在实际操作中，可以采用化学气相外延(CVD)、选择性气相外延等技术沉积硅锗层217。
具体的，首先，在所述凹槽结构两侧的衬底表面形成第三氧化物层(图中未示出)。例如通过热氧化工艺可以在衬底上方形成第三氧化物层。在一些具体实施例中，所述第三氧化层的厚度较厚，例如为30-60nm，示例性的，如32nm、42nm、55nm、58nm等。
接着，刻蚀位于所述凹槽结构一侧的所述衬底的表面上的第三氧化物层，暴露出衬底，在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗(SiGe)层。在实际操作中，可以采用化学气相外延(CVD)、选择性气相外延等技术沉积硅锗层。
在生长了硅锗层之后，刻蚀去除位于所述凹槽结构另一侧的所述衬底的表面上的第三氧化物层，暴露出衬底，为后续沉积高K介电层和栅极堆叠做准备。
在传统的形成硅锗层的工艺过程中，在去除凹槽结构一侧衬底表面上的第三氧化物层时，可能会由于过刻蚀产生边沟。本公开实施例在形成硅锗层前，通过填充层218填充所述边沟，由于填充层的材料与第三氧化物层的材料刻蚀比较大，在去除第三氧化物层不会再产生边沟。
在其他实施例中，形成填充所述边沟的填充层后，还包括：去除位于所述凹槽结构一侧的所述衬底的表面上的保护层，暴露出衬底；在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗(SiGe)层；去除位于所述凹槽结构另一侧的保护层。
在一些实施例中，如附图2k-2l所示，在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层之后，还包括：在所述衬底的上方沉积高K介电层225； 在位于凹槽结构形成硅锗层217的一侧的高K介电层225上方形成第一栅极堆叠233，在位于凹槽结构另一侧的高K介电层223上方形成第二栅极堆叠235，所述第一栅极堆叠233与所述第二栅极堆叠235的材料不同。所述高K介电层225的材料可以包括但不限于BaZrO、HfZrO、HfZrON、HfLaO、HfSiON、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO 3(BST)、Al 2O 3、La 2O 3、Si 3N 4、氮氧化物或者其他适合的材料。可以采用CVD、ALD或者PVD等适合的工艺形成高K介电层225。高K介电层225的厚度范围可以为2nm至10nm。应用高介电常数金属栅极(High-K Metal Gate，HKMG)技术，降低器件的等效氧化层厚度(EOT)，大幅减小栅极的漏电量，达到降低漏电(leakage)的高性能要求。在实际操作中，所述第一栅极堆叠233包括氮化钛227、氧化铝229和氮化钛227的叠层结构，所述第二栅极堆叠235包括氧化镧231和氮化钛227的堆叠结构。具体的，例如可以在高K介电层上方沉积第二栅极堆叠，再通过掩膜刻蚀去除位于凹槽结构形成硅锗层的一侧的高K介电层上方的第二栅极堆叠，然后沉积第一栅极堆叠。在其他实施例中，可以使用图案化的第一掩膜层遮挡一侧，在形成硅锗层的一侧的高K介电层上方依次沉积氮化钛和氧化铝，然后再去除第一掩膜层，在氧化铝堆叠的上方形成第二掩膜层，在位于凹槽结构另一侧的高K介电层上方形成氧化镧，再去除第二掩膜层，在氧化铝和氧化镧的上方同时沉积氮化钛，形成第一栅极堆叠和第二栅极堆叠。通过设置不同的栅极堆叠材料，通过使得后续形成相应的PMOS和NMOS的性能参数可控，可以自由设置和调配栅极材料的功函数值，充分控制阈值电压。
在一些实施例中，如附图2k所示，在所述衬底的上方沉积高K介电层225之前，还包括：在所述硅锗层217的表面和位于所述凹槽结构另一侧的所述衬底的表面上形成界面层223(interface layer，IL)。所述界面层223可以为热氧化物层、氮的氧化物层、化学氧化物层或者其他适合的薄膜层。可以采用CVD，ALD或者PVD等适合的工艺形成界面层，例如可以通过高温纯氧热氧化形成界面层。界面层的厚度范围可以为0.8nm～1.5nm，示例性的，例如1nm。界面层可增加高K介电层与衬底或硅锗层之间的粘着度，且具有防止漏电的功能。 在其他实施例中，所述界面层包括第一界面层和第二界面层，所述第一界面层位于所述锗硅层的表面上，所述第二界面层位于所述凹槽结构的另一侧的衬底的表面上；所述第二界面层的厚度大于或者等于所述第一界面层的厚度，且位于所述第二界面层的上表面与所述填充层218的上表面齐平。所述第二界面层的上表面与所述填充层的上表面齐平，可以进一步降低沉积金属布线和膜层沉积的工艺难度，使得器件的性能更加稳定。
在一些实施例中，在位于所述凹槽结构形成硅锗层的一侧形成PMOS(P型金属氧化物半导体)，在位于所述凹槽结构的另一侧形成NMOS(N型金属氧化物半导体)。在实际操作中，可以先形成PMOS再形成NMOS，也可以先形成NMOS再形成PMOS。如此，由PMOS和NMOS构成CMOS(互补金属氧化物半导体)集成电路，PMOS中的金属原子在高K介电层与IL界面处形成偶极子(dipole)，联合SiGe结构作为沟道共同作用，可有效调节PMOS的阈值电压。另一方面，由于消除了边沟，在之后的高K介电层生长和功函数金属生长的过程中不会出现不连续断裂的情况以及器件的沟道表面被损伤的情况，避免CMOS性能的漂移和不稳定。
本公开实施例还提供了一种半导体结构，如附图3所示，所述半导体结构包括：衬底201，所述衬底包括凹槽结构203；隔离电介质204，所述隔离电介质204填充于所述凹槽结构，所述隔离电介质204包括依次覆盖在所述凹槽结构203底面和侧壁的第一隔离层205、第二隔离层207和第三隔离层209；其中，所述第一隔离层205的上表面低于所述第二隔离层207和所述衬底201的上表面从而构成边沟211；填充层218，所述填充层218填充所述边沟211，所述填充层的上表面与所述第二隔离层的上表面以及所述第三隔离层的上表面齐平，且所述填充层218的上表面高于所述衬底201的上表面。由于填充层218填充所述边沟211，避免边沟影响器件的电学特性，同时降低了后续工艺难度，例如清洗、金属布线和膜层沉积等。
在一些实施例中，如附图3所示，所述半导体结构还包括：硅锗层217，所述硅锗层217位于所述凹槽结构203一侧的所述衬底的表面上，且所述锗硅 层217的上表面高于所述填充层218的上表面。所述硅锗层用于形成PMOS的沟道，硅锗层应力机制对驱动电流有较大的改善作用，硅锗层由于应力作用可提高沟道载流子的迁移率，有利于调节阈值电压。在实际操作中，可以采用化学气相外延(CVD)、选择性气相外延等技术沉积硅锗层217。
在一些实施例中，如附图3所示，所述半导体结构还包括：界面层223，所述界面层223包括第一界面层和第二界面层，所述第一界面层位于所述锗硅层的表面上，所述第二界面层位于所述凹槽结构的另一侧的衬底的表面上。所述界面层223可以为热氧化物层、氮的氧化物层、化学氧化物层或者其他适合的薄膜层。可以采用CVD，ALD或者PVD等适合的工艺形成界面层，例如可以通过高温纯氧热氧化形成界面层。界面层的厚度范围可以为0.8nm～1.5nm，示例性的，例如1nm。界面层可增加高K介电层与衬底或硅锗层之间的粘着度，且具有防止漏电的功能。在其他实施例中，所述第二界面层的厚度不小于所述第一界面层的厚度，且位于所述第二界面层的上表面与所述填充层218的上表面齐平。所述第二界面层的上表面与所述填充层的上表面齐平，可以进一步降低沉积金属布线和膜层沉积的工艺难度，使得器件的性能更加稳定。
在一些实施例中，所述半导体结构还包括：PMOS，所述PMOS位于所述凹槽结构的一侧，所述PMOS的沟道包括硅锗层；NMOS，所述NMOS位于所述凹槽结构的另一侧。如此，由PMOS和NMOS构成CMOS(互补金属氧化物半导体)集成电路，PMOS中的金属原子在高K介电层与IL界面处形成偶极子(dipole)，联合SiGe结构作为沟道共同作用，可有效调节PMOS的阈值电压。另一方面，由于消除了边沟，在之后的高K介电层生长和功函数金属生长的过程中不会出现不连续断裂的情况以及器件的沟道表面被损伤的情况，避免CMOS性能的漂移和不稳定。在实际操作中，所述POMS还包括高K介电层以及氮化钛、氧化铝和氮化钛的叠层结构；所述NOMS还包括高K介电层以及氧化镧和氮化钛的叠层结构。通过设置不同的栅极堆叠材料，通过使得后续形成相应的PMOS和NMOS的性能参数可控，可以自由设置和调配栅极材料的功函数值，充分控制阈值电压。
综上所述，在本公开实施例中，首先通过保护层保护衬底，再形成填充所述边沟的填充层，消除了边沟，避免边沟影响器件的电学特性，同时降低了后续金属布线和膜层沉积的工艺难度。
需要说明的是，本公开实施例提供的半导体结构及其形成方法可以应用于任何包括该结构的集成电路中。各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。本领域技术人员能够对上述形成方法步骤顺序进行变换而并不离开本公开的保护范围，本公开实施例中的各步骤在不冲突的情况下，部分步骤可以同时执行，也可以调用先后顺序执行。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供了一种半导体结构的制备方法，包括：提供衬底，所述衬底包括凹槽结构；在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟；在位于所述凹槽结构两侧的所述衬底表面上形成保护层；形成填充所述边沟的填充层，所述填充层的上表面与所述保护层的上表面齐平。本公开首先通过保护层保护衬底，再形成填充所述边沟的填充层，消除了边沟，避免边沟影响器件的电学特性，同时降低了后续金属布线和膜层沉积的工艺难度。

Claims (18)

  1. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底包括凹槽结构；
    在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟；
    在位于所述凹槽结构两侧的所述衬底表面上形成保护层；
    形成填充所述边沟的填充层，所述填充层的上表面与所述保护层的上表面齐平。
  2. 根据权利要求1所述的制备方法，其中，所述形成填充所述边沟的填充层，包括：
    采用原子层沉积工艺在所述衬底的上方沉积填充层；
    平面化所述填充层使得所述填充层的上表面与所述保护层的上表面齐平。
  3. 根据权利要求1所述的制备方法，在位于所述凹槽结构两侧的所述衬底表面上形成保护层之前，还包括；
    刻蚀部分所述第一隔离层。
  4. 根据权利要求1所述的制备方法，其中，所述填充层的材料与所述第二隔离层的材料相同。
  5. 根据权利要求1-4任一项所述的制备方法，形成填充所述边沟的填充层后，还包括：
    去除所述保护层，暴露出衬底；
    在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层。
  6. 根据权利要求5所述的制备方法，在位于所述凹槽结构一侧的所述衬底的表面上形成硅锗层之后，还包括：
    在所述衬底的上方沉积高K介电层；
    在位于凹槽结构形成硅锗层的一侧的高K介电层上方形成第一栅极堆叠， 在位于凹槽结构另一侧的高K介电层上方形成第二栅极堆叠，所述第一栅极堆叠和所述第二栅极堆叠的材料不同。
  7. 根据权利要求6所述的制备方法，其中：
    所述第一栅极堆叠包括氮化钛、氧化铝和氮化钛的叠层结构，所述第二栅极堆叠包括氧化镧和氮化钛的叠层结构。
  8. 根据权利要求6所述的制备方法，在所述衬底的上方沉积高K介电层之前，还包括：
    在所述硅锗层的表面和位于所述凹槽结构另一侧的所述衬底的表面上形成界面层。
  9. 根据权利要求6所述的制备方法，其中，在位于所述凹槽结构形成硅锗层的一侧形成PMOS，在位于所述凹槽结构的另一侧形成NMOS。
  10. 根据权利要求1所述的制备方法，其中，所述在所述凹槽结构的底部与侧壁上依次形成第一隔离层、第二隔离层和第三隔离层，包括：
    在所述衬底的上方依次沉积第一隔离层、第二隔离层和第三隔离层；
    以衬底的表面为停止层平坦化所述第一隔离层、第二隔离层和第三隔离层。
  11. 根据权利要求2所述的制备方法，其中，平面化所述填充层使得所述填充层的上表面与所述保护层的上表面齐平，包括：
    采用湿法刻蚀工艺刻蚀所述填充层，所述湿法刻蚀工艺的湿法刻蚀剂包括磷酸。
  12. 根据权利要求11所述的制备方法，其中，所述湿法刻蚀工艺的温度控制在155摄氏度至165摄氏度。
  13. 一种半导体结构，包括：
    衬底，所述衬底包括凹槽结构；
    隔离电介质，所述隔离电介质填充于所述凹槽结构中，所述隔离电介质包括依次覆盖在所述凹槽结构底面和侧壁的第一隔离层、第二隔离层和第三隔离层，其中，所述第一隔离层的上表面低于所述第二隔离层和所述衬底的上表面从而构成边沟；
    填充层，所述填充层填充所述边沟，所述填充层的上表面与所述第二隔离层的上表面以及所述第三隔离层的上表面齐平，且所述填充层的上表面高于所述衬底的上表面。
  14. 根据权利要求13所述的半导体结构，还包括：
    硅锗层，所述硅锗层位于所述凹槽结构一侧的所述衬底的表面上，且所述锗硅层的上表面高于所述填充层的上表面。
  15. 根据权利要求14所述的半导体结构，还包括：
    界面层，所述界面层包括第一界面层和第二界面层，所述第一界面层位于所述锗硅层的表面上，所述第二界面层位于所述凹槽结构的另一侧的衬底的表面上。
  16. 根据权利要求15所述的半导体结构，其中，所述第二界面层的厚度不小于所述第一界面层的厚度，且所述第二界面层的上表面与所述填充层的上表面齐平。
  17. 根据权利要求13-16任一项所述的半导体结构，还包括：
    PMOS，所述PMOS位于所述凹槽结构的一侧，所述PMOS的沟道包括硅锗层；
    NMOS，所述NMOS位于所述凹槽结构的另一侧。
  18. 根据权利要求17所述的半导体结构，其中，
    所述POMS还包括高K介电层以及氮化钛、氧化铝和氮化钛的叠层结构；所述NOMS还包括高K介电层以及氧化镧和氮化钛的叠层结构。
PCT/CN2022/136132 2022-01-24 2022-12-02 一种半导体结构及其制备方法 WO2023138228A1 (zh)

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US6352897B1 (en) * 1999-06-09 2002-03-05 United Microelectronics Corp. Method of improving edge recess problem of shallow trench isolation
US20020064912A1 (en) * 1999-07-16 2002-05-30 Shigeki Komori Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device
US20020168850A1 (en) * 2001-04-25 2002-11-14 Sung-Hoan Kim Method of forming shallow trench isolation and method of manufacturing a semiconductor device using the same
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