WO2023137777A1 - 半导体装置、半导体设备和半导体工艺方法 - Google Patents

半导体装置、半导体设备和半导体工艺方法 Download PDF

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WO2023137777A1
WO2023137777A1 PCT/CN2022/073836 CN2022073836W WO2023137777A1 WO 2023137777 A1 WO2023137777 A1 WO 2023137777A1 CN 2022073836 W CN2022073836 W CN 2022073836W WO 2023137777 A1 WO2023137777 A1 WO 2023137777A1
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Prior art keywords
electrostatic chuck
power supply
wafer
voltage
supply unit
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PCT/CN2022/073836
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English (en)
French (fr)
Inventor
刘志强
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长鑫存储技术有限公司
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Priority to US17/664,248 priority Critical patent/US20230230816A1/en
Publication of WO2023137777A1 publication Critical patent/WO2023137777A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32853—Hygiene
    • H01J37/32862—In situ cleaning of vessels and/or internal parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H05F3/02—Carrying-off electrostatic charges by means of earthing connections

Definitions

  • the present disclosure relates to the technical field of semiconductor manufacturing technology, and in particular, to a semiconductor device, semiconductor equipment and a semiconductor processing method.
  • an electrostatic chuck (ESC) is usually used to fix the wafer, and a processing gas and a specific electric field are introduced into the chamber, so that the processing gas generates plasma under the excitation of the electric field, so as to perform plasma processing on the wafer.
  • ESC electrostatic chuck
  • the side walls and top of the chamber are prone to adhere to the film layer formed in the deposition process.
  • a semiconductor device According to various embodiments of the present application, a semiconductor device, a semiconductor device, and a semiconductor processing method are provided.
  • the first aspect of the present application provides a semiconductor device, including: a power supply unit, including a ground terminal and a voltage output terminal, the power supply unit is used to provide an operating voltage and a charge release voltage, and the charge release voltage is lower than the operating voltage; an electrostatic chuck is connected to the power supply unit, and is used to absorb a wafer when the power supply unit provides an operating voltage; The electrostatic chuck is connected to the power supply unit for a preset time to release part of the charge accumulated on the electrostatic chuck to avoid abnormal discharge; and after the preset time, switch the electrostatic chuck to connect with the protection resistor.
  • the resistance of the power supply unit is smaller than the resistance of the protection resistor.
  • the resistance of the protective resistor ranges from 3K ohms to 5K ohms.
  • the power supply unit includes a first DC unit and a second DC unit, and both the first DC unit and the second DC unit include a positive output terminal and a negative output terminal; the positive output terminal of the first DC unit and the negative output terminal of the second DC unit together form a voltage output terminal.
  • the semiconductor device further includes: a capacitance-inductance matching unit, located between the relay unit and the electrostatic chuck, and connected to the relay unit and the electrostatic chuck.
  • the second aspect of the present application discloses a semiconductor device, including the semiconductor device in the foregoing embodiments.
  • the semiconductor device further includes a process chamber, and the electrostatic chuck is located in the process chamber.
  • the semiconductor equipment includes plasma processing equipment.
  • the third aspect of the present application discloses a semiconductor processing method.
  • the method is applied to the semiconductor device in the foregoing embodiments.
  • the method includes a wafer adsorption stage and a wafer release and charge release stage, wherein the wafer adsorption stage includes: the power supply unit outputs an operating voltage to the electrostatic chuck to control the electrostatic chuck to absorb the wafer; the wafer release and charge release stage includes: the voltage output by the power supply unit is adjusted from the operating voltage to the charge release voltage, and maintained for a first preset time, so as to release part of the charges accumulated on the electrostatic chuck to avoid abnormal discharge; The protection resistor is connected and maintained for a second preset time to discharge the residual charge accumulated on the electrostatic chuck.
  • the operating voltage ranges from 3kV to 4kV
  • the charge release voltage ranges from 0 to 200V.
  • the range of the first preset time is 0.1 second to 1 second, and the range of the second preset time is 4 seconds to 4.9 seconds.
  • a process stage is further included between the wafer adsorption stage and the wafer release and charge release stage, and the process stage includes: performing process operations on the wafer.
  • the process stage includes bombarding the wafer with plasma.
  • the semiconductor equipment further includes a process chamber, and the electrostatic chuck is located in the process chamber; before the wafer adsorption stage, it also includes: an equipment preparation stage, and the equipment preparation stage includes: introducing protective gas into the process chamber.
  • a cleaning stage is further included, and the cleaning stage includes: injecting cleaning gas into the process chamber to clean the process chamber.
  • both the shielding gas and the sweeping gas include reducing gas.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the relay unit and the power supply unit cooperate with each other to keep the electrostatic chuck connected to the power supply unit within a preset time after the power supply unit adjusts the working voltage to the charge release voltage, so that a large amount of charge accumulated on the electrostatic chuck can be quickly released through the ground circuit of the power supply unit first, and then the electrostatic chuck is connected to the protection resistor after the preset time to release the remaining charge, reducing the arc discharge phenomenon caused by excessive charge at the initial stage of discharge and slow discharge speed.
  • the formation of impurity particles on the side wall of the chamber improves the wafer yield.
  • FIG. 1 is a schematic diagram of a circuit structure of a semiconductor device in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a circuit structure in which an electrostatic chuck is connected to a power supply voltage in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a circuit structure in which an electrostatic chuck is connected to a protection resistor in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a circuit structure of a semiconductor device in another embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a semiconductor device in an embodiment of the present application.
  • FIG. 6 is a flowchart of a semiconductor process method in an embodiment of the present application.
  • connection or “connected” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection, or an indirect connection through an intermediary, or an internal connection between two components.
  • connection or “connected” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection, or an indirect connection through an intermediary, or an internal connection between two components.
  • an electrostatic chuck (ESC) is usually used to fix the wafer.
  • ESC electrostatic chuck
  • the processing gas By passing a processing gas into the chamber and providing a specific electric field, the processing gas generates plasma under the excitation of the electric field to perform deposition and etching processes on the wafer.
  • the side wall and the top of the chamber are prone to adhere to the film layer formed in the deposition process.
  • an embodiment of the present application provides a semiconductor device, as shown in Figure 1, comprising: a power supply unit 11, including a ground terminal and a voltage output terminal, the power supply unit 11 is used to provide an operating voltage and a charge release voltage, and the charge release voltage is less than the operating voltage; an electrostatic chuck 12 is connected to the power supply unit 11, and is used to absorb a wafer when the power supply unit 11 provides an operating voltage; When the voltage is high, the electrostatic chuck 12 is connected to the power supply unit 11; when the power supply unit 11 provides the charge release voltage, the electrostatic chuck 12 is connected to the power supply unit 11 for a preset time, so as to release part of the charge accumulated on the electrostatic chuck 12 and avoid abnormal discharge; and after the preset time, switch the electrostatic chuck 12 to be connected to the protection resistor 13.
  • the above-mentioned semiconductor device, the relay unit 14 and the power supply unit 11 cooperate with each other to keep the electrostatic chuck 12 connected to the power supply unit 11 within a preset time after the power supply unit 11 adjusts the working voltage to the charge release voltage, so that a large amount of charges accumulated on the electrostatic chuck 12 can be quickly released through the grounding loop of the power supply unit 11, and then the electrostatic chuck 12 is connected to the protective resistor 13 after the preset time, and the remaining charge is released, which reduces the arc discharge phenomenon caused by excessive charge in the initial stage of discharge and slow discharge speed, thereby reducing electric current.
  • the arc discharge damages the surface of the wafer, and also reduces the arc hitting the side wall of the reaction chamber to form impurity particles, which improves the yield of the wafer.
  • the power supply unit 11 may be a high-voltage direct current unit, and may provide an operating voltage or a charge discharge voltage to an electrostatic chuck 12 (electrostatic chuck, ESC). Wherein, when the power supply unit 11 supplies an operating voltage to the electrostatic chuck 12, the electrostatic chuck 12 can absorb and fix the wafer placed on its surface. When the power supply unit 11 supplies the electrostatic chuck 12 with a charge release voltage, the electrostatic chuck 12 no longer attracts the wafer, so that the wafer can be moved to other positions.
  • the relay unit 14 in this embodiment can keep the electrostatic chuck 12 connected to the power supply unit 11 for a preset time when the power supply unit 11 is adjusted from the working voltage to the discharge voltage.
  • the electrostatic chuck 12 After a preset time, the electrostatic chuck 12 is switched to be connected to the protection resistor 13 . Wherein, within a preset time after the power supply unit 11 is adjusted from the working voltage to the charge release voltage, a large amount of charges accumulated in the electrostatic chuck 12 can be quickly released through the ground terminal of the power supply unit 11 . After the preset time, most of the charges in the electrostatic chuck 12 have been released. At this time, the electrostatic chuck 12 is transferred to the protection resistor 13 for subsequent charge release, the probability of arc discharge is greatly reduced, and the situation of arc discharge damage to the wafer surface or hitting the side wall of the reaction chamber is reduced, and the wafer yield rate is improved.
  • the resistance of the internal resistance of the power supply unit 11 is smaller than the resistance of the protection resistor 13 .
  • the resistance value of the protection resistor 13 may be, for example, 3 kohms to 5 kohms, such as 3000 ohms, 3500 ohms, 4000 ohms or 5000 ohms.
  • the resistance value of the power supply unit 11 may be, for example, 500 ohms to 1000 ohms, such as 500 ohms, 700 ohms or 1000 ohms.
  • the power supply unit 11 includes a first DC unit 111 and a second DC unit 112
  • the first DC unit 111 includes a first positive output terminal 111a and a first negative output terminal 111b
  • the second DC unit 112 includes a second positive output terminal 112a and a second negative output terminal 112b
  • the first positive output terminal 111a and the second negative output terminal 112b together form the voltage output terminal of the power supply unit 11.
  • the first positive output terminal 111a of the first DC unit 111 outputs a DC voltage of +1.8kv
  • the second negative output terminal 112b of the second DC unit 112 outputs a DC voltage of -1.8kV.
  • the operating voltage output by the power supply unit 11 is 3.6kV, and the electrostatic chuck 12 adsorbs and fixes the wafer.
  • the internal circuit of the relay unit 14 remains unchanged, so that the electrostatic chuck 12 is connected to the power supply unit 11 for a preset time, as shown in FIG.
  • the internal circuit of the relay unit 14 is adjusted to the circuit shown in FIG. 3 , and the electrostatic chuck 12 is switched to be connected to the protective resistor 13.
  • the probability of arc discharge is greatly reduced.
  • the preset time may be 0.1s
  • the charge release voltage may be 0V
  • the output voltages of the first positive output terminal 111a of the first DC unit 111 and the second negative output terminal 112b of the second DC unit 112 are both 0V.
  • the charge release voltage can be any voltage value between 0V and 200V, such as 0V, 10V, 50V, 100V, 150V or 200V.
  • the first positive output terminal 111a outputs a DC voltage of +5V
  • the second negative output terminal 112b outputs a DC voltage of -5V
  • the first positive output terminal 111a outputs a DC voltage of +25V
  • the second negative output terminal 112b outputs a DC voltage of -25V.
  • the preset time may be any time value from 0.1s to 1s, such as 0.1s, 0.3s, 0.5s or 1s.
  • the semiconductor device further includes a capacitance-inductance matching unit 15 located between the relay unit 14 and the electrostatic chuck 12 and connected to the relay unit 14 and the electrostatic chuck 12 .
  • the capacitance-inductance matching unit 15 can transmit the electric energy provided by the power supply unit 11 to the electrostatic chuck 12 to the greatest extent, reducing the loss of electric energy.
  • the semiconductor device may include a process chamber 21 , and an electrostatic chuck 12 is located in the process chamber 21 for fixing the wafer 30 in the process chamber 21 .
  • the semiconductor device may be a plasma processing device, such as an inductively coupled plasma device (Inductive Coupled Plasma, ICP).
  • ICP Inductive Coupled Plasma
  • a plasma process such as an argon plasma process or a hydrogen plasma process, can be performed on the wafer 30 .
  • the semiconductor device further includes a first radio frequency power supply RF1 and a second radio frequency power supply RF2.
  • the first radio frequency power source RF1 can generate a radio frequency power signal, and generate an induced electric field in the process chamber 21 through an induction coil, and excite the process gas flowing into the chamber into plasma.
  • the second radio frequency unit RF2 is connected to the electrostatic chuck 12 carrying the wafer 30 , and is used to generate a negative bias voltage on the surface of the wafer 30 to attract plasma to move toward the wafer 30 .
  • the semiconductor device further includes an impedance matcher 25 (RF match), and the second radio frequency unit RF2 is connected to the electrostatic chuck 12 through the impedance matcher 25 .
  • the impedance matching device 25 is used to reduce the output power loss of the second radio frequency power supply RF2.
  • the working frequency of the first radio frequency power supply RF1 is 12.5Mhz
  • the working frequency of the second radio frequency power supply RF2 is 13.56Mhz.
  • the semiconductor device further includes a cold trap 23 and a vacuum pump 24 .
  • the cold trap 23 can also be called a cold trap, and the temperature can be set to 120K, for example, to condense and adsorb the water vapor generated in the process chamber 21 .
  • the vacuum pump 24 is used to extract gas and plasma in the process chamber 21 .
  • the cold trap 23 and the vacuum pump 24 cooperate with each other to extract some particles and water vapor generated in the process chamber 21 to form a vacuum environment in the process chamber 21 .
  • the semiconductor device shown in FIG. 5 can be used to perform a hydrogen plasma process, and the complete process flow can be referred to Table 1.
  • Step represents the step number; Time represents the duration of each step; ESC represents the electrostatic chuck, RF1 is the first radio frequency power supply, RF2 is the second radio frequency power supply, the last column represents the hydrogen gas feed rate, sccm is the volume flow unit, that is, the standard liter per minute flow value (standard liter per minute).
  • steps 1-3 are the machine preparation stage in the hydrogen plasma process. It can be seen from Table 1 that during the machine preparation stage, the electrostatic chuck 12 is always in a release state, and has not yet attracted the wafer 30 . The first radio frequency power supply RF1 and the second radio frequency power supply RF2 are not powered on yet. At this time, no hydrogen gas has been injected into the process chamber 21 . Exemplarily, the duration of the machine preparation stage is 7s.
  • the power supply unit 11 starts to supply power to the electrostatic chuck 12 for fixing the wafer 30, and the power supply voltage is kept between 1.6kv and 3.6kv. Moreover, at this stage, hydrogen gas is introduced into the chamber, the process chamber 21 is filled with hydrogen gas, and the air in the process chamber 21 is completely exhausted.
  • the rate of feeding hydrogen may be 170 sccm.
  • the feed rate of hydrogen can be adjusted according to process requirements.
  • Step 5 and Step 6 the output voltage of the power supply unit 11 is stabilized at 3.6 kV.
  • the first radio frequency power supply RF1 is turned on to form an induction electric field in the process chamber 21 to generate plasma by using hydrogen gas.
  • the working power of the first radio frequency power supply RF1 can be 1900W, and the frequency of the working voltage is 12.5Mhz.
  • the duration of Step 5 and Step 6 is 3 s, during which hydrogen gas is continuously fed into the process chamber 21 at a rate of 170 sccm.
  • the second radio frequency power supply RF2 is powered on to generate an adsorption electric field in the process chamber 21 to attract plasma to the surface of the wafer 30 .
  • the working power of the second radio frequency power supply RF2 may be 450W, and the frequency of the working voltage is 13.56Mhz.
  • the duration of steps 7 and 8 may be, for example, 12s.
  • hydrogen gas is continuously fed into the process chamber 21 at a rate of 170 sccm, and the first radio frequency power supply RF1 continues to provide an induction electric field with a working power of 1900W, and the power supply unit 11 continuously provides 3.6KV high-voltage direct current to the electrostatic chuck 12 to fix the wafer 30.
  • the electrostatic chuck 12 accumulates a large amount of charge during this process.
  • Step 9 is the charge release stage.
  • the second radio frequency power supply RF2 stops working, the adsorption electric field no longer exists in the process chamber 21 , and the plasma no longer bombards the surface of the wafer 30 .
  • the hydrogen gas continues to flow into the process chamber 21, and the first radio frequency power source RF1 is also kept in a normal working state.
  • the charge release phase can be divided into a first phase and a second phase.
  • the power supply unit 11 remains connected to the electrostatic chuck 12 , as shown in FIG. 2 .
  • the output voltage of the power supply unit 11 is a charge discharge voltage (for example, 0V ⁇ 200V). It can be seen from Table 1 that the charge release voltage is 0V, so the first positive output terminal 111a of the first DC unit 111 outputs 0V; the second negative output terminal 112b of the second DC unit 112 outputs 0V.
  • the first stage may be called a rapid discharge stage, for example, the first stage lasts for 0.1 second.
  • the second phase may be called a normal discharge phase.
  • the relay unit 14 switches the circuit connection relationship, and switches the electrostatic chuck 12 to be connected to the protection resistor 13 , as shown in FIG. 3 .
  • the charge remaining on the electrostatic chuck 12 is discharged through the protection resistor 13 .
  • the second stage lasts for 4.9s.
  • the amount of charge on the electrostatic chuck 12 is no longer enough to generate arc discharge, which reduces the occurrence probability of arc discharge, reduces the damage to the surface of the wafer 30 by the arc discharge, and reduces the situation that the arc hits the side wall of the reaction chamber to form impurity particles.
  • step 10 the first radio frequency power supply RF1 stops working and no longer generates plasma. At the same time, continue to feed hydrogen gas at a rate of 170 sccm, use the continuously fed hydrogen gas to purge the residual plasma in the chamber and use the vacuum pump 24 to remove it. Exemplarily, the duration of step 10 is 2s.
  • step 11 ends the whole process flow.
  • the plasma gas when using the semiconductor device shown in FIG. 5 to perform the plasma process, can be selected according to actual needs, the duration of each step can be adjusted, and the duration of the first stage and the second stage in the charge release stage can be adjusted.
  • An embodiment of the present application also discloses a semiconductor process method, as shown in FIG. 6, the method is applied to the semiconductor device in the foregoing embodiment, including:
  • S10 wafer adsorption stage: the power supply unit 11 outputs a working voltage to the electrostatic chuck 12 to control the electrostatic chuck 12 to adsorb the wafer;
  • S20 Wafer release and charge release stage: the voltage output by the power supply unit 11 is adjusted from the operating voltage to the charge release voltage, and maintained for a first preset time to release part of the charge accumulated on the electrostatic chuck 12 to avoid abnormal discharge; switch the electrostatic chuck 12 to be connected to the protection resistor 13, and maintain it for a second preset time to release the remaining charge accumulated on the electrostatic chuck 12.
  • step S10 the semiconductor device works in the wafer adsorption stage, and the power supply unit 11 outputs a working voltage of 3kV-4kV to the electrostatic chuck 12 to control the electrostatic chuck 12 to adsorb the wafer.
  • the working voltage may be 3000V, 3600V or 4000V.
  • the connection relationship between the power supply unit 11 and the electrostatic chuck 12 is shown in FIG. 2 .
  • step S20 the semiconductor device is working in the phases of wafer release and charge release, and the output voltage of the power supply unit 11 is adjusted from the working voltage to the charge release voltage and maintained for a first preset time.
  • the charge release voltage may be 0-200V, such as 0V, 10V, 50V, 100V, 150V or 200V.
  • the first preset time may be 0.1 second to 1 second, for example, 0.1 second, 0.2 second, 0.5 second or 1 second.
  • the voltage generated by the charge accumulated on the electrostatic chuck 12 is much greater than the charge release voltage provided by the power supply unit 11, and, because the internal impedance of the power supply unit 11 is small, the charge accumulated on the electrostatic chuck 12 can be quickly released through the ground terminal of the power supply unit 11.
  • the electrostatic chuck 12 is switched to be connected to the protection resistor 13 and maintained for a second preset time, as shown in FIG. 3 .
  • the second preset time may be 4 seconds to 4.9 seconds, such as 4 seconds, 4.5 seconds, 4.8 seconds or 4.9 seconds.
  • the electrostatic chuck 12 is kept connected to the power supply unit 11 during the wafer release and charge release stages, and lasts for a first preset time, so that most of the charges accumulated on the electrostatic chuck 12 are released through the ground terminal of the power supply unit 11. Since the resistance value of the internal resistance of the power supply unit 11 is smaller than the resistance value of the protection resistor 13, the discharge current is larger, and a large amount of charge can be released in a short time. After the first preset time, the electrostatic chuck 12 is connected to the protective resistor 13 to release the remaining charge.
  • the probability of arc discharge is greatly reduced, which reduces the damage of the wafer surface by the arc discharge, and also reduces the impact of the arc on the impurity layer adhered to the side wall of the reaction chamber to form impurity particles, thereby improving the wafer yield.
  • the probability of arc discharge is reduced, downtime for troubleshooting can be reduced, ensuring smooth production of products.
  • the sum of the first preset time and the second preset time is a fixed value, such as 5s.
  • a process stage is further included between the wafer adsorption stage and the wafer release and charge release stage, and the process stage includes: performing process operations on the wafer.
  • the process operations may include bombarding the wafer with plasma.
  • plasma can be used to bombard the wafer surface to remove specific film layers or impurities on the wafer surface.
  • the plasma may include hydrogen plasma, argon plasma, or other plasmas.
  • the process operation may also include a plasma deposition process to deposit a film layer on the surface of the wafer.
  • an equipment preparation stage is also included prior to the wafer adsorption stage.
  • the equipment preparation stage may be, for example, introducing a shielding gas into the process chamber 21, and the shielding gas may include inert gas, argon or hydrogen.
  • the shielding gas may include inert gas, argon or hydrogen.
  • a cleaning stage is further included, and the cleaning stage includes: injecting cleaning gas into the process chamber to clean the process chamber.
  • the shielding gas and the sweeping gas are reducing gases, such as hydrogen.
  • the above semiconductor process method can be applied to ULVAC Entron EX-W300 equipment or the process chamber of ENI/2000 and ENI1250.
  • the optimal process flow of hydrogen plasma provided by some ICP equipment manufacturers can be improved to reduce the probability of arc discharge in the electrostatic chuck during the wafer release stage and improve product yield.

Abstract

一种半导体装置、半导体设备和半导体工艺方法。该半导体工艺方法包括晶圆吸附阶段及晶圆释放与电荷释放阶段，其中，晶圆吸附阶段包括：供电单元向静电卡盘输出工作电压，以控制静电卡盘吸附晶圆；晶圆释放与电荷释放阶段包括：供电单元输出的电压由工作电压调整为电荷释放电压，并保持第一预设时间，以释放掉静电卡盘上积累的部分电荷，避免异常放电；将静电卡盘切换至与保护电阻相连接，并保持第二预设时间，以释放静电卡盘上积累的剩余电荷。上述半导体工艺方法，可以减少电弧放电现象，提高晶圆良率。

Description

半导体装置、半导体设备和半导体工艺方法
相关申请的交叉引用
本申请要求于2022年01月19日提交中国专利局、申请号为202210060483.9的中国专利的优先权，所述专利申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体制备工艺的技术领域，特别是涉及一种半导体装置、半导体设备和半导体工艺方法。
背景技术
在等离子体处理装置中，通常使用静电卡盘(ESC)来固定晶圆，通过向腔室中通入处理气体和特定的电场，使得处理气体在电场的激励下产生等离子体，以对晶圆实施等离子体处理。然而，腔室侧壁和顶部容易附着有沉积工艺中形成的膜层。
传统的等离子体工艺过程中，在静电卡盘去电的过程中，处理腔室中容易发生异常放电的现象，导致腔室侧壁和顶壁沉积的膜层发生脱落，在晶圆表面形成污染粒子，影响产品良率。
发明内容
根据本申请的各种实施例，提供一种半导体装置、半导体设备和半导体工艺方法。
根据一些实施例，本申请第一方面提供一种半导体装置，包括：供电单元，包括接地端和电压输出端，供电单元用于提供工作电压及电荷释放电压，电荷释放电压小于工作电压；静电卡盘，与供电单元相连接，用于在供电单 元提供工作电压时吸附晶圆；释放晶圆后，静电卡盘上积累有电荷；保护电阻，与接地端相连接；继电器单元，在供电单元提供工作电压时，将静电卡盘与供电单元相连接；在供电单元提供电荷释放电压时，将静电卡盘与供电单元连接预设时间，以释放掉静电卡盘上积累的部分电荷，避免异常放电；并在预设时间后，将静电卡盘切换至与保护电阻相连接。
在其中一个实施例中，供电单元的阻值小于保护电阻的阻值。
在其中一个实施例中，保护电阻的阻值范围是3千欧姆至5千欧姆。
在其中一个实施例中，供电单元包括第一直流单元和第二直流单元，第一直流单元及第二直流单元均包括正向输出端及负向输出端；第一直流单元的正向输出端和第二直流单元的负向输出端共同组成电压输出端。
在其中一个实施例中，半导体装置还包括：电容电感匹配单元，位于继电器单元与静电卡盘之间，并与继电器单元及静电卡盘相连接。
根据一些实施例，本申请第二方面公开了一种半导体设备，包括前述实施例中的半导体装置。
在其中一个实施例中，半导体设备还包括工艺腔室，静电卡盘位于工艺腔室内。
在其中一个实施例中，半导体设备包括等离子体工艺设备。
根据一些实施例，本申请第三方面公开了一种半导体工艺方法，该方法应用于前述实施例中的半导体设备，该方法包括晶圆吸附阶段及晶圆释放与电荷释放阶段，其中，晶圆吸附阶段包括：供电单元向静电卡盘输出工作电压，以控制静电卡盘吸附晶圆；晶圆释放与电荷释放阶段包括：供电单元输出的电压由工作电压调整为电荷释放电压，并保持第一预设时间，以释放掉静电卡盘上积累的部分电荷，避免异常放电；将静电卡盘切换至与保护电阻相连接，并保持第二预设时间，以释放静电卡盘上积累的剩余电荷。
在其中一个实施例中，工作电压的范围是3kV～4kV，电荷释放电压的范围是0～200V。
通过将电荷释放电压调低，可以使其远低于静电卡盘中积累的电荷形成 的电压，便于静电卡盘通过供电单元的接地端释放电荷。
在其中一个实施例中，第一预设时间的范围是0.1秒～1秒，第二预设时间的范围是4秒～4.9秒。
在其中一个实施例中，晶圆吸附阶段和晶圆释放与电荷释放阶段之间还包括工艺阶段，工艺阶段包括：对晶圆执行工艺操作。
在其中一个实施例中，工艺阶段包括：使用等离子体轰击晶圆。
在其中一个实施例中，半导体设备还包括工艺腔室，静电卡盘位于工艺腔室内；晶圆吸附阶段之前还包括：设备准备阶段，设备准备阶段包括：向工艺腔室内通入保护气体。
在其中一个实施例中，晶圆释放与电荷释放阶段之后还包括：清扫阶段，清扫阶段包括：向工艺腔室内通入清扫气体，以对工艺腔室进行清扫。
在其中一个实施例中，保护气体及清扫气体均包括还原性气体。
本公开实施例可以/至少具有以下优点：
在上述半导体装置中，继电器单元与供电单元相互配合，可以在供电单元将工作电压调整为电荷释放电压之后的预设时间内，保持静电卡盘与供电单元连接，使得静电卡盘上积累的大量电荷可以先通过供电单元的接地回路快速释放，在预设时间之后再将静电卡盘与保护电阻相连，将剩余的电荷释放，减少了放电初期电荷量过大、放电速度慢所导致的电弧放电现象，进而减少了电弧放电损伤晶圆表面的情况，也减少了电弧击中反应腔室侧壁形成杂质粒子的情况，提高了晶圆良率。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前 提下，还可以根据这些附图获得其他实施例的附图。
图1为本申请一实施例中半导体装置的电路结构示意图。
图2为本申请一实施例中静电卡盘与供电电压相连接的电路结构示意图。
图3为本申请一实施例中静电卡盘与保护电阻相连接的电路结构示意图。
图4为本申请又一实施例中半导体装置的电路结构示意图。
图5为本申请一实施例中半导体设备的结构示意图。
图6为本申请一实施例中半导体工艺方法的流程框图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在描述位置关系时，除非另有规定，否则当一个元件例如层基板被指为在另一膜层“上”时，其能直接在其他膜层上或亦可存在中间膜层。进一步说，当层被指为在另一层“下”时，其可直接在下方，亦可存在一个或多个中间层。亦可以理解的是，当层被指为在两层“之间”时，其可为两层之间的唯一层，或亦可存在一个或多个中间层。本申请所称“上”、“下”是相对于触觉反馈模组在应用过程中与使用者靠近的程度而言，相对靠近使用者的一侧为“上”，相对远离使用者的一侧为“下”。
在使用本文中描述的“包括”、“具有”、和“包含”的情况下，除非使用了明确的限定用语，例如“仅”、“由……组成”等，否则还可以添加另一部件。除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一。
在本申请的描述中，需要说明的是，除非另有明确规定和限定，术语“相连”或“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接连接，亦可以是通过中间媒介间接连接，可以是两个部件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，在本申请的描述中，除非另有说明，“多个”、“相互”、“叠合”、“层叠”和“若干”的含义是两个或两个以上。
在等离子体工艺装置中，通常使用静电卡盘(ESC)来固定晶圆，通过向腔室中通入处理气体并提供特定的电场，使得处理气体在电场的激励下产生等离子体，以对晶圆实施沉积工艺和刻蚀工艺。然而，等离子体工艺装置在经过长期使用之后，腔室侧壁和顶部容易附着有沉积工艺中形成的膜层。
然而，在静电卡盘去电的过程中，等离子体工艺装置的腔室中容易发生电弧放电现象，电弧击中晶圆表面后会对晶圆造成损伤，并且，电弧击中腔室侧壁或顶部附着的膜层后，会产生污染粒子掉落到晶圆表面，影响了晶圆良率。为了解决上述问题，本申请的一个实施例提供了一种半导体装置，如图1所示，包括：供电单元11，包括接地端和电压输出端，供电单元11用于提供工作电压及电荷释放电压，电荷释放电压小于工作电压；静电卡盘12，与供电单元11相连接，用于在供电单元11提供工作电压时吸附晶圆；释放晶圆后，静电卡盘12上积累有电荷；保护电阻13，与接地端相连接；继电器单元14，在供电单元11提供工作电压时，将静电卡盘12与供电单元11相连接；在供电单元11提供电荷释放电压时，将静电卡盘12与供电单元11连接预设时间，以释放掉静电卡盘12上积累的部分电荷，避免异常放电；并在预设时间后，将静电卡盘12切换至与保护电阻13相连接。
上述半导体装置，继电器单元14与供电单元11相互配合，可以在供电单元11将工作电压调整为电荷释放电压之后的预设时间内，保持静电卡盘12与供电单元11相连接，使得静电卡盘12上积累的大量电荷可以先通过供电单元11的接地回路快速释放，在预设时间之后再将静电卡盘12与保护电阻13相连，将剩余的电荷释放，减少了放电初期电荷量过大、放电速度慢所导致的电弧放电现象，进而减少了电弧放电损伤晶圆表面的情况，也减少了电弧击中反应腔室侧壁形成杂质粒子的情况，提高了晶圆良率。
具体地，供电单元11可以是高压直流单元，可以向静电卡盘12(electrostatic chuck，ESC)提供工作电压或电荷释放电压。其中，当供电单元11向静电卡盘12提供工作电压时，静电卡盘12可以将放置在其表面的晶圆吸附固定。而当供电单元11向静电卡盘12提供电荷释放电压时，静电卡盘12则不再吸附晶圆，使得晶圆可以被移动至其他位置。
静电卡盘12在释放晶圆之后，通常会在其表面积累大量电荷，此时，如果直接将静电卡盘12转接至保护电阻13进行接地放电，那么极容易出现电弧放电现象，对晶圆表面造成损伤；并且，电弧放电还容易将工艺腔室侧壁附着的膜层击落，掉落在晶圆表面形成污染颗粒，影响晶圆良率。为了解决上述问题，本实施例中的继电器单元14可以在供电单元11从工作电压调整至电荷释放电压时，保持静电卡盘12与供电单元11连接预设时间。在预设时间之后，再将静电卡盘12切换至与保护电阻13相连接。其中，在供电单元11从工作电压调整至电荷释放电压之后的预设时间内，静电卡盘12中累积的大量电荷可以通过供电单元11的接地端快速释放。在预设时间之后，静电卡盘12中的大部分电荷已经得到了释放，此时将静电卡盘12转接至保护电阻13进行后续的电荷释放，发生电弧放电的概率大大降低，减少了电弧放电损伤晶圆表面或击中反应腔室侧壁的情况，提高了晶圆良率。
在一些实施例中，供电单元11内部电阻的阻值小于保护电阻13的阻值。示例地，保护电阻13的阻值例如可以是3千欧姆至5千欧姆，例如为3000欧姆、3500欧姆、4000欧姆或5000欧姆。供电单元11的阻值例如可以是 500欧姆至1000欧姆，例如可以是500欧姆、700欧姆或1000欧姆。通过将供电单元11的阻值设置为小于保护电阻13的阻值，可以在工作电压调整至电荷释放电压之后的预设时间内形成较大的放电电流，加速电荷的释放。
在一些实施例中，如图2和图3所示，供电单元11包括第一直流单元111和第二直流单元112，第一直流单元111包括第一正向输出端111a和第一负向输出端111b，第二直流单元112包括第二正向输出端112a及第二负向输出端112b，第一正向输出端111a和第二负向输出端112b共同组成供电单元11的电压输出端。
示例地，在图2中，供电单元11提供工作电压时，第一直流单元111的第一正向输出端111a输出+1.8kv的直流电压，第二直流单元112的第二负向输出端112b输出-1.8kV的直流电压，供电单元11输出的工作电压为3.6kV，静电卡盘12将晶圆吸附固定。
示例地，在供电单元11从工作电压调整至电荷释放电压之后的预设时间内，继电器单元14内部的电路保持不变，使得静电卡盘12与供电单元11连接预设时间，如图2所示，静电卡盘12中累积的大量电荷可以通过供电单元11的接地端快速释放。在预设时间之后，继电器单元14内部的电路调整为图3所示电路，静电卡盘12切换至与保护电阻13相连接，此时由于静电卡盘12中的大部分电荷已经得到了释放，即使通过保护电阻13对静电卡盘12进行电荷释放，发生电弧放电的概率也大大降低。示例地，预设时间可以是0.1s，电荷释放电压可以为0V，第一直流单元111的第一正向输出端111a和第二直流单元112的第二负向输出端112b的输出电压均为0V。
在一些实施例中，电荷释放电压可以是0V～200V中间的任意电压值，例如0V、10V、50V、100V、150V或200V。例如，第一正向输出端111a输出+5V的直流电压，第二负向输出端112b输出-5V的直流电压；或者第一正向输出端111a输出+25V的直流电压，第二负向输出端112b输出-25V的直流电压。可选地，预设时间可以是0.1s～1s中任意时间值，例如0.1s、0.3s、0.5s或1s。
在一些实施例中，如图4所示，半导体装置还包括电容电感匹配单元15，位于继电器单元14与静电卡盘12之间，并与继电器单元14及静电卡盘12相连接。电容电感匹配单元15可以将供电单元11提供的电能最大程度传输到静电卡盘12，减少电能的损耗。
本申请的一个实施例还公开了一种半导体设备，包括前述任一实施例中的半导体装置。如图5所示，该半导体设备可以包括工艺腔室21，静电卡盘12位于工艺腔室21中，用于将晶圆30固定在工艺腔室21中。示例地，该半导体设备可以是等离子体工艺设备，例如电感耦合等离子体设备(Inductive Coupled Plasma，ICP)。利用该等离子体工艺设备，可以对晶圆30进行等离子体工艺，例如氩气等离子体工艺或氢气等离子体工艺。
具体地，半导体设备还包括第一射频电源RF1和第二射频电源RF2。其中，第一射频电源RF1可以产生射频功率信号，并通过感应线圈在工艺抢腔室21内产生感应电场，将通入腔室中的工艺气体激发成等离子体。第二射频单元RF2与承载晶圆30的静电卡盘12相连接，用于在晶圆30表面产生负偏压，吸引等离子体朝向晶圆30移动。可选地，半导体设备还包括阻抗匹配器25(RF match)，第二射频单元RF2通过阻抗匹配器25与静电卡盘12相连。阻抗匹配器25用于减少第二射频电源RF2输出功率的损耗。示例地，第一射频电源RF1的工作频率为12.5Mhz，第二射频电源RF2的工作频率为13.56Mhz。
请继续参考图5，半导体设备还包括冷阱23和真空泵24。其中，冷阱23又可以称为冷捕集器，温度例如可以设置为120K，用于将工艺腔室21内产生的水蒸气冷凝吸附。真空泵24用于抽取工艺腔室21内的气体和等离子体。冷阱23和真空泵24相互配合，可以将工艺腔室21内产生的一些粒子和水汽等抽取干净，在工艺腔室21形成真空环境。
作为示例，可以采用图5所示的半导体设备执行氢气等离子体工艺，完整的工艺流程可以参考表1。表1中，Step表示步骤序号；Time表示各个步骤的持续时间；ESC表示静电卡盘，RF1为第一射频电源，RF2为第二射频 电源，最后一列表示氢气的通入速度，sccm为体积流量单位，即标准公升每分钟流量值(standard liter per minute)。
表1
Step Time(sec) ESC on RF1(W) RF2(W) H2(sccm)
1 4 Release 0 0 0
2 1 Release 0 0 0
3 2 Release 0 0 0
4 11 1.6KV-3.6KV 0 0 170
5 2 3.6KV 1900 0 170
6 1 3.6KV 1900 0 170
7 2 3.6KV 1900 450 170
8 10 3.6KV 1900 450 170
9 5 0V→Release 1900 0 170
10 2 Release 0 0 170
11 10 Release 0 0 0
具体地，步骤1-3为氢气等离子体工艺中的机台准备阶段。从表1中可知，在机台准备阶段，静电卡盘12一直处于释放(release)状态，尚未对晶圆30产生吸附。第一射频电源RF1、第二射频电源RF2暂未接通电源。此时也还没有向工艺腔室21中通入氢气。示例地，机台准备阶段的持续时间为7s。
从步骤4开始，供电单元11开始向静电卡盘12供电，用于固定晶圆30，供电电压保持在1.6kv至3.6kv之间。并且，在此阶段开始向腔室内部通入氢气，用氢气充满工艺腔室21，将工艺腔室21中的空气完全排出。示例地，通入氢气的速度可以是170sccm。可选地，可以根据工艺需求调整氢气的通入速度。
在步骤5和步骤6中，供电单元11的输出电压稳定在3.6kV。同时第一射频电源RF1接通电源，以在工艺腔室21中形成感应电场，利用氢气产生等离子体，示例地，第一射频电源RF1的工作功率可以为1900W，工作电压的频率为12.5Mhz。示例地，步骤5和步骤6的持续时间为3s，在此过程中，持续向工艺腔室21中以170sccm的速度通入氢气。
在步骤7和步骤8中，第二射频电源RF2接通电源，用于在工艺腔室21中产生吸附电场，将等离子体吸附向晶圆30表面。示例地，第二射频电源RF2的工作功率可以为450W，工作电压的频率为13.56Mhz。步骤7和步骤8的持续时间例如可以是12s，在此过程中，持续以170sccm的速度向工艺腔室21中通入氢气，并且，第一射频电源RF1持续以1900W的工作功率提供感应电场，供电单元11持续向静电卡盘12提供3.6KV的高压直流电，以固定晶圆30。静电卡盘12在此过程中积累了大量电荷。
步骤9为电荷释放阶段。在此阶段，第二射频电源RF2停止工作，工艺腔室21中不再存在吸附电场，等离子体不再轰击晶圆30表面。继续向工艺腔室21中通入氢气，第一射频电源RF1也保持在正常的工作状态。
示例地，电荷释放阶段可以分为第一阶段和第二阶段。在第一阶段中，供电单元11保持与静电卡盘12的连接状态，如图2所示。供电单元11的输出电压为电荷释放电压(例如为0V～200V)。根据表1可知，电荷释放电压为0V，因此第一直流单元111中的第一正向输出端111a输出0V；第二直流单元112的第二负向输出端112b输出0V。
如图2所示，由于供电单元11的内部阻抗较小(远小于保护电阻13的阻值)，因此静电卡盘12上积累的大部分电荷可以在第一阶段通过供电单元11的接地端快速释放。第一阶段可以称为快速放电阶段，示例地，第一阶段持续0.1秒。
第二阶段可以称为正常放电阶段。在第二阶段中，继电器单元14切换电路连接关系，将静电卡盘12切换至与保护电阻13相连接，如图3所示。静电卡盘12上残留的电荷通过保护电阻13释放。示例地，第二阶段持续4.9s。由于静电卡盘12上积累的大部分电荷已经在第一阶段通过供电单元11的接地端得以释放，因此，在第二阶段将静电卡盘12与保护电阻13相连之后，静电卡盘12上的电荷量已经不足以产生电弧放电，降低了电弧放电的出现概率，减少了电弧放电损伤晶圆30表面的情况，也减少了电弧击中反应腔室侧壁形成杂质粒子的情况，提高了晶圆30的良率。
在步骤10中，第一射频电源RF1停止工作，不再产生等离子体。同时继续以170sccm的速度通入氢气，利用不断通入的氢气将腔室内残留的等离子体吹扫干净并用真空泵24抽走。示例地，步骤10的持续时间为2s。
最后，步骤11结束整个工艺流程。
在其他的实施例中，利用图5所示的半导体设备执行等离子体工艺时，可以根据实际需求选择等离子体气体、调整各个步骤的时长以及调整电荷释放阶段中第一阶段和第二阶段的时长。
本申请的一个实施例还公开了一种半导体工艺方法，如图6所示，该方法应用于前述实施例中的半导体设备，包括：
S10：晶圆吸附阶段：供电单元11向静电卡盘12输出工作电压，以控制静电卡盘12吸附晶圆；
S20：晶圆释放与电荷释放阶段：供电单元11输出的电压由工作电压调整为电荷释放电压，并保持第一预设时间，以释放掉静电卡盘12上积累的部分电荷，避免异常放电；将静电卡盘12切换至与保护电阻13相连接，并保持第二预设时间，以释放静电卡盘12上积累的剩余电荷。
在步骤S10中，半导体设备工作在晶圆吸附阶段，供电单元11向静电卡盘12输出3kV～4kV的工作电压，控制静电卡盘12吸附晶圆。示例地，工作电压可以是3000V、3600V或者4000V。示例地，在晶圆吸附阶段，供电单元11和静电卡盘12之间的连接关系如图2所示。
在步骤S20中，半导体设备工作在晶圆释放与电荷释放阶段，供电单元11的输出电压由工作电压调整为电荷释放电压，并保持第一预设时间。示例地，电荷释放电压例如可以是0～200V，例如为0V、10V、50V、100V、150V或200V。第一预设时间可以是0.1秒～1秒，例如为0.1秒、0.2秒、0.5秒或者1秒。在第一预设时间内，供电电压的输出电压虽然从工作电压调整为电荷释放电压，但是供电单元11和静电卡盘12之间的连接关系仍然如图2所示。此时，静电卡盘12上积累的电荷所产的电压远大于供电单元11提供的电荷释放电压，并且，由于供电单元11的内部阻抗较小，静电卡盘12上 累积的电荷可以通过供电单元11的接地端快速释放。
在第一预设时间之后，静电卡盘12切换至与保护电阻13相连接，并保持第二预设时间，如图3所示。此时，静电卡盘12中的大部分电荷已经通过供电单元11的接地端得以释放，静电卡盘12中剩余的电荷能够产生的电压大幅减小，即使将静电卡盘12与保护电阻13相连接进行电荷释放，也不会因为保护电阻13的阻值过大而产生电弧放电现象。示例地，第二预设时间可以是4秒～4.9秒，例如为4秒、4.5秒、4.8秒或者4.9秒。
上述半导体工艺方法，在晶圆释放与电荷释放阶段先将静电卡盘12与供电单元11保持连接，并持续第一预设时间，以便于将静电卡盘12上积累的大部分电荷通过供电单元11的接地端释放，由于供电单元11的内部电阻的阻值小于保护电阻13的阻值，所以，放电电流更大，可以在短时间内释放大量电荷。在第一预设时间之后再将静电卡盘12转接到保护电阻13，以进行剩余电荷的释放，此时，由于大量电荷已经被释放，发生电弧放电的概率大大降低，减少了电弧放电损伤晶圆表面的情况，也减少了电弧击中反应腔室侧壁上黏附的杂质层、形成杂质粒子的情况，提高了晶圆良率。并且，由于减少了电弧放电的概率，可以减少处理故障的宕机时间，保证产品顺利生产。
在一些实施例中，第一预设时间和第二预设时间之和为固定值，例如为5s。
在一些实施例中，晶圆吸附阶段和晶圆释放与电荷释放阶段之间还包括工艺阶段，工艺阶段包括：对晶圆执行工艺操作。示例地，工艺操作可以包括：使用等离子体轰击晶圆。示例地，可以使用等离子体轰击晶圆表面，以去除晶圆表面特定的膜层或者杂质。等离子体可以包括氢气等离子体、氩气等离子体或其他等离子体。
可选地，工艺操作还可以包括等离子体沉积工艺，以于晶圆表面沉积膜层。
在一些实施例中，在晶圆吸附阶段之前还包括设备准备阶段。设备准备阶段例如可以是向工艺腔室21内通入保护气体，保护气体可以包括惰性气 体、氩气或氢气。通过向工艺腔室21内通入保护气体，可以将工艺腔室21中的空气排出干净，于工艺腔室21中形成无氧环境，防止氧化。
在一些实施例中，晶圆释放与电荷释放阶段之后还包括：清扫阶段，清扫阶段包括：向工艺腔室内通入清扫气体，以对工艺腔室进行清扫。示例地，保护气体及清扫气体均为还原性气体，例如氢气。
作为示例，上述半导体工艺方法例如可以适用于ULVAC Entron EX-W300设备或ENI/2000搭配ENI1250的制程腔体。可以根据上述半导体工艺方法，对一些ICP设备原厂提供的氢气等离子体最佳工艺流程进行改进，以减少晶圆释放阶段静电卡盘发生电弧放电的概率，提升产品良率。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种半导体装置，包括：
    供电单元，包括接地端和电压输出端，所述供电单元用于提供工作电压及电荷释放电压，所述电荷释放电压小于所述工作电压；
    静电卡盘，与所述供电单元相连接，用于在所述供电单元提供工作电压时吸附晶圆；释放所述晶圆后，所述静电卡盘上积累有电荷；
    保护电阻，与所述接地端相连接；
    继电器单元，在所述供电单元提供所述工作电压时，将所述静电卡盘与所述供电单元相连接；在所述供电单元提供所述电荷释放电压时，将所述静电卡盘与所述供电单元连接预设时间，以释放掉所述静电卡盘上积累的部分电荷，避免异常放电；并在所述预设时间后，将所述静电卡盘切换至与所述保护电阻相连接。
  2. 根据权利要求1所述的半导体装置，其中，所述供电单元的阻值小于所述保护电阻的阻值。
  3. 根据权利要求2所述的半导体装置，其中，所述保护电阻的阻值范围是3千欧姆至5千欧姆。
  4. 根据权利要求1所述的半导体装置，其中，所述供电单元包括第一直流单元和第二直流单元，所述第一直流单元及所述第二直流单元均包括正向输出端及负向输出端；所述第一直流单元的正向输出端和所述第二直流单元的负向输出端共同组成所述电压输出端。
  5. 根据权利要求1-4任一项所述的半导体装置，其中，还包括：电容电感匹配单元，位于所述继电器单元与所述静电卡盘之间，并与所述继电器单元及所述静电卡盘相连接。
  6. 一种半导体设备，包括权利要求1-5任一项所述的半导体装置。
  7. 根据权利要求6所述的半导体设备，其中，还包括工艺腔室，所述静电卡盘位于所述工艺腔室内。
  8. 根据权利要求6或7所述的半导体设备，其中，所述半导体设备包括 等离子体工艺设备。
  9. 一种半导体工艺方法，应用于权利要求6-8中任一项所述的半导体设备，所述方法包括晶圆吸附阶段及晶圆释放与电荷释放阶段；
    所述晶圆吸附阶段包括：所述供电单元向所述静电卡盘输出所述工作电压，以控制所述静电卡盘吸附所述晶圆；
    所述晶圆释放与电荷释放阶段包括：
    所述供电单元输出的电压由所述工作电压调整为所述电荷释放电压，并保持第一预设时间，以释放掉所述静电卡盘上积累的部分电荷，避免异常放电；
    将所述静电卡盘切换至与所述保护电阻相连接，并保持第二预设时间，以释放所述静电卡盘上积累的剩余电荷。
  10. 根据权利要求9所述的半导体工艺方法，其中，所述工作电压的范围是3kV～4kV，所述电荷释放电压的范围是0～200V。
  11. 根据权利要求9所述的半导体工艺方法，其中，所述第一预设时间的范围是0.1秒～1秒，所述第二预设时间的范围是4秒～4.9秒。
  12. 根据权利要求9-11任一项所述的半导体工艺方法，其中，所述晶圆吸附阶段和所述晶圆释放与电荷释放阶段之间还包括工艺阶段，所述工艺阶段包括：对所述晶圆执行工艺操作。
  13. 根据权利要求12所述的半导体工艺方法，其中，所述工艺操作包括：使用等离子体轰击所述晶圆。
  14. 根据权利要求12所述的半导体工艺方法，其中，所述半导体设备还包括工艺腔室，所述静电卡盘位于所述工艺腔室内；所述晶圆吸附阶段之前还包括：设备准备阶段，所述设备准备阶段包括：向所述工艺腔室内通入保护气体。
  15. 根据权利要求14所述的半导体工艺方法，其中，所述晶圆释放与电荷释放阶段之后还包括：清扫阶段，所述清扫阶段包括：向所述工艺腔室内通入清扫气体，以对所述工艺腔室进行清扫。
  16. 根据权利要求15所述的半导体工艺方法，其中，所述保护气体及所述清扫气体均包括还原性气体。
PCT/CN2022/073836 2022-01-19 2022-01-25 半导体装置、半导体设备和半导体工艺方法 WO2023137777A1 (zh)

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* Cited by examiner, † Cited by third party
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JPH08203989A (ja) * 1995-01-20 1996-08-09 Hitachi Ltd 静電吸着装置及び方法
JPH09120988A (ja) * 1995-08-24 1997-05-06 Tokyo Electron Ltd プラズマ処理方法
JP2004014868A (ja) * 2002-06-07 2004-01-15 Tokyo Electron Ltd 静電チャック及び処理装置
JP2004047511A (ja) * 2002-07-08 2004-02-12 Tokyo Electron Ltd 離脱方法、処理方法、静電吸着装置および処理装置
CN102044466A (zh) * 2009-10-12 2011-05-04 北京北方微电子基地设备工艺研究中心有限责任公司 一种静电卡盘及其残余电荷的消除方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203989A (ja) * 1995-01-20 1996-08-09 Hitachi Ltd 静電吸着装置及び方法
JPH09120988A (ja) * 1995-08-24 1997-05-06 Tokyo Electron Ltd プラズマ処理方法
JP2004014868A (ja) * 2002-06-07 2004-01-15 Tokyo Electron Ltd 静電チャック及び処理装置
JP2004047511A (ja) * 2002-07-08 2004-02-12 Tokyo Electron Ltd 離脱方法、処理方法、静電吸着装置および処理装置
CN102044466A (zh) * 2009-10-12 2011-05-04 北京北方微电子基地设备工艺研究中心有限责任公司 一种静电卡盘及其残余电荷的消除方法

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