WO2023137593A1

WO2023137593A1 - Bus processing apparatus and system

Info

Publication number: WO2023137593A1
Application number: PCT/CN2022/072595
Authority: WO
Inventors: 樊孝斌; 于鹏鹏
Original assignee: 华为数字能源技术有限公司
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2023-07-27
Also published as: CN116783870A

Abstract

A bus processing apparatus and system. The apparatus comprises: a first switch device, a second switch device, a power supply, a first resistor, and a second resistor. A control electrode of the first switch device is connected to a transmit end (i.e., TX1) of a first transceiver, a first electrode is connected to a receiving end (i.e., RX1) of the first transceiver, and a second electrode is connected to a transmit end (i.e., TX2) of a second transceiver and is connected to the power supply by means of the first resistor. A control electrode of the second switch device is connected to TX2, a first electrode is connected to a receiving end (i.e., RX2) of the second transceiver, and a second electrode is connected to TX1 and is connected to the power supply by means of the second resistor. The first switch device is used for: disconnecting a path between RX1 and TX2 when the level of TX1 is a low level. The second switch device is used for: disconnecting a path between RX2 and TX1 when the level of TX2 is a low level. Therefore, a self-locking phenomenon during CAN bus connection can be avoided.

Description

A bus processing device and system

technical field

The present application relates to the technical field of communications, and in particular to a bus processing device and system.

Background technique

The controller area network (CAN) bus is a field bus that can effectively support the serial communication of the distributed control system. At present, CAN bus has been widely used in industrial automation, ships, medical equipment, industrial equipment and other fields.

The CAN bus can be connected to each other in the form of a cable bus. For example, as shown in FIG. 1A , the first CAN bus 10 may be connected to the second CAN bus 50 through the first transceiver 20 , the isolation device 30 and the second transceiver 40 in sequence. Wherein, the first transceiver 20 is connected to the first CAN bus 10 and can receive or send signals through the first CAN bus 10 ; the second transceiver 40 is connected to the second CAN bus 50 and can receive or send signals through the second CAN bus 50 . Through the architecture of FIG. 1A , the levels of RX1 , TX1 , RX2 , and TX2 may all be low, thus causing self-locking of the first CAN bus 10 and the second CAN bus 50 . Wherein, RX1 is the receiving end of the first transceiver 20 , TX1 is the transmitting end of the first transceiver 20 , RX2 is the receiving end of the second transceiver 40 , and TX2 is the transmitting end of the second transceiver 40 .

Contents of the invention

The present application provides a bus processing device and system for avoiding self-locking phenomenon when CAN bus is connected.

In a first aspect, the embodiment of the present application provides a bus processing device. This method can be adapted for use in the systems shown in Figure 2A or 2B below. The bus processing device includes: a first switch device, a second switch device, a power supply, a first resistor and a second resistor.

Wherein, the control electrode of the first switching device is connected to the transmitting terminal of the first transceiver (hereinafter referred to as TX1), the first electrode of the first switching device is connected to the receiving terminal of the first transceiver (hereinafter referred to as RX1), the second electrode of the first switching device is connected to the transmitting terminal of the second transceiver (hereinafter referred to as TX2), and the second electrode of the first switching device is also connected to the power supply through the first resistor. The control electrode of the second switching device is connected to the sending end of the second transceiver, the first electrode of the second switching device is connected to the receiving end of the second transceiver (hereinafter referred to as RX2), the second electrode of the second switching device is connected to the sending end of the first transceiver, and the second electrode of the second switching device is also connected to the power supply through the second resistor. The first transceiver is connectable to the first CAN bus, and the second transceiver is connectable to the second CAN bus.

The first switching device is used for: disconnecting the path between the receiving end of the first transceiver and the transmitting end of the second transceiver when the level of the transmitting end of the first transceiver is low; the second switching device is used for disconnecting the path between the receiving end of the second transceiver and the transmitting end of the first transceiver when the level of the transmitting end of the second transceiver is low.

Through the two simple switching devices in the device, the levels of RX1, TX1, RX2 and TX2 can be different from being low at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected, which will be explained in detail below.

When the first CAN bus sends a signal, the level of TX1 is high level, and the level of RX1 is low level. The transmission direction of the signal is RX1->TX2->RX2->TX1.

In the first possible situation, when the level of TX1 is high level, the first switching device conducts the path between RX1 and TX2, and RX1 can transmit the signal from the first CAN bus to TX2, so that the level of TX2 is the same as the level of RX1, both of which are low level. RX2 receives the signal from TX2, so that the level of RX2 is the same as the level of TX2, both of which are low level. Since the level of TX2 is low level, the second switching device disconnects the path between RX2 and TX1, and the level of TX1 is its own static level. Since TX1 is connected to a power supply device (for example, a power supply for the first transceiver or a power supply for the isolation device), the level of TX1 is high. In this way, in the first possible situation, the levels of RX1, TX2 and RX2 are low level, and the level of TX1 is high level.

In the second possible situation, when the level of TX1 is high level, the first switching device disconnects the path between RX1 and TX2, and the level of TX2 is its own static level. Since TX2 is connected to a power supply device (for example, a power supply for the second transceiver), the level of TX2 is high level. RX2 receives the signal from TX2, so that the level of RX2 is the same as the level of TX2, both of which are high level.

Then, the second case can have two branches.

Branch 1: if the level of TX2 is high level, the second switching device turns on the path between RX2 and TX1, then the level of TX1 is the same as the level of RX2, both of which are high level. In this way, in branch one of the second possible situation, the level of RX1 is low level, the level of TX2, the level of RX2 and the level of TX1 are high level.

Branch two: if the level of TX2 is high level, the second switching device disconnects the path between RX2 and TX1, and the level of TX1 is its own static level. Since TX1 is connected with a power supply device, the level of TX1 is high level. In this way, in branch two of the second possible situation, the level of RX1 is low level, the level of TX2, the level of RX2 and the level of TX1 are high level.

To sum up, when the first CAN bus sends a signal, no matter what the situation is, the level of TX1 is 1. In this way, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected.

Similarly, when the second CAN bus sends a signal, the level of TX2 is 1. In this way, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected.

In a possible design, any one of the first switching device and the second switching device is at least one of the following: a transistor and an N-type metal oxide semiconductor field effect transistor. Through this design, the bus processing device includes a simple triode or N-type metal oxide semiconductor field effect transistor, which can avoid the self-locking phenomenon when the CAN bus is connected, and has the advantages of simple structure and low cost.

In a possible design, when any switching device in the first switching device and the second switching device is a triode, the control electrode of any switching device is a base, the first electrode of any switching device is an emitter, and the second electrode of any switching device is a collector; or, when any switching device in the first switching device and the second switching device is an N-type metal oxide semiconductor field effect transistor, the control electrode of any switching device is a gate, the first electrode of any switching device is a drain, and the second electrode of any switching device is a source; When any switching device is an NMOS field effect transistor, the control electrode of any switching device is a gate, the first electrode of any switching device is a source, and the second electrode of any switching device is a drain. This design provides a variety of ways for the switch device to connect with other devices, and the design is more flexible.

In a possible design, the above device further includes: a first diode and a second diode. Wherein, the anode of the first diode is connected to the receiving end of the first transceiver, the cathode of the first diode is connected to the sending end of the second transceiver; the anode of the second diode is connected to the receiving end of the second transceiver, and the cathode of the second diode is connected to the sending end of the first transceiver. With this design, the first diode is connected in parallel with the first switching device, which can speed up the disconnection of the first switching device; the second diode is connected in parallel with the second switching device, which can speed up the disconnection of the second switching device. Since the disconnection of the switch device can avoid the self-locking phenomenon when the CAN bus is connected, therefore, accelerating the disconnection of the switch device can accelerate the avoidance of the self-locking phenomenon when the CAN bus is connected.

In a possible design, the above device may further include: a first capacitor and a second capacitor. Both ends of the first capacitor are respectively connected to the receiving end of the first transceiver and the sending end of the second transceiver; two ends of the second capacitor are respectively connected to the receiving end of the second transceiver and the sending end of the first transceiver. Through this design, the first capacitor is connected in parallel with the first switching device, so that the signal of the first switching device can be filtered; the second capacitor is connected in parallel with the second switching device, so that the signal of the second switching device can be filtered.

In a possible design, the above device may further include a third resistor and/or a fourth resistor. The control electrode of the first switching device is connected to the sending end of the first transceiver through the third resistor; the control electrode of the second switching device is connected to the sending end of the second transceiver through the fourth resistor.

Through this design, the third resistor can limit the current input to the control electrode of the first switching device, so as to avoid damage to the first switching device due to excessive current, thereby improving the performance and service life of the first switching device. The fourth resistor can limit the current input to the control electrode of the second switching device, thereby avoiding damage to the second switching device due to excessive current, thereby improving the performance and service life of the second switching device.

In a second aspect, the embodiment of the present application provides a bus processing device. This method can be adapted for use in the systems shown in Figure 2A or 2B below. The bus processing device includes: a first tri-state gate, a second tri-state gate, a first NOT gate, a second NOT gate, a power supply, a fifth resistor and a sixth resistor. Wherein, the input end of the first tri-state gate is connected to the receiving end of the first transceiver (hereinafter referred to as RX1), the output end of the first tri-state gate is connected to the transmitting end of the second transceiver (hereinafter referred to as TX2), the output end of the first tri-state gate is also connected to the power supply through the fifth resistor; the input end of the second tri-state gate is connected to the receiving end of the second transceiver (hereinafter referred to as RX2), the output end of the second tri-state gate is connected to the transmitting end of the first transceiver (hereinafter referred to as TX1), and the output end of the second tri-state gate is also connected to the power supply through the fifth resistor; Connected to the power supply; the input end of the first NOT gate is connected to the sending end of the first transceiver, and the output end of the first NOT gate is connected to the output control end of the first tri-state gate; the input end of the second NOT gate is connected to the sending end of the second transceiver, and the output end of the second NOT gate is connected to the output control end of the second tri-state gate; wherein, the first transceiver is connected with the first CAN bus, and the second transceiver is connected with the second CAN bus. Both the first tri-state gate and the second tri-state gate may be tri-state gates enabled with a low level; or, both the first tri-state gate and the second tri-state gate may be tri-state gates enabled with a high level.

Through the simple devices in the device, the levels of RX1, TX1, RX2 and TX2 are not low at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected. This will be described in detail below.

Case 1: Both the first tri-state gate and the second tri-state gate are tri-state gates enabled with a low level.

When the first CAN bus sends a signal (that is, the state of the first CAN bus is dominant), the level of TX1 is high level, the level of RX1 is low level, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit a signal to TX2 through the first tri-state gate, therefore, the relationship between the input terminal and the output terminal of the first tri-state gate needs to be judged. The high level of TX1 becomes low level through the first NOT gate; when the output control terminal of the first tristate gate is low level, the level of the output terminal of the first tristate gate is the same as the level of the input terminal of the first tristate gate, so the level of TX2 is low level. RX2 receives the signal from TX2, so that the level of RX2 is the same as the level of TX2, therefore, the level of RX2 is low level. RX2 needs to transmit a signal to TX1 through the second tri-state gate, therefore, the relationship between the input terminal and the output terminal of the second tri-state gate needs to be judged. The low level of TX2 becomes high level through the second NOT gate; when the output control terminal of the second tristate gate is high level, the output terminal of the second tristate gate is high impedance, blocking the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is high level. Thus, in case 1, the levels of RX1, TX2 and RX2 are low, and the level of TX1 is high.

Therefore, when the first CAN bus sends a signal, the levels of TX1, RX1, TX2, and RX1 are not low at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected.

Similarly, when the second CAN bus sends a signal (that is, the state of the second CAN bus is dominant), the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not low at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected.

Case 2: Both the first tri-state gate and the second tri-state gate are high-level enabled tri-state gates.

When the first CAN bus sends a signal (that is, the state of the first CAN bus is dominant), the level of TX1 is high level, the level of RX1 is low level, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit a signal to TX2 through the first tri-state gate, therefore, the relationship between the input terminal and the output terminal of the first tri-state gate needs to be judged. The high level of TX1 becomes low level through the first NOT gate; when the output control terminal of the first tristate gate is low level, the output terminal of the first tristate gate is high impedance, which can block the path between RX1 and TX2. Since TX2 is connected with a power supply device, the level of TX2 is high level. RX2 receives the signal from TX2, so that the level of RX2 is the same as the level of TX2, therefore, the level of RX2 is high level. RX2 needs to transmit a signal to TX1 through the second tri-state gate, therefore, the relationship between the input terminal and the output terminal of the second tri-state gate needs to be judged. The high level of TX2 becomes low level through the second NOT gate; when the output control terminal of the second tristate gate is low level, the output terminal of the second tristate gate is high impedance, thereby blocking the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is high level. In this way, in case 2, the level of RX1 is low level, the level of TX2, the level of RX2 and the level of TX1 are high level.

In a third aspect, an embodiment of the present application provides a bus processing system, including: any bus processing device described above, a first transceiver, and a second transceiver.

The technical effects that can be achieved in the above third aspect can be described with reference to the technical effects that can be achieved by any possible design in any of the above first or second aspects, and the repetition will not be discussed.

Description of drawings

FIG. 1A is a schematic diagram of a communication system;

FIG. 1B is a schematic diagram of another communication system;

FIG. 2A is a schematic diagram of a system applicable to the bus processing device provided in the embodiment of the present application;

FIG. 2B is a schematic diagram of another system applicable to the bus processing device provided in the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a bus processing device provided in an embodiment of the present application;

Fig. 4, Fig. 5, Fig. 6, and Fig. 7A-Fig. 7D are respectively schematic diagrams of an expansion scheme of a bus processing device provided in the embodiment of the present application;

FIG. 8 is a schematic diagram of an implementation of a bus processing device provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of another implementation of a bus processing device provided in an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another bus processing device provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of a bus processing system provided by an embodiment of the present application.

Detailed ways

The present application provides a bus processing device and system to avoid self-locking phenomenon when CAN bus is connected.

In the solution provided by the embodiment of the present application, the bus processing device includes a first switching device, a second switching device, a power supply, a first resistor, and a second resistor. Wherein, the control electrode of the first switching device can be connected to the transmitting terminal of the first transceiver (hereinafter referred to as TX1), the first electrode of the first switching device can be connected to the receiving terminal of the first transceiver (hereinafter referred to as RX1), the second electrode of the first switching device can be connected to the transmitting terminal of the second transceiver (hereinafter referred to as TX2), and the second electrode of the first switching device is also connected to the power supply through the first resistor; the control electrode of the second switching device can be connected to TX2, and the first electrode of the second switching device can be connected to the receiving terminal of the second transceiver (hereinafter referred to as RX2), A second electrode of the second switching device may be connected to TX1, and the second electrode of the second switching device is also connected to a power source through a second resistor. The first transceiver is a transceiver connected to the first CAN bus, and the second transceiver is a transceiver connected to the second CAN bus. The first switching device can be used to disconnect the path between RX1 and TX2 when the level of TX1 is low; the second switching device can be used to disconnect the path between RX2 and TX1 when the level of TX2 is low.

Through this solution, when the first CAN bus sends a signal, the level of TX1 is 1 (for details, please refer to the summary of the invention, which will not be repeated here). In this way, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected. When the second CAN bus sends a signal, the level of TX2 is 1. That is to say, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are also 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected.

In the following, some terms used in the embodiments of the present application are explained, so as to facilitate the understanding of those skilled in the art.

1) In this application, when 0 and 1 represent levels, 0 represents low level and 1 represents high level. Wherein, the high level is greater than the low level.

For example, for a transistor-transistor logic (TTL) level, a high level greater than 2.4 volts (V) can be represented by 1; a low level less than 0.4V can be represented by 0. For another example, for a complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) level, a high level greater than 4.99V can be represented by 1; a low level less than 0.01V can be represented by 0.

2) The CAN bus is a bus that can support serial communication of a distributed control system.

The CAN bus can transmit signals according to differential levels. Specifically, the CAN bus can be a twisted pair, and the two lines can be called CAN_H and CAN_L respectively. When there is no signal transmission, the voltages of CAN_H and CAN_L are the same (for example, the voltages of CAN_H and CAN_L are both 2.5 volts (V)), that is, the difference between CAN_H and CAN_L is 0; at this time, the levels of CAN_H and CAN_L are both 0, and the state of the CAN bus is recessive (also called idle). When there is signal transmission, the voltages of CAN_H and CAN_L are different (for example, the voltage of CAN_H is 3.5V, and the voltage of CAN_L is 1.5V), resulting in a voltage difference; at this time, the level of CAN_H is 1, the level of CAN_L is 0, and the state of the CAN bus is dominant.

3) The transceiver in the present application is used for receiving signals from the CAN bus and/or sending signals to the CAN bus.

When the state of the CAN bus is dominant, the transceiver can receive signals from the CAN bus and convert the signals from the CAN bus to TTL level. At this time, the level of the receiving end of the transceiver is 0, and the level of the transmitting end of the transceiver is 1.

When the level of the sending end of the transceiver is 0, it means that the transceiver has a signal to send and needs to occupy the CAN bus, so that the state of the CAN bus is dominant for transmitting signals.

The transceiver in this application may be a device such as a sensor or an electronic device. Wherein, the sensor may be: a speed sensor, a temperature sensor or a humidity sensor and the like. The electronic device may be a computer device with a processor, such as a desktop computer, a personal computer, or a server. It should also be understood that the electronic device may also be a portable electronic device with a processor, such as a mobile phone, a tablet computer, a wearable device with a wireless communication function (such as a smart watch), a vehicle-mounted device, and the like. Exemplary embodiments of portable electronic devices include, but are not limited to

Or portable electronic devices with other operating systems.

In this application, the transceiver can also be replaced by a device capable of converting the signal of the CAN bus into a TTL level, for example, a level converter.

4) A tri-state gate, also known as a tri-state output circuit, is a logic device. The tri-state gate includes an input terminal, an output terminal and an output control terminal; under the control of the output control terminal, the tri-state gate can output three different output values: 0 (corresponding to low level), 1 (corresponding to high level) and high impedance.

The tri-state gate can be a low-level enabled tri-state gate or a high-level enabled tri-state gate.

When the three-state gate is a low-level enabled three-state gate, if the level of the output control terminal is 0, the level of the output terminal is the same as that of the input terminal; if the level of the output control terminal is 1, the state of the output terminal is high impedance. Specifically, the corresponding relationship of the levels of the input terminal, the output terminal and the output control terminal of the low-level enabled tri-state gate is shown in Table 1.

Table 1

输出控制端的电平The level of the output control terminal	输入端的电平input level		输出端的电平output level
11	0或10 or 1	高阻high resistance
00	00	00
00	11	11

When the tri-state gate is a high-level enabled tri-state gate, if the level of the output control terminal is 1, the level of the output terminal is the same as the level of the input terminal; if the level of the output control terminal is 0, the state of the output terminal is high impedance. Specifically, the corresponding relationship of the levels of the input terminal, the output terminal and the output control terminal of the high-level enabled tri-state gate is shown in Table 2.

Table 2

输出控制端的电平The level of the output control terminal	输入端的电平input level	输出端的电平output level
00	0或10 or 1	高阻 high resistance
11	00	00
11	11	11

5) Electrical isolation refers to the electrical isolation of the power supply and the electrical circuit, that is, the electrical isolation of the branch circuit from the entire electrical system, making it an electrically isolated, independent ungrounded safety system, in order to prevent the risk of indirect electrical contact when the exposed conductor is faulty and charged.

6). The connection in this application may be a direct connection, or a connection through one or more modules or one or more devices. For example, A is connected to B, or A is connected to B, may mean: A is directly connected to B, or A is connected to B through C. Wherein, C may represent one or more modules, and may also represent one or more devices.

7) In this application, RX1 is the receiving end of the first transceiver 20, TX1 is the transmitting end of the first transceiver 20, RX2 is the receiving end of the second transceiver 40, and TX2 is the transmitting end of the second transceiver 40.

In the embodiments of the present application, for the number of nouns, unless otherwise specified, it means "singular noun or plural noun", that is, "one or more". "At least one" means one or more, and "plurality" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three kinds of relationships, for example, A and/or B may indicate: A exists alone, A and B exist simultaneously, and B exists independently. "At least one (individual) of the following" or similar expressions refer to any combination of these items (individuals), including any combination of a single item (individuals) or a plurality of item (individuals).

In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing the description, and should not be interpreted as indicating or implying relative importance, nor should they be understood as indicating or implying order.

Currently, when two CAN buses are connected, a self-locking phenomenon may occur. This will be specifically described below in conjunction with FIG. 1A .

Fig. 1A shows a possible system structure diagram after two CAN buses are connected. As shown in FIG. 1A , the system includes: a first CAN bus 10 , a first transceiver 20 , an isolation device 30 , a second transceiver 40 , and a second CAN bus 50 . The first CAN bus 10 can be connected to the second CAN bus 50 through the first transceiver 20 , the isolation device 30 and the second transceiver 40 in sequence.

Wherein, the specific content of the first CAN bus 10 , the first transceiver 20 , the second transceiver 40 and the second CAN bus 50 can refer to the description of the CAN bus and transceivers in the glossary of terms, and the repeated parts will not be repeated.

The isolation device 30 is used to realize electrical isolation between the first CAN bus 10 and the second CAN bus 50 . For example, the isolation device 30 may be equipment such as an isolation transformer, a photoelectric coupling element, and the like. The levels on both sides of the isolation device 30 are the same.

As shown in FIG. 1A , when the first CAN bus 10 sends a signal, the state of the first CAN bus 10 is dominant, and the transmission path of the signal is RX1->TX2->RX2->TX1->RX1. Since the state of the first CAN bus 10 is dominant, the voltage of CAN_H1 is higher than CAN_L1, and the level of RX1 is 0. The levels at both ends of the isolation device 30 are the same, therefore, the levels of TX2 and RX1 are the same, both being 0. RX2 receives the signal from TX2, therefore, the level of RX2 is the same as that of TX2, both are 0. Because the levels at both ends of the isolation device are the same, the levels of TX1 and RX2 are the same, both being 0. Since the level of TX1 is 0, RX1 receives the signal from TX1, so that the level of RX1 is 0. Repeat the above process, and the levels of RX1, TX1, RX2 and TX2 remain at 0. As mentioned above, when the level of the sending end of the transceiver is 0, it means that the transceiver has a signal to send and needs to occupy the CAN bus, so that the state of the CAN bus is dominant for signal transmission. Therefore, if the level of TX1 is continuously 0, the state of the first CAN bus 10 will continue to be dominant, and then the first CAN bus 10 cannot be released, forming a self-locking phenomenon of the CAN bus.

Similarly, when the second CAN bus 20 sends a signal, the levels of RX1, TX1, RX2, and TX2 will continue to be 0, and the state of the second CAN bus 20 will continue to be dominant, so that the second CAN bus cannot be released, forming a self-locking phenomenon of the CAN bus.

In order to solve the self-locking problem of the CAN bus, a bus multi-channel isolation system is currently provided. As shown in Figure 1B, the system includes: OR gate U1, OR gate U2, NAND gate U3, lower edge delay circuit U4, OR gate U5, OR gate U6, NAND gate U7, lower edge delay circuit U8, and NAND gate U9.

Wherein, the connection manner of each device is shown in FIG. 1B . Specifically, one input of the OR gate U1 is connected to 1T and the output of the OR gate U2, the other input of the OR gate U1 is connected to the output of the NAND gate U9, and the output of the OR gate U1 is connected to one input of the NAND gate U3. One input of the OR gate U2 is connected to the output terminal of the lower edge delay circuit U4, and the other input of the OR gate U2 is connected to 2R. One input of the NAND gate U3 is connected to 1R, the other input is connected to the output terminal of the OR gate U1, and the output terminal of the NAND gate U3 is connected to the lower edge delay circuit U4. Among them, the signal of RX1 becomes the signal of 1R after digital isolation, the signal of 1T becomes the signal of TX1 after digital isolation, and the levels at both ends of the digital isolation are equal. The connection mode of the OR gate U5, the OR gate U6, the NAND gate U7, and the lower edge delay circuit U8 is corresponding to the connection mode of the OR gate U1, the OR gate U2, the NAND gate U3, and the lower edge delay circuit U4, and will not be repeated here.

In addition, in this system, the first CAN bus 10 connected to the first transceiver 20 is a remote CAN bus, and the second CAN bus 50 connected to the second transceiver 40 is a local CAN bus. The isolation device 30 includes a digital isolation 301 and a digital isolation 302 .

Taking the signal sent by the first CAN bus 10 as an example, how the system solves the self-locking problem of the CAN bus will be described below. When the first CAN bus 10 sends a signal, the level of TX1 is 1, and the level of RX1 is 0. The signal of RX1 becomes a 1R signal after digital isolation, and the level of 1R is 0. The level 0 is used as the input of the NAND gate U3, so that the level of the output terminal of the NAND gate U3 is 1. The level 1 is still 1 after passing through the lower edge delay circuit U4, that is, the level of the output end of the lower edge delay circuit U4 is 1. Level 1 is used as the input of OR gate U2, so that the level of the output terminal of OR gate U2 is 1, so the level of 1T is also 1. The level of 1T becomes the signal of TX1 after digital isolation, so that the level of TX1 is 1. In this way, through the OR gate U5, the OR gate U6, the NAND gate U7, and the lower edge delay circuit U8, the CAN bus can be prevented from self-locking when the first CAN field bus sends a signal.

However, this system needs to use multiple gate structures and lower-edge delay circuits to avoid bus self-locking. The scheme is relatively complicated and has high requirements on the performance of the controller.

In view of this, the present application provides a bus processing device 60, which can use a simple structure to avoid the self-locking phenomenon when the CAN bus is connected. The bus processing device 60 can be applied to the system shown in FIG. 2A or FIG. 2B .

As shown in FIG. 2A , the system may include a first CAN bus 10 , a first transceiver 20 , an isolation device 30 , a second transceiver 40 , a second CAN bus 50 , and a bus processing device 60 . The first CAN bus 10 can be connected to the second CAN bus 50 through the first transceiver 20 , the isolation device 30 , the bus processing device 60 and the second transceiver 40 in sequence.

As shown in FIG. 2B , the system may include a first CAN bus 10 , a first transceiver 20 , a second transceiver 40 , a second CAN bus 50 , and a bus processing device 60 . The first CAN bus 10 can be connected to the second CAN bus 50 through the first transceiver 20 , the bus processing device 60 and the second transceiver 40 in sequence.

In the system shown in FIG. 2A or FIG. 2B , the voltages of the first CAN bus 10 and the second CAN bus 50 may be the same or different. When the voltages of the first CAN bus 10 and the second CAN bus 50 are different, the voltage of the first CAN bus can be higher than the voltage of the second CAN bus, and the voltage of the first CAN bus can also be lower than the voltage of the second CAN bus.

The implementation of the bus processing device 60 will be specifically described below with reference to the accompanying drawings.

FIG. 3 shows a possible structure of the bus processing device 60 provided by the embodiment of the present application. The bus processing device 60 includes: a first switching device 601 , a second switching device 602 , a power supply 603 , a resistor R1 and a resistor R2 .

Wherein, the second electrode of the first switching device 601 can be connected to the power source 603 through the resistor R1. In this way, the power supply 603 can supply power to the first switching device 601 . And due to the existence of the resistor R1, the current passing through the first switching device 601 can be limited to avoid damage to the first switching device 601 . The second electrode of the second switching device 602 can be connected to a power source 603 through a resistor R2. In this way, the power source 603 can supply power to the second switching device 602 . And due to the existence of the resistor R2, the current passing through the second switching device 602 can be limited to avoid damage to the second switching device 602 . Optionally, the power source 603 is a DC power source such as a storage battery or a lithium battery.

In addition, the control electrode of the first switching device 601 can be connected to TX1, the first electrode of the first switching device 601 can be connected to RX1, the second electrode of the first switching device 601 can be connected to TX2; the control electrode of the second switching device 602 can be connected to TX2, the first electrode of the second switching device 602 can be connected to RX2, and the second electrode of the second switching device 602 can be connected to TX1.

Optionally, when the bus processing device 60 is located in the system shown in FIG. 2A , the first switching device 601 and the second switching device 602 may be connected to the first transceiver 20 through the isolation device 30 . Specifically, the control electrode of the first switching device 601 can be connected to TX1 through the isolation device 30, the first electrode of the first switching device 601 can be connected to RX1 through the isolation device 30; the second electrode of the second switching device 602 can be connected to TX1 through the isolation device 30.

The first switching device 601 can be used to: when the level of TX1 is 0, disconnect the path between RX1 and TX2; that is, when the level of TX1 is 0, the first switching device 601 is in an off state. The second switching device 602 can be used to: disconnect the path between RX2 and TX1 when the level of TX2 is 0. That is to say, when the level of TX2 is 0, the second switching device 602 is in an off state.

Through this device, when the first CAN bus 10 sends a signal, the level of TX1 is 1 (specific content can refer to the content of the invention, which will not be repeated here), so that the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so that the self-locking phenomenon can be avoided when the CAN bus is connected. When the second CAN bus 50 sends a signal, the level of TX2 is 1. That is to say, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are also 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected.

Moreover, the device connects two CAN buses through a simple switching device. In this way, the signals between the two CAN buses can be transmitted without delay, so as to meet the real-time requirements; and the simple switching device can reduce the cost and the power consumption of the bus, and can be used in various complex network topologies. Therefore, the device has a good application prospect.

Optionally, in the bus processing device 60 shown in FIG. 3 , any switching device in the first switching device 601 and the second switching device 602 is one of the following: semiconductor switches such as triodes, N-type metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistors, MOSFETs), and relays. In this way, the structure of the bus processing device 60 is simple and the cost is low.

Wherein, each of the first switching device 601 and the second switching device 602 may include a control electrode, a first electrode and a second electrode. The control electrode is used to control the switching device to be turned on or off. When the switch device is turned on, current can be transmitted between the first electrode and the second electrode of the switch device, and the level of the output terminal is equal to the level of the input terminal; when the switch device is turned off, no current can be transmitted between the first electrode and the second electrode of the switch device. Taking a triode as an example, the control electrode of the switching device is the base, the first electrode of the switching device is the emitter, and the second electrode of the switching device is the collector. Taking an N-type MOSFET as an example, the control electrode of the switching device is the gate, the first electrode of the switching device may be the source, and the second electrode of the switching device may be the drain; or, the control electrode of the switching device is the gate, the first electrode of the switching device may be the drain, and the second electrode of the switching device may be the source.

FIG. 4-7D shows an extension solution of the bus processing device 60 shown in FIG. 3 , and the present application will be described below in conjunction with FIG. 4-7D .

As shown in FIG. 4 , on the basis of the bus processing device 60 shown in FIG. 3 , the bus processing device 60 may further include: a diode D1 and a diode D2 .

Wherein, the anode of the diode D1 is connected to RX1 , and the cathode of the diode D1 is connected to TX2 ; that is, the diode D1 is connected in parallel with the first switching device 601 . The anode of the diode D2 is connected to RX2 , and the cathode of the diode D2 is connected to TX1 ; that is, the diode D2 is connected in parallel with the second switching device 602 .

Optionally, when the bus processing device 60 is located in the system shown in FIG. 2A , the diode D1 and the diode D2 may be connected to the first transceiver 20 through the isolation device 30 . Specifically, the anode of the diode D1 can be connected to RX1 through the isolation device 30 , and the cathode of the diode D2 can be connected to TX1 through the isolation device 30 .

In this device, the diode D1 is connected in parallel with the first switching device 601 , which can accelerate the turn-off of the first switching device 601 . In this way, when the level of TX1 is 0, the first switching device 601 can quickly disconnect the path between RX1 and TX2, so that the level of TX2 quickly becomes 1, thereby quickly avoiding the self-locking phenomenon when the CAN bus is connected. The diode D2 is connected in parallel with the second switching device 602 to speed up the turn-off of the second switching device 602 . In this way, when the level of TX2 is 0, the second switching device 602 can quickly disconnect the path between RX2 and TX1, so that the level of TX1 quickly becomes 1, thereby quickly avoiding the self-locking phenomenon when the CAN bus is connected.

As shown in FIG. 5 , on the basis of the bus processing device 60 shown in FIG. 3 , the bus processing device 60 may further include: a capacitor C1 and a capacitor C2 .

Wherein, both ends of the capacitor C1 are connected to RX1 and TX2 respectively; that is, the capacitor C1 is connected in parallel with the first switching device 601 . Two ends of the capacitor C2 are connected to RX2 and TX1 respectively; that is, the capacitor C2 is connected in parallel with the second switching device 602 .

Optionally, when the bus processing device 60 is located in the system shown in FIG. 2A , the capacitors C1 and C2 may be connected to the first transceiver 20 through the isolation device 30 . Specifically, the capacitor C1 can be connected to RX1 through the isolation device 30 , and the capacitor C2 can be connected to TX1 through the isolation device 30 .

In this device, the capacitor C1 is connected in parallel with the first switching device 601 , so that the signal of the first switching device 601 can be filtered. The capacitor C2 is connected in parallel with the second switching device 602 so as to filter the signal of the second switching device 602 .

As shown in FIG. 6 , on the basis of the bus processing device 60 shown in FIG. 3 , the bus processing device 60 may further include: a resistor R3 and/or a resistor R4.

Wherein, two ends of the resistor R3 are connected to the control electrode of the first switching device 601 and TX1 respectively. In this way, the resistor R3 can limit the current input to the control electrode of the first switching device 601 , therefore, the resistor R3 is a current limiting resistor. By limiting the current input to the control electrode of the first switching device 601 , damage to the first switching device 601 due to excessive current can be avoided, thereby improving the performance and service life of the first switching device 601 .

Optionally, when the bus processing device 60 is located in the system shown in FIG. 2A , the resistor R3 may be connected to the first transceiver 20 through the isolation device 30 . Specifically, the resistor R3 can be connected to TX1 through the isolation device 30 .

Both ends of the resistor R4 are respectively connected to the control electrode of the second switching device 602 and TX2. In this way, the resistor R4 can limit the current input to the control electrode of the second switching device 602, therefore, the resistor R4 is a current limiting resistor. By limiting the current input to the control electrode of the second switching device 602 , damage to the second switching device 602 due to excessive current can be avoided, thereby improving the performance and service life of the second switching device 602 .

It should be understood that the bus processing devices 60 shown in FIGS. 4-6 can be combined. For example, as shown in FIG. 7A , the bus processing device 60 may include: a first switching device 601 , a second switching device 602 , a power supply 603 , a resistor R1 , a resistor R2 , a diode D1 , a diode D2 , a resistor R3 and a resistor R4 . For another example, as shown in FIG. 7B, the bus processing device 60 may include: a first switching device 601, a second switching device 602, a power supply 603, a resistor R1, a resistor R2, a diode D1, a diode D2, a capacitor C1 and a capacitor C2. For another example, as shown in FIG. 7C, the bus processing device 60 may further include: a first switching device 601, a second switching device 602, a power supply 603, a resistor R1, a resistor R2, a diode D1, a diode D2, a capacitor C1, a capacitor C2, a resistor R3, and a resistor R4. For another example, as shown in FIG. 7D, the bus processing device 60 may further include: a first switching device 601, a second switching device 602, a power supply 603, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a resistor R3 and a resistor R4. The connection relationship between devices in FIGS. 7A-7D can refer to the devices shown in FIGS. 3-6 , and details will not be repeated here.

The specific implementation manners of the first switching device 601 and the second switching device 602 in the bus processing device 60 shown in FIGS. 3-7D are introduced below through the bus processing device 60 shown in FIGS. 8-9 respectively. Wherein, the bus processing device 60 shown in FIG. 8 mainly introduces possible situation 1, that is, both the first switching device 601 and the second switching device 602 are triodes; the bus processing device 60 shown in FIG. 9 mainly introduces possible situation 2, that is, both the first switching device 601 and the second switching device 602 are N-type MOSFETs.

As shown in FIG. 8, the bus processing device 60 may include: a transistor Q1, a transistor Q2, a power supply 603, a resistor R1, a resistor R2, a diode D1, a diode D2, a capacitor C1, a capacitor C2, a resistor R3 and a resistor R4.

The base of the triode Q1 is connected to TX1, the emitter of the triode Q1 is connected to RX1, the collector of the triode Q1 is connected to TX2, and the collector of the triode Q1 can also be connected to the power supply 603 through the resistor R1; That is to say, the transistor Q1 can be the first switching device 601 in the bus processing device 60 shown in FIG. 3-FIG. 7D, and the transistor Q2 can be the second switching device 602 in the bus processing device 60 shown in FIG. 3-FIG. 7D.

The connection relationship between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3 and the resistor R4, and the transistor Q1 and the transistor Q2 can refer to the connection relationship between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3 and the resistor R4 and the first switching device 601 and the second switching device 602 in the bus processing device 60 shown in FIGS.

Wherein, TX1, TX2, RX1 and RX2 can all be connected to a power supply device. The power supply device may be a power supply (for example, a DC power supply such as a storage battery or a lithium battery). For example, TX1 is connected to the power supply through the resistor R3, and TX2 can be connected to the power supply through the resistor R4. RX1 and RX2 are respectively connected to the power supply. The power supply connected to TX1 and RX1 may be the power supply for the first transceiver 20 ; the power supply connected to TX2 and RX2 may be the power supply for the second transceiver 40 . If there is an isolation device 30 between the first transceiver 20 and the second transceiver 40 , the power supply connected to TX1 and TX2 may also be the power supply for the isolation device 30 . In this way, when there is no input signal, the levels of TX1, TX2, RX1, and RX2 are 1.

Through the bus processing device 60 shown in FIG. 8 , the levels of TX1 , RX1 , TX2 , and RX1 are not at 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected. This will be described in detail below.

When the first CAN bus 10 sends a signal (that is, the state of the first CAN bus 10 is dominant), the level of TX1 is 1, the level of RX1 is 0, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit a signal to TX2 through the transistor Q1, therefore, it is necessary to judge the conduction of the transistor Q1. Since the level of TX1 is higher than the level of RX1, the transistor Q1 is turned on; at this time, the level of the collector of the transistor Q1 is the same as that of the emitter, that is, the level of RX1 is the same as that of TX2, so the level of TX2 is 0. RX2 receives the signal from TX2, so that the level of RX2 is the same as that of TX2, so the level of RX2 is 0. RX2 needs to transmit a signal to TX1 through the transistor Q2, therefore, it is necessary to judge the conduction of the transistor Q2. Since the levels of RX2 and TX2 are both 0, the transistor Q2 is cut off. When the transistor Q2 is cut off, it is equivalent to a high impedance, which can block the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is 1. In this way, the level of RX1 is 0, the level of TX2 is 0, the level of RX2 is 0, and the level of TX1 is 1.

The first CAN bus 10 can also send a recessive level signal (that is, a signal with a sending level of 1). At this time, the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit a signal to TX2 through the transistor Q1, therefore, it is necessary to judge the conduction of the transistor Q1. Since the level of RX1 is the same as that of TX1, the transistor Q1 is cut off. When the transistor Q1 is cut off, it is equivalent to a high impedance, which can block the path between RX1 and TX2. Since TX2 is connected to a power supply device, the level of TX2 is 1. The level of RX2 is the same as that of TX2, therefore, the level of RX2 is 1. RX2 needs to transmit a signal to TX1 through the transistor Q2, therefore, it is necessary to judge the conduction of the transistor Q2. Since the level of RX2 is equal to the level of TX2, the transistor Q2 is cut off. When the transistor Q2 is cut off, it is equivalent to a high impedance, which can block the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is 1. In this way, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1.

To sum up, through the device shown in FIG. 8, when the first CAN bus 10 sends a signal, the levels of TX1, RX1, TX2, and RX1 are not 0 at the same time, so that the self-locking phenomenon can be avoided when the CAN bus is connected.

Similarly, through the device shown in FIG. 8, when the second CAN bus 50 sends a signal (that is, the state of the second CAN bus 50 is dominant), the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0 at the same time, so that the self-locking phenomenon can be avoided when the CAN bus is connected.

In addition, assuming that both the first CAN bus 10 and the second CAN bus 50 are idle, the level of RX1 is 1, and the level of TX1 is 1. Based on the same reason as that the first CAN bus 10 sends a recessive level signal, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1. Therefore, by the device shown in FIG. 8, when the states of the first CAN bus 10 and the second CAN bus 50 are both idle, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected.

To sum up, using the device shown in FIG. 8 , the relationship between the bus state and the levels of TX1 , RX1 , TX2 and RX2 can be shown in Table 3.

table 3

The second possible situation above will be described below with reference to FIG. 9 , that is, both the first switching device 601 and the second switching device 602 are N-type MOSFETs.

As shown in FIG. 9, the bus processing device 60 may include: N-type MOSFET M1, N-type MOSFET M2, power supply 603, resistor R1, resistor R2, diode D1, diode D2, capacitor C1, capacitor C2, resistor R3 and resistor R4.

Wherein, the gate of N-type MOSFET M1 is connected to TX1, the source of N-type MOSFET M1 is connected to RX1, the drain of N-type MOSFET M1 is connected to TX2, and the drain of N-type MOSFET M1 can also be connected to the power supply 603 through resistor R1; or, the gate of N-type MOSFET M1 is connected to TX1, the drain of N-type MOSFET M1 is connected to RX1, and the drain of N-type MOSFET M1 The source of the N-type MOSFET M1 is connected to TX2, and the source of the N-type MOSFET M1 can also be connected to the power supply 603 through the resistor R1. That is to say, the N-type MOSFET M1 can be the first switching device 601 in the bus processing device 60 shown in FIG. 3-FIG. 7D.

The gate of N-type MOSFET M2 is connected to TX2, the source of N-type MOSFET M2 is connected to RX2, the drain of N-type MOSFET M2 is connected to TX1, and the drain of N-type MOSFET M2 can also be connected to power supply 603 through resistor R2; or, the gate of N-type MOSFET M2 is connected to TX2, the drain of N-type MOSFET M2 is connected to RX2, and the source of N-type MOSFET M2 The pole is connected to TX1, and the source of the N-type MOSFET M2 can also be connected to the power supply 603 through the resistor R2. That is to say, the N-type MOSFET M2 can be the second switching device 602 in the bus processing device 60 shown in FIG. 3-FIG. 7D.

In addition, the connection relationship between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3, and the resistor R4, and the N-type MOSFET M1 and the N-type MOSFET M2 can refer to the connection relationship between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3, and the resistor R4, and the first switching device 601 and the second switching device 602 in the bus processing device 60 shown in FIGS.

Through the bus processing device 60 shown in FIG. 9 , the levels of TX1 , RX1 , TX2 , and RX1 are not 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected. This will be described in detail below.

When the first CAN bus 10 sends a signal (that is, the state of the first CAN bus 10 is dominant), the level of TX1 is 1, the level of RX1 is 0, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit signals to TX2 through N-type MOSFET M1, therefore, it is necessary to judge the conduction of N-type MOSFET M1. Since the level of TX1 is 1, the N-type MOSFET M1 is turned on; at this time, the level of the source of the N-type MOSFET M1 is the same as that of the drain, and the level of RX1 is the same as that of TX2, so the level of TX2 is 0. RX2 receives the signal from TX2, so that the level of RX2 is the same as that of TX2, so the level of RX2 is 0. RX2 needs to transmit signals to TX1 through N-type MOSFET M2, therefore, it is necessary to judge the conduction of N-type MOSFET M2. Since the level of TX2 is 0, the N-type MOSFET M2 is not turned on, thus blocking the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is 1. In this way, the level of RX1 is 0, the level of TX2 is 0, the level of RX2 is 0, and the level of TX1 is 1.

The first CAN bus 10 can also send a recessive level signal (that is, a signal with a sending level of 1). At this time, the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit signals to TX2 through N-type MOSFET M1, therefore, it is necessary to judge the conduction of N-type MOSFET M1. Since the level of TX1 is 1, the N-type MOSFET M1 is turned on; at this time, the level of the source of the N-type MOSFET M1 is the same as the level of the drain, that is, the level of RX1 is the same as that of TX2, so the level of TX2 is 1. The level of RX2 is the same as that of TX2, therefore, the level of RX2 is 1. RX2 needs to transmit signals to TX1 through N-type MOSFET M2, therefore, it is necessary to judge the conduction of N-type MOSFET M2. Since the level of TX2 is 1, the N-type MOSFET M2 is turned on; at this time, the level of the source of the N-type MOSFET M2 is the same as the level of the drain, that is, the level of RX2 is the same as that of TX1, so the level of TX1 is 1. In this way, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1.

In summary, through the device shown in FIG. 9, when the first CAN bus 10 sends a signal, the levels of TX1, RX1, TX2, and RX1 are not at 0 at the same time, so that the self-locking phenomenon can be avoided when the CAN bus is connected.

Similarly, through the device shown in FIG. 9 , when the second CAN bus 50 sends a signal, the levels of TX1, RX1, TX2, and RX1 are not 0 at the same time, so that the self-locking phenomenon can be avoided when the CAN bus is connected.

In addition, assuming that both the first CAN bus 10 and the second CAN bus 50 are idle, the level of RX1 is 1, and the level of TX1 is 1. Based on the same reason as that the first CAN bus 10 sends a recessive level signal, at this time, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1. Therefore, by means of the device shown in FIG. 9, when the states of the first CAN bus 10 and the second CAN bus 50 are both idle, the levels of TX1, RX1, TX2, and RX1 are different from 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected.

To sum up, using the device shown in FIG. 9 , the relationship between the bus state and the levels of TX1 , RX1 , TX2 and RX2 can be shown in Table 4.

Table 4

FIG. 10 shows another possible structure of the bus processing device 60 provided by the embodiment of the present application. The bus processing device 60 includes: a tri-state gate U10, a tri-state gate U12, a NOT gate U11, a NOT gate U13, a power supply 603, a resistor R5 and a resistor R6.

Wherein, the output terminal of the tri-state gate U10 can be connected to the power supply 603 through the resistor R5; thus, the power supply 603 can supply power for the tri-state gate U10. And due to the existence of the resistor 5, the current passing through the tri-state gate U10 can be limited to avoid damage to the tri-state gate U10. The output end of the tri-state gate U12 can be connected to the power supply 603 through the resistor R6; thus, the power supply 603 can supply power to the tri-state gate U12. And due to the existence of the resistor 6, the current passing through the tri-state gate U12 can be limited to avoid damage to the tri-state gate U12. Optionally, the power source 603 is a DC power source such as a storage battery or a lithium battery; the resistance value of the resistor R5 and/or the resistor R6 is 1 kilohm.

Moreover, the input end of the tri-state gate U10 is connected to RX1, the output end of the tri-state gate U10 is connected to TX2; the input end of the tri-state gate U12 is connected to RX2, and the output end of the tri-state gate U12 is connected to TX1. The input terminal of the NOT gate U11 is connected to TX1, and the output terminal of the NOT gate U11 is connected to the output control terminal of the tri-state gate U10, that is, the level of TX1 can be used as the output control of the tri-state gate U10 after being converted by the NOT gate U11. The input terminal of the NOT gate U13 is connected to TX2, and the output terminal of the NOT gate U13 is connected to the output control terminal of the tri-state gate U12, that is, the level of TX2 can be used as the output control of the tri-state gate U11 after being converted by the NOT gate U13.

Wherein, TX1, TX2, RX1 and RX2 can all be connected to a power supply device. The power supply device may be a power supply (for example, a DC power supply such as a storage battery or a lithium battery). The power supply connected to TX1 and RX1 may be the power supply for the first transceiver 20 ; the power supply connected to TX2 and RX2 may be the power supply for the second transceiver 40 . If there is an isolation device 30 between the first transceiver 20 and the second transceiver 40 , the power supply connected to TX1 and TX2 may also be the power supply for the isolation device 30 . In this way, when there is no input signal, the levels of TX1, TX2, RX1, and RX2 are 1.

In some possible implementation manners, both the tri-state gate U10 and the tri-state gate U12 are low-level enabled tri-state gates. For example, the tri-state gate U10 and the tri-state gate U12 may both be HC125 type tri-state gates, wherein the HC125 type tri-state gate is a low-level enabled tri-state gate.

In some other possible implementation manners, both the tri-state gate U10 and the tri-state gate U12 are high-level enabled tri-state gates. For example, both the tri-state gate U10 and the tri-state gate U12 may include: a HC125 type tri-state gate and a NOT gate, wherein the output control terminal of the HC125 tri-state gate is connected to the output terminal of the NOT gate.

Optionally, the NOT gate U11 and/or the NOT gate U13 are LS04 type NOT gates.

Through the bus processing device 60 shown in FIG. 10 , the levels of TX1 , RX1 , TX2 , and RX1 are not at 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected. This will be described in detail below.

Case 1: Both the tri-state gate U10 and the tri-state gate U12 are low-level enabled tri-state gates.

When the first CAN bus 10 sends a signal (that is, the state of the first CAN bus 10 is dominant), the level of RX1 is 0, the level of TX2 is 0, the level of RX2 is 0, and the level of TX1 is 1 (specific content can refer to the content of the invention, and will not be repeated here). In this way, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected.

The first CAN bus 10 can also send a recessive level signal (that is, a signal with a sending level of 1). At this time, the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit a signal to TX2 through the tri-state gate U10, therefore, it is necessary to judge the relationship between the input terminal and the output terminal of the tri-state gate U10. The level 1 of TX1 becomes level 0 through the NOT gate U11; when the level of the output control terminal of the tri-state gate U10 is 0, the level of the output terminal of the tri-state gate U10 is the same as the level of the input terminal of the tri-state gate U10, so the level of TX2 is the same as the level of RX1, both are 1. The level of RX2 is the same as that of TX2, therefore, the level of RX2 is 1. RX2 needs to transmit signals to TX1 through the tri-state gate U12, therefore, it is necessary to judge the relationship between the input terminal and the output terminal of the tri-state gate U12. The level 1 of TX2 becomes 0 through the NOT gate U13; the level of the output control terminal of the tri-state gate U12 is 0, and the level of the output terminal of the tri-state gate U12 is the same as the level of the input terminal of the tri-state gate U12. Therefore, the level of TX1 connected to the output terminal of U7 is 1. In this way, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1.

To sum up, when the first CAN bus 10 sends a signal, the levels of TX1, RX1, TX2, and RX1 are different from 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected.

Similarly, when the second CAN bus 50 sends a signal (that is, the state of the second CAN bus 50 is dominant), the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so that the self-locking phenomenon can be avoided when the CAN bus is connected.

In addition, assuming that both the first CAN bus 10 and the second CAN bus 50 are idle, the level of RX1 is 1, and the level of TX1 is 1. Based on the same reason as that the first CAN bus 10 sends a recessive level signal, at this time, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1. Therefore, through the device shown in Figure 10, when the states of the first CAN bus 10 and the second CAN bus 50 are both idle, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0 at the same time, thereby avoiding the self-locking phenomenon when the CAN bus is connected.

To sum up, in case 1, the relationship between the bus state and the levels of TX1 , RX1 , TX2 and RX2 can be shown in Table 5.

table 5

Case 2: Both the tri-state gate U10 and the tri-state gate U12 are high-level enabled tri-state gates.

When the first CAN bus 10 sends a signal (that is, the state of the first CAN bus 10 is dominant), the level of RX1 is 0, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1 (specific content can refer to the content of the invention, and will not be repeated here). In this way, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so as to avoid the self-locking phenomenon when the CAN bus is connected.

The first CAN bus 10 can also send a recessive level signal (that is, a signal with a sending level of 1). At this time, the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1->TX2->RX2->TX1. RX1 needs to transmit a signal to TX2 through the tri-state gate U10, therefore, it is necessary to judge the relationship between the input terminal and the output terminal of the tri-state gate U10. The level 1 of TX1 becomes level 0 through the NOT gate U11; when the level of the output control terminal of the tri-state gate U10 is 0, the output terminal of the tri-state gate U10 is high impedance, which can block the path between RX1 and TX2. Since TX2 is connected to a power supply device, the level of TX2 is 1. RX2 receives the signal from TX2, so that the level of RX2 is the same as the level of TX2, therefore, the level of RX2 is 1. RX2 needs to transmit signals to TX1 through the tri-state gate U12, therefore, it is necessary to judge the relationship between the input terminal and the output terminal of the tri-state gate U12. The level 1 of TX2 becomes 0 through the NOT gate U13; when the level of the output control terminal of the tri-state gate U12 is 0, the output terminal of the tri-state gate U12 is high impedance, blocking the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is 1. In this way, the level of RX1 is 1, the level of TX2 is 1, the level of RX2 is 1, and the level of TX1 is 1.

To sum up, in case 2, the relationship between the bus state and the levels of TX1 , RX1 , TX2 and RX2 can be shown in Table 6.

Table 6

The embodiment of the present application also provides a bus processing system. Figure 11 shows a possible architecture of the bus processing system 70. As shown in Figure 11, the bus processing system 70 includes: a first transceiver 20, a second transceiver 40, and any of the bus processing devices 60; wherein, the connection relationship between the first transceiver 20, the second transceiver 40 and the bus processing device 60 can refer to the above-mentioned embodiments, and will not be repeated here. The bus processing system 70 can realize the effects of any of the bus processing devices 60 described above, which will not be repeated here.

Apparently, those skilled in the art can make various changes and modifications to this application without departing from the protection scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A bus processing device, characterized by comprising: a first switching device, a second switching device, a power supply, a first resistor and a second resistor;

The control electrode of the first switching device is connected to the sending end of the first transceiver, the first electrode of the first switching device is connected to the receiving end of the first transceiver, the second electrode of the first switching device is connected to the sending end of the second transceiver, and the second electrode of the first switching device is also connected to the power supply through the first resistor;

The control electrode of the second switching device is connected to the sending end of the second transceiver, the first electrode of the second switching device is connected to the receiving end of the second transceiver, the second electrode of the second switching device is connected to the sending end of the first transceiver, and the second electrode of the second switching device is also connected to the power supply through the second resistor;

Wherein, the first transceiver is connected to the first controller area network CAN bus, and the second transceiver is connected to the second CAN bus;

The first switching device is configured to: disconnect the path between the receiving end of the first transceiver and the transmitting end of the second transceiver when the level of the sending end of the first transceiver is low;

The second switching device is configured to disconnect the path between the receiving end of the second transceiver and the sending end of the first transceiver when the level of the sending end of the second transceiver is low.
The device according to claim 1, wherein any one of the first switching device and the second switching device is at least one of the following:

Triode, N-type Metal Oxide Semiconductor Field Effect Transistor.
The device according to claim 2, characterized in that,

When any one of the first switching device and the second switching device is a triode, the control electrode of any one of the switching devices is a base, the first electrode of any one of the switching devices is an emitter, and the second electrode of any one of the switching devices is a collector; or

When any one of the first switching device and the second switching device is an N-type metal-oxide-semiconductor field-effect transistor, the control electrode of any one of the switching devices is a gate, the first electrode of any one of the switching devices is a drain, and the second electrode of any one of the switching devices is a source; or

When any switching device in the first switching device and the second switching device is an N-type metal oxide semiconductor field effect transistor, the control electrode of any switching device is a gate, the first electrode of any switching device is a source, and the second electrode of any switching device is a drain.
The device according to any one of claims 1 to 3, further comprising: a first diode and a second diode;

The anode of the first diode is connected to the receiving end of the first transceiver, and the cathode of the first diode is connected to the sending end of the second transceiver;

The anode of the second diode is connected to the receiving end of the second transceiver, and the cathode of the second diode is connected to the sending end of the first transceiver.
The device according to any one of claims 1 to 4, further comprising: a first capacitor and a second capacitor;

Both ends of the first capacitor are respectively connected to the receiving end of the first transceiver and the transmitting end of the second transceiver;

Both ends of the second capacitor are respectively connected to the receiving end of the second transceiver and the sending end of the first transceiver.
The device according to any one of claims 1 to 5, further comprising a third resistor and/or a fourth resistor;

The control electrode of the first switching device is connected to the sending end of the first transceiver through the third resistor;

The control electrode of the second switching device is connected to the sending end of the second transceiver through the fourth resistor.
A bus processing device, characterized by comprising: a first tri-state gate, a second tri-state gate, a first NOT gate, a second NOT gate, a power supply, a fifth resistor and a sixth resistor;

The input end of the first tri-state gate is connected to the receiving end of the first transceiver, the output end of the first tri-state gate is connected to the transmitting end of the second transceiver, and the output end of the first tri-state gate is also connected to the power supply through the fifth resistor;

The input terminal of the second tristate gate is connected to the receiving terminal of the second transceiver, and the output terminal of the second tristate gate is connected to the transmitting terminal of the first transceiver;

The input terminal of the first NOT gate is connected to the sending terminal of the first transceiver, the output terminal of the first NOT gate is connected to the output control terminal of the first tri-state gate, and the output terminal of the second tri-state gate is also connected to the power supply through the sixth resistor;

The input terminal of the second NOT gate is connected to the sending terminal of the second transceiver, and the output terminal of the second NOT gate is connected to the output control terminal of the second tri-state gate;

Wherein, the first transceiver is connected to the first controller area network CAN bus, and the second transceiver is connected to the second CAN bus;

The first tri-state gate and the second tri-state gate are tri-state gates enabled with a low level; or, the first tri-state gate and the second tri-state gate are tri-state gates enabled with a high level.
A bus processing system, characterized by comprising: the device as claimed in any one of claims 1 to 7, the first transceiver, and the second transceiver.