CN116783870A

CN116783870A - Bus processing device and system

Info

Publication number: CN116783870A
Application number: CN202280005473.3A
Authority: CN
Inventors: 樊孝斌; 于鹏鹏
Original assignee: Huawei Digital Power Technologies Co Ltd
Current assignee: Huawei Digital Power Technologies Co Ltd
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2023-09-19
Also published as: WO2023137593A1

Abstract

A bus processing device and system. The device comprises: the first switching device, the second switching device, the power supply, the first resistor and the second resistor. The control electrode of the first switching device is connected to the transmitting end (namely TX 1) of the first transceiver, the first electrode is connected to the receiving end (namely RX 1) of the first transceiver, the second electrode is connected to the transmitting end (namely TX 2) of the second transceiver, and the first electrode is connected to a power supply through a first resistor; the control electrode of the second switching device is connected to TX2, the first electrode is connected to the receiving terminal of the second transceiver (i.e., RX 2), the second electrode is connected to TX1, and is connected to the power supply through the second resistor. The first switching device is used for: when the level of TX1 is low, the path between RX1 and TX2 is disconnected; the second switching device is used for: when the level of TX2 is low, the path between RX2 and TX1 is opened. Thus, the self-locking phenomenon CAN be avoided when the CAN bus is connected.

Description

Bus processing device and system

Technical Field

The present application relates to the field of communications technologies, and in particular, to a bus processing device and system.

Background

The controller area network (controller area network, CAN) bus is a field bus that is effective to support serial communications for distributed control systems. At present, the CAN bus is widely applied to the fields of industrial automation, ships, medical equipment, industrial equipment and the like.

The CAN buses may be interconnected in the form of cable buses. For example, as shown in fig. 1A, the first CAN bus 10 may be connected to the second CAN bus 50 through the first transceiver 20, the isolation device 30, and the second transceiver 40 in sequence. Wherein the first transceiver 20 is connected with the first CAN bus 10, and CAN receive or transmit signals through the first CAN bus 10; the second transceiver 40 is connected to the second CAN bus 50, and CAN receive or transmit signals through the second CAN bus 50. With the architecture of fig. 1A, the level of RX1, the level of TX1, the level of RX2, and the level of TX2 may all be low, resulting in a self-locking phenomenon of the first CAN bus 10 and the second CAN bus 50. Wherein, RX1 is the receiving end of the first transceiver 20, TX1 is the transmitting end of the first transceiver 20, RX2 is the receiving end of the second transceiver 40, and TX2 is the transmitting end of the second transceiver 40.

Disclosure of Invention

The application provides a bus processing device and a bus processing system, which are used for avoiding the self-locking phenomenon during CAN bus connection.

In a first aspect, an embodiment of the present application provides a bus processing apparatus. This method may be applied to the system shown in fig. 2A or 2B below. The bus processing device includes: the first switching device, the second switching device, the power supply, the first resistor and the second resistor.

Wherein the control electrode of the first switching device is connected to the transmitting terminal (hereinafter abbreviated as TX 1) of the first transceiver, the first electrode of the first switching device is connected to the receiving terminal (hereinafter abbreviated as RX 1) of the first transceiver, the second electrode of the first switching device is connected to the transmitting terminal (hereinafter abbreviated as TX 2) of the second transceiver, and the second electrode of the first switching device is also connected to the power supply through the first resistor. The control electrode of the second switching device is connected to the transmitting terminal of the second transceiver, the first electrode of the second switching device is connected to the receiving terminal of the second transceiver (hereinafter, simply referred to as RX 2), the second electrode of the second switching device is connected to the transmitting terminal of the first transceiver, and the second electrode of the second switching device is also connected to the power supply through the second resistor. The first transceiver may be connected to a first CAN bus and the second transceiver may be connected to a second CAN bus.

The first switching device is used for: when the level of the transmitting end of the first transceiver is low, disconnecting a path between the receiving end of the first transceiver and the transmitting end of the second transceiver; the second switching device is used for: when the level of the transmitting end of the second transceiver is low, the path between the receiving end of the second transceiver and the transmitting end of the first transceiver is disconnected.

By means of two simple switching devices in the device, the level of RX1, the level of TX1, the level of RX2 and the level of TX2 CAN be different to be low, so that the phenomenon of self-locking during CAN bus connection is avoided, and the self-locking is described in detail below.

When the first CAN bus transmits a signal, the level of TX1 is high and the level of RX1 is low. The transmission direction of the signal is RX1- > TX2- > RX2- > TX1.

In a first possible case, when the level of TX1 is high, the first switching device turns on the path between RX1 and TX2, and RX1 may transfer a signal from the first CAN bus to TX2 so that the level of TX2 is the same as the level of RX1, both being low. RX2 receives the signal from TX2 so that the level of RX2 is the same as the level of TX2, both low. Since the level of TX2 is low, the second switching device opens the path between RX2 and TX1, and the level of TX1 is its own static level. Since TX1 is connected with a power supply (e.g., a power supply for powering the first transceiver or a power supply for powering the isolation device), the level of TX1 is high. Thus, in the first possible case, the level of RX1, the level of TX2, and the level of RX2 are low, and the level of TX1 is high.

In a second possible case, when the level of TX1 is high, the first switching device opens the path between RX1 and TX2, and the level of TX2 is its own static level. Since TX2 is connected to a power supply (e.g., a power supply that powers the second transceiver), the level of TX2 is high. RX2 receives the signal from TX2 such that the level of RX2 is the same as the level of TX2, both high.

Then, the second case may have two branches.

Branch one: if the second switching device turns on the path between RX2 and TX1 when the level of TX2 is high, the level of TX1 is the same as the level of RX2, and both are high. Thus, in branch one of the second possible scenario, the level of RX1 is low, and the level of TX2, RX2 and TX1 are high.

Branch two: if the second switching device turns off the path between RX2 and TX1 when the level of TX2 is high, the level of TX1 is its own static level. Since TX1 is connected to the power supply device, the level of TX1 is high. Thus, in branch two of the second possible case, the level of RX1 is low, and the level of TX2, the level of RX2, and the level of TX1 are high.

To sum up, when the first CAN bus transmits a signal, the level of TX1 is 1, regardless of the situation. In this way, the level of TX1, the level of RX1, the level of TX2 and the level of RX1 are not 0 at the same time, so that the self-locking phenomenon is avoided when the CAN bus is connected.

Similarly, when the second CAN bus transmits a signal, the level of TX2 is 1. In this way, the level of TX1, the level of RX1, the level of TX2 and the level of RX1 are not 0 at the same time, so that the self-locking phenomenon is avoided when the CAN bus is connected.

In one possible design, either one of the first switching device and the second switching device is at least one of: triode, N-type metal oxide semiconductor field effect transistor. Through the design, the bus processing device comprises a simple triode or an N-type metal oxide semiconductor field effect transistor, so that the self-locking phenomenon CAN be avoided when the CAN bus is connected, and the bus processing device has the advantages of simple structure and low cost.

In one possible design, when either one of the first switching device and the second switching device is a triode, the control electrode of either switching device is a base electrode, the first electrode of either switching device is an emitter electrode, and the second electrode of either switching device is a collector electrode; or when any one of the first switching device and the second switching device is an N-type metal oxide semiconductor field effect transistor, the control electrode of any one switching device is a grid electrode, the first electrode of any one switching device is a drain electrode, and the second electrode of any one switching device is a source electrode; or when any one of the first switching device and the second switching device is an N-type metal oxide semiconductor field effect transistor, the control electrode of any one switching device is a gate, the first electrode of any one switching device is a source, and the second electrode of any one switching device is a drain. The design provides various modes of connecting the switching device with other equipment, and is flexible.

In one possible design, the apparatus further comprises: a first diode and a second diode. The anode of the first diode is connected to the receiving end of the first transceiver, and the cathode of the first diode is connected to the transmitting end of the second transceiver; the positive pole of the second diode is connected to the receiving end of the second transceiver, and the negative pole of the second diode is connected to the transmitting end of the first transceiver. By the design, the first diode is connected with the first switching device in parallel, so that the disconnection of the first switching device can be accelerated; the second diode is connected in parallel with the second switching device, which can accelerate the opening of the second switching device. The disconnection of the switching device CAN avoid the self-locking phenomenon when the CAN bus is connected, so that the disconnection of the switching device CAN be accelerated to avoid the self-locking phenomenon when the CAN bus is connected.

In one possible design, the apparatus may further include: a first capacitance and a second capacitance. Two ends of the first capacitor are respectively connected to the receiving end of the first transceiver and the transmitting end of the second transceiver; the two ends of the second capacitor are respectively connected to the receiving end of the second transceiver and the transmitting end of the first transceiver. By the design, the first capacitor is connected with the first switching device in parallel, so that the signal of the first switching device can be filtered; the second capacitor is connected in parallel with the second switching device so that the signal of the second switching device can be filtered.

In one possible design, the device may further include a third resistor and/or a fourth resistor. The control electrode of the first switching device is connected to the transmitting end of the first transceiver through a third resistor; the control electrode of the second switching device is connected to the transmitting terminal of the second transceiver through a fourth resistor.

Through the design, the third resistor can limit the current input to the control electrode of the first switching device, so that the first switching device is prevented from being damaged due to overlarge current, and the performance and the service life of the first switching device can be improved. The fourth resistor can limit the current input to the control electrode of the second switching device, so that the second switching device is prevented from being damaged due to overlarge current, and the performance and the service life of the second switching device can be improved.

In a second aspect, an embodiment of the present application provides a bus processing apparatus. This method may be applied to the system shown in fig. 2A or 2B below. The bus processing device includes: the first tri-state gate, the second tri-state gate, the first NOT gate, the second NOT gate, the power supply, the fifth resistor and the sixth resistor. Wherein, the input end of the first tri-state gate is connected to the receiving end (RX 1) of the first transceiver, the output end of the first tri-state gate is connected to the transmitting end (TX 2) of the second transceiver, and the output end of the first tri-state gate is also connected to the power supply through the fifth resistor; the input end of the second tri-state gate is connected to the receiving end (hereinafter abbreviated as RX 2) of the second transceiver, the output end of the second tri-state gate is connected to the transmitting end (hereinafter abbreviated as TX 1) of the first transceiver, and the output end of the second tri-state gate is also connected to the power supply through a sixth resistor; the input end of the first NOT gate is connected to the transmitting end of the first transceiver, and the output end of the first NOT gate is connected to the output control end of the first tri-state gate; the input end of the second NOT gate is connected to the transmitting end of the second transceiver, and the output end of the second NOT gate is connected to the output control end of the second tri-state gate; the first transceiver is connected with the first CAN bus, and the second transceiver is connected with the second CAN bus. The first tri-state gate and the second tri-state gate may both be low-level enabled tri-state gates; alternatively, the first tri-state gate and the second tri-state gate may each be a high-enabled tri-state gate.

The level of RX1, the level of TX1, the level of RX2 and the level of TX2 are different from each other to be low level through simple devices in the device, so that the self-locking phenomenon is avoided when CAN buses are connected. This will be specifically described below.

Case 1: the first tri-state gate and the second tri-state gate are both low-level enabled tri-state gates.

When the first CAN bus transmits a signal (i.e., the state of the first CAN bus is dominant), the level of TX1 is high, the level of RX1 is low, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to pass the signal through the first tri-state gate to TX2 and therefore the relationship between the input and output of the first tri-state gate needs to be determined. The high level of TX1 goes low through the first not gate; when the output control terminal of the first tri-state gate is at a low level, the level of the output terminal of the first tri-state gate is the same as the level of the input terminal of the first tri-state gate, and thus, the level of TX2 is at a low level. RX2 receives the signal from TX2 such that the level of RX2 is the same as the level of TX2, and thus, the level of RX2 is low. RX2 needs to pass the signal to TX1 through the second tri-state gate, and therefore, the relationship between the input and output of the second tri-state gate needs to be determined. The low level of TX2 goes high through the second not gate; when the output control end of the second tri-state gate is at a high level, the output end of the second tri-state gate is at a high resistance, and the path between RX2 and TX1 is blocked. Since TX1 is connected to the power supply device, the level of TX1 is high. Thus, in case 1, the level of RX1, the level of TX2, and the level of RX2 are low, and the level of TX1 is high.

Therefore, when the first CAN bus transmits signals, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from each other to be low, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Similarly, when the second CAN bus transmits a signal (i.e., the state of the second CAN bus is dominant), the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from low levels, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Case 2: the first tri-state gate and the second tri-state gate are both high enabled tri-state gates.

When the first CAN bus transmits a signal (i.e., the state of the first CAN bus is dominant), the level of TX1 is high, the level of RX1 is low, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to pass the signal through the first tri-state gate to TX2 and therefore the relationship between the input and output of the first tri-state gate needs to be determined. The high level of TX1 goes low through the first not gate; when the output control terminal of the first tri-state gate is at a low level, the output terminal of the first tri-state gate is high-impedance, which can block the path between RX1 and TX 2. Since TX2 is connected to a power supply device, the level of TX2 is high. RX2 receives the signal from TX2 such that the level of RX2 is the same as the level of TX2, and thus, the level of RX2 is high. RX2 needs to pass the signal to TX1 through the second tri-state gate, and therefore, the relationship between the input and output of the second tri-state gate needs to be determined. The high level of TX2 goes low through the second not gate; when the output control terminal of the second tri-state gate is at a low level, the output terminal of the second tri-state gate is high-impedance, thereby blocking the path between RX2 and TX1. Since TX1 is connected to the power supply device, the level of TX1 is high. Thus, in case 2, the level of RX1 is low, and the level of TX2, the level of RX2, and the level of TX1 are high.

In a third aspect, an embodiment of the present application provides a bus processing system, including: any of the bus processing devices described above, a first transceiver, and a second transceiver.

The technical effects that can be achieved by the third aspect may be described with reference to the technical effects that can be achieved by any one of the possible designs of the first aspect or the second aspect, and the description will not be repeated.

Drawings

FIG. 1A is a schematic diagram of a communication system;

FIG. 1B is a schematic diagram of another communication system;

FIG. 2A is a schematic diagram of a system to which a bus processing apparatus according to an embodiment of the present application is applicable;

FIG. 2B is a schematic diagram of another system to which the bus processing apparatus according to the embodiment of the present application is applicable;

FIG. 3 is a schematic diagram of a bus processing apparatus according to an embodiment of the present application;

fig. 4, fig. 5, fig. 6, and fig. 7A to fig. 7D are schematic diagrams of an extension scheme of a bus processing apparatus according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an implementation of a bus processing apparatus according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another implementation of a bus processing apparatus according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another bus processing apparatus according to an embodiment of the present application;

fig. 11 is a schematic diagram of a bus processing system according to an embodiment of the present application.

Detailed Description

In the scheme provided by the embodiment of the application, the bus processing device comprises a first switching device, a second switching device, a power supply, a first resistor and a second resistor. Wherein, the control electrode of the first switching device may be connected to the transmitting terminal of the first transceiver (hereinafter abbreviated as TX 1), the first electrode of the first switching device may be connected to the receiving terminal of the first transceiver (hereinafter abbreviated as RX 1), the second electrode of the first switching device may be connected to the transmitting terminal of the second transceiver (hereinafter abbreviated as TX 2), and the second electrode of the first switching device may be further connected to the power supply through the first resistor; the control electrode of the second switching device may be connected to TX2, the first electrode of the second switching device may be connected to a receiving terminal of the second transceiver (hereinafter, simply referred to as RX 2), the second electrode of the second switching device may be connected to TX1, and the second electrode of the second switching device may be further connected to a power supply through a second resistor. The first transceiver is a transceiver connected with the first CAN bus, and the second transceiver is a transceiver connected with the second CAN bus. The first switching device may be for: when the level of TX1 is low, the path between RX1 and TX2 is disconnected; the second switching device may be for: when the level of TX2 is low, the path between RX2 and TX1 is opened.

Through this scheme, when the first CAN bus transmits a signal, the level of TX1 is 1 (the specific content may refer to the summary of the application, and will not be described here again). In this way, the level of TX1, the level of RX1, the level of TX2 and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN bus is connected. When the second CAN bus transmits a signal, the level of TX2 is 1. That is, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are also different from 0, so that the self-locking phenomenon CAN be avoided when the CAN bus is connected.

In the following, some terms in the embodiments of the present application are explained for easy understanding by those skilled in the art.

1) In the present application, when 0 and 1 represent levels, 0 represents a low level and 1 represents a high level. Wherein the high level is greater than the low level.

For example, for a transistor-transistor logic integrated circuit (TTL) level, the high level is greater than 2.4 volts (V), which can be represented by 1; the low level is less than 0.4V and can be represented by 0. For another example, for a complementary metal oxide semiconductor (complemetary metal oxide semiconductor, CMOS) level, the high level is greater than 4.99V, which can be represented by 1; the low level is less than 0.01V and can be represented by 0.

2) The CAN bus is a bus capable of supporting serial communication of a distributed control system.

The CAN bus may transmit signals according to differential levels. Specifically, the CAN bus may be twisted pair, and the two wires may be referred to as can_h and can_l, respectively. When no signal is transmitted, the voltages of can_h and can_l are the same (e.g., can_h and can_l are both 2.5 volts (V)), i.e., can_h and can_l differ by 0; at this time, the levels of can_h and can_l are 0 on average, and the state of the CAN bus is recessive (may also be referred to as idle). When there is signal transmission, the voltages of can_h and can_l are different (for example, the voltage of can_h is 3.5V, the voltage of can_l is 1.5V), thereby generating a voltage difference; at this time, the level of can_h is 1, the level of can_l is 0, and the state of the CAN bus is dominant.

3) The transceiver in the application is used for receiving signals from a CAN bus and/or transmitting signals to the CAN bus.

When the state of the CAN bus is dominant, the transceiver may receive signals from the CAN bus and convert the signals from the CAN bus to TTL levels. At this time, the level of the receiving end of the transceiver is 0, and the level of the transmitting end of the transceiver is 1.

When the level of the transmitting end of the transceiver is 0, the transceiver indicates that there is a signal to be transmitted, and the CAN bus needs to be occupied, so that the state of the CAN bus is dominant for transmitting the signal.

The transceiver in the application can be a sensor or an electronic device. Wherein the sensor may be: a speed sensor, a temperature sensor, a humidity sensor, etc. The electronic device may be a computer device having a processor, such as a desktop computer, a personal computer, or a server, etc. It should also be appreciated that the electronic device may also be a portable electronic device having a processor, such as a cell phone, tablet computer, wearable device with wireless communication capabilities (e.g., smart watch), vehicle-mounted device, etc. Exemplary embodiments of portable electronic devices include, but are not limited to, piggy-backOr other operating system.

In the present application, the transceiver may also be replaced by a device capable of converting the signal of the CAN bus to a TTL level, for example, a level shifter.

4) A tri-state gate, which may also be referred to as a tri-state output circuit, is a logic device. The tri-state gate comprises an input end, an output end and an output control end; under the control of the output control end, the tri-state gate can output three different output values: 0 (corresponding to a low level), 1 (corresponding to a high level), and high resistance.

The tri-state gates may be low-level enabled tri-state gates or high-level enabled tri-state gates.

When the tri-state gate is a tri-state gate with low level enabling, if the level of the output control end is 0, the level of the output end is the same as the level of the input end; if the level of the output control terminal is 1, the state of the output terminal is high resistance. Specifically, the correspondence of the levels of the input terminal, the output terminal, and the output control terminal of the low-level enabled tri-state gate is shown in table 1.

TABLE 1

Level of output control terminal	Level of input terminal	Level of output terminal
1	0 or 1	High resistance
0	0	0
0	1	1

When the tri-state gate is a tri-state gate enabled by a high level, if the level of the output control end is 1, the level of the output end is the same as the level of the input end; if the level of the output control terminal is 0, the state of the output terminal is high resistance. Specifically, the correspondence of the levels of the input terminal, the output terminal, and the output control terminal of the high-level enabled tri-state gate is shown in table 2.

TABLE 2

Level of output control terminal	Level of input terminal	Level of output terminal
0	0 or 1	High resistance
1	0	0
1	1	1

5) The electrical isolation refers to the electrical isolation between a power supply and a power utilization loop, namely, the power utilization branch circuit is isolated from the whole electrical system, so that the power utilization branch circuit is an isolated and independent non-grounding safety system electrically so as to prevent the risk of indirect electric shock under the condition of electrification of a bare conductor fault.

6) The connection in the present application may be a direct connection, or may be through one or more modules or through one or more devices. For example, a is linked to B, or a is linked to B, may represent: a is directly connected with B, or A is connected with B through C. Wherein C may represent one or more modules or one or more devices.

7) In the present application, RX1 is the receiving end of the first transceiver 20, TX1 is the transmitting end of the first transceiver 20, RX2 is the receiving end of the second transceiver 40, and TX2 is the transmitting end of the second transceiver 40.

In the embodiments of the present application, the number of nouns, unless otherwise indicated, means "a singular noun or a plural noun", i.e. "one or more". "at least one" means one or more, and "a plurality" means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s).

In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not be construed as indicating or implying a relative importance or order.

Currently, when two CAN buses are connected, a self-locking phenomenon may occur. This is described in detail below in conjunction with fig. 1A.

Fig. 1A shows a possible system architecture diagram after two CAN buses are connected. As shown in fig. 1A, the system includes: a first CAN bus 10, a first transceiver 20, an isolation device 30, a second transceiver 40, a second CAN bus 50. The first CAN bus 10 may be connected to the second CAN bus 50 through the first transceiver 20, the isolating device 30, and the second transceiver 40 in sequence.

The specific contents of the first CAN bus 10, the first transceiver 20, the second transceiver 40 and the second CAN bus 50 may refer to the descriptions of the CAN bus and the transceivers in the noun explanation section, and the repetition is omitted.

The isolation device 30 is used to achieve electrical isolation between the first CAN bus 10 and the second CAN bus 50. For example, the isolation device 30 may be an isolation transformer, a photoelectric coupling element, or the like. The level of both sides of the isolation device 30 is the same.

As shown in fig. 1A, when the first CAN bus 10 transmits a signal, the state of the first CAN bus 10 is dominant, and the transmission path of the signal is RX1- > TX2- > RX2- > TX1- > RX1. Since the state of the first CAN bus 10 is dominant, the voltage of can_h1 is higher than can_l1, and the level of RX1 is 0. The level at both ends of the isolation device 30 is the same, and thus, the level of TX2 is the same as the level of RX1, and is 0.RX2 receives the signal from TX2, and therefore, the level of RX2 is the same as that of TX2, and is 0. Since the levels at both ends of the isolation device are the same, the level of TX1 is the same as the level of RX2, and both are 0. Since the level of TX1 is 0, RX1 receives a signal from TX1 such that the level of RX1 is 0. The above procedure is repeated, with the levels of RX1, TX1, RX2 and TX2 continuing to be 0. As described above, when the level of the transmitting end of the transceiver is 0, it indicates that the transceiver has a signal to transmit, and the CAN bus needs to be occupied, so that the state of the CAN bus is dominant for transmitting the signal. Therefore, the TX1 level is continuously 0, so that the state of the first CAN bus 10 is continuously dominant, and the first CAN bus 10 cannot be released, thereby forming a self-locking phenomenon of the CAN bus.

Similarly, when the second CAN bus 20 transmits signals, the levels of RX1, TX1, RX2 and TX2 are also continuously 0, and the state of the second CAN bus 20 is continuously dominant, so that the second CAN bus cannot be released, and the self-locking phenomenon of the CAN bus is formed.

In order to solve the problem of self-locking of the CAN bus, a bus multipath isolation system is provided at present. As shown in fig. 1B, the system includes: OR gate U1, OR gate U2, NAND gate U3, trailing edge delay circuit U4, OR gate U5, OR gate U6, NAND gate U7, trailing edge delay circuit U8, NAND gate U9.

The connection manner of each device is shown in fig. 1B. Specifically, one input of the or gate U1 is connected to the output ends of the 1T and the or gate U2, the other input of the or gate U1 is connected to the output end of the nand gate U9, and the output end of the or gate U1 is connected to one input end of the nand gate U3. One input of the or gate U2 is connected to the output end of the lower edge delay circuit U4, and the other input of the or gate U2 is connected to 2R. One input of the NAND gate U3 is connected to 1R, the other input is connected to the output end of the OR gate U1, and the output end of the NAND gate U3 is connected to the lower edge delay circuit U4. The signal of RX1 becomes a signal of 1R after digital isolation, the signal of 1T becomes a signal of TX1 after digital isolation, and the levels at two ends of digital isolation are equal. The connection modes of the or gate U5, the or gate U6, the nand gate U7 and the lower edge delay circuit U8 correspond to the connection modes of the or gate U1, the or gate U2, the nand gate U3 and the lower edge delay circuit U4, and are not described herein again.

In this system, the first CAN bus 10 connected to the first transceiver 20 is a remote CAN bus, and the second CAN bus 50 connected to the second transceiver 40 is a local CAN bus. The isolation device 30 includes digital isolation 301 and digital isolation 302.

In the following, a description will be given of how the system solves the problem of self-locking of the CAN bus by taking the signal transmitted by the first CAN bus 10 as an example. When the first CAN bus 10 transmits a signal, the level of TX1 is 1 and the level of rx1 is 0. The signal of RX1 becomes a signal of 1R after digital isolation, and the level of 1R is 0. Level 0 is taken as an input of the nand gate U3, so that the level of the output of the nand gate U3 is 1. The level 1 is still 1 after passing through the lower edge delay circuit U4, i.e. the level at the output end of the lower edge delay circuit U4 is 1. Level 1 is taken as an input of the or gate U2, so that the level of the output of the or gate U2 is 1, and thus the level of 1T is also 1. The level of 1T becomes the signal of TX1 after digital isolation, so that the level of TX1 is 1. In this way, the CAN bus self-locking CAN be avoided when the first CAN field bus sends signals through the OR gate U5, the OR gate U6, the NAND gate U7 and the lower edge delay circuit U8.

However, the system needs to use a plurality of gate structures and a lower edge delay circuit to avoid bus self-locking, the scheme is complex, and the requirement on the performance of the controller is high.

In view of the above, the present application provides a bus processing device 60, which CAN avoid the occurrence of the self-locking phenomenon when the CAN bus is connected by using a simple structure of the bus processing device 60. The bus processing device 60 may be applied to the system shown in fig. 2A or fig. 2B.

As shown in fig. 2A, the system may include a first CAN bus 10, a first transceiver 20, an isolation device 30, a second transceiver 40, a second CAN bus 50, and a bus processing device 60. The first CAN bus 10 may be connected to the second CAN bus 50 through the first transceiver 20, the isolating device 30, the bus processing device 60, and the second transceiver 40 in this order.

As shown in fig. 2B, the system may include a first CAN bus 10, a first transceiver 20, a second transceiver 40, a second CAN bus 50, and a bus processing device 60. The first CAN bus 10 may be connected to the second CAN bus 50 through the first transceiver 20, the bus processing device 60, and the second transceiver 40 in sequence.

In the system shown in fig. 2A or 2B, the voltages of the first CAN bus 10 and the second CAN bus 50 may be the same or different. When the voltages of the first CAN bus 10 and the second CAN bus 50 are different, the voltage of the first CAN bus may be higher than the voltage of the second CAN bus, and the voltage of the first CAN bus may be lower than the voltage of the second CAN bus.

The implementation of the bus processing device 60 will be described in detail below with reference to the accompanying drawings.

Fig. 3 shows a possible configuration of a bus processing apparatus 60 according to an embodiment of the present application. The bus processing device 60 includes: a first switching device 601, a second switching device 602, a power supply 603, a resistor R1, and a resistor R2.

Wherein the second electrode of the first switching device 601 may be connected to the power supply 603 through a resistor R1. In this way, the power supply 603 may supply power to the first switching device 601. And due to the presence of the resistor R1, the current through the first switching device 601 can be limited, avoiding damaging the first switching device 601. A second electrode of the second switching device 602 may be connected to a power supply 603 through a resistor R2. In this way, the power supply 603 may supply power to the second switching device 602. And due to the presence of the resistor R2, the current through the second switching device 602 can be limited, avoiding damaging the second switching device 602. Optionally, the power supply 603 is a dc power supply such as a battery or a lithium battery.

Further, a control electrode of the first switching device 601 may be connected to TX1, a first electrode of the first switching device 601 may be connected to RX1, and a second electrode of the first switching device 601 may be connected to TX2; the control electrode of the second switching device 602 may be connected to TX2, the first electrode of the second switching device 602 may be connected to RX2, and the second electrode of the second switching device 602 may be connected to TX1.

Alternatively, when the bus processing apparatus 60 is in the system shown in fig. 2A, the first switching device 601 and the second switching device 602 may be connected to the first transceiver 20 through the isolation apparatus 30. Specifically, the control electrode of the first switching device 601 may be connected to TX1 through the isolation device 30, and the first electrode of the first switching device 601 may be connected to RX1 through the isolation device 30; a second electrode of the second switching device 602 may be connected to TX1 through the isolation means 30.

The first switching device 601 may be used to: when the level of TX1 is 0, the path between RX1 and TX2 is disconnected; that is, when the level of TX1 is 0, the first switching device 601 is in an off state. The second switching device 602 may be used to: when the level of TX2 is 0, the path between RX2 and TX1 is disconnected. That is, when the level of TX2 is 0, the second switching device 602 is in an off state.

By means of the device, when the first CAN bus 10 transmits signals, the level of TX1 is 1 (the specific content CAN refer to the summary and will not be described here), so that the level of TX1, the level of RX1, the level of TX2 and the level of RX1 are different from 0, and the self-locking phenomenon CAN be avoided when the CAN buses are connected. When the second CAN bus 50 transmits a signal, the level of TX2 is 1. That is, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are also different from 0, so that the self-locking phenomenon CAN be avoided when the CAN bus is connected.

And, the device connects two CAN buses through simple switching devices. Thus, signals between two CAN buses CAN be transmitted without delay, so that the real-time requirement is met; the simple switching device can reduce the cost and the power consumption of the bus, and can be used in various complex network topologies, so that the device has good application prospect.

Optionally, in the bus processing apparatus 60 shown in fig. 3, any one of the first switching device 601 and the second switching device 602 is one of the following: a semiconductor switch such as a triode or an N-type metal oxide semiconductor field effect transistor (metal oxide semiconductor field effect transistor, MOSFET) and a relay. Thus, the bus processing device 60 is simple in structure and low in cost.

Wherein each of the first switching device 601 and the second switching device 602 may include a control electrode, a first electrode, and a second electrode. The control electrode is used for controlling the on or off of the switching device. When the switching device is turned on, current can be transmitted between the first electrode and the second electrode of the switching device, and the level of the output end is equal to that of the input end; when the switching device is turned off, no current can be transferred between the first electrode and the second electrode of the switching device. Taking a triode as an example, a control electrode of the switching device is a base electrode, a first electrode of the switching device is an emitter electrode, and a second electrode of the switching device is a collector electrode. Taking an N-type MOSFET as an example, the control electrode of the switching device is a grid electrode, the first electrode of the switching device can be a source electrode, and the second electrode of the switching device can be a drain electrode; alternatively, the control electrode of the switching device may be a gate electrode, the first electrode of the switching device may be a drain electrode, and the second electrode of the switching device may be a source electrode.

Fig. 4-7D show an extension of the bus processing device 60 shown in fig. 3, and the application is described below in connection with fig. 4-7D.

As shown in fig. 4, in addition to the bus processing apparatus 60 shown in fig. 3, the bus processing apparatus 60 may further include: diode D1 and diode D2.

Wherein the anode of the diode D1 is connected to RX1, and the cathode of the diode D1 is connected to TX2; that is, the diode D1 is connected in parallel with the first switching device 601. The anode of the diode D2 is connected to RX2, and the cathode of the diode D2 is connected to TX1; that is, diode D2 is connected in parallel with the second switching device 602.

Alternatively, when the bus processing apparatus 60 is in the system shown in fig. 2A, the diode D1 and the diode D2 may be connected to the first transceiver 20 through the isolation apparatus 30. Specifically, the anode of the diode D1 may be connected to RX1 through the isolation device 30, and the cathode of the diode D2 may be connected to TX1 through the isolation device 30.

In this apparatus, the diode D1 is connected in parallel with the first switching device 601, and the opening of the first switching device 601 can be accelerated. In this way, when the level of TX1 is 0, the first switching device 601 CAN rapidly disconnect the path between RX1 and TX2, so that the level of TX2 becomes 1, and thus, the self-locking phenomenon is avoided when the CAN bus is connected. The diode D2 is connected in parallel with the second switching device 602, which may accelerate the opening of the second switching device 602. In this way, when the level of TX2 is 0, the second switching device 602 CAN rapidly disconnect the path between RX2 and TX1, so that the level of TX1 becomes 1, and thus, the self-locking phenomenon is avoided when the CAN bus is connected.

As shown in fig. 5, in addition to the bus processing apparatus 60 shown in fig. 3, the bus processing apparatus 60 may further include: a capacitor C1 and a capacitor C2.

Wherein, two ends of the capacitor C1 are respectively connected to RX1 and TX2; that is, the capacitor C1 is connected in parallel with the first switching device 601. Two ends of the capacitor C2 are respectively connected to RX2 and TX1; that is, the capacitor C2 is connected in parallel with the second switching device 602.

Alternatively, when the bus processing apparatus 60 is in the system shown in fig. 2A, the capacitor C1 and the capacitor C2 may be connected to the first transceiver 20 through the isolation apparatus 30. Specifically, capacitor C1 may be connected to RX1 through isolation device 30, and capacitor C2 may be connected to TX1 through isolation device 30.

In this apparatus, a capacitor C1 is connected in parallel with the first switching device 601, so that a signal of the first switching device 601 can be filtered. The capacitor C2 is connected in parallel with the second switching device 602 so that the signal of the second switching device 602 can be filtered.

As shown in fig. 6, in addition to the bus processing apparatus 60 shown in fig. 3, the bus processing apparatus 60 may further include: resistor R3 and/or resistor R4.

Wherein both ends of the resistor R3 are connected to the control electrode of the first switching device 601 and TX1, respectively. Thus, the resistor R3 may limit the current input to the control electrode of the first switching device 601, and thus, the resistor R3 is a current limiting resistor. By limiting the current input to the control electrode of the first switching device 601, damage to the first switching device 601 due to excessive current can be avoided, and thus performance and lifetime of the first switching device 601 can be improved.

Alternatively, when the bus processing apparatus 60 is in the system shown in fig. 2A, the resistor R3 may be connected to the first transceiver 20 through the isolation apparatus 30. Specifically, resistor R3 may be connected to TX1 through isolation device 30.

The resistor R4 is connected at both ends to the control electrode of the second switching device 602 and TX2, respectively. Thus, the resistor R4 may limit the current input to the control electrode of the second switching device 602, and thus, the resistor R4 is a current limiting resistor. By limiting the current input to the control electrode of the second switching device 602, damage to the second switching device 602 due to excessive current can be avoided, and thus performance and lifetime of the second switching device 602 can be improved.

It will be appreciated that the bus processing means 60 shown in fig. 4-6 may be combined. For example, as shown in fig. 7A, the bus processing device 60 may include: the first switching device 601, the second switching device 602, the power supply 603, the resistor R1, the resistor R2, the diode D1, the diode D2, the resistor R3, and the resistor R4. As another example, as shown in fig. 7B, the bus processing apparatus 60 may include: the first switching device 601, the second switching device 602, the power supply 603, the resistor R1, the resistor R2, the diode D1, the diode D2, the capacitor C1, and the capacitor C2. As another example, as shown in fig. 7C, the bus processing device 60 may further include: the first switching device 601, the second switching device 602, the power supply 603, the resistor R1, the resistor R2, the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3, and the resistor R4. As another example, as shown in fig. 7D, the bus processing device 60 may further include: the first switching device 601, the second switching device 602, the power supply 603, the resistor R1, the resistor R2, the capacitor C1, the capacitor C2, the resistor R3, and the resistor R4. The connection between the devices in fig. 7A-7D may refer to the apparatus shown in fig. 3-6, and will not be described in detail herein.

Specific implementations of the first switching device 601 and the second switching device 602 in the bus processing apparatus 60 shown in fig. 3-7D are described below with respect to the bus processing apparatus 60 shown in fig. 8-9, respectively. The bus processing apparatus 60 shown in fig. 8 mainly describes a possible first case in which the first switching device 601 and the second switching device 602 are transistors; the bus processing apparatus 60 shown in fig. 9 mainly describes a second possible case in which the first switching device 601 and the second switching device 602 are both N-type MOSFETs.

As shown in fig. 8, the bus processing device 60 may include: transistor Q1, transistor Q2, power supply 603, resistor R1, resistor R2, diode D1, diode D2, capacitor C1, capacitor C2, resistor R3, and resistor R4.

The base electrode of the triode Q1 is connected to TX1, the emitter electrode of the triode Q1 is connected to RX1, the collector electrode of the triode Q1 is connected to TX2, and the collector electrode of the triode Q1 can be connected to a power supply 603 through a resistor R1; the base of transistor Q2 is connected to TX2, the emitter of transistor Q2 is connected to RX2, the collector of transistor Q2 is connected to TX1, and the collector of transistor Q2 is also connected to power supply 603 via resistor R2. That is, the transistor Q1 may be the first switching device 601 in the bus processing apparatus 60 shown in fig. 3 to 7D, and the transistor Q2 may be the second switching device 602 in the bus processing apparatus 60 shown in fig. 3 to 7D.

The connection relationship between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3 and the resistor R4 and the transistor Q1 and the transistor Q2 in the bus processing apparatus 60 shown in fig. 3-7D may refer to the connection relationship between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3 and the resistor R4 and the first switching device 601 and the second switching device 602, which are not described herein again.

Wherein, TX1, TX2, RX1 and RX2 can all be connected with a power supply device. The power supply means may be a power source (e.g. a direct current power source such as a battery, lithium battery or the like). For example, TX1 may be connected to a power supply through resistor R3, and TX2 may be connected to a power supply through resistor R4. RX1 and RX2 are connected to a power source, respectively. The power source to which TX1 and RX1 are connected may be a power source that powers the first transceiver 20; the power source for the TX2 and RX2 connections may be the power source that powers the second transceiver 40. The power source to which the TX1 and TX2 are connected may also be the power source that powers the isolation device 30 if the isolation device 30 is present between the first transceiver 20 and the second transceiver 40. Thus, when there is no input signal, the levels of TX1, TX2, RX1, RX2 are 1.

The level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0 by the bus processing device 60 shown in fig. 8, so that the self-locking phenomenon is avoided when the CAN bus is connected. This will be specifically described below.

When the first CAN bus 10 transmits a signal (i.e., the state of the first CAN bus 10 is dominant), the level of TX1 is 1, the level of RX1 is 0, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to transmit a signal to TX2 through transistor Q1, and therefore, it is necessary to determine the conduction of transistor Q1. Since the level of TX1 is higher than the level of RX1, transistor Q1 is turned on; at this time, the collector level and the emitter level of the transistor Q1 are the same, that is, the level of RX1 and the level of TX2 are the same, and thus, the level of TX2 is 0.RX2 receives the signal from TX2 so that the level of RX2 is the same as the level of TX2, so the level of RX2 is 0.RX2 needs to transmit a signal to TX1 through transistor Q2, and therefore, the conduction of transistor Q2 needs to be determined. Since the level of RX2 and TX2 are on average 0, transistor Q2 is turned off. Transistor Q2 is turned off, which corresponds to a high impedance, and blocks the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is 1. Thus, RX1 has a level of 0, TX2 has a level of 0, RX2 has a level of 0, and TX1 has a level of 1.

The first CAN bus 10 may also transmit a signal with a recessive level (i.e. transmit a signal with a level of 1), where the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to transmit a signal to TX2 through transistor Q1, and therefore, it is necessary to determine the conduction of transistor Q1. Since the level of RX1 is the same as that of TX1, transistor Q1 is turned off. Transistor Q1 is turned off, which corresponds to a high impedance, and blocks the path between RX1 and TX 2. Since TX2 is connected to a power supply device, the level of TX2 is 1. The level of RX2 is the same as that of TX2, and thus, the level of RX2 is 1.RX2 needs to transmit a signal to TX1 through transistor Q2, and therefore, the conduction of transistor Q2 needs to be determined. Since the level of RX2 and the level of TX2 are equal, transistor Q2 is turned off. Transistor Q2 is turned off, which corresponds to a high impedance, and blocks the path between RX2 and TX1. Since TX1 is connected to a power supply device, the level of TX1 is 1. Thus, RX1 has a level of 1, TX2 has a level of 1, RX2 has a level of 1, and TX1 has a level of 1.

In summary, with the apparatus shown in fig. 8, when the first CAN bus 10 transmits signals, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Similarly, with the apparatus shown in fig. 8, when the second CAN bus 50 transmits a signal (i.e., the state of the second CAN bus 50 is dominant), the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Further, assuming that the states of the first CAN bus 10 and the second CAN bus 50 are idle, the level of RX1 is 1 and the level of tx1 is 1. For the same reasons as the first CAN bus 10 transmits a signal of an implicit level, the level of RX1 is 1, the level of tx2 is 1, the level of RX2 is 1, and the level of tx1 is 1. Therefore, with the apparatus shown in fig. 8, when the states of the first CAN bus 10 and the second CAN bus 50 are idle, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so that the occurrence of the self-locking phenomenon when the CAN buses are connected CAN be avoided.

To sum up, with the apparatus shown in fig. 8, the relationship between the bus state and the levels of TX1, RX1, TX2, and RX2 can be shown in table 3.

TABLE 3 Table 3

The second possible case described above, in which the first switching device 601 and the second switching device 602 are both N-type MOSFETs, will be described with reference to fig. 9.

As shown in fig. 9, the bus processing device 60 may include: n-type MOSFET M1, N-type MOSFET M2, power supply 603, resistor R1, resistor R2, diode D1, diode D2, capacitor C1, capacitor C2, resistor R3, and resistor R4.

Wherein, the gate of the N-type MOSFET M1 is connected to TX1, the source of the N-type MOSFET M1 is connected to RX1, the drain of the N-type MOSFET M1 is connected to TX2, and the drain of the N-type MOSFET M1 is connected to the power supply 603 through the resistor R1; alternatively, the gate of the N-type MOSFET M1 is connected to TX1, the drain of the N-type MOSFET M1 is connected to RX1, the source of the N-type MOSFET M1 is connected to TX2, and the source of the N-type MOSFET M1 is also connected to the power supply 603 through a resistor R1. That is, the N-type MOSFET M1 may be the first switching device 601 in the bus processing apparatus 60 shown in fig. 3 to 7D.

The gate of the N-type MOSFET M2 is connected to TX2, the source of the N-type MOSFET M2 is connected to RX2, the drain of the N-type MOSFET M2 is connected to TX1, and the drain of the N-type MOSFET M2 is also connected to a power supply 603 through a resistor R2; alternatively, the gate of the N-type MOSFET M2 is connected to TX2, the drain of the N-type MOSFET M2 is connected to RX2, the source of the N-type MOSFET M2 is connected to TX1, and the source of the N-type MOSFET M2 is also connected to the power supply 603 through a resistor R2. That is, the N-type MOSFET M2 may be the second switching device 602 in the bus processing apparatus 60 shown in fig. 3 to 7D.

In addition, the connection relationships between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3, and the resistor R4 and the N-type MOSFETs M1 and M2 in the bus processing apparatus 60 shown in fig. 3 to 7D may refer to the connection relationships between the diode D1, the diode D2, the capacitor C1, the capacitor C2, the resistor R3, and the resistor R4 and the first switching device 601 and the second switching device 602, which are not described herein again.

The level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0 by the bus processing device 60 shown in fig. 9, so that the self-locking phenomenon is avoided when the CAN bus is connected. This will be specifically described below.

When the first CAN bus 10 transmits a signal (i.e., the state of the first CAN bus 10 is dominant), the level of TX1 is 1, the level of RX1 is 0, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to transmit a signal to TX2 through N-type MOSFET M1, and therefore, it is necessary to determine the on state of N-type MOSFET M1. Because the level of TX1 is 1, N-type MOSFET M1 is turned on; at this time, the level of the source and the level of the drain of the N-type MOSFET M1 are the same, and the level of RX1 and the level of TX2 are the same, and thus the level of TX2 is 0.RX2 receives the signal from TX2 so that the level of RX2 is the same as the level of TX2, so the level of RX2 is 0.RX2 needs to transmit a signal to TX1 through N-type MOSFET M2, and therefore, it is necessary to determine the on-state of N-type MOSFET M2. Since the level of TX2 is 0, n-type MOSFET M2 is not turned on, so that the path between RX2 and TX1 can be blocked. Since TX1 is connected to a power supply device, the level of TX1 is 1. Thus, RX1 has a level of 0, TX2 has a level of 0, RX2 has a level of 0, and TX1 has a level of 1.

The first CAN bus 10 may also transmit a signal with a recessive level (i.e. transmit a signal with a level of 1), where the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to transmit a signal to TX2 through N-type MOSFET M1, and therefore, it is necessary to determine the on state of N-type MOSFET M1. Since the level of TX1 is 1, N-type MOSFET M1 is turned on; at this time, the level of the source and the level of the drain of the N-type MOSFET M1 are the same, that is, the level of RX1 and the level of TX2 are the same, and thus, the level of TX2 is 1. The level of RX2 is the same as that of TX2, and thus, the level of RX2 is 1.RX2 needs to transmit a signal to TX1 through N-type MOSFET M2, and therefore, it is necessary to determine the on-state of N-type MOSFET M2. Since the level of TX2 is 1, N-type MOSFET M2 is turned on; at this time, the level of the source and the level of the drain of the N-type MOSFET M2 are the same, that is, the level of RX2 and the level of TX1 are the same, and thus, the level of TX1 is 1. Thus, RX1 has a level of 1, TX2 has a level of 1, RX2 has a level of 1, and TX1 has a level of 1.

In summary, with the apparatus shown in fig. 9, when the first CAN bus 10 transmits signals, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Similarly, with the apparatus shown in fig. 9, when the second CAN bus 50 transmits a signal, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0, so that the occurrence of the latch-up phenomenon at the time of CAN bus connection CAN be avoided.

Further, assuming that the states of the first CAN bus 10 and the second CAN bus 50 are idle, the level of RX1 is 1 and the level of tx1 is 1. For the same reason as the first CAN bus 10 transmits a signal of an implicit level, at this time, the level of RX1 is 1, the level of tx2 is 1, the level of RX2 is 1, and the level of tx1 is 1. Therefore, with the apparatus shown in fig. 9, when the states of the first CAN bus 10 and the second CAN bus 50 are idle, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so that the occurrence of the self-locking phenomenon when the CAN buses are connected CAN be avoided.

To sum up, with the apparatus shown in fig. 9, the relationship between the bus state and the levels of TX1, RX1, TX2, and RX2 can be shown in table 4.

TABLE 4 Table 4

Fig. 10 shows another possible configuration of a bus processing apparatus 60 provided by an embodiment of the present application. The bus processing device 60 includes: tristate gate U10, tristate gate U12, NOT gate U11, NOT gate U13, power supply 603, resistor R5 and resistor R6.

Wherein, the output end of the tri-state gate U10 can be connected to the power supply 603 through the resistor R5; in this way, power supply 603 may provide power to tri-state gate U10. And due to the resistor 5, the current passing through the tri-state gate U10 can be limited, and damage to the tri-state gate U10 is avoided. The output of tristate gate U12 may be connected to power supply 603 through resistor R6; in this way, power supply 603 may provide power to tri-state gate U12. And due to the resistor 6, the current through the tri-state gate U12 can be limited, avoiding damaging the tri-state gate U12. Optionally, the power supply 603 is a dc power supply such as a storage battery or a lithium battery; the resistance value of the resistor R5 and/or the resistor R6 is 1 kiloohm.

And, the input terminal of the tristate gate U10 is connected to RX1, the output terminal of the tristate gate U10 is connected to TX2; the input of tristate gate U12 is connected to RX2 and the output of tristate gate U12 is connected to TX1. The input terminal of the not gate U11 is connected to TX1, and the output terminal of the not gate U11 is connected to the output control terminal of the tri-state gate U10, that is, the level of TX1 can be used as the output control of the tri-state gate U10 after the conversion of the not gate U11. The input terminal of the not gate U13 is connected to TX2, and the output terminal of the not gate U13 is connected to the output control terminal of the tri-state gate U12, that is, the level of TX2 can be used as the output control of the tri-state gate U11 after the conversion of the not gate U13.

Wherein, TX1, TX2, RX1 and RX2 can all be connected with a power supply device. The power supply means may be a power source (e.g. a direct current power source such as a battery, lithium battery or the like). The power source to which TX1 and RX1 are connected may be a power source that powers the first transceiver 20; the power source for the TX2 and RX2 connections may be the power source that powers the second transceiver 40. The power source to which the TX1 and TX2 are connected may also be the power source that powers the isolation device 30 if the isolation device 30 is present between the first transceiver 20 and the second transceiver 40. Thus, when there is no input signal, the levels of TX1, TX2, RX1, RX2 are 1.

In some possible implementations, tri-state gate U10 and tri-state gate U12 are both low-enabled tri-state gates. For example, tri-state gate U10 and tri-state gate U12 may each be a HC125 tri-state gate, where HC125 tri-state gates are low enabled tri-state gates.

In other possible implementations, tri-state gate U10 and tri-state gate U12 are both high-enabled tri-state gates. For example, tri-state gate U10 and tri-state gate U12 may each include: the three-state gate and the NOT gate of HC125 model, wherein the output control end of the three-state gate of HC125 model is connected with the output end of the NOT gate.

Optionally, the NOT gate U11 and/or the NOT gate U13 are NOT gates of LS04 type.

The level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0 by the bus processing device 60 shown in fig. 10, so that the self-locking phenomenon is avoided when the CAN bus is connected. This will be specifically described below.

Case 1: both tri-state gate U10 and tri-state gate U12 are low enabled tri-state gates.

When the first CAN bus 10 transmits a signal (i.e., the state of the first CAN bus 10 is dominant), the level of RX1 is 0, the level of tx2 is 0, the level of RX2 is 0, and the level of tx1 is 1 (for details, reference is made to the summary of the invention, and details are not repeated here). In this way, the level of TX1, the level of RX1, the level of TX2 and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN bus is connected.

The first CAN bus 10 may also transmit a signal with a recessive level (i.e. transmit a signal with a level of 1), where the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to pass a signal through tristate gate U10 to TX2 and therefore the relationship between the input and output of tristate gate U10 needs to be determined. Level 1 of TX1 becomes level 0 through not gate U11; when the level of the output control terminal of the tri-state gate U10 is 0, the level of the output terminal of the tri-state gate U10 is the same as the level of the input terminal of the tri-state gate U10, and therefore, the level of TX2 is the same as the level of RX1, and both are 1. The level of RX2 is the same as that of TX2, and thus, the level of RX2 is 1.RX2 needs to pass a signal through tristate gate U12 to TX1 and therefore the relationship between the input and output of tristate gate U12 needs to be determined. Level 1 of TX2 becomes 0 through not gate U13; the level of the output control terminal of the tri-state gate U12 is 0, and the level of the output terminal of the tri-state gate U12 is the same as the level of the input terminal of the tri-state gate U12, and therefore, the level of TX1 connected to the output terminal of U7 is 1. Thus, RX1 has a level of 1, TX2 has a level of 1, RX2 has a level of 1, and TX1 has a level of 1.

In summary, when the first CAN bus 10 transmits signals, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Similarly, when the second CAN bus 50 transmits a signal (i.e., the state of the second CAN bus 50 is dominant), the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN buses are connected.

Further, assuming that the states of the first CAN bus 10 and the second CAN bus 50 are idle, the level of RX1 is 1 and the level of tx1 is 1. For the same reason as the first CAN bus 10 transmits a signal of an implicit level, at this time, the level of RX1 is 1, the level of tx2 is 1, the level of RX2 is 1, and the level of tx1 is 1. Therefore, with the apparatus shown in fig. 10, when the states of the first CAN bus 10 and the second CAN bus 50 are idle, the level of TX1, the level of RX1, the level of TX2, and the level of RX1 are not 0 at the same time, so that the occurrence of the self-locking phenomenon when the CAN buses are connected CAN be avoided.

To sum up, in case 1, the relationship between the bus state and the levels of TX1, RX1, TX2, and RX2 can be as shown in table 5.

TABLE 5

Case 2: both tri-state gate U10 and tri-state gate U12 are high enabled tri-state gates.

When the first CAN bus 10 transmits a signal (i.e., the state of the first CAN bus 10 is dominant), the level of RX1 is 0, the level of tx2 is 1, the level of RX2 is 1, and the level of tx1 is 1 (for details, reference is made to the summary of the invention, and details are not repeated here). In this way, the level of TX1, the level of RX1, the level of TX2 and the level of RX1 are different from 0, so that the self-locking phenomenon CAN be avoided when the CAN bus is connected.

The first CAN bus 10 may also transmit a signal with a recessive level (i.e. transmit a signal with a level of 1), where the level of RX1 is 1, the level of TX1 is 1, and the transmission direction of the signal is RX1- > TX2- > RX2- > TX1.RX1 needs to pass a signal through tristate gate U10 to TX2 and therefore the relationship between the input and output of tristate gate U10 needs to be determined. Level 1 of TX1 becomes level 0 through not gate U11; when the level of the output control end of the tri-state gate U10 is 0, the output end of the tri-state gate U10 is high-impedance, and the channel between RX1 and TX2 can be blocked. Since TX2 is connected to a power supply device, the level of TX2 is 1.RX2 receives the signal from TX2 such that the level of RX2 is the same as the level of TX2, and thus, the level of RX2 is 1.RX2 needs to pass a signal through tristate gate U12 to TX1 and therefore the relationship between the input and output of tristate gate U12 needs to be determined. Level 1 of TX2 becomes 0 through not gate U13; when the level of the output control end of the tri-state gate U12 is 0, the output end of the tri-state gate U12 is high-impedance, and the path between RX2 and TX1 is blocked. Since TX1 is connected to a power supply device, the level of TX1 is 1. Thus, RX1 has a level of 1, TX2 has a level of 1, RX2 has a level of 1, and TX1 has a level of 1.

To sum up, in case 2, the relationship between the bus state and the levels of TX1, RX1, TX2, and RX2 can be as shown in table 6.

TABLE 6

The embodiment of the application also provides a bus processing system. Fig. 11 shows a possible architecture of the bus processing system 70, as shown in fig. 11, the bus processing system 70 comprises: a first transceiver 20, a second transceiver 40 and any one of the bus processing means 60 described above; the connection relationship between the first transceiver 20, the second transceiver 40 and the bus processing device 60 can refer to the above embodiment, and will not be described herein. The bus processing system 70 may achieve any of the above-described effects of the bus processing apparatus 60, and will not be described herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

A bus processing apparatus, comprising: the power supply comprises a first switching device, a second switching device, a power supply, a first resistor and a second resistor;

the control electrode of the first switching device is connected to the transmitting end of the first transceiver, the first electrode of the first switching device is connected to the receiving end of the first transceiver, the second electrode of the first switching device is connected to the transmitting end of the second transceiver, and the second electrode of the first switching device is also connected to the power supply through the first resistor;

the control electrode of the second switching device is connected to the transmitting end of the second transceiver, the first electrode of the second switching device is connected to the receiving end of the second transceiver, the second electrode of the second switching device is connected to the transmitting end of the first transceiver, and the second electrode of the second switching device is also connected to the power supply through the second resistor;

The first transceiver is connected with a first Controller Area Network (CAN) bus, and the second transceiver is connected with a second CAN bus;

the first switching device is used for: disconnecting a path between a receiving end of the first transceiver and a transmitting end of the second transceiver when a level of the transmitting end of the first transceiver is a low level;

the second switching device is used for: and when the level of the transmitting end of the second transceiver is low, disconnecting a path between the receiving end of the second transceiver and the transmitting end of the first transceiver.
The apparatus of claim 1, wherein any one of the first switching device and the second switching device is at least one of:

triode, N-type metal oxide semiconductor field effect transistor.
The apparatus of claim 2, wherein the device comprises a plurality of sensors,

when any one of the first switching device and the second switching device is a triode, the control electrode of the any one switching device is a base electrode, the first electrode of the any one switching device is an emitter electrode, and the second electrode of the any one switching device is a collector electrode; or alternatively

When any one of the first switching device and the second switching device is an N-type metal oxide semiconductor field effect transistor, the control electrode of the any one switching device is a gate, the first electrode of the any one switching device is a drain, and the second electrode of the any one switching device is a source; or alternatively

When any one of the first switching device and the second switching device is an N-type metal oxide semiconductor field effect transistor, the control electrode of the any one switching device is a gate, the first electrode of the any one switching device is a source, and the second electrode of the any one switching device is a drain.
A device according to any one of claims 1 to 3, further comprising: a first diode and a second diode;

the positive electrode of the first diode is connected to the receiving end of the first transceiver, and the negative electrode of the first diode is connected to the transmitting end of the second transceiver;

the positive electrode of the second diode is connected to the receiving end of the second transceiver, and the negative electrode of the second diode is connected to the transmitting end of the first transceiver.
The apparatus according to any one of claims 1 to 4, further comprising: a first capacitor and a second capacitor;

Two ends of the first capacitor are respectively connected to the receiving end of the first transceiver and the transmitting end of the second transceiver;

and two ends of the second capacitor are respectively connected to the receiving end of the second transceiver and the transmitting end of the first transceiver.
The device according to any one of claims 1 to 5, further comprising a third resistor and/or a fourth resistor;

the control electrode of the first switching device is connected to the transmitting end of the first transceiver through the third resistor;

the control electrode of the second switching device is connected to the transmitting terminal of the second transceiver through the fourth resistor.
A bus processing apparatus, comprising: the first three-state gate, the second three-state gate, the first NOT gate, the second NOT gate, the power supply, the fifth resistor and the sixth resistor;

the input end of the first tri-state gate is connected to the receiving end of the first transceiver, the output end of the first tri-state gate is connected to the transmitting end of the second transceiver, and the output end of the first tri-state gate is also connected to the power supply through the fifth resistor;

the input end of the second tri-state gate is connected to the receiving end of the second transceiver, and the output end of the second tri-state gate is connected to the transmitting end of the first transceiver;

The input end of the first NOT gate is connected to the transmitting end of the first transceiver, the output end of the first NOT gate is connected to the output control end of the first tri-state gate, and the output end of the second tri-state gate is also connected to the power supply through the sixth resistor;

the input end of the second NOT gate is connected to the transmitting end of the second transceiver, and the output end of the second NOT gate is connected to the output control end of the second tri-state gate;

the first transceiver is connected with a first Controller Area Network (CAN) bus, and the second transceiver is connected with a second CAN bus;

the first tri-state gate and the second tri-state gate are low level enabled tri-state gates; alternatively, the first and second tri-state gates are high-enabled tri-state gates.
A bus processing system, comprising: the apparatus of any of claims 1 to 7, the first transceiver, and the second transceiver.