CN217063992U

CN217063992U - Level switching time-sharing multiplexing and isolating circuit and TWS earphone system

Info

Publication number: CN217063992U
Application number: CN202220242614.0U
Authority: CN
Inventors: 张纯林
Original assignee: Zhuhai Shengsheng Microelectronic Co ltd
Current assignee: Zhuhai Shengsheng Microelectronic Co ltd
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-07-26
Anticipated expiration: 2032-01-28

Abstract

The utility model provides a multiplexing and buffer circuit of level switch timesharing, TWS earphone system, it includes first equipment unit and second equipment unit, communicate through Power TX RX between first equipment unit and the second equipment unit, first equipment unit includes the treater, a communication circuit, level switch timesharing multiplexing circuit, a Power module, level switch timesharing multiplexing circuit is used for the level signal that the control treater sent with switching level operating condition, second equipment unit includes Power supply communication isolation module, the second communication circuit, the second Power module, Power supply communication isolation module and level switch timesharing multiplexing circuit connection are in order to carry out Power supply isolation communication, thereby realize VBUS and communication module's isolation. The utility model discloses a level conversion and communication are kept apart, have realized level interconversion between the signal transmission module, have realized the isolation between electric energy transmission voltage and the communication module, have improved the communication reliability of box and the wireless earphone that charges.

Description

Level switching time-sharing multiplexing and isolating circuit and TWS earphone system

Technical Field

The utility model relates to an electronic equipment technical field, concretely relates to multiplexing and isolating circuit of level switching timesharing and be applied to a TWS headphone system of this circuit.

Background

Wireless headsets are widely used due to their wireless, lightweight nature. TWS headphones are generally used with a charging box because of the problems of small battery capacity and short standby time. In order to reduce the contact interface between the earphone box and the wireless earphone as much as possible, the charging interface of the earphone box and the wireless earphone and a scheme of time-sharing multiplexing of carrier communication, power supply and communication exist in the prior art, but when the contact interface of the earphone box and the wireless earphone is multiplexed into a communication interface, the problem of low communication reliability exists.

The utility model with patent application number CN110769343A discloses a method for communication between wireless earphone and charging box, TWS earphone and system, but this patent has the following disadvantages:

the communication level can not be converted, the electric energy transmission voltage and the communication of the receiving equipment are not isolated, the electric energy transmission voltage can enter the communication receiving module, and once the electric energy transmission voltage is higher than the communication level, a circuit of the communication module can be damaged.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a multiplexing and isolating circuit of level switching timesharing, TWS earphone system based on power supply and communication, it has mainly solved the problem that the communication level can not be converted and transmission voltage and communication do not realize the isolation, a multiplexing and isolating circuit of power supply and communication level switching timesharing is provided, through level conversion and communication isolation, realized the purpose of automatic control communication state in transmission process, improved the communication reliability of charging box and wireless earphone.

In order to solve the above problem, the utility model discloses the technical scheme who adopts as follows:

a level switching time-sharing multiplexing and isolating circuit comprises a first equipment unit and a second equipment unit, wherein the first equipment unit and the second equipment unit are communicated through Power/TX/RX, the first equipment unit comprises a processor, a first communication circuit, a level switching time-sharing multiplexing circuit and a first Power module, the first Power module provides Power for each circuit module of the first equipment unit, the processor is connected with the first communication circuit, and the level switching time-sharing multiplexing circuit is used for controlling a level signal sent by the processor to switch a level working state; the second equipment unit comprises a power supply communication isolation module, a second communication circuit and a second power supply module, the second power supply module provides power for each circuit module of the second equipment unit, the power supply communication isolation module is connected with the second communication circuit, and the power supply communication isolation module is connected with the level conversion time-sharing multiplexing circuit to carry out power supply isolation communication, so that isolation of the VBUS and the communication module is realized.

The further scheme is that the level conversion time-sharing multiplexing circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, wherein the grid of the first MOS tube is connected with Power _ ctl, the grid of the second MOS tube is connected with comm _ receive, the grid of the fourth MOS tube is connected with VCC _ L, the grid of the fifth MOS tube is connected with VCC _ H, the drain of the first MOS tube is connected with the grid of the third MOS tube, the source and the drain of the third MOS tube are connected with a third diode, the source and the drain of the fourth MOS tube are connected with a fourth diode, the source and the drain of the fifth MOS tube are connected with a fifth diode, the drain of the second MOS tube is connected with a second resistor, and the anode of the third diode, the anode of the fourth diode and the second resistor are respectively connected to Power/TX/RX.

A further scheme is, level transition time sharing multiplex circuit still includes first resistance second resistance, third resistance and first electric capacity, the first end of first electric capacity, the first termination VBUS of first resistance, first electric capacity second end ground connection, first resistance second end is connected first MOS pipe drain electrode with between the third MOS pipe grid, the first termination Power TX RX of second resistance, second resistance second end is connected to second MOS pipe drain electrode, the first end of third resistance is connected to fifth MOS pipe source pole and fifth diode positive pole, third resistance second end VCC _ H.

In a further aspect, the power supply communication isolation module includes a sixth MOS transistor, a voltage regulator diode, a sixth diode, and a seventh diode, the gate of the sixth MOS transistor is connected to the negative electrode of the voltage regulator diode, the source of the sixth MOS transistor is connected to VBUS/TX/RX, the drain of the sixth MOS transistor is connected to VBUS, the positive electrode of the voltage regulator diode is grounded, the negative electrodes of the sixth diode and the seventh diode are connected to VBUS/TX/RX, the positive electrode of the sixth diode is connected to VBUS, and the positive electrode of the seventh diode is connected to TX/RX.

In a further aspect, the power supply communication isolation module further includes a fourth resistor, a fifth resistor, and a second capacitor, where a first end of the fourth resistor is connected to VBUS/TX/RX, a second end of the fourth resistor is connected to VZ, a first end of the fifth resistor is connected to VCC _ L, a second end of the fifth resistor is connected to TX/RX, a first end of the second capacitor is connected to VBUS, and a second end of the second capacitor is connected to ground.

In a further aspect, the first device unit is a charging box and the second device unit is a TWS headset.

A TWS earphone system comprises the level switching time division multiplexing and isolating circuit.

Therefore, the utility model provides a multiplexing and buffer circuit of power supply and communication level conversion timesharing, electric energy transmission and communication interface signal line only need just can accomplish with two lines (a ground wire, the multiplexing line of an electric energy transmission and communication line), have realized the isolation between electric energy transmission voltage and the communication module, and the high voltage when can guaranteeing electric energy transmission can not enter communication module, has guaranteed communication module safety. During communication, the level signal sent by the CPU can be controlled by the level conversion time-sharing multiplexing circuit to switch the level working state, and the level conversion between the signal transmission modules can be realized.

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Drawings

Fig. 1 is a schematic diagram of an embodiment of the level switching time division multiplexing and isolating circuit of the present invention.

Fig. 2 is a schematic circuit diagram of a level shift time division multiplexing circuit in an embodiment of the level shift time division multiplexing and isolating circuit of the present invention.

Fig. 3 is a schematic circuit diagram of a power supply communication isolation module in an embodiment of the level switching time division multiplexing and isolation circuit of the present invention.

Detailed Description

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined below to clearly and completely describe the technical solution of the embodiments of the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. All other embodiments, which can be obtained by a person skilled in the art without any inventive work based on the described embodiments of the present invention, belong to the protection scope of the present invention.

Referring to fig. 1, a level switching time division multiplexing and isolating circuit includes a first device unit 1 and a second device unit 2, where the first device unit 1 and the second device unit 2 communicate with each other through Power/TX/RX, the first device unit 1 includes a processor 11, a first communication circuit 12, a level switching time division multiplexing circuit 13, and a first Power module, the first Power module provides Power for each circuit module of the first device unit 1, the processor 11 is connected to the first communication circuit 12, and the level switching time division multiplexing circuit 13 is configured to control a level signal sent by the processor 11 to switch a level operating state.

The second equipment unit 2 comprises a power supply communication isolation module 21, a second communication circuit and a second power supply module, the second power supply module provides power for each circuit module of the second equipment unit 2, the power supply communication isolation module 21 is connected with the second communication circuit, and the power supply communication isolation module 21 is connected with the level conversion time-sharing multiplexing circuit 13 to carry out power supply isolation communication, so that isolation between the VBUS and the communication module is realized.

As shown in fig. 2, the level conversion time division multiplexing circuit 13 includes a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, and a fifth MOS transistor Q5, the gate of the first MOS transistor Q1 is connected to Power _ ctl, the gate of the second MOS transistor Q2 is connected to comm _ receive, the gate of the fourth MOS transistor Q4 is connected to VCC _ L, the gate of the fifth MOS transistor Q5 is connected to VCC _ H, the drain of the first MOS transistor Q1 is connected to the gate of the third MOS transistor Q3, the source and the drain of the third MOS transistor Q3 are connected to a third diode D3, the source and the drain of the fourth MOS transistor Q4 are connected to a fourth diode D4, the source and the drain of the fifth MOS transistor Q5 are connected to a fifth diode D5, the drain of the second MOS transistor Q2 is connected to a second resistor R2, and the positive pole of the third diode D3, the positive pole of the fourth diode D5, and the positive pole of the second resistor R867/TX 874 are respectively connected to RX/TX 874/RX/TX.

In this embodiment, the level shift time division multiplexing circuit 13 further includes a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1, a first end of the first capacitor C1 and a first end of the first resistor R1 are connected to VBUS, a second end of the first capacitor C1 is grounded, a second end of the first resistor R1 is connected between a drain of the first MOS transistor Q1 and a gate of the third MOS transistor Q3, a first end of the second resistor R2 is connected to Power/TX/RX, a second end of the second resistor R2 is connected to a drain of the second MOS transistor Q2, a first end of the third resistor R3 is connected to a source of the fifth MOS transistor Q5 and an anode of the fifth diode D5, and a second end of the third resistor R3 is connected to VCC _ H.

As shown in fig. 3, the power supply communication isolation module 21 includes a sixth MOS transistor Q6, a zener diode D8, a sixth diode D6 and a seventh diode D7, the gate of the sixth MOS transistor Q6 is connected to the negative electrode of the zener diode D8, the source of the sixth MOS transistor Q6 is connected to VBUS/TX/RX, the drain of the sixth MOS transistor Q6 is connected to VBUS, the positive electrode of the zener diode D8 is grounded, the negative electrode of the sixth diode D6 and the negative electrode of the seventh diode D7 are connected to VBUS/TX/RX, the positive electrode of the sixth diode D6 is connected to VBUS, and the positive electrode of the seventh diode D7 is connected to TX/RX.

In this embodiment, the power supply communication isolation module 21 further includes a fourth resistor R4, a fifth resistor R5, and a second capacitor C2, a first end of the fourth resistor R4 is connected to VBUS/TX/RX, a second end of the fourth resistor R4 is connected to VZ, a first end of the fifth resistor R5 is connected to VCC _ L, a second end of the fifth resistor R5 is connected to TX/RX, a first end of the second capacitor C2 is connected to VBUS, and a second end of the second capacitor C2 is connected to ground.

In this embodiment, the first device unit 1 is a charging box and the second device unit 2 is a TWS headset.

As can be seen, the charging box of the present embodiment is composed of a processor 11, a first communication circuit 12, a level conversion time division multiplexing circuit 13, and a power supply; the WS headset of this embodiment is composed of a power supply communication isolation module 21, a communication module, and a power supply module. The processor 11 controls when the power supply and communication level conversion time division multiplexing and isolating circuit operates in the power transmission mode and when it operates in the communication mode.

In addition, the CMOS field effect transistor is used for power gating of the communication level, so that the cost is reduced, the service life and the working reliability of the semiconductor device are superior to those of a relay scheme with a mechanical contact, and the problem of weak driving capability of a signal analog switch is avoided.

The present embodiment further provides a control method applied to the level switching multiplexing and isolating circuit, where the level switching multiplexing and isolating circuit of the present embodiment adopts the above level switching multiplexing and isolating circuit, and the method includes the following steps:

when Power _ ctl is at a high level, the first MOS transistor Q1 is turned on, and the Power source VBUS and VBUS/TX/RX are shorted, thereby enabling Power to be transferred from the first device unit 1 to the second device unit 2, while VBUS is greater than VCC _ H. It can be seen that, in combination with the Power supply and communication level conversion time division multiplexing and isolation circuit, when the Power _ ctl is at a high level, the first MOS transistor Q1 is turned on, and the Power supply VBUS and VBUS OR TX/RX are shorted, so that the electric energy is transmitted to the second device unit 2.

During the power transmission, VBUS/TX in the second device unit 2 is equal to VBUS of the first device unit 1, VBUS in the second device unit 2 is greater than VZ, so that power is conducted to realize power transmission to the power supply module of the second device unit 2, and at the same time, since VBUS of the second device unit 2 is greater than VCC _ L, the power supply VBUS is not conducted to TX/RX to realize isolation of VBUS from the communication module. It can be seen that, at the same time, since VBUS is greater than VCC _ H, the first MOS transistor Q1XX will not conduct, preventing VBUS from flowing backward to TX/RX to damage the processor 11.

Specifically, in the power transmission mode, in the second device unit 2, the operation principle of the power supply communication isolation module 21 is described with reference to the example in fig. 3. In the second device unit 2, VBUS or TX/TX is equal to VBUS of the first device unit 1, VBUS is larger than VZ, and thus power is turned on and power transfer to the power supply module can be achieved. Meanwhile, due to the unidirectional conduction characteristic of the diode, VBUS is larger than VCC _ L, so that VBUS can not be conducted to TX/RX, and isolation of VBUS and the communication module is achieved.

When the circuit works in the communication mode, Power _ ctl is at a low level, the first MOS transistor Q1 is turned off, and the Power supply VBUS is turned off to VBUS/TX/RX, so as to switch from the Power transmission mode to the communication mode, wherein it is defined that the first device unit 1 transmits data to the second device unit 2 in a transmitting state, and vice versa in a receiving state. It can be seen that the power supply and communication level translation time division multiplexing and isolation circuitry is controlled by the processor 11 to operate in the communication mode in the first equipment unit 1. When VBUS _ ctl is low, therefore, the first MOS transistor Q1 is turned off, and VBUS is turned off to VBUS or TX/RX, thereby realizing switching from the power transmission mode to the communication mode. The communication mode is divided into two states, namely a transmitting state and a receiving state, and the state that the first equipment unit 1 transmits data to the second equipment unit 2 is defined as the transmitting state and the state that the data is received is defined as the receiving state.

In the sending state, comm _ receive is low level, TX/RX is high level and VCC _ H, VCC _ L is less than VCC _ H, and due to the conduction characteristic of NMOS pipe, the maximum voltage transmitted in the circuit is GATE-VTH. The Mos gate voltage is VCC _ L, so that the highest voltage VBUS/TX/RX is VCC _ L-VTH, thereby realizing level conversion from VCC _ H to VCC _ L domain in communication engineering. Therefore, the level conversion time-sharing multiplexing and isolating circuit of the embodiment forms a power domain bidirectional switching circuit, and the working principle is as follows: in the sending state, comm _ receive is low level, TX/RX () is high level VCC _ H, VCC _ L is less than VCC _ H, due to the conduction characteristic of NMOS pipe, the highest voltage VBUS _ TX/RX can be transmitted at large voltage GATE-VTH, Mos GATE is VCC _ L, therefore, the level conversion from VCC _ H to VCC _ L domain in communication engineering is realized.

The present embodiment further provides a TWS headset system including the level-switching time-division multiplexing and isolating circuit. To the utility model provides a please refer to above-mentioned method embodiment for introduction of box, TWS earphone and TWS headphone system charges, the utility model discloses no longer describe herein.

Therefore, the utility model provides a multiplexing and buffer circuit of power supply and communication level conversion timesharing, electric energy transmission and communication interface signal line only need just can accomplish with two lines (a ground wire, the multiplexing line of an electric energy transmission and communication line), have realized the isolation between electric energy transmission voltage and the communication module, and the high voltage when can guaranteeing electric energy transmission can not enter communication module, has guaranteed communication module safety. During communication, the level signal sent by the CPU can be controlled by the level conversion time division multiplexing circuit 13 to switch the level operating state, and level interconversion between the signal transmission modules can be realized.

It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention cannot be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are all within the protection scope of the present invention.

Claims

1. A level switching time division multiplexing and isolating circuit is characterized by comprising:

the first device unit and the second device unit communicate with each other through Power/TX/RX, the first device unit includes a processor, a first communication circuit, a level conversion time division multiplexing circuit, and a first Power module, the first Power module provides Power for each circuit module of the first device unit, the processor is connected with the first communication circuit, and the level conversion time division multiplexing circuit is used for controlling a level signal sent by the processor to switch a level working state;

the second equipment unit comprises a power supply communication isolation module, a second communication circuit and a second power supply module, the second power supply module provides power for each circuit module of the second equipment unit, the power supply communication isolation module is connected with the second communication circuit, and the power supply communication isolation module is connected with the level conversion time-sharing multiplexing circuit to carry out power supply isolation communication, so that isolation between the VBUS and the communication module is realized.

2. The circuit of claim 1, wherein:

the level conversion time-sharing multiplexing circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, wherein the grid of the first MOS tube is connected with Power _ ctl, the grid of the second MOS tube is connected with comm _ receive, the grid of the fourth MOS tube is connected with VCC _ L, the grid of the fifth MOS tube is connected with VCC _ H, the drain of the first MOS tube is connected with the grid of the third MOS tube, the source and the drain of the third MOS tube are connected with a third diode, the source and the drain of the fourth MOS tube are connected with a fourth diode, the source and the drain of the fifth MOS tube are connected with a fifth diode, the drain of the second MOS tube is connected with a second resistor, and the anode of the third diode, the anode of the fourth diode and the second resistor are respectively connected to Power/TX/RX.

3. The circuit of claim 2, wherein:

level transition timesharing multiplex circuit still include first resistance second resistance, third resistance and first electric capacity, the first end of first electric capacity, the first end VBUS that terminates of first resistance, first electric capacity second end ground connection, first resistance second end is connected first MOS pipe drain electrode with between the third MOS pipe grid, the first end of second resistance connects Power TX RX, second resistance second end is connected to second MOS pipe drain electrode, the first end of third resistance is connected to fifth MOS pipe source and fifth diode are anodal, third resistance second end VCC _ H.

4. The circuit of claim 1, wherein:

the power supply communication isolation module comprises a sixth MOS tube, a voltage stabilizing diode, a sixth diode and a seventh diode, wherein the grid electrode of the sixth MOS tube is connected with the negative electrode of the voltage stabilizing diode, the source electrode of the sixth MOS tube is connected with VBUS/TX/RX, the drain electrode of the sixth MOS tube is connected with VBUS, the positive electrode of the voltage stabilizing diode is grounded, the negative electrode of the sixth diode and the negative electrode of the seventh diode are connected with VBUS/TX/RX, the positive electrode of the sixth diode is connected with VBUS, and the positive electrode of the seventh diode is connected with TX/RX.

5. The circuit of claim 4, wherein:

the power supply communication isolation module further comprises a fourth resistor, a fifth resistor and a second capacitor, wherein the first end of the fourth resistor is connected with VBUS/TX/RX, the second end of the fourth resistor is connected with VZ, the first end of the fifth resistor is connected with VCC _ L, the second end of the fifth resistor is connected with TX/RX, the first end of the second capacitor is connected with VBUS, and the second end of the second capacitor is grounded.

6. The circuit of any of claims 1 to 5, wherein:

the first device unit is a charging box and the second device unit is a TWS headset.

7. A TWS headset system comprising the level-switched time division multiplexing and isolation circuit of any of claims 1 to 6.