WO2023134034A1 - 延迟锁相环、延迟锁相环控制方法及电子设备 - Google Patents

延迟锁相环、延迟锁相环控制方法及电子设备 Download PDF

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Publication number
WO2023134034A1
WO2023134034A1 PCT/CN2022/085078 CN2022085078W WO2023134034A1 WO 2023134034 A1 WO2023134034 A1 WO 2023134034A1 CN 2022085078 W CN2022085078 W CN 2022085078W WO 2023134034 A1 WO2023134034 A1 WO 2023134034A1
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Prior art keywords
delay
frequency
output
clock signal
locked loop
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PCT/CN2022/085078
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English (en)
French (fr)
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谷银川
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长鑫存储技术有限公司
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Priority to US17/805,091 priority Critical patent/US11695421B1/en
Publication of WO2023134034A1 publication Critical patent/WO2023134034A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular, to a delay-locked loop, a delay-locked loop control method, and electronic equipment.
  • a delay-locked loop (Delay-Locked Loop, DLL) is a circuit that delays and adjusts the clock signal to achieve clock signal synchronization in the system. Because the synchronization does not change with changes in external conditions, such as temperature and voltage, it is widely used in the field of timing.
  • the existing delay-locked loop is in a high-frequency state whether it is in the working state or in the standby state, resulting in a delay-locked loop. Ring power consumption is high.
  • the purpose of the present disclosure is to provide a DLL, a DLL control method and an electronic device, so as to reduce the power consumption of the DLL.
  • a delay-locked loop including: a secondary channel, which is used to divide the input clock signal to generate a frequency-divided clock signal.
  • the frequency-divided clock signal of a frequency is adjusted to obtain an output clock signal; when the delay-locked loop is locked in a standby state, the frequency-divided clock signal is adjusted to have a second frequency; wherein the second frequency lower than the first frequency; the main channel is configured to output an output clock replica signal with the same phase as the output clock signal when the target instruction is acquired.
  • a delay-locked loop control method includes: dividing the input clock signal to generate a frequency-divided clock signal; During the locking process of the delay-locked loop, the frequency-divided clock signal with the first frequency is adjusted through the secondary channel to obtain an output clock signal; when the delay-locked loop is locked in a standby state, the adjustment The frequency-divided clock signal has a second frequency; wherein the second frequency is lower than the first frequency; when the target instruction is obtained, the main path is controlled to output the same phase as the output clock signal Output clock replica signal.
  • an electronic device including: the above-mentioned delay-locked loop.
  • the input clock signal is adjusted through the sub-path to obtain an output clock signal, and at the same time, the output clock signal has the same
  • the output clock of the phase is copied to the signal output for subsequent command control. Since the secondary channel first divides the frequency of the input clock signal during the phase adjustment process, and during the locking process of the delay phase-locked loop and in the standby state, the frequency-divided clock signal has different frequencies; by using a higher frequency in the standby state
  • the low second frequency can reduce the standby current of the DLL without affecting the output accuracy of the DLL when the DLL is in standby, so as to reduce the power consumption of the DLL Purpose.
  • FIG. 1 is a schematic circuit diagram of a delay-locked loop according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a first frequency divider in a delay-locked loop according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of steps of a DLL control method according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals denote the same or similar parts in the drawings, and thus their repeated descriptions will be omitted.
  • DRAM Dynamic Random Access Memory
  • RDRAM Rambus Dynamic Random Access Memory
  • DDR Double Data Rate Synchronous Dynamic Random Access Memory
  • the delay phase-locked loop In order to ensure the accuracy of the CPU when reading data from the DRAM, it is required that the delay phase-locked loop must continue to work before the read command and other commands are enabled. It can be seen that the power consumption of the delay-locked loop is also a part that cannot be ignored.
  • an embodiment of the present disclosure provides a schematic circuit diagram of a delay-locked loop.
  • the delay-locked loop includes: secondary path 100 and main path 200; wherein, secondary path 100 is used to divide the input clock signal CLK input to generate frequency-divided clock signal CLK Div, in the delay-locked loop locking process Among them, the frequency-divided clock signal with the first frequency is adjusted to obtain the output clock signal CLK output; when the delay-locked loop is locked in a standby state, the frequency-divided clock signal CLK Div is adjusted to have a second frequency; here, the first The second frequency is lower than the first frequency.
  • the main channel 200 is used to output the output clock replica signal DLL output having the same phase as the output clock signal CLK output when the target instruction is acquired.
  • the target command may be various control commands such as a read command, a write command, and a refresh command, and the exemplary embodiments of the present disclosure make no special limitation on the target command.
  • the delay-locked loop is divided into a sub-path 100 and a main path 200, and the input clock signal CLK input is adjusted through the sub-path 100 to obtain an output clock signal CLK output.
  • the output clock replica signal having the same phase as the output clock signal CLK output can also be output to the DLL output through the main channel 200 for subsequent command control. Since the auxiliary channel 100 first divides the frequency of the input clock signal CLK input in the phase adjustment process to generate the frequency-divided clock signal CLK Div; CLK Div has a different frequency; by using a lower second frequency in standby, the DLL can be reduced without compromising the DLL output accuracy while the DLL is in standby. The standby current is reduced to achieve the purpose of reducing the power consumption of the delay phase-locked loop.
  • the locking process of the delay-locked loop refers to the process in which the delay-locked loop adjusts the phase difference between the input clock signal CLK input and the output clock signal CLK output through the delay line. After the adjustment reaches the target phase difference, for example, the phase difference is At zero time, the delay line can be locked, so that the clock signals in the subsequent operation of the system can be synchronized.
  • the standby state of the delay-locked loop refers to the state after the delay-locked loop is locked.
  • the main channel 200 is in the closed state. Only when the target instruction is obtained, the main channel 200 is opened to output the above-mentioned output clock replication signal DLL output.
  • the secondary path 100 may include: a first frequency divider 110 , a first delay line 120 , a phase detector 130 and a delay line controller 140 .
  • the first frequency divider 110 may be used to divide the frequency of the input clock signal CLK input to generate the frequency-divided clock signal CLK Div.
  • the frequency-divided clock signal CLK Div can have different frequencies, for example, a first frequency, a second frequency, and the like. It should be noted that, the embodiments of the present disclosure make no special limitation on specific magnitudes of the first frequency and the second frequency.
  • the first frequency divider 110 can generate multiple frequency-divided clock signals CLK Div with different frequencies, so that the user can select an appropriate frequency as the frequency of the frequency-divided clock signal CLK Div according to needs.
  • the frequency-divided clock signal CLK Div has a first frequency; when the delay-locked loop is locked in a standby state, the frequency-divided clock signal CLK Div has a second frequency. frequency.
  • the first delay line 120 can be used to adjust the delay of the frequency-divided clock signal CLK Div to obtain the output clock signal CLK output with a target phase.
  • the delay adjustment process since the frequency-divided clock signal CLK Div through the first delay line 120 has the first frequency, it can be ensured that the first delay line 120 adjusts the frequency-divided clock signal CLK Div in a high-frequency state, thereby improving delay adjustment. accuracy.
  • the first frequency divider 110 can reduce the frequency of the divided clock signal CLK Div from the first frequency to the second frequency. Frequency, so as to ensure that the first delay line 120 is in a low-frequency state, thereby achieving the purpose of reducing power consumption and saving energy.
  • the phase detector 130 can be used to obtain the output clock signal CLK output, and compare the output clock signal CLK output with the input clock signal CLK input to determine the output clock signal CLK output and the input clock signal CLK input phase difference, at the same time, a control signal can be generated according to the phase difference, and the control signal is sent to the delay line controller 140.
  • the delay line controller 140 is configured to output a corresponding adjustment signal based on the control signal to adjust the delay parameter of the first delay line 120 so that the output clock signal CLK output has a target phase.
  • the exemplary embodiments of the present disclosure have a target phase No special restrictions are made.
  • the first delay line 120 can be adjusted so that the first delay line 120 has different delay parameters, and the delay parameter refers to delay time.
  • the means of adjusting the delay time of the first delay line 120 include but not limited to adjusting the length of the delay line and changing the quantity and specifications of the delay devices, wherein the delay line can be composed of a high-resistance line with a larger resistance and a low-resistance line with a smaller resistance , adjusting the length of the delay line includes simultaneously adjusting the length of the high-resistance line and the length of the low-resistance line, thereby adjusting the delay time of the delay line while the total length remains unchanged.
  • the exemplary embodiments of the present disclosure make no special limitation on delay parameters.
  • the main path 200 may include: a second frequency divider 210 and a second delay line 220 .
  • the second frequency divider 210 has the same inherent delay as that of the first frequency divider 110 , where the inherent delay refers to the delay existing in the device itself.
  • the second frequency divider 210 may be a replica of the first frequency divider 110 , and the second frequency divider 210 has exactly the same structure as the first frequency divider 110 .
  • the structure of the second frequency divider 210 and the first frequency divider 110 can also be set differently, for example, the second frequency divider 210 can be composed of a plurality of delay units, as long as these delays are guaranteed It only needs to be the same as the inherent delay of the first frequency divider 110, which is not limited in the exemplary embodiment of the present disclosure.
  • the second delay line 220 needs to follow the first delay line 120 to perform delay adjustment on the frequency-divided clock signal CLK Div to obtain the output clock replica signal DLL output. That is to say, during the delay adjustment process of the auxiliary path 100, even if the main path 200 is in the closed state of not outputting a signal, the second delay line 220 of the main path 200 will automatically follow the first delay line 120 to adjust, completely unaffected by The influence of the state of the main channel 200.
  • the second delay line 220 can follow the first delay line 120 to adjust the delay of the frequency-divided clock signal CLK Div. , to control the second delay line 220 .
  • a synchronous control manner is adopted, and specific synchronous control manners are not described in detail in the exemplary embodiments of the present disclosure.
  • the delay-locked loop in addition to reducing power consumption through the secondary channel 100 being in different frequency states, the delay-locked loop is in the locking process and the standby state after locking through the main channel 200 It is in the off state to reduce power consumption, so as to achieve the purpose of further reducing power consumption.
  • the above-mentioned secondary path 100 may further include a first clock output enabling unit 150, and the output clock signal CLK output is transmitted to the phase detector 130 through the first clock output enabling unit 150, so as to The phase detector 130 compares the phases of the output clock signal CLK output and the input clock signal CLK input.
  • the main path 200 may further include a second clock output enabling unit 230, and the second clock output enabling unit 230 controls the output terminal of the delay-locked loop to output the above-mentioned output clock replication signal when the target instruction is received. DLL output. That is to say, under the effect of the target instruction, the second clock output enabling unit 230 will be turned on and in a conduction state, so that the output clock replication signal DLL output can be transmitted out.
  • the above-mentioned main channel 200 is in the closed state, which mainly means that the second clock output enabling unit 230 is in the non-enabled state when the target instruction is not received, so that the above-mentioned output clock replication signal DLL is not output. output.
  • the structure of the second clock output enabling unit 230 can be determined according to the actual situation.
  • the second clock output enabling unit 230 can be a flip-flop, etc., which is used to output the above-mentioned Output clock copy signal DLL output.
  • the exemplary embodiment of the present disclosure does not specifically limit the structure of the second clock output enabling unit 230 .
  • the inherent delay of the first clock output enabling unit 150 and the inherent delay of the second clock output enabling unit 230 may be the same.
  • the structure of the first clock output enabling unit 150 may be the same as the structure of the second clock output enabling unit 230, the difference is that the first clock output enabling unit 150 needs to be in an open state continuously without the need for a target instruction trigger.
  • the first frequency divider 110 may have different structures according to the required frequency after frequency division.
  • the first frequency divider 110 may include a frequency division unit 111 , a delay unit 112 , a first multiplexer 113 and a logical AND gate 114 .
  • the frequency division unit 111 can be used to perform frequency division processing on the input clock signal CLK input, so as to obtain frequency division clock signals CLK Div of different frequencies.
  • the delay unit 112 can be used to compensate the delay of the frequency division unit 111 , so as to choose not to perform frequency division by the frequency division unit 111 when the user does not wish to perform frequency division.
  • the input end of the first multiplexer 113 is used to access the output end of the frequency division unit 111 and the output end of the delay unit 112, and the control end of the first multiplexer 113 is used to access the Logic circuit logic AND gate 114
  • the output terminal is used to select and output the output signal of the frequency division unit 111 or select the output signal of the delay unit 112 under the control of the output result of the logic AND gate 114 .
  • the input terminal of the logic AND gate 114 is connected with the delay-locked loop lock signal DLL_LOCK Flag and the first test signal Testmode1, for when the delay-locked loop lock signal DLL_LOCK Flag and the first test signal Testmode1 are simultaneously enabled,
  • the first multiplexer 113 is controlled to output the output signal of the delay unit 112 .
  • the first multiplexer 113 selects the output signal of the output delay unit 112, no The input clock signal CLK input is frequency-divided so that the frequency-divided clock signal CLK Div output by the delay-locked loop is always in the same frequency state, that is, in a higher first frequency.
  • the output signal of the logical AND gate 114 will control the first multiplexer 113 to select the output signal of the frequency dividing unit 111, thereby achieving The purpose of frequency division processing of the input clock signal CLK input.
  • the frequency dividing unit 111 includes a plurality of flip-flops 1111 connected in series, and a plurality of second multiplexers 1112.
  • the output end of the previous stage flip-flop 1111 is connected to the input end of the subsequent stage flip-flop 1111, so that multiple flip-flops 1111 are connected in series, so as to trigger the signal from the previous stage under the trigger of the input clock signal CLK input.
  • a plurality of second multiplexers 1112 are used to lead the output end of each stage flip-flop 1111 to the input end of the first stage flip-flop 1111 respectively, so as to realize the input clock signal CLK input through the circulation of the signal. crossover.
  • flip-flops 1111 and second multiplexers 1112 may be set according to the frequency obtained by frequency division, for example, the required first frequency and second frequency. For example, four flip-flops 1111 may be set, and three second multiplexers 1112 may be set.
  • the four input terminals of the two second multiplexers 1112 are respectively connected to the output terminals of the four flip-flops 1111, and the output terminals of the two second multiplexers 1112 are connected to the third second multiplexer
  • the control end of three second multiplexers 1112 is respectively connected to three A second test signal, as shown in Figure 2, three second test signals comprise Testmode2, Testmode3 and Testmode4, under the combination of three different second test signals Testmode2, Testmode3 and Testmode4, the control input clock signal CLK input produces Different frequency division clock signal CLK Div.
  • the frequency division unit 111 in FIG. 2 can generate the frequency-divided clock signal CLK Div that is 1/2, 1/4, 1/6 and 1/8 times the frequency of the input clock signal CLK input.
  • the delay unit 112 can be composed in various ways, as long as the determined delay unit 112 is synchronized with the delay of the frequency dividing unit 111 .
  • the delay unit 112 may include a plurality of series-connected inverters.
  • the number of inverters is the same as the number of flip-flops, so as to meet the requirements of delay synchronization. need.
  • the exemplary embodiment of the present disclosure does not limit the specific structure of the delay unit 112 .
  • the first frequency divider 110 may further include a driver 115, the input terminal of the driver 115 is connected to the output terminal of the first multiplexer 113, and the output terminal of the driver 115 outputs a frequency-divided clock signal CLK Div.
  • the driver 115 is mainly used to enhance the intensity of the frequency-divided clock signal CLK Div to be output.
  • the first frequency divider 110 used in the delay-locked loop of the embodiment of the present disclosure is not limited to the above structure.
  • the delay-locked loop provided by the exemplary embodiment of the present disclosure can adjust the first delay line only through the auxiliary path during the locking process of the delay-locked loop by setting the main path and the secondary path, so as to achieve the purpose of adjusting the delay ; and the final signal is output through the main channel, so that the adjustment and output can be set separately.
  • the main channel can be closed or the operating frequency of the secondary channel can be reduced according to the situation, thereby minimizing the delay-locked loop. Current consumption, to achieve the purpose of energy saving.
  • a delay-locked loop control method is also provided.
  • the delay-locked loop control method is used for the above-mentioned delay-locked loop. Referring to Fig. 3, the delay-locked-loop control method comprises the following steps:
  • Step S310 divide the input clock signal to generate a frequency-divided clock signal
  • Step S320 during the locking process of the delay-locked loop, adjust the frequency-divided clock signal with the first frequency through the secondary path to obtain the output clock signal;
  • Step S330 in the case that the delay-locked loop is locked in a standby state, adjusting the frequency-divided clock signal to have a second frequency; wherein, the second frequency is lower than the first frequency;
  • Step S340 if the target instruction is acquired, control the main path to output an output clock replica signal with the same phase as the output clock signal.
  • Exemplary embodiments of the present disclosure also provide an electronic device, which may include the above-mentioned delay-locked loop.
  • an electronic device which may include the above-mentioned delay-locked loop.
  • the specific structural details of the delay-locked loop have been described in detail in the above-mentioned implementation manners, and will not be repeated here.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • a software program When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present disclosure will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in, or transmitted from, one computer-readable storage medium to another computer-readable storage medium.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or may be a data storage device including one or more servers, data centers, etc.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (solid state disk, SSD)), etc.
  • a computer may include the aforementioned apparatus.

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Abstract

一种延迟锁相环、延迟锁相环控制方法及电子设备，涉及集成电路技术领域。延迟锁相环包括：副通路(100)，用于将输入时钟信号(CLK input)进行分频产生分频时钟信号(CLK Div)，在延迟锁相环锁定过程中，对具有第一频率的分频时钟信号进行调整获得输出时钟信号(CLK output)；在延迟锁相环锁定处于待机状态的情况下，调整分频时钟信号(CLK Div)具有第二频率；其中，第二频率低于第一频率；主通路(200)，用于在获取到目标指令的情况下，输出与输出时钟信号(CLK output)相位相同的输出时钟复制信号(DLL output)，可以降低延迟锁相环的功耗。

Description

延迟锁相环、延迟锁相环控制方法及电子设备
交叉引用
本公开要求于2022年1月14日提交的申请号为202210043659.X名称为“延迟锁相环、延迟锁相环控制方法及电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种延迟锁相环、延迟锁相环控制方法及电子设备。
背景技术
延迟锁相环(Delay-Locked Loop，DLL)是对时钟信号进行延迟调整，以实现系统中时钟信号同步的电路。由于该同步不随外界条件，如温度、电压等的变化而改变，因此，被广泛地应用在时序领域。
然而，现有的延迟锁相环，为了保证CPU(Central Processing Unit，中央处理器)读取数据的精确性，无论是在工作状态，还是在待机状态，均处于高频状态，导致延迟锁相环功耗较高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种延迟锁相环、延迟锁相环控制方法及电子设备，以降低延迟锁相环的功耗。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本发明的实践而习得。
根据本公开的第一方面，提供一种延迟锁相环，包括：副通路，用于将输入时钟信号进行分频产生分频时钟信号，在所述延迟锁相环锁定过程中，对具有第一频率的所述分频时钟信号进行调整获得输出时钟信 号；在所述延迟锁相环锁定处于待机状态的情况下，调整所述分频时钟信号具有第二频率；其中，所述第二频率低于所述第一频率；主通路，用于在获取到目标指令的情况下，输出与所述输出时钟信号相位相同的输出时钟复制信号。
根据本公开的一个方面，提供一种延迟锁相环控制方法，所述延迟锁相环包括主通路和副通路；所述控制方法包括：将输入时钟信号进行分频产生分频时钟信号；在所述延迟锁相环锁定过程中，通过所述副通路对具有第一频率的所述分频时钟信号进行调整获得输出时钟信号；在所述延迟锁相环锁定处于待机状态的情况下，调整所述分频时钟信号具有第二频率；其中，所述第二频率低于所述第一频率；在获取到目标指令的情况下，控制所述主通路输出与所述输出时钟信号相位相同的输出时钟复制信号。
根据本公开的一个方面，提供一种电子设备，包括：上述的延迟锁相环。
本公开示例性实施方式中，通过将延迟锁相环分为副通路和主通路，通过副通路对输入时钟信号进行调整，以获得输出时钟信号，同时，通过主通路将与输出时钟信号具有相同相位的输出时钟复制信号输出，用于后续的指令控制中。由于副通路在相位调整过程中会先对输入时钟信号进行分频，并且在延时锁相环锁定过程中，以及待机状态下，分频时钟信号具有不同的频率；通过在待机状态下使用较低的第二频率，可以在延迟锁相环待机的情况下，在不影响延迟锁相环输出精度的情况下，减小延迟锁相环的待机电流，达到减小延迟锁相环功耗的目的。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人 员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施方式的一种延迟锁相环的电路示意图；
图2为本公开一实施方式的延迟锁相环中的第一分频器的结构示意图；
图3为本公开一实施方式的延迟锁相环控制方法的步骤流程图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免模糊本公开的各方面。
附图中所示的方框图仅仅是功能实体，不一定必须与物理上独立的实体相对应。即，可以采用软件形式来实现这些功能实体，或在一个或多个软件硬化的模块中实现这些功能实体或功能实体的一部分，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
随着中央处理器速度的不断提高，存储器性能成为系统性能的一个限制因素。提高存储器性能的一个重要方面，即提高资料传输至动态随机存取存储器(DRAM，Dynamic Random Access Memory)内与从DRAM传输出资料的速度。在诸如Rambus动态随机存取存储器(RDRAM，Rambus Dynamic Random Access Memory)和双倍速率同步动态随机存储器(DDR，Double Data Rate Synchronous Dynamic RandomAccess  Memory，DDR SDRAM)等高速DRAM技术中，延迟锁相环是一种最大限度地减少输入时钟和控制信号之间的相位差的电路。
为了保证CPU在从DRAM中读取数据时的精确性，要求延迟锁相环在读指令等指令使能前，需要持续保持工作状态。可见，延迟锁相环的功耗也是不容忽视的部分。
基于此，参照图1，本公开实施例提供了一种延迟锁相环的电路示意图。图1中，该延迟锁相环包括：副通路100和主通路200；其中，副通路100用于将输入时钟信号CLK input进行分频产生分频时钟信号CLK Div，在延迟锁相环锁定过程中，对具有第一频率的分频时钟信号进行调整获得输出时钟信号CLK output；在延迟锁相环锁定处于待机状态的情况下，调整分频时钟信号CLK Div具有第二频率；此处，第二频率低于第一频率。
主通路200则用于在获取到目标指令的情况下，输出与输出时钟信号CLK output相位相同的输出时钟复制信号DLL output。其中，对于DRAM而言，目标指令可以是读指令、写指令、刷新指令等各种控制指令，本公开示例性实施方式对于目标指令不作特殊限定。
本公开实施例提供的延迟锁相环，通过将延迟锁相环分为副通路100和主通路200，通过副通路100对输入时钟信号CLK input进行调整，以获得输出时钟信号CLK output，同时，还可以通过主通路200将与输出时钟信号CLK output具有相同相位的输出时钟复制信号输出DLL output，用于后续的指令控制中。由于副通路100在相位调整过程中会先对输入时钟信号CLK input进行分频，以产生分频时钟信号CLK Div；并且在延时锁相环锁定过程中，以及待机状态下，分频时钟信号CLK Div具有不同的频率；通过在待机状态下使用较低的第二频率，可以在延迟锁相环待机的情况下，在不影响延迟锁相环输出精度的情况下，减小延迟锁相环的待机电流，达到减小延迟锁相环功耗的目的。
在实际应用中，延迟锁相环锁定过程指的是延迟锁相环通过延迟线调整输入时钟信号CLK input和输出时钟信号CLK output相位差的过程，在调整达到目标相位差，例如，相位差为零时，可以锁定延迟线，使得系统在后续运行中的时钟信号均能实现同步。延迟锁相环的待机状态指 的是延迟锁相环锁定后的状态。
需要说明的是，无论是延迟锁相环的锁定过程，还是待机状态，主通路200均处于关闭状态。只有在获取到目标指令时，主通路200才打开，用于输出上述的输出时钟复制信号DLL output。
具体的，本公开示例性实施方式中，参照图1，副通路100可以包括：第一分频器110、第一延迟线120、相位检测器130和延迟线控制器140。
其中，第一分频器110可以用于将输入时钟信号CLK input进行分频产生分频时钟信号CLK Div。根据实际需要，该分频时钟信号CLK Div可以具有不同的频率，例如，第一频率、第二频率等。需要说明的是，本公开实施例对于第一频率和第二频率的具体大小不作特殊限定。而且根据实际情况，第一分频器110可以产生多个不同频率的分频时钟信号CLK Div，以便于用户根据需要选择合适的频率作为分频时钟信号CLK Div的频率。
本公开示例性实施方式中，在延迟锁相环锁定过程中，分频时钟信号CLK Div具有第一频率；在延迟锁相环锁定处于待机状态的情况下，分频时钟信号CLK Div具有第二频率。
第一延迟线120则可以用于对分频时钟信号CLK Div进行延迟调整，以获得具有目标相位的输出时钟信号CLK output。在延迟调整过程中，由于经过第一延迟线120的分频时钟信号CLK Div具有第一频率，可以确保第一延迟线120在高频状态下调整分频时钟信号CLK Div，从而可以提高延迟调整的精度。
需要说明的是，在延迟锁相环锁定之后，或者说是在第一延迟线120锁定之后，第一分频器110则可以将分频时钟信号CLK Div的频率从第一频率降低为第二频率，从而可以确保第一延迟线120处于低频状态，达到减小功耗、节约能源的目的。
本公开示例性实施方式中，相位检测器130可以用于获取输出时钟信号CLK output，并将该输出时钟信号CLK output与输入时钟信号CLK input进行比较，确定出输出时钟信号CLK output与输入时钟信号CLK input的相位差，同时，根据该相位差可以产生控制信号，并将该控制 信号发送给延迟线控制器140。而延迟线控制器140则可以用于基于控制信号输出对应的调整信号，以调整第一延迟线120的延迟参数，以使得输出时钟信号CLK output具有目标相位。例如，使得输出时钟信号CLK output与输入时钟信号CLK input具有相同的相位，或者，输出时钟信号CLK output与输入时钟信号CLK input之间具有指定的相位差等，本公开示例性实施方式对于目标相位不作特殊限定。
在实际应用中，可对第一延迟线120进行调整以使得第一延迟线120具有不同的延迟参数，延迟参数指的是延迟时间。调整第一延迟线120的延迟时间的手段包括但不限于调整延迟线的长度以及改变延迟器件的数量和规格，其中，延迟线可由电阻较大的高阻线和电阻较小的低阻线构成，调整延迟线的长度包括同时调整高阻线的长度和低阻线的长度，从而在总长度不变的情况调整延迟线的延迟时间。本公开示例性实施方式对于延迟参数不作特殊限定。
本公开示例性实施方式中，参照图1，主通路200可以包括：第二分频器210和第二延迟线220。
其中，第二分频器210则具有与第一分频器110相同的固有延迟，此处的固有延迟指的是器件自身存在的延迟。通常，不同的器件具有不同的固有延迟，又由于第一分频器110具有多种器件，为了确保第二分频器210与第一分频器110的固有延迟相同，本公开示例性实施方式中，第二分频器210可以是第一分频器110的复制品，第二分频器210具有与第一分频器110完全相同的结构。
需要说明的是，在实际应用中，还可以设置第二分频器210与第一分频器110不同的结构，例如，第二分频器210可以由多个延迟单元组成，只要保证这些延迟单元的固有延迟与第一分频器110的固有延迟相同即可，本公开示例性实施方式对此不作限定。
在本公开的示例性实施方式中，第二延迟线220则需要跟随第一延迟线120对分频时钟信号CLK Div进行延迟调整，以获得输出时钟复制信号DLL output。也就是说，在副通路100进行延迟调整过程中，即使主通路200处于不输出信号的关闭状态，主通路200的第二延迟线220也会自动跟着第一延迟线120进行调整，完全不受主通路200所处状态 的影响。
在实际应用中，第二延迟线220跟随第一延迟线120对分频时钟信号CLK Div进行延迟调整的方式可以有多种，通过上述的延迟线控制器140，控制第一延迟线120的同时，控制第二延迟线220。或者，采用同步控制的方式，本公开示例性实施方式对于具体的同步控制方式不再赘述。
本公开实施例提供的延迟锁相环，除过通过副通路100处于不同的频率状态来减小功耗之外，还通过主通路200在延迟锁相环在锁定过程中，以及锁定后待机状态时处于关闭状态来减小功耗，从而达到进一步减小功耗的目的。
在本公开的示例性实施方式中，上述的副通路100还可以包括第一时钟输出使能单元150，输出时钟信号CLK output通过该第一时钟输出使能单元150传输至相位检测器130，以供相位检测器130对输出时钟信号CLK output与输入时钟信号CLK input的相位进行比较。
同样的，主通路200还可以包括第二时钟输出使能单元230，第二时钟输出使能单元230在接收到目标指令的情况下，控制延迟锁相环的输出端输出上述的输出时钟复制信号DLL output。也就是说，在目标指令的作用下，第二时钟输出使能单元230会打开，处于导通状态，以便于输出时钟复制信号DLL output可以传输出去。
也就是说，上述的主通路200处于关闭状态，主要指的是第二时钟输出使能单元230在没有接收到目标指令的时候，处于非使能状态，从而不输出上述的输出时钟复制信号DLL output。
在实际应用中，第二时钟输出使能单元230的结构可以根据实际情况确定，例如，第二时钟输出使能单元230可以是一个触发器等，在目标指令的触发下，用于输出上述的输出时钟复制信号DLL output。本公开示例性实施方式对于第二时钟输出使能单元230的结构不作特殊限定。
需要说明的是，第一时钟输出使能单元150的固有延迟与第二时钟输出使能单元230的固有延迟可以相同。作为一种示例，第一时钟输出使能单元150的结构可以与第二时钟输出使能单元230的结构相同，不 同的是第一时钟输出使能单元150需要持续处于打开状态，而无需目标指令的触发。
本公开示例性实施方式中，根据所需要的分频后的频率不同，第一分频器110可以有不同的结构。作为一种示例，参照图2，第一分频器110可以包括分频单元111、延迟单元112、第一多路选择器113和逻辑与门114。
其中，分频单元111可以用于对输入时钟信号CLK input进行分频处理，从而获得不同频率的分频时钟信号CLK Div。
延迟单元112则可以用于补偿分频单元111的延迟，以在用户不期望进行分频的情况下，选择不通过分频单元111进行分频。
第一多路选择器113的输入端用于接入分频单元111的输出端和延迟单元112的输出端，第一多路选择器113的控制端则用于接入Logic circuit逻辑与门114的输出端；用于在逻辑与门114输出结果的控制下，选择输出分频单元111的输出信号，或者选择输出延迟单元112的输出信号。
另外，逻辑与门114的输入端接入延迟锁相环锁定信号DLL_LOCK Flag和第一测试信号Testmode1，用于在延迟锁相环锁定信号DLL_LOCK Flag和第一测试信号Testmode1同时使能的情况下，控制第一多路选择器113输出延迟单元112的输出信号。例如，在高频使能的情况下，如果延迟锁相环锁定信号DLL_LOCK Flag和第一测试信号Testmode1均处于高电平，则第一多路选择器113选择输出延迟单元112的输出信号，不对输入时钟信号CLK input进行分频处理，以使延迟锁相环输出的分频时钟信号CLK Div始终处于同一频率状态，即处于较高的第一频率。
然而，在第一测试信号Testmode1未使能的情况下，例如低电平情况下，逻辑与门114的输出信号会控制第一多路选择器113选择输出分频单元111的输出信号，从而达到对输入时钟信号CLK input进行分频处理的目的。
在实际应用中，根据实际情况，可以设置不同的分频单元111，只要能获得所需频率的分频时钟信号CLK Div即可。本公开示例性实施方 式中，分频单元111包括多个依次串接的触发器1111，和多个第二多路选择器1112。
参照图2，前一级触发器1111的输出端连接后一级触发器1111的输入端，从而将多个触发器1111串接起来，以在输入时钟信号CLK input的触发下，实现信号从前一级触发器1111向后一级触发器1111的传输。
另外，多个第二多路选择器1112则用于将每一级触发器1111的输出端分别引向第一级触发器1111的输入端，通过信号的循环以实现对输入时钟信号CLK input的分频。
在实际应用中，根据需要分频获得的频率大小，例如，所需要的第一频率和第二频率的大小，可以设置不同数量的触发器1111和第二多路选择器1112。例如，可以设置触发器1111有四个，设置第二多路选择器1112有三个。
其中两个第二多路选择器1112的四个输入端分别接入四个触发器1111的输出端，该其中两个第二多路选择器1112的输出端接入第三个第二多路选择器1112的输入端；同时，第三个第二多路选择器1112的输出端接入第一级触发器1111的输入端；三个第二多路选择器1112的控制端分别接入三个第二测试信号，如图2所示，三个第二测试信号包括Testmode2、Testmode3和Testmode4，在三个不同的第二测试信号Testmode2、Testmode3和Testmode4的组合下，控制输入时钟信号CLK input产生不同的分频时钟信号CLK Div。例如，图2中的分频单元111可以产生1/2、1/4、1/6和1/8倍于输入时钟信号CLK input频率的分频时钟信号CLK Div。
在实际应用中，延迟单元112可以由多种方式组成，只要所确定的延迟单元112与分频单元111的延迟同步即可。例如，延迟单元112可以包括多个串接的反相器，在反相器和触发器1111的延迟相同的情况下，反相器的个数与触发器的个数相同，以满足延迟同步的需求。本公开示例性实施方式对于延迟单元112的具体结构不作限定。
在本公开的示例性实施方式中，第一分频器110还可以包括驱动器115，驱动器115的输入端与第一多路选择器113的输出端相连，驱动器 115的输出端输出分频时钟信号CLK Div。驱动器115主要用于增强所要输出的分频时钟信号CLK Div的强度。
需要说明的是，用于本公开实施例的延迟锁相环中的第一分频器110不限于上述的结构。
综上，本公开示例性实施方式提供的延迟锁相环，通过设置主通路和副通路，在延迟锁相环锁定过程中，可以仅仅通过副通路来调整第一延迟线，达到调整延迟的目的；并且通过主通路来输出最终信号，从而可以将调整和输出分别来设置，根据所处的阶段，可以根据情况关闭主通路或降低副通路的工作频率，从而最大限度地降低延迟锁相环的电流损耗，达到节能的目的。
需要说明的是，尽管在附图中以特定顺序描述了本发明中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
此外，在本示例实施例中，还提供了一种延迟锁相环控制方法。该延迟锁相环控制方法用于上述的延迟锁相环。参照图3，该延迟锁相环控制方法包括以下步骤：
步骤S310，将输入时钟信号进行分频产生分频时钟信号；
步骤S320，在延迟锁相环锁定过程中，通过副通路对具有第一频率的分频时钟信号进行调整获得输出时钟信号；
步骤S330，在延迟锁相环锁定处于待机状态的情况下，调整分频时钟信号具有第二频率；其中，第二频率低于第一频率；
步骤S340，在获取到目标指令的情况下，控制主通路输出与输出时钟信号相位相同的输出时钟复制信号。
上述延迟锁相环控制方法的具体细节已经在对应的延迟锁相环中进行了详细的描述，因此此处不再赘述。
在本公开的示例性实施例还提供了一种电子设备，该电子设备可以包括上述的延迟锁相环。其中，延迟锁相环的具体结构细节已经在上述实施方式中进行了详细说明，此处不再赘述。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本公开实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。本公开实施例中，计算机可以包括前面所述的装置。
尽管在此结合各实施例对本公开进行了描述，然而，在实施所要求保护的本公开过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其他单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本公开进行了描述，显而易见的，在不脱离本公开的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本公开的示例性说明，且视为已覆盖本公开范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种延迟锁相环，包括：
    副通路，用于将输入时钟信号进行分频产生分频时钟信号，在所述延迟锁相环锁定过程中，对具有第一频率的所述分频时钟信号进行调整获得输出时钟信号；在所述延迟锁相环锁定处于待机状态的情况下，调整所述分频时钟信号具有第二频率；其中，所述第二频率低于所述第一频率；
    主通路，用于在获取到目标指令的情况下，输出与所述输出时钟信号相位相同的输出时钟复制信号。
  2. 根据权利要求1所述的延迟锁相环，其中，所述副通路包括：
    第一分频器，用于将输入时钟信号进行分频产生所述分频时钟信号；
    第一延迟线，用于对所述分频时钟信号进行延迟调整，以获得具有目标相位的所述输出时钟信号；
    相位检测器，用于获取所述输出时钟信号，并将所述输出时钟信号与所述输入时钟信号进行比较，确定出所述输出时钟信号与所述输入时钟信号的相位差，根据所述相位差产生控制信号，并将所述控制信号发送给延迟线控制器；
    所述延迟线控制器，用于基于所述控制信号输出对应的调整信号，以调整所述第一延迟线的延迟参数。
  3. 根据权利要求2所述的延迟锁相环，其中，所述主通路包括：
    第二分频器，与所述第一分频器具有相同的固有延迟；
    第二延迟线，跟随所述第一延迟线对所述分频时钟信号进行延迟调整，以获得所述输出时钟复制信号。
  4. 根据权利要求3所述的延迟锁相环，其中，所述副通路还包括第一时钟输出使能单元，所述输出时钟信号通过所述第一时钟输出使能单元传输至所述相位检测器；
    所述主通路还包括第二时钟输出使能单元，所述第二时钟输出使能单元在接收到所述目标指令的情况下，控制延迟锁相环的输出端输出所述输出时钟复制信号。
  5. 根据权利要求4所述的延迟锁相环，其中，所述第一时钟输出使 能单元的固有延迟与所述第二时钟输出使能单元的固有延迟相同。
  6. 根据权利要求2-5中任一项所述的延迟锁相环，其中，所述第一分频器用于，在所述第一延迟线锁定后，将所述分频时钟信号的频率从所述第一频率降低为所述第二频率。
  7. 根据权利要求6所述的延迟锁相环，其中，所述第一分频器包括：
    分频单元，用于对所述输入时钟信号进行分频处理；
    延迟单元，用于补偿所述分频单元的延迟；
    第一多路选择器，输入端用于接入所述分频单元的输出端和所述延迟单元的输出端，控制端用于接入逻辑与门的输出端；
    所述逻辑与门的输入端接入延迟锁相环锁定信号和第一测试信号，用于在所述延迟锁相环锁定信号和所述第一测试信号同时使能的情况下，控制所述第一多路选择器输出所述延迟单元的输出信号，在所述第一测试信号未使能的情况下，控制所述第一多路选择器输出所述分频单元的输出信号。
  8. 根据权利要求7所述的延迟锁相环，其中，所述分频单元包括多个依次串接的触发器，和多个第二多路选择器；
    前一级所述触发器的输出端连接后一级所述触发器的输入端；
    多个所述第二多路选择器用于将每一级所述触发器的输出端分别引向第一级所述触发器的输入端，以实现对所述输入时钟信号的分频。
  9. 根据权利要求8所述的延迟锁相环，其中，所述触发器有四个，所述第二多路选择器有三个；
    其中两个所述第二多路选择器的四个输入端分别接入四个所述触发器的输出端，所述其中两个所述第二多路选择器的输出端接入第三个所述第二多路选择器的输入端；
    第三个所述第二多路选择器的输出端接入第一级所述触发器的输入端；
    三个所述第二多路选择器的控制端分别接入三个第二测试信号，用于在三个不同的所述第二测试信号的组合下，控制所述输入时钟信号产生不同的所述分频时钟信号。
  10. 根据权利要求8所述的延迟锁相环，其中，所述延迟单元包括 多个串接的反相器。
  11. 根据权利要求10所述的延迟锁相环，其中，在所述反相器和所述触发器的延迟相同的情况下，所述反相器的个数与所述触发器的个数相同。
  12. 根据权利要求7-11中任一项所述的延迟锁相环，其中，所述第一分频器还包括驱动器，所述驱动器的输入端与所述第一多路选择器的输出端相连，所述驱动器的输出端输出所述分频时钟信号。
  13. 根据权利要求3所述的延迟锁相环，其中，所述第二分频器与所述第一分频器具有相同的结构。
  14. 一种延迟锁相环控制方法，所述延迟锁相环包括主通路和副通路；所述控制方法包括：
    将输入时钟信号进行分频产生分频时钟信号；
    在所述延迟锁相环锁定过程中，通过所述副通路对具有第一频率的所述分频时钟信号进行调整获得输出时钟信号；
    在所述延迟锁相环锁定处于待机状态的情况下，调整所述分频时钟信号具有第二频率；其中，所述第二频率低于所述第一频率；
    在获取到目标指令的情况下，控制所述主通路输出与所述输出时钟信号相位相同的输出时钟复制信号。
  15. 一种电子设备，包括：如权利要求1-13中任一项所述的延迟锁相环。
PCT/CN2022/085078 2022-01-14 2022-04-02 延迟锁相环、延迟锁相环控制方法及电子设备 WO2023134034A1 (zh)

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CN116743155A (zh) * 2023-08-14 2023-09-12 浙江力积存储科技有限公司 一种延迟锁相环和存储器
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