WO2023134019A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023134019A1
WO2023134019A1 PCT/CN2022/083040 CN2022083040W WO2023134019A1 WO 2023134019 A1 WO2023134019 A1 WO 2023134019A1 CN 2022083040 W CN2022083040 W CN 2022083040W WO 2023134019 A1 WO2023134019 A1 WO 2023134019A1
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layer
substrate
hole
semiconductor structure
conductive
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PCT/CN2022/083040
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English (en)
French (fr)
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高远皓
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长鑫存储技术有限公司
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Priority to US18/320,235 priority Critical patent/US20230307354A1/en
Publication of WO2023134019A1 publication Critical patent/WO2023134019A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • TSV Thine Silicon Via
  • TSV Thine Silicon Via
  • Through-silicon via technology can effectively shorten the length of interconnection lines between chips and reduce signal delay through vertical interconnection, thereby improving the signal transmission performance and operating frequency of electronic systems, increasing broadband and realizing miniaturization of device integration. It is a future semiconductor technology. important direction of development.
  • three-dimensional packaging technology generally uses through-silicon via technology to realize chip-to-chip interconnection; through-silicon via technology is filled with conductive substances such as copper, tungsten, and polysilicon to realize the vertical electrical interconnection of through-silicon holes, which can transfer signals from the chip to the chip.
  • through-silicon via technology is filled with conductive substances such as copper, tungsten, and polysilicon to realize the vertical electrical interconnection of through-silicon holes, which can transfer signals from the chip to the chip.
  • One side is conducted to the other side of the chip, and by combining chip stacking technology, the three-dimensional integration of multi-layer chips is realized.
  • a semiconductor structure and a manufacturing method thereof are provided.
  • an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, including:
  • the ring-shaped sacrificial barrier layer is removed to obtain an interconnection hole, the width of the upper portion of the interconnection hole is greater than the width of the lower portion of the interconnection hole.
  • the base includes a substrate and a dielectric layer located on the surface of the substrate; forming the ring-shaped sacrificial barrier layer in the base includes:
  • the first patterned mask layer has an annular opening, and the annular opening defines the shape and position of the annular groove;
  • the sacrificial material layer covering the surface of the dielectric layer is removed, and the sacrificial material layer remaining in the annular groove is the annular sacrificial barrier layer.
  • the forming an etching hole in the substrate includes:
  • the second patterned mask layer has an opening pattern, and the opening pattern exposes the annular sacrificial barrier layer and the inner side of the annular sacrificial barrier layer the medium layer;
  • the sidewall of the upper part of the interconnection hole is an inclined sidewall.
  • the angle between the upper sidewall of the interconnection hole and the upper surface of the substrate is 60°-80°.
  • the method further includes:
  • a conductive structure is formed in the interconnection hole, and the conductive structure fills the interconnection hole.
  • the method before forming the conductive structure in the interconnection hole, the method further includes:
  • An oxygen pad layer is formed at least on the sidewall and bottom of the interconnect hole; the conductive structure is located on the surface of the oxygen pad layer.
  • the backside of the substrate is thinned until the conductive structure is exposed, so as to form a conductive interconnection structure.
  • the oxygen pad layer is also located on the surface of the substrate; forming a conductive structure in the interconnection hole includes:
  • the conductive material layer on the substrate and the seed material layer on the substrate to obtain a seed layer and a conductive layer in the interconnect holes, the seed layer and the conductive
  • a semiconductor structure comprising:
  • the interconnection hole is located in the base, and the width of the upper part of the interconnection hole is greater than the width of the lower part of the interconnection hole.
  • the base includes: a substrate and a dielectric layer located on the surface of the substrate; the interconnection hole penetrates the dielectric layer and extends into the substrate.
  • the sidewall of the upper part of the interconnection hole is an inclined sidewall.
  • the angle between the upper sidewall of the interconnection hole and the upper surface of the substrate is 60°-80°.
  • the semiconductor structure further includes: a conductive structure that fills up the interconnection hole.
  • the semiconductor structure further includes an oxygen cushion layer, and the oxygen cushion layer is located at least between the conductive structure and the substrate.
  • the conductive structure includes:
  • the conductive layer is located on the surface of the seed layer and fills up the interconnection holes.
  • the conductive structure extends through the substrate.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the width of the upper part of the interconnection hole is set to be larger than the width of the lower part, so that such an interconnection hole can avoid sealing in advance when filling the conductive layer in the subsequent process, so as to obtain a hole-free conductive structure.
  • the semiconductor structure provided by the embodiments of the present disclosure has an interconnection hole whose width at the upper part is greater than that at the bottom. Such interconnection hole can avoid sealing in advance when filling the conductive layer in a subsequent process, thereby obtaining a conductive structure without holes.
  • Figure (a) in Figure 1 shows a cross-sectional schematic diagram of a semiconductor structure in an embodiment of the present disclosure
  • Figure (b) in Figure 2 shows that the structure shown in Figure (a) in Figure 1 is being filled with metal
  • the schematic diagram of the cross-sectional structure, the (c) figure in Fig. 1 shows the cross-sectional structural schematic diagram of the structure shown in the (a) figure in Fig. 1 after metal filling;
  • Figure 2 (a) shows a cross-sectional schematic diagram of a semiconductor structure in another embodiment of the present disclosure
  • Figure 2 (b) shows that the structure shown in Figure 2 (a) is removed.
  • the schematic diagram of the cross-sectional structure of the structure obtained after the mask layer shows the schematic cross-sectional structure of the structure obtained after depositing a metal material layer in the hole in the structure shown in Figure 2 (b)
  • Figure 2 Figure (d) in Figure 2 shows a cross-sectional schematic diagram of the structure obtained after removing the metal material layer on the dielectric layer in the structure shown in Figure (c) in Figure 2;
  • FIG. 3 shows a flowchart of a method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 4 shows a schematic cross-sectional structure diagram of the structure obtained in step S201 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 5 shows a flowchart of step S20 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 6 shows a schematic cross-sectional structure diagram of the structure obtained in step S203 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • step S204 shows a schematic cross-sectional structure diagram of the structure obtained in step S204 in the method for preparing the semiconductor structure provided in the first embodiment of the present disclosure
  • FIG. 8 shows a schematic cross-sectional structure diagram of the structure obtained in step S205 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 9 shows a flowchart of step S30 in the method for manufacturing a semiconductor structure provided in Embodiment 1 of the present disclosure.
  • FIG. 10 shows a schematic cross-sectional structure diagram of the structure obtained in step S302 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 11 shows a schematic cross-sectional structure diagram of the structure obtained in step S303 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 12 shows a schematic cross-sectional structure diagram of the structure obtained in step S40 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 13 shows a flowchart of step S60 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • FIG. 14 shows a schematic cross-sectional structure diagram of the structure obtained in step S602 in the method for preparing a semiconductor structure provided in Embodiment 1 of the present disclosure
  • Figure 15 shows a schematic cross-sectional structure of the structure obtained in step S603 in the method for preparing a semiconductor structure provided in the first embodiment of the present disclosure; Figure 15 also shows a cross-sectional view of the semiconductor structure provided in another embodiment of the present disclosure Schematic.
  • three-dimensional packaging technology generally uses through-silicon via technology to realize chip-to-chip interconnection; through-silicon via technology is filled with conductive substances such as copper, tungsten, and polysilicon to realize the vertical electrical interconnection of through-silicon holes, which can transfer signals from the chip to the chip.
  • through-silicon via technology is filled with conductive substances such as copper, tungsten, and polysilicon to realize the vertical electrical interconnection of through-silicon holes, which can transfer signals from the chip to the chip.
  • One side is conducted to the other side of the chip, and by combining chip stacking technology, the three-dimensional integration of multi-layer chips is realized.
  • the structure includes a substrate 101', a dielectric layer 102' located on the surface of the substrate 101', and a The hole 20' in the bottom 101', and the hole 20' has a high aspect ratio; as shown in Figure 1 (b), when the metal material layer 30' is deposited in the hole 20', due to the The smaller the angle, the faster the deposition speed of the metal material layer 30 ′, causing the hole 20 ′ to be sealed in advance; as shown in (c) of FIG. 1 , there is a cavity 40 ′ in the hole 20 ′.
  • the hole 20' in this structure is formed based on the mask layer 103' on the surface of the dielectric layer 102', as shown in
  • the step shown in Figure 2 (b) is the step of removing the mask layer 103'; as shown in Figure 2 (c), when depositing the metal material layer 30' in the hole 20', the edge of the hole 20' The angle is small, and the deposition speed of the metal material layer 30' is fast, causing the hole 20' to be sealed in advance, and there is a cavity 40' in the hole 20';
  • the step shown in Figure 2 (d) is to remove the mask layer 103'
  • the step is to remove the metal material layer 30' on the dielectric layer 102' to obtain the metal layer 40' in the hole 20'; the resulting structure may also have a seed layer 60'.
  • a method for preparing a semiconductor structure including:
  • Step S10 providing a substrate.
  • Step S20 forming a ring-shaped sacrificial barrier layer in the substrate.
  • step S30 an etching hole is formed in the substrate, and the etching hole is located inside the ring-shaped sacrificial barrier layer.
  • Step S40 removing the ring-shaped sacrificial barrier layer to obtain an interconnection hole, the width of the upper part of the interconnection hole is greater than the width of the lower part of the interconnection hole.
  • the interconnection hole can avoid being sealed in advance when the conductive layer is filled in the subsequent process, thereby obtaining a conductive structure without holes.
  • the base 10 may include a substrate 101 and a dielectric layer 102 on the surface of the substrate 101 .
  • the substrate 101 may include but not limited to any one of a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate or a gallium arsenide substrate, etc.; the dielectric layer 102 may be Including but not limited to oxide layers, such as silicon oxide layers.
  • the substrate 101 includes a silicon substrate, and the dielectric layer 102 includes a silicon oxide layer.
  • the silicon oxide layer grows easily and stably, and has ideal interface properties with the silicon substrate; at the same time, there is a very good selective etching ratio between the silicon oxide layer and the silicon substrate.
  • step S20 may include:
  • Step S201 please continue to refer to FIG. 4, forming a first patterned mask layer 201 on the surface of the dielectric layer 102, the first patterned mask layer 201 has an annular opening 202, and the annular opening 202 defines the shape of the annular groove 203 and Location.
  • step S202 please refer to FIG. 6 , etching the dielectric layer 102 based on the first patterned mask layer 201 to form an annular groove 203 in the dielectric layer 102 .
  • Step S203 please continue to refer to FIG. 6 , removing the first patterned mask layer 201 .
  • Step S204 please refer to FIG. 7 , forming a sacrificial material layer 204 on the surface of the dielectric layer 102 , the sacrificial material layer 204 fills the annular groove 203 and covers the surface of the dielectric layer 102 .
  • Step S205 please refer to FIG. 8 , remove the sacrificial material layer 204 covering the surface of the dielectric layer 102 , and the sacrificial material layer 204 remaining in the annular groove 203 is the annular sacrificial barrier layer 20 .
  • step S30 please refer to FIG. 9, as an example, step S30 may include:
  • Step S301 referring to FIG. 10 , forming a second patterned mask layer 301 on the surface of the dielectric layer 102, the second patterned mask layer 301 has an opening pattern (not shown in FIG. 10 ), and the opening pattern exposes The annular sacrificial barrier layer 20 and the dielectric layer 102 inside the annular sacrificial barrier layer 20 .
  • step S302 please continue to refer to FIG. 10 , etching the substrate 10 based on the second patterned mask layer 301 to form etching holes 30 .
  • Step S303 please refer to FIG. 11 , remove the second patterned mask layer 301 .
  • step S40 referring to FIG. 12 , the ring-shaped sacrificial barrier layer 20 is removed to obtain the interconnection hole 40 ; specifically, the width of the upper portion of the interconnection hole 40 is greater than the width of the lower portion of the interconnection hole 40 .
  • the embodiment of the present disclosure does not specifically limit the realization that the width of the upper part of the interconnection hole 40 is greater than the width of the lower part.
  • the sidewall of the upper part of the interconnection hole 40 may include but not limited to inclined sidewalls, curved sidewalls or zigzag sidewalls, etc. wait.
  • the upper sidewall of the interconnection hole 40 is an inclined sidewall.
  • setting the upper sidewall of the interconnection hole 40 as an inclined sidewall can make the arrival angle of the edge of the interconnection hole 40 larger, which is more conducive to forming an interconnection structure without holes.
  • the embodiment of the present disclosure does not specifically limit the angle of inclination of the inclined side wall; as an example, the angle between the upper side wall of the interconnection hole 40 and the upper surface of the substrate 10 is 60°-80°, for example, it may be 60° °, 65°, 70°, 75° or 80°, etc.; it should be noted that the above data is only an example, and the inclination angle of the inclined side wall in the actual embodiment is not limited to the above data.
  • the preparation method may also include after step S40:
  • the preparation method may also include before step S60:
  • Step S50 please continue to refer to FIG. 12 , at least forming an oxygen pad layer 50 on the sidewall and bottom of the interconnection hole 40 ; on this basis, the conductive structure 60 may be located on the surface of the oxide pad layer 50 .
  • the oxygen pad layer 50 can protect the surface of the substrate 10 in the subsequent process and prevent the surface of the substrate 10 from being damaged by the etching process.
  • the oxygen cushion layer 50 can also play an isolation role between the follow-up film layer and the substrate 10, avoiding the direct contact between the follow-up film layer and the substrate 10 surface, thereby providing a good surface for the formation of the follow-up film layer, reducing the inner surface of the substrate 10 Generation of dislocation defects.
  • the embodiment of the present disclosure does not specifically limit the material and structure of the oxygen cushion layer 50.
  • the oxygen cushion layer 50 may include but not limited to an oxide layer, such as a silicon oxide layer; It is not specifically limited, and the method of forming the oxygen pad layer 50 may include but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal oxidation and so on.
  • step S60 please refer to FIG. 13, as an example, step S60 may include:
  • step S601 please refer to FIG. 14 , forming a seed material layer 601 on the surface of the oxygen pad layer 50 .
  • step S602 please continue to refer to FIG. 14 , forming a conductive material layer 602 on the surface of the seed material layer 601 , and the conductive material layer 602 fills the interconnection holes 40 .
  • Step S603 please refer to FIG. 15, remove the conductive material layer 602 on the substrate 10 and the seed material layer 601 on the substrate 10 to obtain the seed layer 603 and the conductive layer 604 in the interconnection hole 40; the seed Layer 603 together with conductive layer 604 constitutes conductive structure 60 .
  • the embodiments of the present disclosure do not specifically limit the materials of the conductive material layer 602 and the conductive layer 604; the materials of the conductive material layer 602 and the conductive layer 604 may include but are not limited to platinum (Pt), gold (Au) , copper (Cu), titanium (Ti) or tungsten (W) and so on.
  • the conductive material layer 602 includes a copper layer, and on this basis, the conductive layer 604 also includes a copper layer; choosing copper as the conductive material can not only reduce costs, but also be well compatible with existing processes, thereby simplifying the process .
  • the preparation method may further include a step of thinning the backside of the substrate 10; the backside of the substrate 10 may be thinned until the conductive structure 60 is exposed, so as to form a conductive interconnection structure.
  • the semiconductor structure may include a substrate 10 and an interconnection hole 40 (not shown in FIG. 15 ).
  • the interconnection hole 40 is located in the substrate 10 , and the width of the upper part of the interconnection hole 40 is greater than the width of the lower part of the interconnection hole 40 .
  • the width of the upper part of the interconnection hole is greater than the width of the lower part, such an interconnection hole can avoid sealing in advance when the conductive layer is filled in the subsequent process, so as to obtain a conductive structure without holes.
  • the embodiment of the present disclosure does not specifically limit the realization that the width of the upper part of the interconnection hole 40 is greater than the width of the lower part.
  • the sidewall of the upper part of the interconnection hole 40 may include but not limited to inclined sidewalls, curved sidewalls or zigzag sidewalls, etc. wait.
  • the upper sidewall of the interconnection hole 40 is an inclined sidewall.
  • the arrival angle of the edge of the interconnection hole 40 can be made larger, which is more conducive to forming an interconnection structure without holes.
  • the embodiment of the present disclosure does not specifically limit the angle of inclination of the inclined side wall; as an example, the angle between the upper side wall of the interconnection hole 40 and the upper surface of the substrate 10 is 60°-80°, for example, it may be 60° °, 65°, 70°, 75° or 80°, etc.; it should be noted that the above data is only an example, and the inclination angle of the inclined side wall in the actual embodiment is not limited to the above data.
  • the base 10 may include a substrate 101 and a dielectric layer 102 on the surface of the substrate 101 ; on this basis, the interconnection hole 40 may penetrate the dielectric layer 102 and extend into the substrate 101 .
  • the semiconductor structure may further include a conductive structure 60 ; specifically, the conductive structure 60 fills the interconnection hole 40 .
  • the conductive structure 60 may penetrate through the substrate 10 to form a conductive interconnection structure.
  • the conductive structure 60 may include a seed layer 603 and a conductive layer 604 .
  • the seed layer 603 is located on the surface of the oxygen pad layer 50 ;
  • the conductive layer 604 is located on the surface of the seed layer 603 and fills the interconnection holes 40 .
  • the embodiment of the present disclosure does not specifically limit the material of the conductive layer 604; the material of the conductive layer 604 may include but not limited to platinum (Pt), gold (Au), copper (Cu), titanium (Ti) or tungsten (W) etc. one or more.
  • the conductive layer 604 includes a copper layer; choosing copper as the conductive material can not only reduce the cost, but also be well compatible with the existing process, thereby simplifying the process.
  • the semiconductor structure may further include an oxygen pad layer 50 ; wherein the oxygen pad layer 50 is at least located between the conductive structure 60 and the substrate 10 .
  • the oxygen pad layer 50 can protect the surface of the substrate 10 in subsequent processes, preventing the surface of the substrate 10 from being damaged by the etching process; at the same time,
  • the oxygen cushion layer 50 can also play an isolation role between the subsequent film layer and the substrate 10, avoiding direct contact between the subsequent film layer and the surface of the substrate 10, thereby providing a good surface for the formation of the subsequent film layer and reducing dislocation defects in the substrate 10 generation.
  • the embodiment of the present disclosure does not specifically limit the material and structure of the oxygen pad layer 50 , and the oxygen pad layer 50 may include but not limited to an oxide layer, such as a silicon oxide layer or a silicon nitride layer.

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Abstract

本公开实施例涉及一种半导体结构及其制备方法。该制备方法包括提供基底；于所述基底内形成环形牺牲阻挡层；于所述基底内形成刻蚀孔，所述刻蚀孔位于所述环形牺牲阻挡层内侧；去除所述环形牺牲阻挡层，以得到互连孔，所述互连孔上部的宽度大于所述互连孔下部的宽度。本公开实施例通过将互连孔上部的宽度设置为大于下部的宽度，使得互连孔在后续工艺中进行导电层填充时可以避免提前封口，从而得到无孔洞的导电结构。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开基于申请号为202210031093.9、申请日为2022年01月12日、发明名称为“半导体结构及其制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体技术领域，特别是涉及半导体结构及其制备方法。
背景技术
TSV(Through Silicon Via，硅通孔)技术是一项高密度封装技术，正在逐渐取代目前工艺比较成熟的引线键合技术，被认为是第四代封装技术。硅通孔技术可以通过垂直互连有效缩短芯片间互连线的长度，减小信号延迟，从而提高电子系统的信号传输性能和工作频率，增加宽带和实现器件集成的小型化，是未来半导体技术发展的重要方向。
目前，三维封装技术普遍使用硅通孔技术实现芯片与芯片间互联；硅通孔技术通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连，可以将信号从芯片的一面传导至芯片的另一面，并通过结合芯片堆叠技术，实现多层芯片的三维集成。
然而，在对高深宽比孔洞进行金属填充时，存在到达角度的问题；孔洞边缘处由于角度小，金属沉积速度快，导致孔洞提前封口，孔洞内存在空洞问题。
发明内容
根据本公开实施例的各种实施例，提供一种半导体结构及其制备方法。
根据一些实施例，本公开实施例一方面提供一种半导体结构的制备方法，包括：
提供基底；
于所述基底内形成环形牺牲阻挡层；
于所述基底内形成刻蚀孔，所述刻蚀孔位于所述环形牺牲阻挡层内侧；
去除所述环形牺牲阻挡层，以得到互连孔，所述互连孔上部的宽度大于所述互连孔下部的宽度。
根据一些实施例，所述基底包括衬底及位于所述衬底表面的介质层；所述于所述基底内形成环形牺牲阻挡层，包括：
于所述介质层的表面形成第一图形化掩膜层，所述第一图形化掩膜层内具有环形开口，所述环形开口定义出所述环形槽的形状及位置；
基于所述第一图形化掩膜层刻蚀所述介质层，以于所述介质层内形成所述环形槽；
去除所述第一图形化掩膜层；
于所述介质层的表面形成牺牲材料层，所述牺牲材料层填满所述环形槽且覆盖所述介质层的表面；
去除覆盖所述介质层表面的所述牺牲材料层，保留于所述环形凹槽内的所述牺牲材料层即为所述环形牺牲阻挡层。
根据一些实施例，所述于所述基底内形成刻蚀孔，包括：
于所述介质层的表面形成第二图形化掩膜层，所述第二图形化掩膜层内具有开口图形，所述开口图形暴露出所述环形牺牲阻挡层及所述环形牺牲阻挡层内侧的所述介质层；
基于所述第二图形化掩膜层刻蚀所述基底，以形成所述刻蚀孔；
去除所述第二图形化掩膜层。
根据一些实施例，所述互连孔上部的侧壁为倾斜侧壁。
根据一些实施例，所述互连孔上部的侧壁与所述基底上表面的夹角为60° ～80°。
根据一些实施例，所述去除所述环形牺牲阻挡层，以得到互连孔之后，还包括：
于所述互连孔内形成导电结构，所述导电结构填满所述互连孔。
根据一些实施例，所述于所述互连孔内形成导电结构之前，还包括：
至少于所述互连孔的侧壁及底部形成垫氧层；所述导电结构位于所述垫氧层的表面。
根据一些实施例，所述于所述互连孔内形成所述导电结构之后，还包括：
对所述基底进行背面减薄，直至暴露出所述导电结构，以形成导电互连结构。
根据一些实施例，所述垫氧层还位于所述基底的表面；所述于所述互连孔内形成导电结构，包括：
于所述垫氧层的表面形成籽晶材料层；
于所述籽晶材料层的表面形成导电材料层，所述导电材料层填满所述互连孔；
去除位于所述基底上的所述导电材料层及位于所述基底上的籽晶材料层，以得到位于所述互连孔内的籽晶层及导电层，所述籽晶层与所述导电层共同构成所述导电结构。
根据一些实施例，本公开实施例的另一方面公开了一种半导体结构，所述半导体结构包括：
基底；
互连孔，位于所述基底内，所述互连孔上部的宽度大于所述互连孔下部的宽度。
根据一些实施例，所述基底包括：衬底及位于所述衬底表面的介质层；所述互连孔贯穿所述介质层并延伸至所述衬底内。
根据一些实施例，所述互连孔上部的侧壁为倾斜侧壁。
根据一些实施例，所述互连孔上部的侧壁与所述基底上表面的夹角为60° ～80°。
根据一些实施例，所述半导体结构还包括：导电结构，所述导电结构填满所述互连孔。
根据一些实施例，所述半导体结构还包括垫氧层，所述垫氧层至少位于所述导电结构与所述基底之间。
根据一些实施例，所述导电结构包括：
籽晶层，位于所述垫氧层的表面；
导电层，位于所述籽晶层的表面，且填满所述互连孔。
根据一些实施例，所述导电结构贯穿所述基底。
本公开实施例可以/至少具有以下优点：
本公开实施例提供的半导体结构的制备方法，将互连孔上部的宽度设置为大于下部的宽度，这样的互连孔在后续工艺中进行导电层填充时可以避免提前封口，从而得到无孔洞的导电结构。
本公开实施例提供的半导体结构，具有上部宽度大于下部宽度的互连孔，这样的互连孔可以在后续工艺中进行导电层填充时可以避免提前封口，从而得到无孔洞的导电结构。
本公开实施例的一个或多个实施例的细节在下面的附图和描述中提出。本公开实施例的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1中的(a)图显示为本公开实施例一实施例中半导体结构的截面结构示意图，图2中的(b)图显示为图1中(a)图所示的结构在进行金属填充时的截面 结构示意图，图1中的(c)图显示为图1中(a)图所示的结构进行金属填充后所得结构的截面结构示意图；
图2中的(a)图显示为本公开实施例另一实施例中半导体结构的截面结构示意图，图2中的(b)图显示为去除图2中(a)图所示的结构中的掩膜层之后所得结构的截面结构示意图，图2中的(c)图显示为于图2中(b)图所示的结构中的孔洞内沉积金属材料层后所得结构的截面结构示意图，图2中的(d)图显示为去除图2中(c)图所示的结构中介质层上的金属材料层后所得结构的截面结构示意图；
图3显示为本公开实施例一实施例中提供的半导体结构的制备方法的流程图；
图4显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S201所得结构的截面结构示意图；
图5显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S20的流程图；
图6显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S203所得结构的截面结构示意图；
图7显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S204所得结构的截面结构示意图；
图8显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S205所得结构的截面结构示意图；
图9显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S30的流程图；
图10显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S302所得结构的截面结构示意图；
图11显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S303所得结构的截面结构示意图；
图12显示为本公开实施例一实施例中提供的半导体结构的制备方法中， 步骤S40所得结构的截面结构示意图；
图13显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S60的流程图；
图14显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S602所得结构的截面结构示意图；
图15显示为本公开实施例一实施例中提供的半导体结构的制备方法中，步骤S603所得结构的截面结构示意图；图15亦显示为本公开实施例另一实施例中提供的半导体结构的截面结构示意图。
具体实施方式
为了便于理解本公开实施例，下面将参考相关附图对本公开实施例进行更全面的描述。附图中给出了本公开实施例的首选实施例。但是，本公开实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开实施例的技术领域的技术人员通常理解的含义相同。本文中在本公开实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开实施例教导之下，下面讨论的第一元件、部件、 区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开实施例的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
请参阅图1-图15。需要说明的是，本实施例中所提供的图示仅以示意方式说明本公开实施例的基本构想，虽图示中仅显示与本公开实施例中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
目前，三维封装技术普遍使用硅通孔技术实现芯片与芯片间互联；硅通孔技术通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连，可以将信号从芯片的一面传导至芯片的另一面，并通过结合芯片堆叠技术，实现多层芯片的三维集成。
然而，在对高深宽比孔洞进行金属填充时，存在到达角度的问题；孔洞边缘处由于角度小，金属沉积速度快，导致孔洞提前封口，孔洞内存在空洞 问题。以对如图1中(a)图所示的结构进行金属填充为例，该结构包括衬底101'、位于衬底101'表面的介质层102'，以及贯穿介质层102'并延伸至衬底101'内的孔洞20'，且该孔洞20'具有高深宽比；如图1中(b)图所示，于孔洞20'内沉积金属材料层30'时，由于孔洞20'边缘处的角度小，金属材料层30'的沉积速度快，导致孔洞20'提前封口；如图1中(c)图所示，孔洞20'内存在空洞40'。
更具体的，以对如图2中(a)图所示的结构进行金属填充为例，该结构中的孔洞20'是基于介质层102'表面的掩膜层103'而形成的，如图2中(b)图所示的步骤为去除掩膜层103'的步骤；如图2中(c)图所示，于孔洞20'内沉积金属材料层30'时，由于孔洞20'边缘处的角度小，金属材料层30'的沉积速度快，导致孔洞20'提前封口，孔洞20'内存在空洞40'；如图2中(d)图所示的步骤为去除掩膜层103'的步骤为去除位于介质层102'上的金属材料层30'，以得到位于孔洞20'内的金属层40'；所得结构中还可能具有籽晶层60'。
请参阅图3，在本公开实施例的一实施例中，提供了一种半导体结构的制备方法，包括：
步骤S10，提供基底。
步骤S20，于基底内形成环形牺牲阻挡层。
步骤S30，于基底内形成刻蚀孔，该刻蚀孔位于环形牺牲阻挡层内侧。
步骤S40，去除环形牺牲阻挡层，以得到互连孔，该互连孔上部的宽度大于互连孔下部的宽度。
具体地，请继续参阅图3，通过将互连孔上部的宽度设置为大于下部的宽度，使得互连孔在后续工艺中进行导电层填充时可以避免提前封口，从而得到无孔洞的导电结构。
作为示例，请参阅图4，在步骤S10中，基底10可以包括衬底101及位于衬底101表面的介质层102。其中，衬底101可以包括但不仅限于硅衬底、蓝宝石衬底、玻璃衬底、碳化硅衬底、氮化镓衬底或砷化镓衬底等等中的任一种；介质层102可以包括但不仅限于氧化层，譬如氧化硅层。
作为示例，衬底101包括硅衬底，介质层102包括氧化硅层。
具体地，氧化硅层生长容易，且稳定，与硅衬底具有理想的界面特性；同时，氧化硅层与硅衬底之间具有非常好的选择腐蚀比率。
对于步骤S20，请参阅图5，作为示例，步骤S20可以包括：
步骤S201，请继续参阅图4，于介质层102的表面形成第一图形化掩膜层201，第一图形化掩膜层201内具有环形开口202，环形开口202定义出环形槽203的形状及位置。
步骤S202，请参阅图6，基于第一图形化掩膜层201刻蚀介质层102，以于介质层102内形成环形槽203。
步骤S203，请继续参阅图6，去除第一图形化掩膜层201。
步骤S204，请参阅图7，于介质层102的表面形成牺牲材料层204，牺牲材料层204填满环形槽203且覆盖介质层102的表面。
步骤S205，请参阅图8，去除覆盖介质层102表面的牺牲材料层204，保留于环形槽203内的牺牲材料层204即为环形牺牲阻挡层20。
对于步骤S30，请参阅图9，作为示例，步骤S30可以包括：
步骤S301，请参阅图10，于介质层102的表面形成第二图形化掩膜层301，第二图形化掩膜层301内具有开口图形(图10中未示出)，该开口图形暴露出环形牺牲阻挡层20及环形牺牲阻挡层20内侧的介质层102。
步骤S302，请继续参阅图10，基于第二图形化掩膜层301刻蚀基底10，以形成刻蚀孔30。
步骤S303，请参阅图11所示，去除第二图形化掩膜层301。
对于步骤S40，请参阅图12，去除环形牺牲阻挡层20，以得到互连孔40；具体的，互连孔40上部的宽度大于互连孔40下部的宽度。
本公开实施例对于互连孔40上部宽度大于下部宽度的实现方式并不做具体限定，互连孔40上部的侧壁可以包括但不限于倾斜侧壁、弧形侧壁或锯齿形侧壁等等。
作为示例，互连孔40上部的侧壁为倾斜侧壁。
具体地，将互连孔40上部的侧壁设定为倾斜侧壁，能使得互连孔40边缘的到达角度较大，更利于形成无孔洞的互连结构。
可以理解，本公开实施例对于倾斜侧壁的倾斜角度并不做具体限定；作为示例，互连孔40上部的侧壁与基底10上表面的夹角为60°～80°，譬如可以是60°、65°、70°、75°或80°等等；需要说明的是，上述数据仅作为示例，在实际实施例中倾斜侧壁的倾斜角度并不以上述数据为限。
作为示例，请继续参阅图3，该制备方法在步骤S40之后还可以包括：
S60：于互连孔40内形成导电结构60，导电结构60填满互连孔40。
作为示例，请继续参阅图3，该制备方法在步骤S60之前还可以包括：
步骤S50，请继续参阅图12，至少于互连孔40的侧壁及底部形成垫氧层50；在此基础上，导电结构60可以位于垫氧层50的表面。
具体地，通过在互连孔40的侧壁及底部形成垫氧层50，垫氧层50能够在在后续工艺中对基底10的表面起到保护作用，避免基底10表面受到刻蚀工艺的损伤；同时，垫氧层50还可以在后续膜层和基底10之间起到隔离作用，避免后续膜层与基底10表面直接接触，从而为后续膜层的形成提供良好的表面，减少基底10内位错缺陷的产生。
本公开实施例对于垫氧层50的材质和结构并不做具体限定，垫氧层50可以包括但不仅限于氧化层，譬如氧化硅层；并且，本公开实施例对于垫氧层50的形成方式亦不做具体限定，形成垫氧层50的方式可以包括但不限于化学气相沉积、物理气相沉积、原子层沉积或热氧化法等等。
对于步骤S60，请参阅图13，作为示例，步骤S60可以包括：
步骤S601，请参阅图14，于垫氧层50的表面形成籽晶材料层601。
步骤S602，请继续参阅图14，于籽晶材料层601的表面形成导电材料层602，导电材料层602填满互连孔40。
步骤S603，请参阅图15，去除位于基底10上的导电材料层602及位于基底10上的籽晶材料层601，以得到位于互连孔40内的籽晶层603及导电层604；籽晶层603与导电层604共同构成导电结构60。
可以理解，本公开实施例对于导电材料层602及导电层604的材质均不做具体限定；导电材料层602及导电层604的材质均可以包括但不限于铂(P t)、金(Au)、铜(Cu)、钛(Ti)或钨(W)等等中的一种或几种。作为示例，导电材料层602包括铜层，在此基础上，导电层604也包括铜层；选用铜作为导电材料不仅能够降低成本，而且能够很好地与现有工艺相兼容，进而简化工艺过程。
作为示例，该制备方法在步骤S60之后，还可以包括对基底10进行背面减薄的步骤；可以对基底10进行背面减薄，直至暴露出导电结构60，以形成导电互连结构。
本公开实施例提供一种半导体结构。请继续参阅图15，该半导体结构可以包括基底10及互连孔40(图15中未标示出)。其中，互连孔40位于基底10内，互连孔40上部的宽度大于互连孔40下部的宽度。
具体地，互连孔上部的宽度大于下部的宽度，这样的互连孔在后续工艺中进行导电层填充时可以避免提前封口，从而得到无孔洞的导电结构。
本公开实施例对于互连孔40上部宽度大于下部宽度的实现方式并不做具体限定，互连孔40上部的侧壁可以包括但不限于倾斜侧壁、弧形侧壁或锯齿形侧壁等等。
作为示例，请继续参阅图15，互连孔40上部的侧壁为倾斜侧壁。
具体地，通过将互连孔40上部的侧壁设定为倾斜侧壁，能使得互连孔40边缘的到达角度较大，更利于形成无孔洞的互连结构。
可以理解，本公开实施例对于倾斜侧壁的倾斜角度并不做具体限定；作为示例，互连孔40上部的侧壁与基底10上表面的夹角为60°～80°，譬如可以是60°、65°、70°、75°或80°等等；需要说明的是，上述数据仅作为示例，在实际实施例中倾斜侧壁的倾斜角度并不以上述数据为限。
作为示例，请继续参阅图15，基底10可以包括衬底101及位于衬底101表面的介质层102；在此基础上，互连孔40可以贯穿介质层102并延伸至衬底101内。
作为示例，请继续参阅图15，该半导体结构还可以包括导电结构60；具体的，导电结构60填满互连孔40。
作为示例，导电结构60可以贯穿基底10，以形成导电互连结构。
对于导电结构60，请继续参阅图15，作为示例，导电结构60可以包括籽晶层603及导电层604。其中，籽晶层603位于垫氧层50的表面；导电层604位于籽晶层603的表面，且填满互连孔40。
可以理解，本公开实施例对于导电层604的材质并不做具体限定；导电层604的材质可以包括但不限于铂(Pt)、金(Au)、铜(Cu)、钛(Ti)或钨(W)等等中的一种或几种。作为示例，导电层604包括铜层；选用铜作为导电材料不仅能够降低成本，而且能够很好地与现有工艺相兼容，进而简化工艺过程。
作为示例，请继续参阅图15，该半导体结构还可以包括垫氧层50；其中，垫氧层50至少位于导电结构60与基底10之间。
具体地，导电结构60与基底10之间具有垫氧层50，垫氧层50能够在在后续工艺中对基底10的表面起到保护作用，避免基底10表面受到刻蚀工艺的损伤；同时，垫氧层50还可以在后续膜层和基底10之间起到隔离作用，避免后续膜层与基底10表面直接接触，从而为后续膜层的形成提供良好的表面，减少基底10内位错缺陷的产生。
本公开实施例对于垫氧层50的材质和结构并不做具体限定，垫氧层50可以包括但不仅限于氧化层，譬如氧化硅层、氮化硅层。
应该理解的是，虽然图3、图5、图9及图13的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图3、图5、图9及图13中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或 者阶段的至少一部分轮流或者交替地执行。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开实施例构思的前提下，还可以做出若干变形和改进，这些都属于本公开实施例的保护范围。因此，本公开实施例专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种半导体结构的制备方法，包括：
    提供基底；
    于所述基底内形成环形牺牲阻挡层；
    于所述基底内形成刻蚀孔，所述刻蚀孔位于所述环形牺牲阻挡层内侧；
    去除所述环形牺牲阻挡层，以得到互连孔，所述互连孔上部的宽度大于所述互连孔下部的宽度。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述基底包括衬底及位于所述衬底表面的介质层；所述于所述基底内形成环形牺牲阻挡层，包括：
    于所述介质层的表面形成第一图形化掩膜层，所述第一图形化掩膜层内具有环形开口，所述环形开口定义出所述环形槽的形状及位置；
    基于所述第一图形化掩膜层刻蚀所述介质层，以于所述介质层内形成所述环形槽；
    去除所述第一图形化掩膜层；
    于所述介质层的表面形成牺牲材料层，所述牺牲材料层填满所述环形槽且覆盖所述介质层的表面；
    去除覆盖所述介质层表面的所述牺牲材料层，保留于所述环形凹槽内的所述牺牲材料层即为所述环形牺牲阻挡层。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，所述于所述基底内形成刻蚀孔，包括：
    于所述介质层的表面形成第二图形化掩膜层，所述第二图形化掩膜层内具有开口图形，所述开口图形暴露出所述环形牺牲阻挡层及所述环形牺牲阻挡层内侧的所述介质层；
    基于所述第二图形化掩膜层刻蚀所述基底，以形成所述刻蚀孔；
    去除所述第二图形化掩膜层。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，所述互连孔上 部的侧壁为倾斜侧壁。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，所述互连孔上部的侧壁与所述基底上表面的夹角为60°～80°。
  6. 根据权利要求1至5中任一项所述的半导体结构的制备方法，其中，所述去除所述环形牺牲阻挡层，以得到互连孔之后，还包括：
    于所述互连孔内形成导电结构，所述导电结构填满所述互连孔。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，所述于所述互连孔内形成导电结构之前，还包括：
    至少于所述互连孔的侧壁及底部形成垫氧层；所述导电结构位于所述垫氧层的表面。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，所述于所述互连孔内形成所述导电结构之后，还包括：
    对所述基底进行背面减薄，直至暴露出所述导电结构，以形成导电互连结构。
  9. 根据权利要求7所述的半导体结构的制备方法，其中，所述垫氧层还位于所述基底的表面；所述于所述互连孔内形成导电结构，包括：
    于所述垫氧层的表面形成籽晶材料层；
    于所述籽晶材料层的表面形成导电材料层，所述导电材料层填满所述互连孔；
    去除位于所述基底上的所述导电材料层及位于所述基底上的籽晶材料层，以得到位于所述互连孔内的籽晶层及导电层，所述籽晶层与所述导电层共同构成所述导电结构。
  10. 一种半导体结构，其中，所述半导体结构包括：
    基底；
    互连孔，位于所述基底内，所述互连孔上部的宽度大于所述互连孔下部的宽度。
  11. 根据权利要求10所述的半导体结构，其中，所述基底包括：衬底及位 于所述衬底表面的介质层；所述互连孔贯穿所述介质层并延伸至所述衬底内。
  12. 根据权利要求10所述的半导体结构，其中，所述互连孔上部的侧壁为倾斜侧壁。
  13. 根据权利要求10所述的半导体结构，其中，所述互连孔上部的侧壁与所述基底上表面的夹角为60°～80°。
  14. 根据权利要求10至13中任一项所述的半导体结构，其中，还包括：导电结构，所述导电结构填满所述互连孔。
  15. 根据权利要求14所述的半导体结构，其中，还包括垫氧层，所述垫氧层至少位于所述导电结构与所述基底之间。
  16. 根据权利要求15所述的半导体结构，其中，所述导电结构包括：
    籽晶层，位于所述垫氧层的表面；
    导电层，位于所述籽晶层的表面，且填满所述互连孔。
  17. 根据权利要求15所述的半导体结构，其中，所述导电结构贯穿所述基底。
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US20050158982A1 (en) * 2004-01-19 2005-07-21 Sony Corporation Semiconductor device manufacturing method
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KR20040000700A (ko) * 2002-06-25 2004-01-07 주식회사 하이닉스반도체 반도체 소자의 층간 절연막 식각 방법
US20050158982A1 (en) * 2004-01-19 2005-07-21 Sony Corporation Semiconductor device manufacturing method
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