WO2023133942A1 - 电路分析方法、装置、电子设备和存储介质 - Google Patents

电路分析方法、装置、电子设备和存储介质 Download PDF

Info

Publication number
WO2023133942A1
WO2023133942A1 PCT/CN2022/073937 CN2022073937W WO2023133942A1 WO 2023133942 A1 WO2023133942 A1 WO 2023133942A1 CN 2022073937 W CN2022073937 W CN 2022073937W WO 2023133942 A1 WO2023133942 A1 WO 2023133942A1
Authority
WO
WIPO (PCT)
Prior art keywords
layout
environment
parasitic parameter
circuit
module
Prior art date
Application number
PCT/CN2022/073937
Other languages
English (en)
French (fr)
Inventor
尤劭
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/810,598 priority Critical patent/US20230222280A1/en
Publication of WO2023133942A1 publication Critical patent/WO2023133942A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular to a circuit analysis method, device, electronic equipment and storage medium.
  • Simulation can be divided into pre-simulation and post-simulation, and these two processes should be included in a complete circuit design.
  • Pre-simulation is functional simulation, the goal is to analyze the correctness of the logical relationship of the circuit, and the waveform of any signal and register inside the circuit can be observed as needed.
  • Pre-simulation is an ideal simulation and does not contain any physical information (such as parasitic effects, interconnection delay, etc.), and the simulation speed is fast.
  • Post-simulation is to back-mark parasitic parameters and interconnection delays into the extracted circuit netlist for simulation, analyze the circuit, and ensure that the circuit meets the design requirements.
  • Post-simulation uses the same methodology as pre-simulation, except that parasitics and interconnect delays are added. Post-simulation is much slower than pre-simulation.
  • the present disclosure provides a circuit analysis method, device, electronic equipment and storage medium.
  • an embodiment of the present disclosure provides a circuit analysis device, including: an information module configured to obtain multiple layout units; an environment configuration module configured to set corresponding layouts one by one based on the type and/or parameters of the layout units A parasitic parameter extraction environment; a batch processing module configured to extract a plurality of parasitic parameter netlists of the layout units in batches under the layout parasitic parameter extraction environment.
  • an embodiment of the present disclosure provides a circuit analysis method, the method comprising: acquiring a plurality of layout units; setting corresponding layout parasitic parameter extraction environments one by one based on the types and/or parameters of the layout units; The parasitic parameter netlists of multiple layout units are extracted in batches under the layout parasitic parameter extraction environment.
  • an embodiment of the present disclosure provides an electronic device, including: a memory configured to store a computer program; a processor configured to execute the computer program in the memory, so as to implement any one of the methods described in the second aspect Steps.
  • an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the operation steps of any one of the methods described in the second aspect are implemented.
  • the disclosed solution can provide an environment configuration module to set corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters, and then extract multiple parasitic netlists of the layout units in batches.
  • the parasitic netlists of multiple layout units can also be extracted in batches in an automatically set environment without the need for the user to perform complex environment settings manually.
  • the time for parasitic parameter extraction can be greatly reduced, thereby shortening the time required for post-circuit simulation.
  • FIG. 1 is a schematic diagram of a program module of a circuit analysis device provided in an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a circuit analysis process provided in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of an implementation flow of a circuit analysis method provided by an embodiment of the present disclosure
  • Fig. 4 is a schematic diagram of the implementation flow of a parasitic parameter extraction method provided by a specific example of the present disclosure
  • Fig. 5 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of program modules of a circuit analysis device provided in an embodiment of the present disclosure.
  • the unit includes:
  • An information module 110 configured to acquire multiple layout units
  • the environment configuration module 120 is configured to set a corresponding layout parasitic parameter extraction (Layout Parasitic Extraction, LPE) environment one by one based on the type and/or parameters of the layout unit;
  • LPE layout parasitic parameter extraction
  • the batch processing module 130 is configured to extract the parasitic netlists of multiple layout units in batches under the layout parasitic parameter extraction environment.
  • the solutions of the embodiments of the present disclosure can provide an environment configuration module to set corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters, and then extract multiple parasitic netlists of the layout units in batches.
  • the parasitic netlists of multiple layout units can also be extracted in batches under the automatically set layout parasitic parameter extraction environment without the need for the user to perform complex environment settings manually.
  • the time for parasitic parameter extraction can be greatly reduced, thereby shortening the time required for post-circuit simulation.
  • FIG. 2 is a schematic diagram of a circuit analysis process provided in the embodiment of the present disclosure.
  • the circuit layout includes a plurality of layout units A, B, C and D
  • the circuit schematic diagram includes a plurality of circuit units A', B', C' and D' corresponding to the plurality of layout units.
  • the parasitic parameter netlist is actually flattened and has no hierarchical structure.
  • the cell hierarchy in the figure is only for describing its logical structure.
  • both circuit units and layout units are acquired by the information module 110 in batches.
  • the batch processing module 130 includes an export module 131 configured to batch export GDS files of layout units in a GDS export environment and export circuit netlists of circuit units in batches in a netlist export environment.
  • an export module 131 configured to batch export GDS files of layout units in a GDS export environment and export circuit netlists of circuit units in batches in a netlist export environment.
  • both the GDS export environment and the netlist export environment are set by the environment configuration module 120 based on layout unit types and/or parameters.
  • the GDS file is a file in Graphic Data System (GDS) format.
  • GDS Graphic Data System
  • the export module 131 may include a layout export module 1311 and a netlist export module 1312; the layout export module 1311 is configured to export the GDS files of layout units in batches under the GDS export environment, and the netlist export module 1312 is configured to In the netlist export environment, export the circuit netlist of the circuit unit in batches.
  • the GDS file of the layout unit represents the designed integrated circuit layout, which contains the physical information of each device or hardware unit of the designed integrated circuit.
  • the physical information can be the shape of each device or hardware unit on the chip. , area and position information;
  • the circuit netlist corresponding to the circuit unit represents a text file describing the logical information between circuit components, that is, the connection relationship between circuit components, which contains the relationship between each device unit of the designed integrated circuit connection line information.
  • the information module 110 can acquire multiple layout units at a time.
  • the information module 110 can acquire layout units in batches, and then the environment configuration module 120 sets corresponding layout parasitic parameter extraction environments for the multiple layout units one by one, and batch processing
  • the module 130 simultaneously extracts the parasitic parameter netlists of multiple layout units in batches under the layout parasitic parameter extraction environment set by the environment configuration module 120 .
  • the information module 110 can acquire multiple layout units at a time, in other words, the information module 110 can acquire layout units in batches. Then the environment configuration module 120 sets corresponding layout parasitic parameter extraction environment for multiple layout units one by one, and the batch processing module 130 extracts the parasitic parameter netlist of the corresponding layout unit one by one under the layout parasitic parameter extraction environment set by the environment configuration module 120.
  • the environment configuration unit 120 is also configured to set a verification environment
  • the batch processing module 130 also includes a verification module 132
  • the verification module 132 is configured to perform layout based on the GDS file and the circuit netlist under the verification environment Compare circuit verification (Layout versus schematic, LVS).
  • the main function of the layout comparison circuit verification is to verify whether the integrated circuit layout and the circuit schematic diagram, that is, the circuit structure of the circuit netlist, are consistent, and the obtained GDS file and the circuit netlist are input into the verification module 132, and the verification module 132
  • the consistency of the circuit structure between the GDS file and the circuit netlist will be verified and in this process the verification module 132 will establish a corresponding relationship between the physical information in the GDS file and the logical information in the circuit netlist, and verify
  • the module 132 will output the verification result and a data file with a one-to-one correspondence between physical information and logical information.
  • the layout comparison circuit verification result includes verification results and data files.
  • the verification results in the embodiments of the present disclosure include verification pass and verification failure; verification pass indicates that the circuit structure of the GDS file and circuit netlist in LVS verification is correct, and verification failure indicates that the circuit structure of the GDS file and circuit netlist in LVS verification is incorrect.
  • the data file output by the verification module 132 in the embodiment of the present disclosure is a data file obtained when the verification is passed, and the data file includes the physical information of each device unit and its corresponding connection line information.
  • the batch processing module 130 includes a parasitic parameter extraction module 133 configured to batch extract a plurality of parasitic parameter netlists of the layout units under the layout parasitic parameter extraction environment.
  • the parasitic parameter extraction module 133 of the disclosed embodiment only extracts the parasitic parameter netlist of the layout unit whose circuit structure is correct in the LVS verification GDS file and netlist.
  • Geometric elements define the shapes that will be created in various materials to manufacture integrated circuits.
  • groups of geometric elements representing circuit device components such as contacts, gates, etc., are selected and placed in the design area. These sets of geometric elements may be custom designed, selected from a library of previously created designs, or some combination of the two.
  • geometrical elements representing connection lines are then placed between these geometrical elements according to a predetermined route. These connecting lines will form the wiring for interconnecting electronic devices.
  • extensive analysis will be performed on the final layout of the integrated circuit.
  • a layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the logical design of the integrated circuit.
  • Layout designs can also be analyzed to confirm compliance with various design requirements, such as minimum spacing between geometric elements.
  • the layout design can be modified to include the use of redundant geometrical elements or to add corrective features to various geometrical elements, to offset limitations in the manufacturing process, etc.
  • the layout design can be analyzed to determine parasitic parameter values of nets in the layout design, such as parasitic capacitance, parasitic resistance, parasitic inductance, etc., which can be used to determine whether the layout design includes voltage drops, signal delays, or signal noise.
  • the parasitic parameter is extracted according to the data file output by the verification module 132, and then the parasitic parameter netlist corresponding to the designed integrated circuit is obtained, and the parasitic parameter netlist contains a plurality of parasitic parameter information, wherein the plurality of parasitic parameter information It may include the parasitic parameter information corresponding to each device unit and/or the parasitic parameter information of each connecting line (wire), the parasitic parameter information corresponding to each device unit or wire may be one or more, and the parasitic parameter information includes The properties of parasitic parameters (such as parasitic resistance, parasitic capacitance or parasitic inductance), also includes parasitic parameter values, such as (parasitic resistance value, parasitic capacitance value and parasitic inductance value), wherein, in the parasitic parameter netlist, each device A cell or line is associated with its corresponding parasitic properties and parasitic values.
  • the parasitic parameter may be a parasitic parameter in a standard parasitic file (Standard Parasitic File, SPF) format.
  • the environment configuration module 120 communicates with at least one electronic design automation (Electronic Design Automation, EDA) software, and the environment configuration module 120 performs GDS export environment, netlist export environment, Automatic configuration of verification environment and layout parasitic extraction environment.
  • EDA Electronic Design Automation
  • the environment configuration module 120 communicates with a plurality of different types of EDA software, and the environment configuration module 120 automatically configures different types of GDS export environments and netlist export environments by calling interfaces of different EDA software , verification environment and layout parasitic parameter extraction environment.
  • EDA electronic design automation
  • integrated circuit design the connection relationship between various components of the circuit can be detected by EDA, so as to test and verify whether the integrated circuit works correctly.
  • the environment configuration module in the embodiment of the present disclosure can automatically configure the environment in the parasitic parameter extraction process (including GDS export environment, netlist export environment, verification environment and layout parasitic parameter extraction environment) based on the type and/or parameters of the layout unit , without requiring manual configuration by the user.
  • the parasitic parameter extraction process including GDS export environment, netlist export environment, verification environment and layout parasitic parameter extraction environment
  • the circuit analysis device further includes: a result output module 140 configured to generate a report corresponding to the layout unit according to the LVS result and the parasitic parameter netlist.
  • the report extracts the batch processing results of all layout units, including the error type and number of verification failures, and the parasitic parameter netlist, etc., and presents it to the user in a visual way.
  • the LVS verification of layout units A, C, and D passes, while the LVS verification of layout unit B fails, and the LVS verification passed is extracted.
  • Parasitic parameters of layout cells A, C, and D to obtain a netlist of parasitic parameters of layout cells A, C, and D.
  • a report corresponding to the layout unit is generated according to the LVS result and the parasitic parameter netlist.
  • the circuit analysis device further includes: a simulation module 150 configured to perform post-simulation according to the parasitic parameter netlist.
  • post-simulation refers to back-marking the parasitic parameters in the parasitic parameter netlist, such as parasitic resistance, parasitic capacitance or parasitic inductance, into the extracted circuit netlist for simulation, and analyzing the integrated circuit to ensure that the integrated circuit conforms to the design Require.
  • the information module 110 has a graphical user interface (Graphical User Interface, GUI), configured to acquire the layout unit.
  • GUI graphical User Interface
  • the circuit analysis device can rapidly and batchly extract the parasitic parameters of multiple layout units included in the specified information, and obtain the parasitic parameter netlist, and then according to The parasitic parameter netlist is subjected to post-batch simulation.
  • the solutions of the embodiments of the present disclosure can provide an environment configuration module to set corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters, and then extract multiple parasitic netlists of the layout units in batches.
  • the parasitic netlists of multiple layout units can also be extracted in batches in an automatically set environment without the need for the user to perform complex environment settings manually.
  • the time for parasitic parameter extraction can be greatly reduced, thereby shortening the time required for post-circuit simulation.
  • the exemplary solutions or techniques of the embodiments of the present disclosure can be applied to the layout of integrated circuits of memory, where the memory can be a volatile memory, such as a dynamic random access memory DRAM, and the memory can also be a nonvolatile memory, such as a read-only memory Memory (ROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), Magnetic Resistive Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Ferroelectric Random Access Memory (FRAM), etc.
  • ROM read-only memory Memory
  • PROM Programmable Read Only Memory
  • EPROM Erasable Programmable Read Only Memory
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • PRAM Phase Change Random Access Memory
  • MRAM Magnetic Resistive Random Access Memory
  • RRAM Resistive Random Access Memory
  • FRAM Ferroelectric Random Access Memory
  • FIG. 3 is a schematic diagram of the implementation flow of a circuit analysis method provided by an embodiment of the present disclosure. As shown in FIG. 3 , the circuit analysis method includes the following steps:
  • Step 310 Obtain multiple layout units
  • Step 320 Set corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters;
  • Step 330 Batch extract the parasitic parameter netlists of multiple layout cells under the layout parasitic parameter extraction environment.
  • setting the corresponding layout parasitic parameter extraction environment one by one based on the type and/or parameters of the layout unit includes: performing automatic configuration of the layout parasitic parameter extraction environment by calling the interface of EDA software.
  • setting corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters includes: automatically configuring different types of layout parasitic parameter extraction environments by calling interfaces of different EDA software.
  • the circuit analysis method before extracting the parasitic parameter netlists of multiple layout cells in batches under the layout parasitic parameter extraction environment, the circuit analysis method further includes:
  • setting corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters includes: setting a netlist export environment;
  • Acquiring a plurality of layout units includes: acquiring circuit units corresponding to the layout units;
  • the method further includes: exporting circuit netlists of circuit units in batches under a netlist exporting environment.
  • setting corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters includes: setting a verification environment;
  • the circuit analysis method also includes: under the verification environment, performing layout comparison and circuit verification based on the GDS file and the circuit netlist.
  • the circuit analysis method further includes: generating a report corresponding to the layout unit according to the verification result of the layout comparison circuit verification and the parasitic parameter netlist.
  • the circuit analysis method further includes: a simulation module configured to perform post-simulation according to the parasitic parameter netlist.
  • Fig. 4 is a schematic flow diagram of a parasitic parameter extraction method provided in a specific example of the present disclosure. As shown in Fig. 4, the method includes the following steps:
  • Step 410 Obtain specified information input by the user from the graphical interactive interface
  • the specified information includes a layout unit list, a layout library, a circuit library, and the like.
  • the layout unit list includes information of multiple layout units. After obtaining the layout cell list from the graphical interactive interface, obtain the corresponding layout cell from the layout library based on the information (such as ID) of each layout cell in the layout cell list, and obtain the correspondence of multiple layout cells from the circuit library. multiple circuit units.
  • Step 420 Set the GDS export environment, and export the GDS files of the layout units in batches under the GDS export environment;
  • multiple layout units in the layout unit list can be processed one by one, multiple layout units in the layout unit list can also be processed in batches, and multiple layout units in the layout unit list can also be processed Simultaneous batch processing.
  • the GDS file of the layout unit represents the designed integrated circuit layout, which contains the physical information of each device or hardware unit of the designed integrated circuit.
  • the physical information can be the shape of each device or hardware unit on the chip. , area and location information.
  • Step 430 Set the netlist export environment, and export the circuit netlist of the circuit unit in batches under the netlist export environment;
  • Step 440 judging whether the GDS file and the circuit netlist are successfully exported
  • the circuit netlist corresponding to the circuit unit represents a text file describing the logic information between the circuit components, that is, the connection relationship between the circuit components, which contains the connection line information between the various device units of the designed integrated circuit .
  • step 450 if the judgment result is that the GDS file and the circuit netlist are exported successfully, then step 450 is performed; if the judgment result is that the GDS file and the circuit netlist are not successfully exported, then step 480 is performed.
  • Step 450 Set up a verification environment, and perform LVS verification based on the GDS file and the circuit netlist in the verification environment;
  • Step 460 Determine whether the LVS verification is passed
  • the main function of LVS verification is to verify whether the circuit structure of the integrated circuit layout and the circuit schematic diagram, that is, the circuit netlist, are consistent, and to verify the consistency of the obtained GDS file and the circuit structure of the circuit netlist, and in the process Establish a one-to-one correspondence between the physical information in the GDS file and the logical information in the circuit netlist, and output the verification result and the data file with the one-to-one correspondence between the physical information and the logical information after the verification is completed.
  • the layout comparison circuit verification result includes verification results and data files.
  • the verification results in the embodiments of the present disclosure include verification pass and verification failure; verification pass indicates that the circuit structure of the GDS file and circuit netlist in LVS verification is correct, and verification failure indicates that the circuit structure of the GDS file and circuit netlist in LVS verification is incorrect.
  • step 470 if the judging result is that the LVS verification is passed, then step 470 is executed; if the judging result is that the LVS verification is not passed, then step 480 is executed.
  • Step 470 Set the layout parasitic parameter extraction environment, and extract the parasitic parameter netlist of the layout unit under the layout parasitic parameter extraction environment; here, perform parasitic parameter extraction on the layout unit, and then obtain the parasitic parameter netlist corresponding to the designed integrated circuit, the
  • the parasitic parameter netlist contains a plurality of parasitic parameter information, wherein the plurality of parasitic parameter information may include the parasitic parameter information corresponding to each device unit and/or the parasitic parameter information of each connecting line (wire), each device
  • the parasitic parameter information corresponding to the unit or wire can be one or more, and the parasitic parameter information includes the attribute of the parasitic parameter (such as parasitic resistance or parasitic capacitance), and also includes the value of the parasitic parameter, such as (parasitic resistance value and parasitic capacitance value ), wherein, in the parasitic parameter netlist, each device unit or circuit is associated with its corresponding parasitic parameter attribute and parasitic parameter value.
  • Step 480 Determine whether all the layout units in the layout unit list have been processed
  • step 490 if the judgment result is that all the layout units in the layout unit list have been processed, execute step 490; if the judgment result is that all the layout units in the layout unit list have not been processed, execute step 420 to continue Unprocessed layout cells in the cell list are processed.
  • Step 490 Generate a report corresponding to the layout unit according to the LVS result and the parasitic parameter netlist.
  • the report extracts batch processing results of all layout units, including error types and numbers of verification failures, parasitic parameter netlists, etc., and presents them to the user in a visualized manner.
  • the parasitic parameter extraction method provided in the embodiments of the present disclosure can extract the parasitic parameters of multiple layout units in batches, and can also be based on the type and/or parameters of the layout units in each process (GDS export, netlist export, LVS verification and Layout parasitic parameter extraction) set the corresponding environment one by one, without manual setting by the user.
  • Each module in the above-mentioned circuit analysis device can be fully or partially realized by software, hardware and a combination thereof.
  • the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, and can also be stored in the memory of the computer device in the form of software, so that the processor can invoke and execute the corresponding operations of the above-mentioned modules.
  • FIG. 5 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • the electronic device in the embodiments of the present disclosure includes a memory for storing computer programs; a processor for executing the computer programs in the memory to implement each of the circuit analysis methods described in the above embodiments Steps, for details, refer to the related descriptions in the foregoing method embodiments, which will not be repeated in this embodiment.
  • the memory can be independent or integrated with the processor.
  • the device further includes a bus for connecting the memory and the processor.
  • the embodiments of the present disclosure also provide a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions,
  • the computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions,
  • various parts of the present disclosure may be implemented in hardware, software, firmware or a combination thereof.
  • various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system.
  • a suitable instruction execution system For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques known in the art: Discrete logic circuits, ASICs with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing module, each unit may exist separately physically, or two or more units may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are realized in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.
  • the storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, and the like.
  • the solution of the present disclosure can provide an environment configuration module to set corresponding layout parasitic parameter extraction environments one by one based on layout unit types and/or parameters, and then extract multiple parasitic netlists of the layout units in batches.
  • the parasitic netlists of multiple layout units can also be extracted in batches in an automatically set environment without the need for the user to perform complex environment settings manually.
  • the time for parasitic parameter extraction can be greatly reduced, thereby shortening the time required for post-circuit simulation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

一种电路分析方法、装置、电子设备和存储介质，所述电路分析装置包括：信息模块（110），配置为获取多个版图单元；环境配置模块（120），配置为基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境；批量处理模块（130），配置为在所述版图寄生参数提取环境下批量提取多个所述版图单元的寄生参数网表。

Description

电路分析方法、装置、电子设备和存储介质
相关申请的交叉引用
本公开基于申请号为202210031057.2、申请日为2022年1月12日、发明名称为“电路分析方法、装置、电子设备和存储介质”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种电路分析方法、装置、电子设备和存储介质。
背景技术
仿真可以分为前仿真和后仿真，在一个完整的电路设计中应该包括这两个过程。
前仿真是功能仿真，目标是分析电路的逻辑关系的正确性，可以根据需要观察电路输入输出端口和电路内部任一信号和寄存器的波形。前仿真是比较理想的仿真，并不包含任何物理信息(如寄生效应、互连延迟等)，仿真速度快。
后仿真是将寄生参数、互连延迟反标到所提取的电路网表中进行仿真，对电路进行分析，确保电路符合设计要求。后仿真所使用的方法与前仿真并没有什么不同，只是加入寄生参数以及互连延迟。后仿真的速度相对于前仿真慢得多。
相关技术中，随着集成电路规模的不断增大，芯片上晶体管的数量不断增加，这导致寄生电阻和电容的数目急剧膨胀，电路后仿真中所需要的时间随之增加，电路验证时间越来越长，一定程度上影响了芯片的设计周 期和产品交付时间。
发明内容
为至少在一定程度上克服相关技术中存在的问题，本公开提供一种电路分析方法、装置、电子设备和存储介质。
第一方面，本公开实施例提供一种电路分析装置，包括：信息模块，配置为获取多个版图单元；环境配置模块，配置为基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境；批量处理模块，配置为在所述版图寄生参数提取环境下批量提取多个所述版图单元的寄生参数网表。
第二方面，本公开实施例提供一种电路分析方法，所述方法包括：获取多个版图单元；基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境；在所述版图寄生参数提取环境下批量提取多个所述版图单元的寄生参数网表。
第三方面，本公开实施例提供一种电子设备，包括：存储器，用于存储计算机程序；处理器，用于执行所述存储器中的计算机程序，以实现第二方面任一项所述方法的操作步骤。
第四方面，本公开实施例提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现第二方面任一项所述方法的操作步骤。
本公开的方案能够提供环境配置模块，以基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，进而批量提取多个所述版图单元的寄生网表。如此，无需用户手动进行复杂的环境设置，也可以在自动设置的环境下批量提取多个所述版图单元的寄生网表。这样就能够大大减少寄生参数提取的时间，从而缩短电路后仿真所需要的时间。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本公开的一些实施方式，而不应将其视为是对本公开范围的限制。
图1是本公开实施例中提供的一种电路分析装置的程序模块示意图；
图2是本公开实施例中提供的电路分析流程的示意图；
图3是本公开实施例提供的一种电路分析方法的实现流程示意图；
图4是本公开一具体示例提供的一种寄生参数提取方法的实现流程示意图；
图5是本公开实施例提供的一种电子设备的硬件结构示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执 行的顺序有可能根据实际情况改变。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
图1是本公开实施例中提供的一种电路分析装置的程序模块示意图。该装置包括：
信息模块110，配置为获取多个版图单元；
环境配置模块120，配置为基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取(Layout Parasitic Extraction，LPE)环境；
批量处理模块130，配置为在版图寄生参数提取环境下批量提取多个版图单元的寄生网表。
本公开实施例的方案能够提供环境配置模块，以基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，进而批量提取多个所述版图单元的寄生网表。如此，无需用户手动进行复杂的环境设置，也可以在自动设置的版图寄生参数提取环境下批量提取多个所述版图单元的寄生网表。这样就能够大大减少寄生参数提取的时间，从而缩短电路后仿真所需要的时间。
为了更好的理解本公开实施例，参照图2，图2是本公开实施例中提供的电路分析流程的示意图。在图2中，电路版图包括多个版图单元A、B、C和D，而电路原理图包括多个版图单元对应的多个电路单元A’、B’、C’和D’。需要说明的是，寄生参数网表实际上被扁平化，无层次结构，图中的单元层次仅仅为了描述其逻辑结构。这里，电路单元和版图单元均由信 息模块110批量获取。
在一些实施例中，批量处理模块130包括导出模块131，导出模块131配置为在GDS导出环境下批量导出版图单元的GDS文件以及在网表导出环境下批量导出电路单元的电路网表。这里，GDS导出环境和网表导出环境均由环境配置模块120基于版图单元的类型和/或参数进行设置。这里，GDS文件为图形数据系统(Graphic Data System，GDS)格式的文件。
在另一些实施例中，导出模块131可以包括版图导出模块1311和网表导出模块1312；版图导出模块1311配置为在GDS导出环境下批量导出版图单元的GDS文件，网表导出模块1312配置为在网表导出环境下批量导出电路单元的电路网表。
这里，版图单元的GDS文件表示设计的集成电路版图，该集成电路版图中包含了设计的集成电路的各个器件或硬件单元的物理信息，该物理信息可以为各器件或硬件单元在芯片上的形状、面积和位置信息；电路单元对应的电路网表表示的是描述电路元件之间的逻辑信息即电路元件互相之间的连接关系的文本文件，其中包含有设计的集成电路的各个器件单元之间的连接线路信息。
在一些实施例中，信息模块110一次可以获取多个版图单元，换言之，信息模块110可批量获取版图单元，而后环境配置模块120对多个版图单元逐一设置对应的版图寄生参数提取环境，批量处理模块130则在环境配置模块120设置的版图寄生参数提取环境下同时批量提取多个所述版图单元的寄生参数网表。
在另一些实施例中，信息模块110一次可以获取多个版图单元，换言之，信息模块110可批量获取版图单元。而后环境配置模块120对多个版图单元逐一设置对应的版图寄生参数提取环境，批量处理模块130则在环境配置模块120设置的版图寄生参数提取环境下逐一提取对应的版图单元的寄生参数网表。
在一些实施例中，环境配置单元120还配置为设置验证环境，批量处理模块130还包括验证模块132，验证模块132配置为在验证环境下，基于所述GDS文件和所述电路网表进行版图对比电路验证(Layout versus schematic，LVS)。
这里，版图对比电路验证的主要作用是验证集成电路版图与电路原理图也就是电路网表的电路结构是否一致，将获取到的GDS文件和电路网表输入该验证模块132中，该验证模块132会对GDS文件和电路网表的电路结构一致性进行验证并且在这个过程中验证模块132会将GDS文件中的物理信息和电路网表中的逻辑信息一一建立对应关系，在验证完毕之后验证模块132会将验证结果和具有物理信息和逻辑信息一一对应关系的数据文件进行输出。这里，版图对比电路验证结果(LVS结果)包括验证结果和数据文件。
本公开实施例中的验证结果包括验证通过和验证失败；验证通过表示LVS验证中GDS文件和电路网表的电路结构无误，验证失败表示LVS验证GDS文件和电路网表的电路结构有误。在这里需要说明的是，本公开实施例中验证模块132输出的数据文件是在验证通过的情况下获取的数据文件，数据文件包括有每一器件单元的物理信息和其对应的连接线路信息。
在本公开实施例中，批量处理模块130包括寄生参数提取模块133，寄生参数提取模块133配置为在所述版图寄生参数提取环境下批量提取多个所述版图单元的寄生参数网表。
需要说明的是，本公开实施例的寄生参数提取模块133基于验证模块132输出的验证结果和数据文件，仅提取LVS验证GDS文件和网表的电路结构无误的版图单元的寄生参数网表。
在制造集成电路的设计流程中，集成电路的物理设计可以描述特定的几何元件，通常称为“版图”设计。几何元件定义了将在各种材料中创建以制造集成电路的形状。通常，将选择代表电路器件组件的几何元件组， 例如触点、栅极等，并将它们放置在设计区域中。这些几何元件组可以是定制设计的、从先前创建的设计库中选择的，或者两者的某种组合。一旦放置了代表电路设备组件的几何元件组，然后根据预定路线将代表连接线的几何元件放置在这些几何元件之间。这些连接线路将形成用于互连电子设备的布线。通常，将对集成电路的最终版图设计进行大量分析。例如，可以分析版图设计以确认它准确地表示了集成电路的逻辑设计中所描述的电路器件及其关系。还可以分析版图设计以确认其符合各种设计要求，例如几何元件之间的最小间距。更进一步地，版图设计可以被修改以包括使用冗余几何元件或向各种几何元件添加校正特征，以抵消制造过程中的限制等。在物理设计分析期间，可以分析版图设计以确定版图设计中的网络的寄生参数值，例如寄生电容、寄生电阻、寄生电感等，其可用于确定版图设计是否包括电压降、信号延迟或信号噪声。
这里，根据验证模块132输出的数据文件进行寄生参数提取，然后得到设计的集成电路对应的寄生参数网表，该寄生参数网表中包含有多个寄生参数信息，其中，该多个寄生参数信息可包括每一器件单元对应的寄生参数信息和/或每一连接线路(导线)的寄生参数信息，每一器件单元或导线对应的寄生参数信息可为一个或多个，寄生参数信息中包含有寄生参数的属性(例如寄生电阻、寄生电容或寄生电感)，还包含有寄生参数值，例如(寄生电阻值、寄生电容值和寄生电感值)，其中，在寄生参数网表中，每一器件单元或线路与其对应的寄生参数的属性和寄生参数值是关联的。这里，寄生参数可以为标准寄生文件(Standard Parasitic File，SPF)格式的寄生参数。
在一些实施例中，环境配置模块120与至少一个电子设计自动化(Electronic Design Automation，EDA)软件连通，所述环境配置模块120通过调用所述EDA软件的接口进行GDS导出环境、网表导出环境、验证环境和版图寄生参数提取环境的自动配置。
在一些实施例中，环境配置模块120与多个类型不同的所述EDA软件连通，所述环境配置模块120通过调用不同所述EDA软件的接口自动配置不同类型的GDS导出环境、网表导出环境、验证环境和版图寄生参数提取环境。
这里，电子设计自动化意指使用计算机来设计及仿真集成电路上的电子电路的性能，EDA可用于处理苛求复杂的半导体集成电路设计工作。在集成电路设计中，可以通过EDA检测出电路各部件之间的连接关系，从而测试验证该集成电路是否正确地工作。
本公开实施例中的环境配置模块可以基于版图单元的类型和/或参数对寄生参数提取过程中的环境(包括GDS导出环境、网表导出环境、验证环境和版图寄生参数提取环境)进行自动配置，而无需用户手动配置。
在一些实施例中，电路分析装置还包括：结果输出模块140，配置为根据LVS结果和所述寄生参数网表生成对应所述版图单元的报表。该报表提取所有版图单元的批量处理结果，包括验证失败的错误类型、数目以及寄生参数网表等，并以可视化的方式呈现给用户。
参照图2，经过本公开实施例提供的电路分析装置对多个版图单元进行批量处理后，版图单元A、C、D的LVS验证通过，而版图单元B的LVS验证失败，提取LVS验证通过的版图单元A、C、D的寄生参数，以得到版图单元A、C、D的寄生参数网表。最终根据LVS结果和寄生参数网表生成对应所述版图单元的报表。需要说明的是，对于验证失败的版图单元，则需要版图工程师对版图单元进行修正。
在一些实施例中，电路分析装置还包括：仿真模块150，配置为根据所述寄生参数网表进行后仿真。
这里，后仿真指的是将寄生参数网表中的寄生参数，例如寄生电阻、寄生电容或寄生电感反标到所提取的电路网表中进行仿真，对集成电路进行分析，确保集成电路符合设计要求。
在一些实施例中，信息模块110具有图形化交互界面(Graphical User Interface，GUI)，以配置为获取所述版图单元。本公开实施例中用户通过图形化交互界面输入指定信息后，电路分析装置即可快速批量地对指定信息中包括的多个版图单元进行批量的寄生参数提取，并得到寄生参数网表，再根据所述寄生参数网表进行批量后仿真。
本公开实施例的方案能够提供环境配置模块以基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，进而批量提取多个所述版图单元的寄生网表。如此，无需用户手动进行复杂的环境设置，也可以在自动设置的环境下批量提取多个所述版图单元的寄生网表。这样就能够大大减少寄生参数提取的时间，从而缩短电路后仿真所需要的时间。
本公开实施例的示例方案或技术可以应用至存储器的集成电路版图，这里的存储器可以是易失性存储器，例如，动态随机存取存储器DRAM，存储器也可以是非易失性存储器，例如，只读存储器(ROM)、可编程只读存储器(PROM)、可擦除可编程只读存储器(EPROM)、电可擦除可编程只读存储器(EEPROM)、相变随机存取存储器(PRAM)、磁电阻式随机存取存储器(MRAM)、电阻式随机存取存储器(RRAM)、铁电随机存取存储器(FRAM)等。
基于上述电路分析装置，本公开实施例还提供一种电路分析方法，图3是本公开实施例提供的一种电路分析方法的实现流程示意图，如图3所示，电路分析方法包括如下步骤：
步骤310：获取多个版图单元；
步骤320：基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境；
步骤330：在版图寄生参数提取环境下批量提取多个版图单元的寄生参数网表。
在一些实施例中，基于版图单元的类型和/或参数逐一设置对应的版图 寄生参数提取环境，包括：通过调用EDA软件的接口进行版图寄生参数提取环境的自动配置。
在一些实施例中，基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，包括：通过调用不同EDA软件的接口自动配置不同类型的版图寄生参数提取环境。
在一些实施例中，在在版图寄生参数提取环境下批量提取多个版图单元的寄生参数网表之前，电路分析方法还包括：
设置GDS导出环境，在GDS导出环境下批量导出版图单元的GDS文件。
在一些实施例中，基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，包括：设置网表导出环境；
获取多个版图单元，包括：获取所述版图单元对应的电路单元；
所述方法还包括：在网表导出环境下批量导出电路单元的电路网表。
在一些实施例中，基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，包括：设置验证环境；
电路分析方法还包括：在验证环境下，基于GDS文件和电路网表进行版图对比电路验证。
在一些实施例中，电路分析方法还包括：根据版图对比电路验证的验证结果和寄生参数网表生成对应版图单元的报表。
在一些实施例中，电路分析方法还包括：仿真模块，配置为根据寄生参数网表进行后仿真。
关于上述实施例中的电路分析方法，其中各个步骤中执行操作的具体步骤已经在有关该电路分析装置的实施例中进行了详细描述，此处不再详细阐述说明。
图4是本公开一具体示例提供的一种寄生参数提取方法的实现流程示意图，如图4所示，所述方法包括如下步骤：
步骤410：从图形化交互界面中获取用户输入的指定信息；
本公开实施例中，指定信息包括版图单元列表、版图库和电路库等。版图单元列表中包括多个版图单元的信息。从图形化交互界面中获取版图单元列表后，基于该版图单元列表中的各个版图单元的信息(例如标识ID)从版图库中获取对应的版图单元，并从电路库中获取多个版图单元对应的多个电路单元。
步骤420：设置GDS导出环境，在GDS导出环境下批量导出版图单元的GDS文件；
本公开实施例中，可以对版图单元列表中的多个版图单元进行逐一处理，也可以对版图单元列表中的多个版图单元进行分批处理，还可以版图单元列表中的多个版图单元进行同时批量处理。
这里，版图单元的GDS文件表示设计的集成电路版图，该集成电路版图中包含了设计的集成电路的各个器件或硬件单元的物理信息，该物理信息可以为各器件或硬件单元在芯片上的形状、面积和位置信息。
步骤430：设置网表导出环境，在网表导出环境下批量导出电路单元的电路网表；
步骤440：判断是否成功导出GDS文件和电路网表；
这里，电路单元对应的电路网表表示的是描述电路元件之间的逻辑信息即电路元件互相之间的连接关系的文本文件，其中包含有设计的集成电路的各个器件单元之间的连接线路信息。
本公开实施例中，若判断结果为成功导出GDS文件和电路网表，则执行步骤450；若判断结果为未成功导出GDS文件和电路网表，则执行步骤480。
步骤450：设置验证环境，在验证环境下基于GDS文件和电路网表进行LVS验证；
步骤460：判断LVS验证是否通过；
这里，LVS验证的主要作用是验证集成电路版图与电路原理图也就是电路网表的电路结构是否一致，对获取到的GDS文件和电路网表的电路结构一致性进行验证，并且在这个过程中将GDS文件中的物理信息和电路网表中的逻辑信息一一建立对应关系，在验证完毕之后验将验证结果和具有物理信息和逻辑信息一一对应关系的数据文件进行输出。这里，版图对比电路验证结果(LVS结果)包括验证结果和数据文件。
本公开实施例中的验证结果包括验证通过和验证失败；验证通过表示LVS验证中GDS文件和电路网表的电路结构无误，验证失败表示LVS验证GDS文件和电路网表的电路结构有误。
本公开实施例中，若判断结果为LVS验证通过，则执行步骤470；若判断结果为LVS验证未通过，则执行步骤480。
步骤470：设置版图寄生参数提取环境，在版图寄生参数提取环境下提取版图单元的寄生参数网表；这里，对版图单元进行寄生参数提取，然后得到设计的集成电路对应的寄生参数网表，该寄生参数网表中包含有多个寄生参数信息，其中，该多个寄生参数信息可包括每一器件单元对应的寄生参数信息和/或每一连接线路(导线)的寄生参数信息，每一器件单元或导线对应的寄生参数信息可为一个或多个，寄生参数信息中包含有寄生参数的属性(例如寄生电阻或寄生电容)，还包含有寄生参数值，例如(寄生电阻值和寄生电容值)，其中，在寄生参数网表中，每一器件单元或线路与其对应的寄生参数的属性和寄生参数值是关联的。
步骤480：判断版图单元列表中的版图单元是否全部处理完毕；
本公开实施例中，若判断结果为版图单元列表中的版图单元全部处理完毕，则执行步骤490；若判断结果为版图单元列表中的版图单元未全部处理完毕，则执行步骤420，继续对版图单元列表中未处理的版图单元进行处理。
步骤490：根据LVS结果和寄生参数网表生成对应版图单元的报表。
本公开实施例中，该报表提取所有版图单元的批量处理结果，包括验证失败的错误类型、数目以及寄生参数网表等，并以可视化的方式呈现给用户。
关于上述实施例中的寄生参数提取方法，其中各个步骤中执行操作的具体步骤已经在有关该电路分析装置的实施例中进行了详细描述，此处不再详细阐述说明。
本公开实施例中的提供的寄生参数提取方法可以批量提取多个版图单元的寄生参数，且还可以基于版图单元的类型和/或参数在各个流程中(GDS导出、网表导出、LVS验证和版图寄生参数提取)逐一设置对应的环境，而无需用户手动设置。
上述电路分析装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。
为了更好的理解本公开实施例，参照图5，图5是本公开实施例提供的一种电子设备的硬件结构示意图。如图5所示，本公开实施例的电子设备包括存储器，用于存储计算机程序；处理器，用于执行所述存储器中的计算机程序，以实现上述实施例中描述的电路分析方法中的各个步骤，具体可以参见前述方法实施例中的相关描述，本实施例不再赘述。
可选地，存储器既可以是独立的，也可以跟处理器集成在一起。当存储器独立设置时，该设备还包括总线，用于连接所述存储器和处理器。
基于上述实施例中所描述的内容，本公开实施例中还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，以实现如上述实施例中描述的电路分析方法中的各个步骤，具体可以参见前述电路分析方法实施例中的相关描述，本实施例不再赘述。
可以理解的是，上述各实施例中相同或相似部分可以相互参考，在一些实施例中未详细说明的内容可以参见其他实施例中相同或相似的内容。
需要说明的是，在本公开的描述中，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性。此外，在本公开的描述中，除非另有说明，“多个”的含义是指至少两个。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本公开的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本公开的实施例所属技术领域的技术人员所理解。
应当理解，本公开的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本公开各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现 并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开的方案能够提供环境配置模块，以基于版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，进而批量提取多个所述版图单元的寄生网表。如此，无需用户手动进行复杂的环境设置，也可以在自动设置的环境下批量提取多个所述版图单元的寄生网表。这样就能够大大减少寄生参数提取的时间，从而缩短电路后仿真所需要的时间。

Claims (19)

  1. 一种电路分析装置，包括：
    信息模块，配置为获取多个版图单元；
    环境配置模块，配置为基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境；
    批量处理模块，配置为在所述版图寄生参数提取环境下批量提取多个所述版图单元的寄生参数网表。
  2. 根据权利要求1所述的装置，其中，所述环境配置模块与至少一个EDA软件连通，所述环境配置模块通过调用所述EDA软件的接口进行所述版图寄生参数提取环境的自动配置。
  3. 根据权利要求2所述的装置，其中，所述环境配置模块与多个类型不同的所述EDA软件连通，所述环境配置模块通过调用不同所述EDA软件的接口自动配置不同类型的所述版图寄生参数提取环境。
  4. 根据权利要求1所述的装置，其中，所述环境配置模块还配置为设置GDS导出环境，所述批量处理模块包括导出模块，所述导出模块配置为在所述GDS导出环境下批量导出所述版图单元的GDS文件。
  5. 根据权利要求4所述的装置，其中，所述信息模块还配置为获取所述版图单元对应的电路单元，所述环境配置模块还配置为设置网表导出环境，所述导出模块还配置为在所述网表导出环境下批量导出所述电路单元的电路网表。
  6. 根据权利要求5所述的装置，其中，所述环境配置模块还配置为设置验证环境，所述批量处理模块还包括验证模块，所述验证模块配置为在所述验证环境下，基于所述GDS文件和所述电路网表进行版图对比电路验证。
  7. 根据权利要求6所述的装置，其中，所述装置还包括：结果输出 模块，配置为根据所述版图对比电路验证的验证结果和所述寄生参数网表生成对应所述版图单元的报表。
  8. 根据权利要求1所述的装置，其中，所述信息模块具有图形化交互界面，配置为获取所述版图单元。
  9. 根据权利要求1所述的装置，其中，还包括：仿真模块，配置为根据所述批量处理模块输出的所述寄生参数网表进行后仿真。
  10. 一种电路分析方法，所述方法包括：
    获取多个版图单元；
    基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境；
    在所述版图寄生参数提取环境下批量提取多个所述版图单元的寄生参数网表。
  11. 根据权利要求10所述的方法，其中，所述基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，包括：通过调用EDA软件的接口进行所述版图寄生参数提取环境的自动配置。
  12. 根据权利要求11所述的方法，其中，所述基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，包括：通过调用不同EDA软件的接口自动配置不同类型的所述版图寄生参数提取环境。
  13. 根据权利要求10所述的方法，其中，所述在所述环境下批量提取多个所述版图单元的寄生参数网表之前，所述方法还包括：
    设置GDS导出环境，在所述GDS导出环境下批量导出所述版图单元的GDS文件。
  14. 根据权利要求13所述的方法，其中，所述基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，包括：设置网表导出环境；
    所述获取多个版图单元，包括：获取所述版图单元对应的电路单元；
    所述方法还包括：在所述网表导出环境下批量导出所述电路单元的电路网表。
  15. 根据权利要求14所述的方法，其中，所述基于所述版图单元的类型和/或参数逐一设置对应的版图寄生参数提取环境，还包括：
    设置验证环境；
    所述方法还包括：在所述验证环境下，基于所述GDS文件和所述电路网表进行版图对比电路验证。
  16. 根据权利要求15所述的方法，其中，所述方法还包括：
    根据所述版图对比电路验证的验证结果和所述寄生参数网表生成对应所述版图单元的报表。
  17. 根据权利要求10所述的方法，其中，所述方法还包括：
    根据所述寄生参数网表进行后仿真。
  18. 一种电子设备，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述存储器中的计算机程序，以实现权利要求10至17中任一项所述方法的操作步骤。
  19. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求10至17中任一项所述方法的操作步骤。
PCT/CN2022/073937 2022-01-12 2022-01-26 电路分析方法、装置、电子设备和存储介质 WO2023133942A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/810,598 US20230222280A1 (en) 2022-01-12 2022-07-02 Method and apparatus for analyzing circuit, electronic device, and storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210031057.2A CN116467989A (zh) 2022-01-12 2022-01-12 电路分析方法、装置、电子设备和存储介质
CN202210031057.2 2022-01-12

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/810,598 Continuation US20230222280A1 (en) 2022-01-12 2022-07-02 Method and apparatus for analyzing circuit, electronic device, and storage medium

Publications (1)

Publication Number Publication Date
WO2023133942A1 true WO2023133942A1 (zh) 2023-07-20

Family

ID=87177534

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/073937 WO2023133942A1 (zh) 2022-01-12 2022-01-26 电路分析方法、装置、电子设备和存储介质

Country Status (2)

Country Link
CN (1) CN116467989A (zh)
WO (1) WO2023133942A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117313635A (zh) * 2023-10-25 2023-12-29 上海合芯数字科技有限公司 确定芯片设计数据的方法、装置、电子设备及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103995943A (zh) * 2014-06-09 2014-08-20 上海华力微电子有限公司 电路后仿真方法
US20150278419A1 (en) * 2014-03-31 2015-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design method
CN107679311A (zh) * 2017-09-26 2018-02-09 上海华虹宏力半导体制造有限公司 存储器ip模块寄生参数的提取方法
CN108830008A (zh) * 2018-06-28 2018-11-16 中国科学院微电子研究所 一种标准单元库全模型的测试方法及测试系统
CN112765916A (zh) * 2021-01-22 2021-05-07 上海华虹宏力半导体制造有限公司 集成电路后仿真参数网表的生成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150278419A1 (en) * 2014-03-31 2015-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design method
CN103995943A (zh) * 2014-06-09 2014-08-20 上海华力微电子有限公司 电路后仿真方法
CN107679311A (zh) * 2017-09-26 2018-02-09 上海华虹宏力半导体制造有限公司 存储器ip模块寄生参数的提取方法
CN108830008A (zh) * 2018-06-28 2018-11-16 中国科学院微电子研究所 一种标准单元库全模型的测试方法及测试系统
CN112765916A (zh) * 2021-01-22 2021-05-07 上海华虹宏力半导体制造有限公司 集成电路后仿真参数网表的生成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117313635A (zh) * 2023-10-25 2023-12-29 上海合芯数字科技有限公司 确定芯片设计数据的方法、装置、电子设备及存储介质
CN117313635B (zh) * 2023-10-25 2024-05-24 上海合芯数字科技有限公司 确定芯片设计数据的方法、装置、电子设备及存储介质

Also Published As

Publication number Publication date
CN116467989A (zh) 2023-07-21

Similar Documents

Publication Publication Date Title
US8875077B1 (en) Fault sensitivity analysis-based cell-aware automated test pattern generation flow
US8117576B2 (en) Method for using an equivalence checker to reduce verification effort in a system having analog blocks
US11176295B1 (en) Matched net and device analysis based on parasitics
US20070094622A1 (en) Methods, Apparatus and Computer Program Products for Generating Selective Netlists that Include Interconnection Influences at Pre-Layout and Post-Layout Design Stages
US9348965B2 (en) Parasitic component library and method for efficient circuit design and simulation using the same
US9183332B2 (en) Method for simulation of partial VLSI ASIC design
US10268787B2 (en) Hybrid timing analysis method and associated system and non-transitory computer readable medium
JPH05167046A (ja) ファクトリ・プログラムドデバイスの製造システム及び製造方法
JP2011081786A (ja) 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング
US8230382B2 (en) Model based simulation of electronic discharge and optimization methodology for design checking
US10591526B1 (en) Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design
WO2023133942A1 (zh) 电路分析方法、装置、电子设备和存储介质
TW201807607A (zh) 在標準單元認知下利用多個探測點來做缺陷特性分析與波形分析
TWI716079B (zh) 用於功能對等檢測的模擬方法
US20040088627A1 (en) Fault simulator for verifying reliability of test pattern
US8739093B1 (en) Timing characteristic generation and analysis in integrated circuit design
US20230222280A1 (en) Method and apparatus for analyzing circuit, electronic device, and storage medium
TWI775299B (zh) 在電子設計自動化平台上進行電壓規則檢查的電腦實施方法
WO2023015649A1 (zh) 集成电路的后仿真方法和装置
CN112861455B (zh) Fpga建模验证系统及方法
US20060026479A1 (en) Verification vector creating method, and electronic circuit verifying method using the former method
US9177095B1 (en) Methods, systems, and articles of manufacture for creating or manipulating electrical data sets for an electronic design
JP7355462B1 (ja) 回路設計装置、回路設計方法、及び、プログラム
US20240028811A1 (en) Pcell verification
US7072819B2 (en) Method for locating functional mistakes in digital circuit designs

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22919588

Country of ref document: EP

Kind code of ref document: A1