WO2023130805A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2023130805A1
WO2023130805A1 PCT/CN2022/126753 CN2022126753W WO2023130805A1 WO 2023130805 A1 WO2023130805 A1 WO 2023130805A1 CN 2022126753 W CN2022126753 W CN 2022126753W WO 2023130805 A1 WO2023130805 A1 WO 2023130805A1
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Prior art keywords
layer
isolation
group
alignment
conductive layer
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PCT/CN2022/126753
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English (en)
French (fr)
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薛东
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长鑫存储技术有限公司
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Priority to US18/327,063 priority Critical patent/US20230307378A1/en
Publication of WO2023130805A1 publication Critical patent/WO2023130805A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor device and a method for manufacturing the semiconductor device.
  • the redistribution layer (RDL, Redistribution Layer) of the semiconductor chip is to change the contact position (I/O pad) of the originally designed IC line through the wafer-level metal wiring process and the bump process, so that the IC can be applied to different Package form.
  • the depth of the alignment groove formed is relatively large, resulting in a large aspect ratio of the alignment groove, which brings a lot of problems to the alignment of the lithography machine.
  • the noise is very likely to cause the alignment failure of the lithography machine.
  • the purpose of the present disclosure is to overcome the disadvantage of the relatively large depth of the alignment groove in the prior art, and provide a semiconductor device with a small alignment groove depth and a method for manufacturing the semiconductor device.
  • a method for manufacturing a semiconductor device including:
  • a substrate including an alignment area and a connection area
  • the etching rate of the protective layer is lower than the etching rate of the isolation material layer group, so as to remove the isolation material layer group formed on the connection area an isolation layer group, and an alignment groove is formed on the isolation layer group in the alignment region, and the depth of the alignment groove is smaller than the thickness of the isolation layer group;
  • a second conductive layer group is formed on the isolation layer group and the first conductive layer, and the second conductive layer group covers the alignment groove.
  • the gas used to etch the isolation layer group and the protection layer includes: C4F6 and O2.
  • forming an isolation material layer group on the first conductive layer includes:
  • a third isolation material layer is formed on the second isolation material layer, the thickness of the third isolation material layer is greater than the thickness of the first isolation material layer.
  • the step of forming the alignment groove includes:
  • the protection layer and part of the third isolation material layer are removed to form the alignment groove on the third isolation material layer.
  • forming the second conductive layer group includes forming multiple conductive layers.
  • forming the second conductive layer group on the isolation layer group and the first conductive layer includes:
  • a titanium nitride layer is formed over the aluminum metal layer.
  • connection area is located on both sides of the alignment area.
  • a semiconductor device comprising:
  • a substrate including an alignment area and a connection area
  • the isolation layer group is arranged on the first conductive layer and is located on the alignment area, and the alignment groove is arranged on the isolation layer group, and the depth of the alignment groove is smaller than that of the isolation layer the thickness of the group;
  • the second conductive layer group is arranged on the isolation layer group and the first conductive layer, and the second conductive layer group covers the alignment groove.
  • the isolation layer group includes:
  • the third isolation layer is arranged on the second isolation layer, and the thickness of the third isolation layer is greater than the thickness of the first isolation layer.
  • the depth of the alignment groove is smaller than the thickness of the third isolation layer.
  • the alignment groove has a depth of 0.4-0.6 microns. .
  • the second conductive layer group includes multiple conductive layers.
  • the second conductive layer group includes:
  • a titanium metal layer disposed on the isolation layer group and the first conductive layer;
  • the titanium nitride layer is arranged on the aluminum metal layer.
  • the thickness of the titanium metal layer is between 0.1-0.15 microns
  • the thickness of the aluminum metal layer is between 4.2-4.7 microns
  • the thickness of the titanium nitride layer is Between 0.04-0.06 microns.
  • a protective layer is formed on the isolation material layer group, and the protective layer is located on the alignment area; when the isolation material layer group and the protective layer are etched, since the etching rate of the protective layer is lower than that of the The etching rate of the isolation layer group makes it possible to form an alignment groove on the isolation material layer group in the alignment area while removing the isolation material layer group on the connection area, and the depth of the alignment groove is less than that of the isolation material layer group Thickness, so the depth of the alignment groove is shallow, and the aspect ratio is small.
  • the laser emitted by the lithography machine hits the alignment groove and has fewer reflections in the alignment groove.
  • the lithography machine can be well aligned through the alignment groove, and the problem of alignment failure of the lithography machine can be improved; moreover, the shallower depth
  • the groove bottom of the alignment groove is not easy to form an inclined structure, which is also beneficial for the photolithography machine to align through the alignment groove.
  • FIG. 1 is a schematic block diagram of an exemplary embodiment of a manufacturing method of a semiconductor device of the present disclosure.
  • FIG. 2 is a schematic structural view of a substrate provided in the method for manufacturing a semiconductor device of the present disclosure.
  • FIG. 3 is a schematic diagram of the structure after the first conductive layer is formed on the basis of FIG. 2 .
  • FIG. 4 is a schematic diagram of the structure after the isolation layer group is formed on the basis of FIG. 3 .
  • FIG. 5 is a schematic structural diagram after forming a protective layer on the basis of FIG. 4 .
  • FIG. 6 is a schematic structural diagram after forming a preset pattern on the basis of FIG. 5 .
  • FIG. 7 is a schematic diagram of the structure after etching on the basis of FIG. 6 .
  • FIG. 8 is a schematic diagram of the structure after removing the preset pattern on the basis of FIG. 7 .
  • FIG. 9 is a schematic structural diagram after forming a second conductive layer group on the basis of FIG. 8 .
  • Substrate 2. First conductive layer;
  • Isolation material layer group 31. The first isolation material layer; 32. The second isolation material layer; 33. The third isolation material layer;
  • Isolation layer group 41. The first isolation layer; 42. The second isolation layer; 43. The third isolation layer;
  • the second conductive layer group 101. Titanium metal layer; 102. Aluminum metal layer; 103. Titanium nitride layer;
  • A alignment area
  • B connection area
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor device. As shown in FIG. 1 , the method for manufacturing a semiconductor device may include the following steps:
  • a substrate 1 is provided, including an alignment area A and a connection area B.
  • Step S20 forming a first conductive layer 2 on the substrate 1 .
  • Step S30 forming an isolation material layer group 3 on the first conductive layer 2 .
  • Step S40 forming a protection layer 7 on the isolation material layer group 3 , and the protection layer 7 is located on the alignment region A.
  • Step S50 etching the isolation material layer group 3 and the protective layer 7, the etching rate of the protective layer 7 is lower than the etching rate of the isolation material layer group 3, so as to remove the
  • the isolation material layer group 3 forms an isolation layer group 4, and an alignment groove 8 is formed on the isolation layer group 4 in the alignment area A, and the depth of the alignment groove 8 is smaller than that of the isolation layer. Thickness of layer set 4.
  • Step S60 forming a second conductive layer group 10 on the isolation layer group 4 and the first conductive layer 2 , and the second conductive layer group 10 covers the alignment groove 8 .
  • the protection layer 7 is formed on the isolation material layer group 3, and the protection layer 7 is located on the alignment area A; when the isolation material layer group 3 and the protection layer 7 are etched, due to the protection The etch rate of layer 7 is lower than that of the isolation layer group 4, so that while the isolation material layer group 3 on the connection area B is removed, an alignment groove 8 can be formed on the isolation material layer group 3 in the alignment area A , the depth of the alignment groove 8 is less than the thickness of the isolation material layer group 3, that is, the depth of the alignment groove 8 is relatively shallow, and the aspect ratio is small.
  • the laser emitted by the lithography machine After reaching the alignment groove 8, the number of reflections in the alignment groove 8 is less, which will reduce the error of the laser, thereby improving the alignment accuracy of the laser, so that the photolithography machine can pass through the alignment groove 8 well.
  • Alignment can improve the problem of alignment failure of the lithography machine; moreover, the groove bottom of the shallower alignment groove 8 is not easy to form an inclined structure, which is also beneficial for the lithography machine to align through the alignment groove 8 .
  • the depth and width of the alignment groove 8 are relatively large, the laser emitted by the lithography machine will reflect more times in the alignment groove 8 after it hits the alignment groove 8, and the laser accuracy after multiple reflections will decrease. As a result, the alignment of the photolithography machine is affected, resulting in alignment failure.
  • a substrate 1 is provided, including an alignment area A and a connection area B.
  • the substrate 1 may be a semiconductor die that has been prepared, and the semiconductor die may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor), referred to as a MOS transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor
  • the MOS tube can be a PMOS (positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor) tube or an NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) tube
  • the MOS tube can include a storage capacitor, a bit lines, word lines, gates, sources and drains, etc.
  • the substrate 1 may include an alignment region A and a connection region B, specifically, two connection regions B may be provided, and the two connection regions B are located on both sides of the alignment region A.
  • connection areas B can also be set to multiple, and the specific position of the connection area B can be set as required; the number of alignment areas A can also be set to multiple, and the alignment area The specific location of the area A can also be set as required.
  • Step S20 forming a first conductive layer 2 on the substrate 1 .
  • a first conductive material layer is formed on the substrate 1 by methods such as deposition, sputtering or evaporation, and then the first conductive material layer is etched to form a patterned first conductive layer 2 .
  • the first conductive layer 2 is formed not only in the alignment region A, but also in the connection region B.
  • the first conductive layer 2 can be connected to the gate, source or drain in the substrate 1, and can input signals to the gate, source or drain in the substrate 1 through the first conductive layer 2, or connect the substrate The signal stored in 1 is output through the first conductive layer 2.
  • the material of the first conductive layer 2 is, for example, aluminum.
  • the thickness of the first conductive layer 2 is, for example, between 0.6-1.0 microns, such as 0.6, 0.8 or 1.0 microns.
  • the material of the first conductive layer 2 may include metals such as copper and silver.
  • Step S30 forming an isolation material layer group 3 on the first conductive layer 2 .
  • a first isolation material layer 31 is formed on the first conductive layer 2 by methods such as deposition, sputtering, or evaporation.
  • the first isolation material layer 31 is formed not only in the alignment area A, but also in the connection area B, that is, the orthographic projection of the first isolation material layer 31 on the substrate 1 is located in the alignment area A and the connection area B.
  • the material of the first isolation material layer 31 includes, for example, silicon oxide.
  • the thickness of the first isolation material layer 31 is, for example, between 0.6-1.0 microns. For example, the thickness of the first isolation material layer 31 may be 0.6, 0.8 or 1.0 microns.
  • the second isolation material layer 32 is formed on the first isolation material layer 31 by methods such as deposition, sputtering or evaporation.
  • the second isolation material layer 32 is formed not only in the alignment area A, but also in the connection area B, that is, the orthographic projection of the second isolation material layer 32 on the substrate 1 is located in the alignment area A and the connection area B.
  • the material of the second isolation material layer 32 includes, for example, silicon nitride, and the thickness of the second isolation material layer 32 is, for example, between 0.5-0.7 microns.
  • the thickness of the second isolation material layer 32 may be 0.5, 0.6 or 0.7 microns.
  • a third isolation material layer 33 is formed on the second isolation material layer 32 by methods such as deposition, sputtering or evaporation.
  • the third isolation material layer 33 is formed not only in the alignment area A, but also in the connection area B, that is, the orthographic projection of the third isolation material layer 33 on the substrate 1 is located in the alignment area A and the connection area B.
  • the material of the third isolation material layer 33 includes, for example, silicon oxide.
  • the thickness of the third isolation material layer 33 is greater than the thickness of the first isolation material layer 31 .
  • the thickness of the third isolation material layer 33 is, for example, between 4.0-5.0 microns.
  • the thickness of the third isolation material layer 33 may be 4.0, 4.5 or 5.0 microns.
  • the substrate 1 and the first conductive layer 2 can be protected by the isolation material layer group 3, and the thickness of the third isolation material layer 33 is relatively thick, which can play a role in planarization, and provide a solid foundation for the subsequent formation of the second conductive layer 33.
  • the layer group 10 provides a better base, which facilitates the formation of the second conductive layer group 10 with a relatively uniform thickness, which is beneficial to improve the conductivity uniformity of the semiconductor device.
  • the thicker thickness of the third isolation material layer 33 can prevent the second isolation material layer 32 from being etched when the alignment groove 8 is formed, so as to protect the second isolation material layer 32 and prevent the alignment groove 8 from exposing the first isolation material layer.
  • the second isolation material layer 32 is used to improve the performance of the semiconductor device.
  • Step S40 forming a protection layer 7 on the isolation material layer group 3 , and the protection layer 7 is located on the alignment region A.
  • a protective material layer is formed on the isolation material layer group 3 by methods such as deposition, sputtering, or evaporation, and the protective material layer is formed by etching the protective material layer with a mixed gas of CHF3 and O2.
  • the protective layer 7 is only formed in the alignment area A, and the protective layer 7 is not formed in the connection area B, that is, the orthographic projection of the protective layer 7 on the substrate 1 is only located in the alignment area A.
  • the material of the protective layer 7 includes, for example, silicon oxide, and the thickness of the protective layer 7 is between 0.4-0.6 microns.
  • the thickness of the protective layer 7 can be 0.4, 0.5 or 0.6 microns.
  • Step S50 etching the isolation material layer group 3 and the protective layer 7, the etching rate of the protective layer 7 is lower than the etching rate of the isolation material layer group 3, so as to remove the
  • the isolation material layer group 3 forms an isolation layer group 4, and an alignment groove 8 is formed on the isolation layer group 4 in the alignment area A, and the depth of the alignment groove 8 is smaller than that of the isolation layer. Thickness of layer set 4.
  • a photoresist is coated on the protective layer 7, and then the photoresist is exposed and developed, so that the photoresist forms a preset pattern 9, the preset pattern 9 is formed only in the alignment area A.
  • the material of the third isolation material layer 33 can also be amorphous carbon, and the protective layer 7 can also be silicon oxide. Because the light absorbance of the protective layer 7 is less than the light absorbance of the third isolation material layer 33, when forming a photoresist on the protective layer 7, the protective layer 7 absorbs light to a lower degree, so the protective layer 7 can reduce the light absorption rate. The degree of absorption, thereby improving the accuracy of graphics. At the same time, since amorphous carbon is easier to etch than silicon oxide, it is beneficial to subsequent pattern transfer. As can be seen from FIG.
  • the third isolation material layer 33 is greater than the thickness of the protective layer 7 if a photoresist is directly formed on the third isolation material layer 33, the third isolation material layer 33 is less sensitive to light.
  • the absorptivity is relatively large, and the thickness of the third isolation material layer 33 is relatively thick, so the accuracy of patterning will be reduced.
  • the isolation material layer group 3 and the protective layer 7 are etched, the isolation layer material group and the protective layer 7 located below the preset pattern 9 will not be etched due to the protection of the preset pattern 9; Both the isolation material layer group 3 protected by the pattern 9 and the protection layer 7 will be etched.
  • the isolation material layer group 3 is relatively shallow; in the connection area B, due to the absence of the barrier of the protective layer 7, the etching depth of the isolation material layer group 3 is relatively deep; finally, after the etching is completed, the isolation material layer group 3 in the connection area B is completely etched away, and the isolation The material layer group 3 forms the isolation layer group 4, and the isolation layer group 4 forms the bump.
  • the isolation layer group 4 in the alignment area A that is not protected by the preset pattern 9 is not completely etched away, and only the alignment groove 8 is formed on the third isolation material layer 33 .
  • the depth of the alignment groove 8 is not only smaller than the thickness of the isolation layer group 4 , but also the depth of the alignment groove 8 is smaller than the thickness of the third isolation layer 43 .
  • the depth of the alignment groove 8 is, for example, between 0.4-0.6 microns.
  • the depth of the alignment groove 8 can be 0.4, 0.5 or 0.6 microns.
  • the gas for etching the isolation material layer group 3 and the protective layer 7 can include C4F6 and O2, and the ratio of C4F6 to O2 can be (40-60):(20-40), for example, 50:30, because the etching can be adjusted Therefore, the gas composition ratio can better etch the isolation material layer group 3 and the protective layer 7 .
  • the thicker isolation layer group 4 and the shallower alignment groove 8 can be formed on the isolation layer group 4 in the same etching process, which saves a one-step etching process. , Improve production efficiency and reduce production costs.
  • the preset pattern 9 is removed.
  • the material of the preset pattern 9 is photoresist, which can be removed by exposure and development, that is, the preset pattern 9 is illuminated, and then the light is removed by a developer.
  • the preset pattern 9 may also be removed through an ashing process.
  • protection layer 7 is removed, and the remaining protection layer 7 can be removed by etching with a mixed gas including CHF3, O2 and CF4.
  • the etching gas when the etching gas is etching the isolation material layer group 3, the etching gas can also etch the preset pattern 9 and the protective layer 7, that is, forming the groove 8, the preset pattern 9 and the protective layer 7 can be removed at the same time, so that the etching steps can be reduced.
  • Step S60 forming a second conductive layer group 10 on the isolation layer group 4 and the first conductive layer 2 , and the second conductive layer group 10 covers the alignment groove 8 .
  • the second conductive layer group 10 is formed on the isolation layer group 4 and the exposed first conductive layer 2 by methods such as deposition, sputtering or evaporation, and the second conductive layer Group 10 covers alignment groove 8 .
  • the orthographic projection of the second conductive layer group 10 on the substrate 1 is located in the alignment area A and the connection area B.
  • the second conductive layer group 10 in the connection area B is connected to the first conductive layer 2 , so that the connection between the first conductive layer 2 and an external circuit can be realized. It is also possible to pattern the second conductive layer group 10 so that the second conductive layer group 10 forms new connection lines to achieve the purpose of redistribution of lines.
  • the material of the second conductive layer group 10 includes aluminum, for example.
  • the titanium metal layer 101 can be formed on the isolation layer group and the first conductive layer by methods such as deposition, sputtering or evaporation; the thickness of the titanium metal layer 101 is, for example, between 0.1-0.15 microns, for example, 0.12 microns.
  • an aluminum metal layer 102 is formed on the titanium metal layer 101 by methods such as deposition, sputtering or vapor deposition.
  • the thickness of the aluminum metal layer 102 is, for example, between 4.2-4.7 microns.
  • the thickness of the aluminum metal layer 102 can be 4.2, 4.5 or 4.7 microns.
  • a titanium nitride layer 103 is formed on the aluminum metal layer 102 by methods such as deposition, sputtering, or vapor deposition.
  • the thickness of the titanium nitride layer 103 is, for example, between 0.04-0.06 microns. The thickness may be 0.05 microns.
  • the titanium metal layer 101 , the aluminum metal layer 102 and the titanium nitride layer 103 form the second conductive layer group 10 .
  • the aluminum metal layer 102 as a rewiring layer, is not easy to be formed on the third isolation material layer 33, thereby causing the aluminum metal layer 102 to be easily disconnected; the titanium metal layer 101 is arranged on the aluminum metal layer 102 and the third isolation material layer 33
  • the aluminum metal layer 102 is easily deposited on the titanium metal layer 101, that is, the titanium metal layer 101 can improve the adhesion of the deposition of the aluminum metal layer 102, thereby reducing the open circuit caused by the insufficient deposition of the aluminum metal layer 102
  • the open circuit position of the aluminum metal layer 102 can be connected by the titanium metal layer 101, further avoiding the occurrence of the open circuit situation of the aluminum metal layer 102, and improving product yield.
  • the aluminum metal layer 102 is relatively thick, the stress brought by it is relatively large, and the aluminum metal layer 102 is also prone to warping, thereby affecting the conductive effect; due to the high density of titanium nitride, the titanium nitride layer 103 is arranged on On the aluminum metal layer 102, the warpage of the aluminum metal layer 102 can be improved by the gravity of the titanium nitride, and the conductive effect can be improved.
  • the impedance of the second conductive layer group 10 of the three-layer structure is relatively low, which improves the conductive effect of the semiconductor device.
  • the second conductive layer group 10 when the second conductive layer group 10 is formed on the groove 8, since part of the second conductive layer 10 is located in the groove 8, the depth and width of the groove 8 The ratio will be further reduced, so when the lithography machine performs alignment, the alignment accuracy can be further improved.
  • the material of the second conductive layer group 10 may also include copper, and nickel-gold or nickel-palladium-gold may also be plated on the copper lines as required.
  • the thick copper structure is a better choice for high current and high power devices due to its advantages of low resistance, high heat dissipation and low cost.
  • the second conductive layer group 10 can also increase the distance between the interfaces, provide a larger bump (isolation layer group 4) area, reduce the stress between the substrate and the element, and increase the reliability of the element; replace part of the circuit design, accelerate IC chip (Integrated Circuit Chip) development time.
  • the semiconductor device may include a substrate 1, a first conductive layer 2, an isolation layer Group 4 and the second conductive layer group 10; the substrate 1 may include an alignment region A and a connection region B; the first conductive layer 2 is disposed on the substrate 1; the isolation layer group 4 is disposed on the first conductive layer On the layer 2, and located on the alignment area A, the isolation layer group 4 is provided with an alignment groove 8, and the depth of the alignment groove 8 is smaller than the thickness of the isolation layer group 4; The second conductive layer group 10 is disposed on the isolation layer group 4 and the first conductive layer 2 , and the second conductive layer group 10 covers the alignment groove 8 .
  • the substrate 1 may be a semiconductor die that has been prepared, and the semiconductor die may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor), referred to as a MOS transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor
  • the MOS tube can be a PMOS (positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor) tube or an NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) tube
  • the MOS tube can include a storage capacitor, a bit lines, word lines, gates, sources and drains, etc.
  • the substrate 1 may include an alignment region A and a connection region B, specifically, two connection regions B may be provided, and the two connection regions B are located on both sides of the alignment region A.
  • connection areas B can also be set to multiple, and the specific position of the connection area B can be set as required; the number of alignment areas A can also be set to multiple, and the alignment area The specific location of the area A can also be set as required.
  • the first conductive layer 2 is formed not only in the alignment region A but also in the connection region B.
  • the first conductive layer 2 can be connected to the gate, source or drain in the substrate 1, and can input signals to the gate, source or drain in the substrate 1 through the first conductive layer 2, or connect the substrate
  • the signal stored in 1 is output through the first conductive layer 2.
  • the material of the first conductive layer 2 is, for example, aluminum.
  • the thickness of the first conductive layer 2 is, for example, between 0.6-1.0 microns, for example, the thickness of the first conductive layer 2 may be 0.8 microns.
  • the material of the first conductive layer 2 can be copper, silver and other metals.
  • the isolation layer group 4 may include a first isolation layer 41, a second isolation layer 42, and a third isolation layer 43; the first isolation layer 41 is disposed on the first conductive layer 2; the second isolation layer 42 is disposed on the first isolation layer 41 ; the third isolation layer 43 is disposed on the second isolation layer 42 , and the thickness of the third isolation layer 43 is greater than the thickness of the first isolation layer 41 .
  • the material of the first isolation layer 41 includes, for example, silicon oxide, and the thickness of the first isolation layer 41 is, for example, between 0.6-1.0 microns.
  • the thickness of the first isolation layer 41 may be 0.8 microns.
  • the material of the second isolation layer 42 includes, for example, silicon nitride, and the thickness of the second isolation layer 42 is, for example, between 0.5-0.7 microns.
  • the thickness of the second isolation layer 42 may be 0.6 microns.
  • the material of the third isolation layer 43 includes, for example, silicon oxide, and the thickness of the third isolation layer 43 is, for example, between 4.0-5.0 microns.
  • the thickness of the third isolation layer 43 may be 4.5 microns.
  • the isolation layer group 4 is only formed in the alignment area A, that is, the orthographic projection of the isolation layer group 4 on the substrate 1 is only located in the alignment area A.
  • the substrate 1 and the first conductive layer 2 can be protected by the isolation material group 4, and the thickness of the third isolation layer 43 is relatively thick, which can play a role in planarization, and is the second conductive layer group formed subsequently. 10 provides a better base to facilitate the formation of the second conductive layer group 10 with a relatively uniform thickness, which is beneficial to improve the conductivity uniformity of the semiconductor device. Moreover, the thicker thickness of the third isolation layer 43 can prevent the second isolation layer 42 from being etched when the alignment groove 8 is formed, so as to protect the second isolation layer 42 and prevent the alignment groove 8 from exposing the second isolation layer. 42, to improve semiconductor device performance.
  • the alignment groove 8 is disposed on the third isolation layer 43, and is not disposed on the second isolation layer 42 and the first isolation layer 41, and the depth of the alignment groove 8 is smaller than that of the third isolation layer 43. Therefore, the depth of the alignment groove 8 is shallow and the aspect ratio is small.
  • the laser emitted by the lithography machine hits the alignment groove 8 and then enters the alignment groove 8 If the number of reflections is less, the error of the laser will be reduced, thereby improving the alignment accuracy of the laser, so that the lithography machine can be well aligned through the alignment groove 8, and the problem of alignment failure of the lithography machine can be improved; Moreover, the groove bottom of the shallow alignment groove 8 is not easy to form an inclined structure, which is also beneficial for the photolithography machine to perform alignment and exposure through the alignment groove 8 .
  • the depth of the alignment groove 8 is greater than or equal to 0.4 ⁇ m and less than or equal to 0.6 ⁇ m, for example, the depth of the alignment groove 8 may be 0.5 ⁇ m.
  • a partition wall is provided between two adjacent alignment grooves 8 , and a partition wall is also provided on the outermost side of the alignment groove 8 .
  • the number and structure of the alignment grooves 8 can be set in multiples according to the needs, and the alignment grooves 8 can be arranged in parallel or crossed to form a required alignment pattern.
  • the second conductive layer group 10 is disposed on the isolation layer group 4 and the first conductive layer 2, and the second conductive layer group 10 covers the alignment groove 8, that is, the second conductive layer group 10
  • the orthographic projection on the substrate 1 is located in the alignment area A and the connection area B.
  • the second conductive layer group 10 in the connection region B is connected to the first conductive layer 2 . It is also possible to pattern the second conductive layer group 10 so that the second conductive layer group 10 forms new connection lines to achieve the purpose of redistribution of lines.
  • the second conductive layer group 10 may include a titanium metal layer 101, an aluminum metal layer 102, and a titanium nitride layer 103; the titanium metal layer 101 is disposed on the isolation layer group and the first conductive layer; the aluminum metal layer 102 is disposed on On the titanium metal layer 101 ; the titanium nitride layer 103 is set on the aluminum metal layer 102 .
  • the thickness of the titanium metal layer 101 is, for example, 0.1 ⁇ m.
  • the thickness of the aluminum metal layer 102 is, for example, between 4.2-4.7 microns, for example, the thickness of the aluminum metal layer 102 may be 4.5 microns.
  • the thickness of the titanium nitride layer 103 is, for example, between 0.04-0.06 microns, for example, the thickness of the titanium nitride layer 103 may be 0.05 microns.
  • the titanium metal layer 101 , the aluminum metal layer 102 and the titanium nitride layer 103 form the second conductive layer group 10 .
  • the aluminum metal layer 102 as a rewiring layer, is not easy to be formed on the third isolation material layer 33, thereby causing the aluminum metal layer 102 to be easily disconnected; the titanium metal layer 101 is arranged on the aluminum metal layer 102 and the third isolation material layer 33
  • the aluminum metal layer 102 is easily deposited on the titanium metal layer 101, that is, the titanium metal layer 101 can improve the adhesion of the deposition of the aluminum metal layer 102, thereby reducing the open circuit caused by the insufficient deposition of the aluminum metal layer 102
  • the open circuit position of the aluminum metal layer 102 can be connected by the titanium metal layer 101, further avoiding the occurrence of the open circuit situation of the aluminum metal layer 102, and improving product yield.
  • the aluminum metal layer 102 is relatively thick, the stress brought by it is relatively large, and the aluminum metal layer 102 is also prone to warping, thereby affecting the conductive effect; due to the high density of titanium nitride, the titanium nitride layer 103 is arranged on On the aluminum metal layer 102, the warpage of the aluminum metal layer 102 can be improved by the gravity of the titanium nitride, and the conductive effect can be improved.
  • the impedance of the second conductive layer group 10 of the three-layer structure is relatively low, which improves the conductive effect of the semiconductor device.
  • the material of the second conductive layer group 10 may also be copper, and nickel-gold or nickel-palladium-gold may also be plated on the copper lines as required. Thick copper structure is the best choice for high current and high power devices due to its advantages of low resistance, high heat dissipation and low cost.

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Abstract

一种半导体器件及其制备方法；该制备方法包括：提供一衬底（1），包括对位区域（A）和连接区域（B）；在衬底（1）之上形成第一导电层（2）；在第一导电层（2）之上形成隔离材料层组（3）；在隔离材料层组（3）之上形成保护层（7），且保护层（7）位于对位区域（A）上；对隔离材料层组（3）以及保护层（7）进行蚀刻，对保护层（7）的蚀刻速率小于对隔离材料层组（3）的蚀刻速率，以去除连接区域（B）上的隔离材料层组（3）形成隔离层组（4），并在对位区域（A）的隔离层组（4）上形成对位凹槽（8），对位凹槽（8）的深度小于隔离层组（4）的厚度；在隔离层组（4）和第一导电层（2）之上形成第二导电层组（10），第二导电层组（10）覆盖对位凹槽（8）。对位凹槽（8）的深度较浅，深宽比较小，光刻机可以很好地通过对位凹槽（8）进行对准。

Description

半导体器件及其制备方法
交叉引用
本公开要求于2022年1月7日提交的申请号为202210014858.8名称为“半导体器件及其制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件及半导体器件的制备方法。
背景技术
半导体芯片的重新布线(RDL，Redistribution Layer)是将原来设计的IC线路接点位置(I/O pad)，通过晶圆级金属布线制程和凸块制程改变其接点位置，使IC能适用于不同的封装形式。
但是，目前在重新布线制作过程中，由于工艺的限制，形成的对位凹槽的深度较大，造成对位凹槽具有较大的深宽比，给光刻机的对准带来很大的噪音，极有可能导致光刻机对准失败。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的对位凹槽的深度较大的不足，提供一种对位凹槽的深度较小的半导体器件及半导体器件的制备方法。
根据本公开的一个方面，提供了一种半导体器件的制备方法，包括：
提供一衬底，包括对位区域和连接区域；
在所述衬底之上形成第一导电层；
在所述第一导电层之上形成隔离材料层组；
在所述隔离材料层组之上形成保护层，且所述保护层位于所述对位 区域上；
对所述隔离材料层组以及所述保护层进行蚀刻，对所述保护层的蚀刻速率小于对所述隔离材料层组的蚀刻速率，以去除所述连接区域上的所述隔离材料层组形成隔离层组，并在所述对位区域的所述隔离层组上形成对位凹槽，所述对位凹槽的深度小于所述隔离层组的厚度；
在所述隔离层组和所述第一导电层之上形成第二导电层组，所述第二导电层组覆盖所述对位凹槽。
在本公开的一种示例性实施例中，对所述隔离层组以及所述保护层进行蚀刻的气体包括：C4F6和O2。
在本公开的一种示例性实施例中，在所述第一导电层之上形成隔离材料层组，包括：
在所述第一导电层之上形成第一隔离材料层；
在所述第一隔离材料层之上形成第二隔离材料层；
在所述第二隔离材料层之上形成第三隔离材料层，所述第三隔离材料层的厚度大于所述第一隔离材料层的厚度。
在本公开的一种示例性实施例中，形成所述对位凹槽的步骤包括：
移除所述保护层和部分所述第三隔离材料层，以在所述第三隔离材料层上形成所述对位凹槽。
在本公开的一种示例性实施例中，在形成所述第二导电层组之前，还包括移除所述保护层。
在本公开的一种示例性实施例中，形成所述第二导电层组包括形成多层导电层。
在本公开的一种示例性实施例中，所述在所述隔离层组和所述第一导电层之上形成第二导电层组包括：
在所述隔离层组和所述第一导电层之上形成钛金属层；
在所述钛金属层之上形成铝金属层；
在所述铝金属层之上形成氮化钛层。
在本公开的一种示例性实施例中，所述连接区域位于所述对位区域的两侧。
根据本公开的另一个方面，提供了一种半导体器件，包括：
衬底，包括对位区域和连接区域；
第一导电层，设于所述衬底之上；
隔离层组，设于所述第一导电层之上，且位于所述对位区域上，所述隔离层组上设置有对位凹槽，所述对位凹槽的深度小于所述隔离层组的厚度；
第二导电层组，设于所述隔离层组和所述第一导电层之上，所述第二导电层组覆盖所述对位凹槽。
在本公开的一种示例性实施例中，所述隔离层组包括：
第一隔离层，设于所述第一导电层之上；
第二隔离层，设于所述第一隔离层之上；
第三隔离层，设于所述第二隔离层之上，所述第三隔离层的厚度大于所述第一隔离层的厚度。
在本公开的一种示例性实施例中，所述对位凹槽的深度小于所述第三隔离层的厚度。
在本公开的一种示例性实施例中，所述对位凹槽的深度在0.4-0.6微米之间。。
在本公开的一种示例性实施例中，所述第二导电层组包括多层导电层。
在本公开的一种示例性实施例中，所述第二导电层组包括：
钛金属层，设于所述隔离层组和所述第一导电层之上；
铝金属层，设于所述钛金属层之上；
氮化钛层，设于所述铝金属层之上。
在本公开的一种示例性实施例中，所述钛金属层的厚度在0.1-0.15微米之间，所述铝金属层的厚度在4.2-4.7微米之间，所述氮化钛层的厚度在0.04-0.06微米之间。
本公开的半导体器件的制备方法，在隔离材料层组之上形成保护层，且保护层位于对位区域上；对隔离材料层组以及保护层进行蚀刻时，由于对保护层的蚀刻速率小于对隔离层组的蚀刻速率，使得在去除连接区域上的隔离材料层组的同时，可以在对位区域的隔离材料层组上形成对位凹槽，对位凹槽的深度小于隔离材料层组的厚度，因此对位凹槽的深 度较浅，深宽比较小，当光刻机在进行对准时，光刻机发出的激光射至对位凹槽后在对位凹槽内的反射次数较少，就会减小激光的误差，从而提高激光的对准精度，使得光刻机可以很好地通过对位凹槽进行对准，改善光刻机对准失败的问题；而且，深度较浅的对位凹槽的槽底部不容易形成倾斜结构，同样有利于光刻机通过对位凹槽进行对准。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开半导体器件的制备方法一示例实施方式的流程示意框图。
图2为本公开半导体器件的制备方法中提供的衬底的结构示意图。
图3为在图2的基础上形成第一导电层后的结构示意图。
图4为在图3的基础上形成隔离层组后的结构示意图。
图5为在图4的基础上形成保护层后的结构示意图。
图6为在图5的基础上形成预设图案后的结构示意图。
图7为在图6的基础上蚀刻后的结构示意图。
图8为在图7的基础上去除预设图案后的结构示意图。
图9为在图8的基础上形成第二导电层组后的结构示意图。
附图标记说明：
1、衬底；2、第一导电层；
3、隔离材料层组；31、第一隔离材料层；32、第二隔离材料层；33、第三隔离材料层；
4、隔离层组；41、第一隔离层；42、第二隔离层；43、第三隔离层；
7、保护层；8、对位凹槽；9、预设图案；
10、第二导电层组；101、钛金属层；102、铝金属层；103、氮化钛层；
A、对位区域；B、连接区域。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开示例实施方式提供了一种半导体器件的制备方法，如图1所示，该半导体器件的制备方法可以包括以下步骤：
步骤S10，提供一衬底1，包括对位区域A和连接区域B。
步骤S20，在所述衬底1之上形成第一导电层2。
步骤S30，在所述第一导电层2之上形成隔离材料层组3。
步骤S40，在所述隔离材料层组3之上形成保护层7，且所述保护层7位于所述对位区域A上。
步骤S50，对所述隔离材料层组3以及所述保护层7进行蚀刻，对所述保护层7的蚀刻速率小于对所述隔离材料层组3的蚀刻速率，以去除所述连接区域B上的所述隔离材料层组3形成隔离层组4，并在所述对位区域A的所述隔离层组4上形成对位凹槽8，所述对位凹槽8的深度小于所述隔离层组4的厚度。
步骤S60，在所述隔离层组4和所述第一导电层2之上形成第二导电层组10，所述第二导电层组10覆盖所述对位凹槽8。
本公开的半导体器件的制备方法，在隔离材料层组3之上形成保护层7，且保护层7位于对位区域A上；对隔离材料层组3以及保护层7进行蚀刻时，由于对保护层7的蚀刻速率小于对隔离层组4的蚀刻速率，使得在去除连接区域B上的隔离材料层组3的同时，可以在对位区域A的隔离材料层组3上形成对位凹槽8，对位凹槽8的深度小于隔离材料层组3的厚度，即使得对位凹槽8的深度较浅，深宽比较小，当光刻机在进行对准时，光刻机发出的激光射至对位凹槽8后在对位凹槽8内的反射次数较少，就会减小激光的误差，从而提高激光的对准精度，使得光刻机可以很好地通过对位凹槽8进行对准，改善光刻机对准失败的问题；而且，深度较浅的对位凹槽8的槽底部不容易形成倾斜结构，同样有利于光刻机通过对位凹槽8进行对准。如果对位凹槽8的深宽比较大，光刻机发出的激光射至对位凹槽8后在对位凹槽8内的反射次数较多，多次反射后的激光精度就会降低，从而对光刻机的对准造成影响，导致对准失败。
下面对该半导体器件的制备方法进行详细说明。
步骤S10，提供一衬底1，包括对位区域A和连接区域B。
在本示例实施方式中，衬底1可以是已经制备完成的半导体管芯，半导体管芯可以是MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)，简称MOS管，MOS管可以是PMOS(positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)管或NMOS(Negative channel-Metal-Oxide-Semiconductor，N型金属氧化物半导体)管，MOS管可以包括存储电容、位线、字线、栅极、源极和漏极等等。
参照图2所示，衬底1可以包括对位区域A和连接区域B，具体来讲，连接区域B可以设置为两个，两个连接区域B位于对位区域A的两侧。
当然，在本公开的其他示例实施方式中，连接区域B的数量还可以设置为多个，连接区域B的具体位置可以根据需要设置；对位区域A的数量也可以设置为多个，对位区域A的具体位置也可以根据需要设置。
步骤S20，在所述衬底1之上形成第一导电层2。
在本示例实施方式中，在衬底1之上通过沉积、溅射或蒸镀等方法形成第一导电材料层，然后对第一导电材料层进行蚀刻形成图案化的第一导电层2。参照图3所示，第一导电层2不仅形成在对位区域A，而且形成在连接区域B。第一导电层2可以与衬底1内的栅极、源极或漏极连接，通过第一导电层2可以向衬底1内的栅极、源极或漏极输入信号，或将衬底1内存储的信号通过第一导电层2输出。第一导电层2的材质例如为铝。第一导电层2的厚度例如在0.6-1.0微米之间，例如为0.6，0.8或1.0微米。
当然，在本公开的其他示例实施方式中，第一导电层2的材质可以包括铜、银等金属。
步骤S30，在所述第一导电层2之上形成隔离材料层组3。
在本示例实施方式中，参照图4所示，在第一导电层2之上通过沉积、溅射或蒸镀等方法形成第一隔离材料层31。第一隔离材料层31不仅形成在对位区域A，而且形成在连接区域B，即第一隔离材料层31在衬底1上的正投影位于对位区域A和连接区域B内。第一隔离材料层31的材质例如包括氧化硅，第一隔离材料层31的厚度例如在0.6-1.0微米之间，例如，第一隔离材料层31的厚度可以是0.6，0.8或1.0微米。
在第一隔离材料层31之上通过沉积、溅射或蒸镀等方法形成第二隔离材料层32。第二隔离材料层32不仅形成在对位区域A，而且形成在连接区域B，即第二隔离材料层32在衬底1上的正投影位于对位区域A和连接区域B内。第二隔离材料层32的材质例如包括氮化硅，第二隔离材料层32的厚度例如在0.5-0.7微米之间，例如，第二隔离材料层32的厚度可以是0.5或0.6或0.7微米。
在第二隔离材料层32之上通过沉积、溅射或蒸镀等方法形成第三隔离材料层33。第三隔离材料层33不仅形成在对位区域A，而且形成在连接区域B，即第三隔离材料层33在衬底1上的正投影位于对位区域A和连接区域B内。第三隔离材料层33的材质例如包括氧化硅。第三隔离材料层33的厚度大于第一隔离材料层31的厚度。第三隔离材料层33的厚度例如在4.0-5.0微米之间，例如，第三隔离材料层33的厚度可以是4.0，4.5或5.0微米。
通过隔离材料层组3可以对衬底1以及第一导电层2起到保护的作用，而且第三隔离材料层33的厚度较厚，可以起到平坦化的作用，为后续形成的第二导电层组10提供一个较好的基底，便于形成厚度较为均匀的第二导电层组10，有利于提高半导体器件的导电均匀性。而且，第三隔离材料层33的厚度较厚可以防止在形成对位凹槽8时刻蚀至第二隔离材料层32，用于保护第二隔离材料层32，防止对位凹槽8暴露出第二隔离材料层32，以提高半导体器件性能。
步骤S40，在所述隔离材料层组3之上形成保护层7，且所述保护层7位于所述对位区域A上。
在本示例实施方式中，参照图5所示，在隔离材料层组3之上通过沉积、溅射或蒸镀等方法形成保护材料层，通过CHF3和O2的混合气体对保护材料层进行蚀刻形成保护层7，保护层7仅形成在对位区域A，在连接区域B没有形成保护层7，即保护层7在衬底1上的正投影仅位于对位区域A内。保护层7的材质例如包括氧化硅，保护层7的厚度在0.4-0.6微米之间，例如，保护层7的厚度可以是0.4，0.5或0.6微米。
步骤S50，对所述隔离材料层组3以及所述保护层7进行蚀刻，对所述保护层7的蚀刻速率小于对所述隔离材料层组3的蚀刻速率，以去除所述连接区域B上的所述隔离材料层组3形成隔离层组4，并在所述对位区域A的所述隔离层组4上形成对位凹槽8，所述对位凹槽8的深度小于所述隔离层组4的厚度。
在本示例实施方式中，参照图6所示，在保护层7之上涂覆形成光刻胶，然后，对光刻胶进行曝光显影，以使光刻胶形成预设图案9，预设图案9仅形成在对位区域A。
参照图6所示，在一些实施例中，该第三隔离材料层33的材料还可以为无定形碳，保护层7还可以为氧化硅。由于保护层7的吸光率小于第三隔离材料层33的吸光率，因此在保护层7上形成光刻胶时，保护层7对光的吸收程度较低，因此保护层7能够减小对光的吸收程度，从而提高图形化的精确度。同时由于无定形碳相对于氧化硅较容易刻蚀，因此有利于后续图形传递。从图6中可以看出，由于第三隔离材料层33的厚度大于保护层7的厚度，因此如果直接在第三隔离材料层33上形成光刻胶时，第三隔离材料层33对光的吸收率较大，且第三隔离材料层33的厚度较厚，因此会降低图形化的精确度。
参照图7所示，对隔离材料层组3以及保护层7进行蚀刻，位于预设图案9下方的隔离层材料组以及保护层7由于有预设图案9的保护均不会被蚀刻；没有预设图案9保护的隔离材料层组3以及保护层7均会被蚀刻。
但是，由于蚀刻气体对保护层7的蚀刻速率小于对隔离材料层组3的蚀刻速率，在同样的蚀刻时间后，在对位区域A由于有保护层7的阻挡，对隔离材料层组3的蚀刻深度较浅；在连接区域B由于没有保护层7的阻挡，对隔离材料层组3的蚀刻深度较深；最终，蚀刻完成后，连接区域B的隔离材料层组3被完全蚀刻去除，隔离材料层组3形成隔离层组4，隔离层组4形成凸块。而对位区域A的没有被预设图案9保护的隔离层组4没有被完全蚀刻去除，只是在第三隔离材料层33上形成对位凹槽8。对位凹槽8的深度不仅小于隔离层组4的厚度，而且对位凹槽8的深度小于第三隔离层43的厚度。对位凹槽8的深度例如在0.4-0.6微米之间，例如，对位凹槽8的深度可以是0.4，0.5或0.6微米。
对隔离材料层组3以及保护层7进行蚀刻的气体可以包括C4F6和O2，C4F6与O2的比例可以为(40-60)：(20-40)，例如为50：30，由于可以调整刻蚀气体的组成比例，因此可以更好的刻蚀隔离材料层组3和保护层7。
由于保护层7的阻挡可以在同一次刻蚀过程中既形成厚度较厚的隔离层组4，又在隔离层组4上形成深度较浅的对位凹槽8，节省了一步刻蚀工艺过程，提高了生产效率，降低了生产成本。
然后，参照图8所示，移除预设图案9，预设图案9的材料是光刻胶，可以通过曝光显影的方法去除，即对预设图案9进行光照，然后通过显影液去除光照后的预设图案9。当然，在本公开的其他一些示例实施方式中，也可以通过灰化工艺移除预设图案9。
最后，移除保护层7，可以通过包括CHF3、O2和CF4的混合气体蚀刻移除剩余的保护层7。
需要说明的是，在一些实施例中，刻蚀气体在对隔离材料层组3进行刻蚀时，刻蚀气体还可以对预设图案9，保护层7进行刻蚀，也就是在形成凹槽8的同时，可以同时移除掉预设图案9和保护层7，从而可以减少刻蚀步骤。
步骤S60，在所述隔离层组4和所述第一导电层2之上形成第二导电层组10，所述第二导电层组10覆盖所述对位凹槽8。
在本示例实施方式中，参照图9所示，在隔离层组4和裸露的第一导电层2之上通过沉积、溅射或蒸镀等方法形成第二导电层组10，第二导电层组10覆盖对位凹槽8。第二导电层组10在衬底1上的正投影位于对位区域A和连接区域B。在连接区域B的第二导电层组10与第一导电层2连接，由此可以实现第一导电层2与外电路的连接。还可以对第二导电层组10进行图案化处理，使得第二导电层组10形成新的连接线路，达到线路重新分布的目的。第二导电层组10的材料例如包括铝。
具体地，首先，可以在隔离层组和第一导电层之上通过沉积、溅射或蒸镀等方法形成钛金属层101；钛金属层101的厚度例如在0.1-0.15微米之间，例如为0.12微米。然后，在钛金属层101之上通过沉积、溅射或蒸镀等方法形成铝金属层102，铝金属层102的厚度例如在4.2-4.7微米之间，例如，铝金属层102的厚度可以为4.2，4.5或4.7微米。然后，在铝金属层102之上通过沉积、溅射或蒸镀等方法形成氮化钛层103，氮化钛层103的厚度例如在0.04-0.06微米之间，例如，氮化钛层103的厚度可以为0.05微米。钛金属层101、铝金属层102和氮化钛层103形成第二导电层组10。
铝金属层102作为重布线层，不容易形成在第三隔离材料层33之上，从而导致铝金属层102容易产生断路；将钛金属层101设置在铝金属层 102和第三隔离材料层33之间，一方面，铝金属层102容易沉积在钛金属层101之上，即钛金属层101可以改善铝金属层102的沉积的粘结性，从而减少铝金属层102由于沉积不够导致的断路情况的发生；另一方面，即使铝金属层102有断路的位置，通过钛金属层101可以连接铝金属层102的断路位置，进一步避免铝金属层102的断路情况的发生，提高产品良率。
另外，由于铝金属层102较厚，因此带来的应力较大，铝金属层102还容易产生翘曲，从而影响导电效果；由于氮化钛的密度较大，将氮化钛层103设置在铝金属层102之上，通过氮化钛的重力可以改善铝金属层102的翘曲度，提高导电效果。
而且三层结构的第二导电层组10阻抗较低，提高半导体器件的导电效果。
需要说明的是，由于凹槽8的深宽比较小，当在凹槽8上形成第二导电层组10时，由于部分第二导电层10位于凹槽8内，因此凹槽8的深宽比会进一步减小，因此当光刻机进行对准时，可以进一步提高对准精度。
当然，在本公开的其他示例实施方式中，第二导电层组10的材料还可以包括铜，根据需要也可在铜线路上镀镍金或者镍钯金。厚铜结构由于具有低电阻、高散热和低成本的优点，成为大电流以及大功率器件的较佳选择。
第二导电层组10还可加大接口之间的间距，提供较大的凸块(隔离层组4)面积，降低基板与元件间的应力，增加元件的可靠性；取代部分线路设计，加速IC芯片(Integrated Circuit Chip)开发时间。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体器件的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
基于同一发明构思，本公开示例实施方式还提供了一种半导体器件，该半导体器件通过上述制备方法制备，参照图9所示，该半导体器件可 以包括衬底1、第一导电层2、隔离层组4以及第二导电层组10；衬底1可以包括对位区域A和连接区域B；第一导电层2设于所述衬底1之上；隔离层组4设于所述第一导电层2之上，且位于所述对位区域A上，所述隔离层组4上设置有对位凹槽8，所述对位凹槽8的深度小于所述隔离层组4的厚度；第二导电层组10设于所述隔离层组4和所述第一导电层2之上，所述第二导电层组10覆盖所述对位凹槽8。
在本示例实施方式中，衬底1可以是已经制备完成的半导体管芯，半导体管芯可以是MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)，简称MOS管，MOS管可以是PMOS(positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)管或NMOS(Negative channel-Metal-Oxide-Semiconductor，N型金属氧化物半导体)管，MOS管可以包括存储电容、位线、字线、栅极、源极和漏极等等。
参照图2所示，衬底1可以包括对位区域A和连接区域B，具体来讲，连接区域B可以设置为两个，两个连接区域B位于对位区域A的两侧。
当然，在本公开的其他示例实施方式中，连接区域B的数量还可以设置为多个，连接区域B的具体位置可以根据需要设置；对位区域A的数量也可以设置为多个，对位区域A的具体位置也可以根据需要设置。
在本示例实施方式中，第一导电层2不仅形成在对位区域A，而且形成在连接区域B。第一导电层2可以与衬底1内的栅极、源极或漏极连接，通过第一导电层2可以向衬底1内的栅极、源极或漏极输入信号，或将衬底1内存储的信号通过第一导电层2输出。第一导电层2的材质例如为铝。第一导电层2的厚度例如在0.6-1.0微米之间，例如，第一导电层2的厚度可以是0.8微米。第一导电层2的材质可以是铜、银等金属。
在本示例实施方式中，隔离层组4可以包括第一隔离层41、第二隔离层42以及第三隔离层43；第一隔离层41设于第一导电层2之上；第二隔离层42设于第一隔离层41之上；第三隔离层43设于第二隔离层42之上，第三隔离层43的厚度大于第一隔离层41的厚度。
第一隔离层41的材质例如包括氧化硅，第一隔离层41的厚度例如在0.6-1.0微米之间，例如，第一隔离层41的厚度可以是0.8微米。
第二隔离层42的材质例如包括氮化硅，第二隔离层42的厚度例如0.5-0.7微米之间，例如，第二隔离层42的厚度可以是0.6微米。
第三隔离层43的材质例如包括氧化硅，第三隔离层43的厚度例如在4.0-5.0微米之间，例如，第三隔离层43的厚度可以是4.5微米。
隔离层组4仅形成在对位区域A，即隔离层组4在衬底1上的正投影仅位于对位区域A。
通过隔离材料组4可以对衬底1以及第一导电层2起到保护的作用，而且第三隔离层43的厚度较厚，可以起到平坦化的作用，为后续形成的第二导电层组10提供一个较好的基底，便于形成厚度较为均匀的第二导电层组10，有利于提高半导体器件的导电均匀性。而且，第三隔离层43的厚度较厚可以防止在形成对位凹槽8时刻蚀至第二隔离层42，用于保护第二隔离层42，防止对位凹槽8暴露出第二隔离层42，以提高半导体器件性能。
在本示例实施方式中，对位凹槽8设置在第三隔离层43上，没有设置在第二隔离层42和第一隔离层41上，对位凹槽8的深度小于第三隔离层43的厚度，因此，对位凹槽8的深度较浅，深宽比较小，当光刻机在进行对准时，光刻机发出的激光射至对位凹槽8后在对位凹槽8内的反射次数较少，就会减小激光的误差，从而提高激光的对准精度，使得光刻机可以很好地通过对位凹槽8进行对准，改善光刻机对准失败的问题；而且，深度较浅的对位凹槽8的槽底部不容易形成倾斜结构，同样有利于光刻机通过对位凹槽8进行对准和曝光。对位凹槽8的深度大于等于0.4微米且小于等于0.6微米，例如，对位凹槽8的深度可以是0.5微米。
在本示例实施方式中，对位凹槽8设置为两个，相邻两个对位凹槽8之间设置有隔离壁，且对位凹槽8的最外侧也设置有隔离壁。当然，对位凹槽8的数量以及结构可以根据需要设置为多个，而且，多个对位凹槽8之间可以平行设置，也可以交叉设置，形成要求的对位图案。
在本示例实施方式中，第二导电层组10设于隔离层组4和第一导电 层2之上，第二导电层组10覆盖所述对位凹槽8，即第二导电层组10在衬底1上的正投影位于对位区域A和连接区域B。在连接区域B的第二导电层组10与第一导电层2连接。还可以对第二导电层组10进行图案化处理，使得第二导电层组10形成新的连接线路，达到线路重新分布的目的。
具体地，第二导电层组10可以包括钛金属层101、铝金属层102以及氮化钛层103；钛金属层101设于隔离层组和第一导电层之上；铝金属层102设于钛金属层101之上；氮化钛层103设于铝金属层102之上。钛金属层101的厚度例如为0.1微米。铝金属层102的厚度例如在4.2-4.7微米之间，，例如，铝金属层102的厚度可以为4.5微米。氮化钛层103的厚度例如在0.04-0.06微米之间，例如，氮化钛层103的厚度可以为0.05微米。钛金属层101、铝金属层102和氮化钛层103形成第二导电层组10。
铝金属层102作为重布线层，不容易形成在第三隔离材料层33之上，从而导致铝金属层102容易产生断路；将钛金属层101设置在铝金属层102和第三隔离材料层33之间，一方面，铝金属层102容易沉积在钛金属层101之上，即钛金属层101可以改善铝金属层102的沉积的粘结性，从而减少铝金属层102由于沉积不够导致的断路情况的发生；另一方面，即使铝金属层102有断路的位置，通过钛金属层101可以连接铝金属层102的断路位置，进一步避免铝金属层102的断路情况的发生，提高产品良率。
另外，由于铝金属层102较厚，因此带来的应力较大，铝金属层102还容易产生翘曲，从而影响导电效果；由于氮化钛的密度较大，将氮化钛层103设置在铝金属层102之上，通过氮化钛的重力可以改善铝金属层102的翘曲度，提高导电效果。
而且三层结构的第二导电层组10阻抗较低，提高半导体器件的导电效果。
当然，在本公开的其他示例实施方式中，第二导电层组10的材料还可以是铜，根据需要也可在铜线路上镀镍金或者镍钯金。厚铜结构由于具有低电阻、高散热和低成本的优点，成为大电流以及大功率器件的最 佳选择。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种半导体器件的制备方法，其中，包括：
    提供一衬底，包括对位区域和连接区域；
    在所述衬底之上形成第一导电层；
    在所述第一导电层之上形成隔离材料层组；
    在所述隔离材料层组之上形成保护层，且所述保护层位于所述对位区域上；
    对所述隔离材料层组以及所述保护层进行蚀刻，对所述保护层的蚀刻速率小于对所述隔离材料层组的蚀刻速率，以去除所述连接区域上的所述隔离材料层组形成隔离层组，并在所述对位区域的所述隔离层组上形成对位凹槽，所述对位凹槽的深度小于所述隔离层组的厚度；
    在所述隔离层组和所述第一导电层之上形成第二导电层组，所述第二导电层组覆盖所述对位凹槽。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，对所述隔离层组以及所述保护层进行蚀刻的气体包括：C4F6和O2。
  3. 根据权利要求1所述的半导体器件的制备方法，其中，在所述第一导电层之上形成隔离材料层组，包括：
    在所述第一导电层之上形成第一隔离材料层；
    在所述第一隔离材料层之上形成第二隔离材料层；
    在所述第二隔离材料层之上形成第三隔离材料层，所述第三隔离材料层的厚度大于所述第一隔离材料层的厚度。
  4. 根据权利要求3所述的半导体器件的制备方法，其中，形成所述对位凹槽的步骤包括：
    移除所述保护层和部分所述第三隔离材料层，以在所述第三隔离材料层上形成所述对位凹槽。
  5. 根据权利要求1所述的半导体器件的制备方法，其中，在形成所述第二导电层组之前，还包括移除所述保护层。
  6. 根据权利要求1所述的半导体器件的制备方法，其中，形成所述第二导电层组包括形成多层导电层。
  7. 根据权利要求6所述的半导体器件的制备方法，其中，所述在所 述隔离层组和所述第一导电层之上形成第二导电层组包括：
    在所述隔离层组和所述第一导电层之上形成钛金属层；
    在所述钛金属层之上形成铝金属层；
    在所述铝金属层之上形成氮化钛层。
  8. 根据权利要求1所述的半导体设备的制备方法，其中，所述连接区域位于所述对位区域的两侧。
  9. 一种半导体器件，其中，包括：
    衬底，包括对位区域和连接区域；
    第一导电层，设于所述衬底之上；
    隔离层组，设于所述第一导电层之上，且位于所述对位区域上，所述隔离层组上设置有对位凹槽，所述对位凹槽的深度小于所述隔离层组的厚度；
    第二导电层组，设于所述隔离层组和所述第一导电层之上，所述第二导电层组覆盖所述对位凹槽。
  10. 根据权利要求9所述的半导体器件，其中，所述隔离层组包括：
    第一隔离层，设于所述第一导电层之上；
    第二隔离层，设于所述第一隔离层之上；
    第三隔离层，设于所述第二隔离层之上，所述第三隔离层的厚度大于所述第一隔离层的厚度。
  11. 根据权利要求10所述的半导体器件，其中，所述对位凹槽的深度小于所述第三隔离层的厚度。
  12. 根据权利要求9所述的半导体器件，其中，所述对位凹槽的深度在0.4-0.6微米之间。
  13. 根据权利要求9所述的半导体器件，其中，所述第二导电层组包括多层导电层。
  14. 根据权利要求13所述的半导体器件，其中，所述第二导电层组包括：
    钛金属层，设于所述隔离层组和所述第一导电层之上；
    铝金属层，设于所述钛金属层之上；
    氮化钛层，设于所述铝金属层之上。
  15. 根据权利要求14所述的半导体器件，其中，所述钛金属层的厚度在0.1-0.15微米之间，所述铝金属层的厚度在4.2-4.7微米之间，所述氮化钛层的厚度在0.04-0.06微米之间。
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CN106597818A (zh) * 2015-10-19 2017-04-26 无锡华润上华科技有限公司 对位标记、形成对位标记的方法及半导体器件
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