TW200931490A - Semiconductor structure having alignment marks and method of forming the same - Google Patents
Semiconductor structure having alignment marks and method of forming the same Download PDFInfo
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200931490 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構及其製法，且特別是 有關於具有對準標記之半導體結構及其製法。 【先前技彳标】 隨著半導體製程的快速發展’可整合越來越多的電子 ⑩ 元件至一單一晶片中。而用以電性連接這些電子元件的金 屬内連線圖案也變得更為複雜。為了增加元件的高操作速 度且不增加金屬内連線所佔據的晶片範圍，通常會採用多 層金屬化(multi-level metallization)結構。多層金屬化結構 包括許多層的金屬内連線、介於金屬内連線間用以絕緣的 金屬間介電層、以及用以電性連接不同層金屬間之内連線 的介層窗插塞(via plug)。 由於積體電路結構中電路元件的密度不斷地增加，且 〇 元件尺寸不斷地縮小，精準地將光罩對準至晶圓上的正確 位置以使每一層材料皆具有正確的圖案且彼此準確地對 齊，對於積體電路的效能及可靠度顯得格外重要。為了能 準確地對準，通常使用前一層圖形所預留的對準標記 (alignment mark)來進行定位，而使步進機（stepper)能於正 確的位置轉移光罩上的電路圖案至晶圓上。對準標記通常 是形成於晶圓上的凹槽，使來自步進機的光線(例如是可見 光或雷射光）產生繞射。這些標記會對光線造成不同程度 的繞射，這些訊號可由步進機接收，而定位出正確的曝光200931490 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having alignment marks and a method of fabricating the same. [Previous technical standards] With the rapid development of semiconductor processes, more and more electronic components can be integrated into a single wafer. Metal interconnect patterns for electrically connecting these electronic components have also become more complicated. In order to increase the high operating speed of the components without increasing the range of wafers occupied by the metal interconnects, a multi-level metallization structure is typically employed. The multi-layer metallization structure comprises a plurality of layers of metal interconnects, an inter-metal dielectric layer interposed between the metal interconnects, and a via plug for electrically connecting the interconnects between the different layers of metal. (via plug). Since the density of circuit components in the integrated circuit structure is continuously increasing, and the size of the germanium components is continuously reduced, the photomasks are precisely aligned to the correct positions on the wafer so that each layer of material has the correct pattern and is accurate to each other. Alignment is especially important for the performance and reliability of integrated circuits. In order to be accurately aligned, the alignment mark reserved by the previous layer of the pattern is usually used for positioning, and the stepper can transfer the circuit pattern on the mask to the wafer at the correct position. on. The alignment marks are typically grooves formed on the wafer that illuminate light from the stepper, such as visible light or laser light. These markers cause different degrees of diffraction to the light, and these signals can be received by the stepper to locate the correct exposure.
Client’s Docket Ν〇·:96-023 TT5s Docket No:0492-A41291-TW/f/JYChen 5 200931490 位置。曝光光罩便能藉以調整，而將電路圖案轉移到晶圓 上預定的精確位置。 在積體電路的金屬化製程中，.常使用化學機械研磨 (chemical-mechanical polishing,CMP)，去除介層窗以外多 餘的金屬。然而’常用的化學機械研磨的漿料容易會有污 染物或研磨顆粒附著在對準標記中，而影響後續的對準結 果。此外’在形成各圖案化材料層之後’用以監控圖案是 否俦#的叠合禪f己(overlay mark)i|常亦吾有一定的深度， ❹ 而容易遭遇與對準標記類似的問題。 因此，業界亟需針對化學機械研磨顆粒殘留在對準標 記或疊合標記的問題提出改良。 ， 【發明内容】 本發明提供一種具有對準標記之半導體結構，包括半導 體基板，其包括元件區及對準標記區，位於元件區上之導 ❹ 線層，位於對準標記區上之閒置圖案，其中閒置圖案與導 線層位於同一層，覆蓋導線層及閒置圖案之金屬間介電 層，以及對準標記凹槽，形成於金屬間介電層中， 閒置圖案。 路出 本發明另提供-種具有對準標記之半導體結構的形 法，包括提供半導體基板，包括元件區及對準標纪區、 元件區與對準標記區分別形成導線層及閒置圖案，^ ; 置圖案與導線層位於同一層，形成金屬間介電層'，^莒蜀 線層及閒置圖案，以閒置圖案為終止層來餘刻二二Client’s Docket Ν〇·:96-023 TT5s Docket No:0492-A41291-TW/f/JYChen 5 200931490 Location. The exposure mask can then be adjusted to transfer the circuit pattern to a predetermined precise location on the wafer. In the metallization process of the integrated circuit, chemical-mechanical polishing (CMP) is often used to remove excess metal outside the via. However, conventional chemical mechanically ground slurries tend to have contaminants or abrasive particles attached to the alignment marks, which affect subsequent alignment results. Further, the 'overlay mark i| used to monitor the pattern after the formation of each layer of the patterned material is often a certain depth, and it is easy to encounter a problem similar to the alignment mark. Therefore, there is an urgent need in the industry to improve the problem of chemical mechanical polishing particles remaining in alignment marks or superimposed marks. SUMMARY OF THE INVENTION The present invention provides a semiconductor structure having alignment marks, including a semiconductor substrate including an element region and an alignment mark region, a conductive layer on the element region, and an idle pattern on the alignment mark region. The idle pattern is located on the same layer as the wire layer, and the inter-metal dielectric layer covering the wire layer and the idle pattern, and the alignment mark groove are formed in the inter-metal dielectric layer, and the pattern is idle. The invention further provides a method for forming a semiconductor structure having an alignment mark, comprising providing a semiconductor substrate, including an element region and an alignment mark region, an element region and an alignment mark region respectively forming a wire layer and an idle pattern, The pattern is placed on the same layer as the wire layer to form an inter-metal dielectric layer, a layer of 莒蜀 and an idle pattern, with the idle pattern as the termination layer.
Client's DocketN〇.:96-023 日1 )| 電 TT's Docket No:0492-A41291-TW/f/JYChen 200931490 層以形成對準標記凹槽。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 本發明在此提供一種具有對準標記之半導體結構及其 製法’主要係包括利用前後層光罩複合而成具有較小深度 ❹ 或落差的對準標記來改善研磨微粒或污染物殘留的問題。 雖然於下文之敘述中，對於實施例之描述主要是針對曝光 時之對準標記(alignment mark)，然此技藝人士當可明瞭對 於可用於監控圖案偏移之疊合標記(overlaymark)亦可以本 發明之實施例所述之方法解決。因此，下文中所有關於改 善對準標記之實施方式，當可完全適用於疊合標記之應 用。而於申請專利範圍中所用之“對準標記”同理地亦指 廣泛定義地包含曝光時之對準標記或疊合標記等。 ❾ 第1A-1D圖為一系列剖面圖，用來說明發明人所知的 一種形成介層窗插塞與對準標記凹槽的製造過程。但應注 意的是’以下的說明並非此技術領域之公知常識，僅用來 顯示發明人所發現的問題。 如第1A圖所示，在具有元件區110及對準標記區120 之半導體基板100上，形成有鋁導線層112於元件區110。 於半導體基板100上並沉積有介電層114而覆蓋鋁導線層 112。接著如第1B圖所示，利用例如微影及银刻之方式圖 案化介電層114以形成介層窗開口 116而露出部分的鋁導Client's DocketN〇.:96-023 Day 1)|Electric TT's Docket No:0492-A41291-TW/f/JYChen 200931490 Layers to form alignment mark grooves. The above and other objects, features and advantages of the present invention will become more <RTIgt; A semiconductor structure having alignment marks and its method of manufacture mainly includes the use of alignment masks having a small depth ❹ or drop composited by a front and back layer reticle to improve the problem of abrasive particles or contaminant residue. Although in the following description, the description of the embodiment is mainly directed to the alignment mark at the time of exposure, it is clear to those skilled in the art that the overlay mark which can be used for monitoring the pattern shift can also be used. The method described in the embodiments of the invention is solved. Therefore, all of the following embodiments for improving the alignment mark are fully applicable to the application of the overlay mark. The "alignment mark" used in the scope of the patent application also refers to a broadly defined alignment mark or superimposed mark or the like at the time of exposure. ❾ 1A-1D is a series of cross-sectional views illustrating a manufacturing process for forming a via plug and alignment mark recess as known to the inventors. However, it should be noted that the following description is not a common knowledge in this technical field and is only used to show the problems discovered by the inventors. As shown in FIG. 1A, on the semiconductor substrate 100 having the element region 110 and the alignment mark region 120, an aluminum wire layer 112 is formed on the element region 110. The aluminum wiring layer 112 is covered on the semiconductor substrate 100 and deposited with a dielectric layer 114. Next, as shown in FIG. 1B, the dielectric layer 114 is patterned by, for example, lithography and silver etching to form a via opening 116 to expose a portion of the aluminum guide.
Client’s Docket No. :96-023 TT's Docket No:0492-A41291-TW/f/JYChen n 200931490 線層112，並同時也於對準標記區12〇中形成對準標記凹 槽126(alignment mark 〇pening)。在以蝕刻方式圖案化介電 層114以形成介層窗開口 116時，為了確認鋁導線層 上沒有任何介電材料殘留，一般會進行一道過姓刻（over 二tch)以確保後續填人金屬而形成之介層窗插塞(via p㈣能 電性連接上下層金屬層。而對準標記區12〇中之對準標記 凹槽126之深度會因過钱刻（〇ver etching)步驟的影響而具 介層宣開口 II6遷赛農 著请參照第1C圖’沉積鎢金屬層118於半導體基板100 上以填滿介層窗開口 116。由於對準標記凹槽126之寬度 遠大於介層窗開口 116，所以鎢金屬層118僅順應性地覆 蓋在對準標記凹槽126中而使其深度略減為h2(如第1D圖 中所標示）。接著進行鎢金屬層118之化學機械研磨，研磨 將持續進行以磨除多餘的鎢金屬直至露出介電層114而形 成介層窗插塞118a，如第1D圖所示。然而，研磨漿料中 @ 之微粒或污染物124很容易於此時掉入對準標記凹槽126 中’且由於過蝕刻（over etch)步驟的影響，使對準摞記凹槽 126之深度h2很深，例如約略大於〇.9微米。雖然一般會 使用研磨布來清除化學機械研磨後所於留下之微粒或污染 物’然而過深的對準標記凹槽126往往大於研磨布所能清 理的極限’因此無法清除凹槽中之微粒或污染物。殘留的 微粒或污染物會影響對準標記所繞射的訊號，減低下一層 光罩圖案的準確性。層與層之間圖案彼此對位不準將影響 元件的效能與良率。Client's Docket No. : 96-023 TT's Docket No: 0492-A41291-TW/f/JYChen n 200931490 The line layer 112, and also forms an alignment mark groove 126 in the alignment mark area 12〇 (alignment mark 〇pening) ). When the dielectric layer 114 is patterned in an etched manner to form the via opening 116, in order to confirm that there is no residual dielectric material on the aluminum wiring layer, a common over-etch (over two tch) is generally performed to ensure subsequent filling of the metal. The formed via plug (via p (4) can electrically connect the upper and lower metal layers. The depth of the alignment mark recess 126 in the alignment mark region 12" is affected by the 〇ver etching step. Referring to FIG. 1C, a deposited tungsten metal layer 118 is deposited on the semiconductor substrate 100 to fill the via opening 116. The width of the alignment mark recess 126 is much larger than the via window. Opening 116, so tungsten metal layer 118 only conformally covers the alignment mark recess 126 to slightly reduce its depth to h2 (as indicated in Figure 1D). Chemical mechanical polishing of the tungsten metal layer 118 is then performed, The grinding will continue to remove excess tungsten metal until the dielectric layer 114 is exposed to form the via plug 118a, as shown in Figure 1D. However, the particles or contaminants 124 in the slurry are readily susceptible to this. When falling into the alignment mark groove 126' Due to the influence of the over etch step, the depth h2 of the alignment recess 126 is deep, for example, approximately greater than 9.9 μm, although abrasive cloth is generally used to remove the chemical mechanical polishing. Particles or contaminants 'however too deep the alignment mark grooves 126 tend to be larger than the limit that the cloth can clean.' Therefore, it is impossible to remove particles or contaminants in the grooves. Residual particles or contaminants can affect the alignment marks. The signal is shot to reduce the accuracy of the next layer of mask pattern. The alignment of the layers between layers will not affect the performance and yield of the component.
Client’s Docket Ν〇·:96-023 TT’s Docket No:〇492-A41291-TW/fiTrchen g 200931490 第2A-2E圖為一系列剖面圖，用來說明本發明之一實 施例中，形成對準標記凹槽及介層窗插塞的製造過程。如 第2A圖所示，在一半導體基板200上可分為元件區21〇 與對準標記區220。元件區210的基板中可包括各種主動 元件、被動元件、元件間的導電通路、及介電材料層等， 係藉著例如金屬層、介電層、及半導體層等層與層之間相 互對準匹配堆豐而成為簡化圖不，此處予以省略。____般 一#料層與T 一落積層Η孓對準J：依用41步邊迦wafer stepper)將光罩（reticle)的電路圖案轉移至半導體基板上之 材料層上。然而’在光罩上之電路圖案轉移至基板前，晶 圓必須先相對於光罩準確地放置或對準。而通常位於晶圓 中晶粒與晶粒間的切割道上之對準標記區220,可形成有 對準標記（alignment mark)，這些標記通常是由數個凹槽形 成’步進機就疋利用對準標記區220中這些對準標記凹槽 之南度差所產生的繞射光線差異，來定位出正確的曝光方 位，一旦完成對準，便能將光罩上的電路圖案正確地投影 轉移至半導體基板200上。 首先’如第2A圖所示，在半導體基板2〇〇形成金屬層 212。金屬層212可由物理氣相沉積或電鍍來形成，可例如 是鋁、銅、金、或前述之組合。接著如第2B圖所示，利 用例如微影及蝕刻的方式’圖案化金屬層212以分別於元 件區210形成導線層212a以及於對準標記區220形成閒置 圖案212b。閒置圖案212b將在後續作為一钱刻終止層， 藉以控制隨後將形成的對準標記凹槽之深度。在形成閒置Client's Docket Ν〇:: 96-023 TT's Docket No: 〇 492-A41291-TW/fiTrchen g 200931490 Figure 2A-2E is a series of cross-sectional views illustrating the formation of alignment marks in one embodiment of the present invention. The manufacturing process of the slot and the via window plug. As shown in Fig. 2A, the semiconductor substrate 200 can be divided into an element region 21A and an alignment mark region 220. The substrate of the element region 210 may include various active elements, passive elements, conductive paths between the elements, and a layer of dielectric material, etc., by layers such as a metal layer, a dielectric layer, and a semiconductor layer. The quasi-matching stack is a simplified diagram and is omitted here. ____ Like a #层层与T一落层层Η孓J: The 41-step wafer stepper) is used to transfer the circuit pattern of the reticle onto the material layer on the semiconductor substrate. However, before the circuit pattern on the reticle is transferred to the substrate, the crystal must first be accurately placed or aligned with respect to the reticle. The alignment mark region 220, which is usually located on the scribe line between the die and the die in the wafer, may be formed with alignment marks, which are usually formed by a plurality of grooves. Aligning the difference of the diffracted rays generated by the south difference of the alignment mark grooves in the mark area 220 to locate the correct exposure direction, once the alignment is completed, the circuit pattern on the photomask can be correctly projected and transferred. On the semiconductor substrate 200. First, as shown in Fig. 2A, a metal layer 212 is formed on the semiconductor substrate 2. Metal layer 212 may be formed by physical vapor deposition or electroplating, and may be, for example, aluminum, copper, gold, or a combination of the foregoing. Next, as shown in Fig. 2B, the metal layer 212 is patterned by, for example, lithography and etching to form the wiring layer 212a in the element region 210 and the idle pattern 212b in the alignment mark region 220, respectively. The idle pattern 212b will be subsequently used as a stop layer to control the depth of the alignment mark grooves that will be subsequently formed. In the formation of idle
Clients Docket No. :96-023 TT’s Docket N〇:0492-A41291-TW/CTYChen 200931490 圖案212b後，形成金屬間介電層214於半導體基板200 上以作為金屬層與金屬層之間的絕緣。常用的金屬間介電 層214例如有氧化碎、填石夕玻璃（ph〇sphosilicate glass, PSG)、侧石夕玻璃（borosilicate glass, BSG)、棚構石夕玻璃 (borophosphosilicate glass，BPSG)、或前述之組合。此外， 也可為低介電常數層，例如無機介電材料、有機介電材料、 多孔洞之介電材料、有機聚合物、有機矽石玻璃、氟化矽 毯導(FSG)、包盤石、免 類（HydrogenClients Docket No.: 96-023 TT's Docket N〇: 0492-A41291-TW/CTYChen 200931490 After the pattern 212b, an intermetal dielectric layer 214 is formed on the semiconductor substrate 200 to serve as insulation between the metal layer and the metal layer. The commonly used intermetal dielectric layer 214 is, for example, oxidized ash, ph〇sphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or Combination of the foregoing. In addition, it may also be a low dielectric constant layer, such as an inorganic dielectric material, an organic dielectric material, a porous dielectric material, an organic polymer, an organic vermiculite glass, a fluorinated ruthenium blanket (FSG), a coated stone, Free class (Hydrogen
Silsesquioxane)系列之材料、含甲基的石夕酸鹽類 (Methylsilsesquioxane簡稱MSQ)系列之材料、多孔洞之有 機系列材料、或前述之組合。^可利用化學氣相沉積（CVD) 或旋塗(spin_on)方式來形成金屬間介電層214。 接著，如第2C圖所示，例如以微影及蝕刻方式圖案化 金屬間介電層214以形成介層窗開口 216於元件區210而 露出部分的導線層212a，以及形成對準標記凹槽226於對 準標記區220而露出部分的閒置圖案212b，其中對準標記 凹槽226可作為曝光時之對準標記(alignment mark)或是用 來監控圖案偏移的疊合標記(overlay mark)。另外，在形成 w層由開口 216與對準標記凹槽226前，亦可視需要先對 金屬間介電層214進行化學機械研磨平坦化，以利之後的 曝光步驟。如前文所述，為了減小阻容遲滯(RC dela力對元 件操作速度的影響，介層窗開口 216往往具有很深的深 度，例如約0.9微米。且在以蝕刻方式形成介層窗開口 216 時，往往會刻意過蝕刻（over_etch)來確保完全移除金屬間介Materials of the Silsesquioxane series, materials containing methyl group of Methylsilsesquioxane (MSQ), organic series of porous holes, or a combination thereof. The inter-metal dielectric layer 214 can be formed by chemical vapor deposition (CVD) or spin-on. Next, as shown in FIG. 2C, the inter-metal dielectric layer 214 is patterned, for example, by lithography and etching to form a via opening 216 in the element region 210 to expose a portion of the wire layer 212a, and an alignment mark groove is formed. The portion 226 is exposed to the mark region 220 to expose a portion of the idle pattern 212b, wherein the alignment mark groove 226 can be used as an alignment mark during exposure or an overlay mark for monitoring pattern shift. . In addition, before the formation of the w layer by the opening 216 and the alignment mark recess 226, the inter-metal dielectric layer 214 may be first subjected to chemical mechanical polishing to facilitate the subsequent exposure step. As previously mentioned, in order to reduce the RC delay (the effect of the RC dela force on the operating speed of the component, the via opening 216 tends to have a deep depth, such as about 0.9 microns. And the via opening 216 is formed in an etched manner. At times, it is often deliberately over-etched to ensure complete removal of intermetallic
Client’s Docket No. :96-023 TT's Docket No：0492-A41291-TW/i7JYChen 200931490 電材料。在一實施例中，介層窗開口 216之口徑約小於 微米，其深度約小於0.9微米。在蝕刻形成對^標^^ 0·4 226時’由於已先於對準標記區22()上形成可作& = 止層之閒置圖案212b’因此形成介層窗開口 216所承^ 蝕刻步驟不會使對準標記凹槽226之深度增加。這=之過 在前次金屬層212圖案化時，於對準標記區22〇所留=於 閒置圖案212b不易被金屬間介電層214之蝕刻劑所蝕办之 性却I鋅或1，1坐態太柢藶疫對準遜t己凹撞226孓 H1 ’改善深度H1易因過钱刻步驟而變深之問題。在一 施例中，對準標記凹槽226之寬度約略大於3微米，其= 度H1約略小於〇.9微米。對準標記凹槽226之深度^ 藉著閒置圖案212b之高度來作調整。 又 ° 閒置圖案212b之寬度不小於對準標記凹槽226，較佳 是大於對準標記凹槽226之寬度。例如閒置圖案212b之寬 度可大於對準標記凹槽226約1.5微米。 隨後如第2D圖所示’可例如以物理氣相沉積或電鍍方 式形成金屬層218於半導體基板200上’金屬層218 填 滿介層窗開口 216並順應性地覆蓋在對準標記凹槽226之 侧壁與底部，使對準標記凹槽之深度略減為H2(如第2£圖 所標示）。金屬層218可例如選甩鎢、鋁、銅、金、或前述 之組合。除此之外，例如選用鎢金屬來作為連接上下層金 屬層之介層窗插塞時，亦可在填入鶴金屬前，先沉積由一 層欽/氮化欽（未顯不）所構成的接觸金屬層與阻障層（或黏 著層）以利後續形成鎢插塞。Client’s Docket No. :96-023 TT's Docket No:0492-A41291-TW/i7JYChen 200931490 Electrical materials. In one embodiment, the via opening 216 has a diameter of less than about microns and a depth of less than about 0.9 microns. When etching forms a pair of ^^0·4 226', since the idle pattern 212b' which can be used as the & = stop layer is formed before the alignment mark region 22 (), the via opening 216 is formed. The step does not increase the depth of the alignment mark groove 226. This is the case where the alignment of the previous metal layer 212 is left in the alignment mark region 22, and the idle pattern 212b is not easily etched by the etchant of the intermetal dielectric layer 214, but I zinc or 1, 1 sitting state too plague to align t have a concave 226 孓 H1 'improve the depth H1 easy to deepen due to the money engraving step. In one embodiment, the width of the alignment mark recess 226 is approximately greater than 3 microns, which = degree H1 is approximately less than 〇.9 microns. The depth of the alignment mark groove 226 is adjusted by the height of the idle pattern 212b. Further, the width of the idle pattern 212b is not less than the alignment mark groove 226, preferably larger than the width of the alignment mark groove 226. For example, the width of the idle pattern 212b can be greater than about 1.5 microns of the alignment mark recess 226. The metal layer 218 can then be formed, for example, by physical vapor deposition or electroplating on the semiconductor substrate 200 as shown in FIG. 2D. The metal layer 218 fills the via opening 216 and conformally covers the alignment mark recess 226. The side walls and the bottom are such that the depth of the alignment mark groove is slightly reduced to H2 (as indicated by the second figure). Metal layer 218 can be, for example, selected from the group consisting of tungsten, aluminum, copper, gold, or a combination of the foregoing. In addition, for example, when tungsten metal is used as the interlayer window plug connecting the upper and lower metal layers, it may be deposited by a layer of chin/nitriding (not shown) before filling the crane metal. The metal layer and the barrier layer (or adhesive layer) are contacted to facilitate subsequent formation of a tungsten plug.
Client’s Docket No. :96-023 TTss Docket No:0492-A41291-TW/^JYChen 200931490 接著，如第2E圖所示，實施介層窗金屬之化學機械研 磨以移除過多的金屬層218直至露出金屬間介電層214而 形成介層窗插塞218a。然而，應注意的是，化學機械研磨 往往會使用含有例如氧化矽或氧化鋁之微粒的漿料來磨 平，這些微粒及污染物很容易掉入對準標記凹槽226中而 影響後續對準。在本發明之實施例中，由於對準標記凹槽 226在介層窗CMP後之深度H2可由下方之閒置圖案212b 來鸯高，因此可|地使用研糜布或基他清薄方绛來將含 〇 留於對準標記凹槽226中之微粒及污染.物清除，解決對準 標記凹槽226因深度太深，而無法清除内部微粒及污染物 的問題，更進一步地提升步進機對準之精度而提升產品的 良率。 雖然在上述實施例中，閒置圖案212b較佳是在金屬層 212之圖案化時與導線層212a同時形成而大抵與導線層 212a等高，然而在其他實施例中，亦可藉由額外的沉積與 蝕刻製程，使用與導線層212不同的材料層圖案化來形 ® 成。例如，使用不同於金屬層212之其他金屬層或其他非 金屬材料層來形成閒置圖案212b。在此情況下，可獨立調 整閒置圖案212b的高低，以控制對準標記凹槽226之课度 H2，使其更符合製程需求且易於清除其中因化學機械研磨 製程而殘留的微粒或污染物，而增加對準之精度以提升產 品的品質。本發明除了可改善對準標記中微粒或污染物殘 留的問題，亦能改善例如疊合標記(overlay mark)或其他具 有較大深度之半導體結構中的微粒殘留問題。疊合標記通Client's Docket No. : 96-023 TTss Docket No: 0492-A41291-TW/^JYChen 200931490 Next, as shown in FIG. 2E, chemical mechanical polishing of the via metal is performed to remove excess metal layer 218 until the metal is exposed. The dielectric layer 214 is formed to form a via plug 218a. However, it should be noted that chemical mechanical polishing tends to be smoothed using a slurry containing particles such as cerium oxide or aluminum oxide, which easily fall into the alignment mark recess 226 to affect subsequent alignment. . In the embodiment of the present invention, since the depth H2 of the alignment mark groove 226 after the via CMP can be raised by the underlying idle pattern 212b, the mortar cloth or the ketal can be used. The particles and the contamination contained in the alignment mark groove 226 are removed, and the problem that the alignment mark groove 226 is too deep to remove internal particles and contaminants is solved, thereby further improving the stepping machine. Improve the yield of the product by the accuracy of the alignment. Although in the above embodiment, the idle pattern 212b is preferably formed simultaneously with the wire layer 212a at the time of patterning of the metal layer 212 and is substantially equal to the wire layer 212a, in other embodiments, additional deposition may be used. In contrast to the etching process, a layer of material different from the wire layer 212 is patterned to form. For example, the other metal layer or other non-metal material layer different from the metal layer 212 is used to form the idle pattern 212b. In this case, the height of the idle pattern 212b can be independently adjusted to control the degree H2 of the alignment mark groove 226 to make it more in line with the process requirements and to easily remove particles or contaminants remaining in the chemical mechanical polishing process. Increase the accuracy of the alignment to improve the quality of the product. In addition to improving the problem of particulate or contaminant retention in the alignment mark, the present invention can also improve particle retention problems in, for example, overlay marks or other semiconductor structures having greater depth. Overlapping mark
Client’s Docket N〇.:96-023 TT，s Docket No:0492-A41291-TW/£7YChen 12 200931490 常是在形成圖案化材料層後，用以監控卿成之圖案是否 偏移。因此，亦可使_似於本發明實施觸述之方法， 於2 口m方形一置圖案’以解決疊合標記中可能的 污染物殘留問題。 雖然本發明已以數個較佳實施例揭露如上，然其並非 用以限定本發明’任何技術領域中具有 在不脫離本發明之精神釦仏闽七丸n r矛範圍内’當可作任意之更動盥潤 飾，因此本發明之保護益固木、μ ^ Ο 參 —土 7 : 一 — f 宣視*毯1之申赞專利範圍所界 疋有马率。 i 【圖式簡單說明】 第ΙΑ-iD圖為—系列剖面圖，用來 塞與對準標記凹槽的製造過程。 第2A-2E圖為一系列a丨丨；sj . 夕面圖，用來說明本發明之一實 施例中，形成對準標記凹择 氕及介層窗插塞的製造過程。 【主要元件符號說明】 100〜半導體基板；11〇〜 ^ & a 人 几件區，120〜對準標記區；112、 銘導線層；mi電層；116〜介層窗開口 凹槽旧〜鎢金屬層；118a〜介層窗插塞；h〜賴丰^ 微粒或巧染物；謂〜半導體基板;_〜元件區；220〜對準Client’s Docket N〇.:96-023 TT,s Docket No:0492-A41291-TW/£7YChen 12 200931490 It is often used to monitor the pattern of the patterned material after it is formed. Therefore, it is also possible to solve the problem of possible residual contaminants in the superimposed marks by the method of performing the tactile method according to the present invention by placing a pattern on a 2-m square. Although the present invention has been disclosed above in several preferred embodiments, it is not intended to limit the invention in any of the technical fields without departing from the spirit of the invention. More 盥 盥 , , , , , , , , , , 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本i [Simple description of the diagram] The ΙΑ-iD diagram is a series of sectional views for the manufacturing process of the plug and alignment mark grooves. Fig. 2A-2E is a series of a 丨丨; sj. 夕 图 diagrams for explaining the manufacturing process of forming the alignment mark recess and the via plug in an embodiment of the present invention. [Main component symbol description] 100~ semiconductor substrate; 11〇~^ & a person several pieces of area, 120~ alignment mark area; 112, Ming wire layer; mi electric layer; 116~ via window opening groove old ~ Tungsten metal layer; 118a~ via window plug; h~ Laifeng ^ particles or fine dye; said ~ semiconductor substrate; _ ~ component area; 220 ~ alignment
標記區；212~金屬層；2l2a〜導綠M ‘ ,10U 等綠層，212b〜閒置圖幸；214〜 金屬間介電層；216〜介層窗開 ’、 ®開口，226〜對準標記凹槽；H1、 H2〜深度；218〜金屬層；21.介層窗插塞。槽Marked area; 212~ metal layer; 2l2a~ green M', 10U green layer, 212b~ idle picture; 214~ intermetal dielectric layer; 216~ via window opening ', ® opening, 226~ alignment mark Groove; H1, H2~depth; 218~ metal layer; 21. via window plug. groove
Client’s Docket No. :96-023 TTss Docket N〇:0492-A41291 -TW/f/JYChen 13Client’s Docket No. :96-023 TTss Docket N〇:0492-A41291 -TW/f/JYChen 13
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| US10229877B2 (en) | 2016-06-22 | 2019-03-12 | Nanya Technology Corporation | Semiconductor chip and multi-chip package using thereof |
| TWI763153B (en) * | 2020-11-27 | 2022-05-01 | 新唐科技股份有限公司 | Alignment mark structure |
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| US10229877B2 (en) | 2016-06-22 | 2019-03-12 | Nanya Technology Corporation | Semiconductor chip and multi-chip package using thereof |
| US10438887B2 (en) | 2016-06-22 | 2019-10-08 | Nanya Technology Corporation | Semiconductor chip and multi-chip package using thereof and method for manufacturing the same |
| TWI763153B (en) * | 2020-11-27 | 2022-05-01 | 新唐科技股份有限公司 | Alignment mark structure |
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