WO2023130734A1 - 一种时域交织模数转换器同步装置及方法 - Google Patents

一种时域交织模数转换器同步装置及方法 Download PDF

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Publication number
WO2023130734A1
WO2023130734A1 PCT/CN2022/114171 CN2022114171W WO2023130734A1 WO 2023130734 A1 WO2023130734 A1 WO 2023130734A1 CN 2022114171 W CN2022114171 W CN 2022114171W WO 2023130734 A1 WO2023130734 A1 WO 2023130734A1
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analog
signal
digital
time
module
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PCT/CN2022/114171
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English (en)
French (fr)
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罗浚洲
许强
王悦
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普源精电科技股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters

Definitions

  • the present application belongs to the field of control systems, and in particular relates to a time-domain interleaving analog-to-digital converter synchronization device and method.
  • Analog-to-Digital Converter (ADC) circuit refers to a circuit that converts analog signals into digital signals, and has a very wide range of applications. According to the Nyquist theorem, in order to increase the bandwidth of the ADC, the sampling rate must be increased first. There are many ways to increase the sampling rate. The simple and effective way is to use multiple ADCs in parallel so that they collect the same signal at different times, and finally splicing the collected signals at the output end in order, and finally output a higher sampling rate. Rate data, such an ADC is a time-domain interleaved ADC.
  • the time-domain interleaved ADC data output clock is 1/N of the sampling clock, and N is related to the number of cores of the interleaved ADC. Therefore, in circuit design, the sampling clock is generally divided to generate a data output clock signal, and the frequency divider output In the case of no synchronization, there will be phase uncertainty. For example, there are two phases of 0° and 180° when the frequency is divided by 2, and there are four phases of 0°, 90°, 180° and 270° when the frequency is divided by 4. Determinism will lead to data out-of-sync problems when the data receiving end receives data from multiple ADCs.
  • the purpose of the embodiment of the present application is to provide a time-domain interleaved analog-to-digital converter synchronization device and method, which can solve the problem of asynchronous data transmission of the time-domain interleaved analog-to-digital converter.
  • the embodiment of the present application provides a time-domain interleaved analog-to-digital converter synchronization device, the device includes: a time-domain interleaved analog-to-digital conversion module, in the first state, the time-domain interleaved analog-to-digital conversion module The input end of the input end is connected to the signal input end, and the target analog signal is interleaved and sampled through a plurality of sub-analog-to-digital conversion modules, and a multi-channel target digital signal is output; a calibration module, the input end of the calibration module is interleaved with the time-domain analog-to-digital conversion module The output terminal is connected to calibrate the multi-channel target digital signal according to the delay error value in the first state to obtain a multi-channel calibration digital signal, wherein the delay error value is in the second state, Determined according to the reference analog signal and the synchronous control signal, the reference analog signal is clock-synchronous with the time-domain interleaved analog-to-
  • an embodiment of the present application provides a method for synchronizing a time-domain interleaved analog-to-digital converter, the method is applied to the device for synchronizing a time-domain interleaved analog-to-digital converter described in the first aspect, and the method includes: In the second state, the delay error value is determined according to a reference analog signal and a synchronous control signal, wherein the reference analog signal is synchronous with the clock of the time-domain interleaved analog-to-digital conversion module, and the synchronous control signal is synchronous with the reference analog signal Phase synchronization; in the first state, the multi-channel target digital signal is calibrated according to the delay error value to obtain a multi-channel calibration digital signal, wherein the multi-channel target digital signal is interleaved by the time-domain modulus in the device In the first state, the converting module performs interleaved sampling on the target analog signal through a plurality of sub-analog-to-digital converting modules.
  • an embodiment of the present application provides an electronic device, the electronic device includes a processor, a memory, and a program or instruction stored in the memory and operable on the processor, and the program or instruction is The processor implements the steps of implementing the method for synchronizing a time-domain interleaved analog-to-digital converter as described in the second aspect.
  • an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, time-domain interleaving as described in the second aspect is implemented Steps of an analog-to-digital converter synchronization method.
  • the embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, the processor is used to run programs or instructions, and implement the second aspect Steps of the time domain interleaved analog-to-digital converter synchronization method.
  • the input end of the time-domain interleaved analog-to-digital conversion module is connected to the signal input end, and the target analog signal is converted by multiple sub-analog-to-digital conversion modules Carry out interleaved sampling, output multi-channel target digital signal;
  • Calibration module the input end of described calibration module is connected with the output end of described time-domain interleaved analog-to-digital conversion module, is used for according to delay error value under described first state
  • Calibrate the multi-channel target digital signal to obtain a multi-channel calibration digital signal, wherein the delay error value is determined according to the reference analog signal and the synchronous control signal in the second state, the reference analog signal and the
  • the waveform generator module in the second state, the waveform generator
  • FIG. 1 is a schematic structural diagram of a time-domain interleaved analog-to-digital converter synchronization device provided by an embodiment of the present application;
  • FIG. 2 is a schematic structural diagram of a calibration module in another time-domain interleaved analog-to-digital converter synchronization device provided in an embodiment of the present application;
  • FIG. 3 is a schematic flowchart of a method for synchronizing a time-domain interleaved analog-to-digital converter provided in an embodiment of the present application
  • Fig. 4 is a schematic flowchart of another method for synchronizing a time-domain interleaved analog-to-digital converter according to an embodiment of the present application.
  • a device for synchronizing a time-domain interleaved analog-to-digital converter provided in an embodiment of the present application will be described in detail below through specific embodiments and application scenarios with reference to the accompanying drawings.
  • Fig. 1 shows a time-domain interleaving analog-to-digital converter synchronization device provided by an embodiment of the present invention.
  • the time-domain interleaved analog-to-digital converter synchronization device includes: a time-domain interleaved analog-to-digital conversion module 110 , a calibration module 120 and a waveform generator module 130 .
  • Time-domain interleaved analog-to-digital conversion module 110 in the first state, the input end of the time-domain interleaved analog-to-digital conversion module 110 is connected to the signal input end, for receiving the target analog signal in the first state, as shown in Fig. 1 Input signal (Analog input signal, Ain), and carry out interleaved sampling to described target analog signal through a plurality of sub-analog-to-digital conversion modules, obtain multi-channel target digital signal, as D1, D2, ..., DN among Fig. 1.
  • the sampling clock will be frequency-divided to generate a data output clock signal, and the output of the frequency divider will have a phase uncertainty problem when it is not synchronized. This phase uncertainty The nature will cause the multi-channel target digital signal obtained at the output end to have data asynchronous problems.
  • Calibration module 120 the input end of described calibration module is connected with the output end of described time-domain interleaved analog-to-digital conversion module, is used for receiving the asynchronous multi-channel target digital signal that time-domain interleaved analog-to-digital conversion module 110 outputs, and in In the first state, the multi-channel target digital signal is calibrated according to the delay error value to obtain a multi-channel calibration digital signal, such as Do1, Do2, ..., DoN in Figure 1, wherein the delay error value
  • it is determined according to a reference analog signal and a synchronization control signal, the reference analog signal is synchronized with the clock of the time-domain interleaved analog-to-digital conversion module 110, and the synchronization control signal is phase-synchronous with the reference analog signal , and finally solve the problem of asynchronous data transmission of the time-domain interleaved analog-to-digital converter caused by phase uncertainty, and realize the data synchronization of the time-domain interleaved analog-to-digit
  • the delay error value is determined according to a reference analog signal and a synchronization control signal
  • the reference analog signal is synchronized with the clock of the time-domain interleaved analog-to-digital conversion module
  • the synchronization control signal is phase-synchronized with the reference analog signal to overcome Data desynchronization due to phase uncertainty.
  • the waveform generator module 130 in the second state, the waveform generator module 130 is connected to the input terminal of the time-domain interleaved analog-to-digital conversion module 110, and is used to output a reference analog signal and a synchronous control signal.
  • the waveform generator module 130 may be, for example, the waveform generator shown in FIG. 1 .
  • the multi-channel target digital signal is calibrated by the calibration module 120, and finally the output multi-channel calibration digital signal is synchronous.
  • each sub-analog-to-digital conversion module can receive a synchronization signal to reset respectively, which is characterized in that the synchronization signal can be a clock signal, and its timing requirements are high, and the synchronization signal always exists.
  • the synchronization signal frequency will fall within the signal bandwidth, interfere with the analog signal, and degrade signal integrity.
  • the circuit connection of the embodiment of the present invention is simple, and there is no need to reset multiple sub-analog-to-digital conversion modules with a synchronous signal with high timing requirements, and it also avoids the existence of the synchronous signal all the time, and the frequency of the synchronous signal falls within the signal bandwidth, which will interfere with the
  • the analog signal reduces the signal integrity problem of the system, and finally solves the problem of asynchronous data transmission of the time-domain interleaved analog-to-digital converter, and realizes the data synchronization of the time-domain interleaved analog-to-digital converter.
  • a time-domain interleaved analog-to-digital converter synchronization device provided in an embodiment of the present invention is used to interleave and sample the target analog signal through a plurality of sub-analog-to-digital conversion modules in the first state through the time-domain interleaved analog-to-digital conversion module, and output A multi-channel target digital signal; a calibration module, the input of the calibration module is connected to the output of the time-domain interleaved analog-to-digital conversion module, and is used to calibrate the multi-channel according to the delay error value in the first state
  • the target digital signal is to obtain a multi-channel calibration digital signal, wherein the delay error value is determined according to a reference analog signal and a synchronous control signal in the second state, and the reference analog signal is interleaved with the time domain modulus
  • the clock of the conversion module is synchronized, and the synchronization control signal is synchronized with the phase of the reference analog signal, which can solve the problem of asynchronous data transmission of
  • the first output terminal VO of the waveform generator module 130 is connected to the input terminal of the time-domain interleaving analog-to-digital conversion module 110, for outputting The clock synchronization reference analog signal of the time-domain interleaved analog-to-digital conversion module 110.
  • the second output terminal of the waveform generator module 130 is connected to the control terminal of the calibration module 120 for outputting a synchronous control signal (Synchronous Control Signal) that is phase-synchronized with the reference analog signal, and the synchronous control signal is input to
  • the calibration module 120 is, for example, the signal SYNCin in FIG. 1 .
  • the time-domain interleaved analog-to-digital conversion module 110 is configured to receive the reference analog signal output by the waveform generator module 130 in the second state, wherein the reference analog signal is synchronized with the clock of the time-domain interleaved analog-to-digital conversion module 110 .
  • the time-domain interleaved analog-to-digital conversion module 110 interleaves and samples the reference analog signal through a plurality of sub-analog-to-digital conversion modules to obtain a multi-channel reference digital signal. Due to the phase uncertainty problem described above, the multi-channel reference digital signal Signals are out of sync.
  • the calibration module 120 is configured to receive the asynchronous multi-channel reference digital signal output by the time-domain interleaving analog-to-digital conversion module 110 in the second state, and control the synchronization according to the multi-channel reference digital signal and the output of the waveform generator module 130 signal, determine a plurality of delay error values corresponding to a plurality of channels.
  • the waveform generator module 130 in the second state, outputs a reference analog signal with a certain amplitude and a certain frequency, wherein the reference analog signal is synchronized with the clock of the time-domain interleaved analog-to-digital conversion module 110, such as CLK1 and CLK2 in Fig.
  • the clock of the time-domain interleaved analog-to-digital conversion module 110 is the sampling clock, and the clocks of the data output of multiple sub-analog-to-digital conversion modules are 1/N of the sampling clock, where N is time-domain interleaving
  • the number of sub-analog-to-digital conversion modules in the analog-to-digital converter, and the reference analog signal is interleaved and sampled through the N sub-analog-to-digital conversion modules, and the reference digital signals of N channels obtained are passed through the waveform generator module 130 outputs a synchronous control signal that is phase-synchronous with the reference analog signal, such as the signal SYNCin in Figure 1, to determine N delay error values corresponding to N channels, and the N delay error values are respectively used in the In the first state described above, delay adjustment is performed on the target digital signals of N channels output by the N sub-ADC modules to obtain synchronous multi-channel calibration digital signals.
  • the delay error value is determined according to the reference analog signal and the synchronous control signal, which may specifically include: determining the multi-channel reference digital signal according to the reference analog signal, and then determining the delay error value according to the multi-channel reference digital signal and the synchronous control signal .
  • the first output terminal of the waveform generator module in the second state, is connected to the input terminal of the time-domain interleaved analog-to-digital conversion module, Used to output a reference analog signal synchronized with the clock of the time-domain interleaved analog-to-digital conversion module;
  • the second output terminal of the waveform generator module is connected to the control terminal of the calibration module, and is also used to output the reference analog signal A synchronous control signal for signal phase synchronization;
  • the time-domain interleaved analog-to-digital conversion module is also used to interleave and sample the reference analog signal through a plurality of sub-analog-to-digital conversion modules in the second state, and output a multi-channel reference digital signal ;
  • the calibration module is also used to determine the delay error value according to the multi-channel reference digital signal and the synchronous control signal in the second state, which can solve the time-domain interlea
  • the analog reference signal with a certain amplitude and a certain frequency output by the waveform generator module may be a sine wave or a square wave.
  • the calibration module determines the delay error value according to the multi-channel reference digital signal and the synchronous control signal, including: the reference of each channel in the multi-channel reference digital signal The digital signal is compared with the synchronous control signal to obtain multiple delay error values respectively corresponding to multiple channels.
  • the time-domain interleaving analog-to-digital converter synchronization device further includes: a switching module 140, the switching module 140 is connected to the time-domain interleaving analog-to-digital conversion module 110 and the waveform generator module 130 respectively. connected for controlling said device to switch between said first state and said second state.
  • the switch module 140 may include a switch (Switch, SW) switch, and the switch connects the input end of the time domain interleaving analog-to-digital conversion module 110 and the signal input end Ain , the time-domain interleaved analog-to-digital converter synchronization device is in the first state, and the device provided by the embodiment of the present application can calibrate the multi-channel target digital signal according to the delay error value in the first state to obtain a multi-channel Calibrate digital signals.
  • switch Switch, SW
  • the time-domain interleaved analog-to-digital converter synchronizing device When the switch is connected to the input end of the waveform generator module 130 and the time-domain interleaved analog-to-digital conversion module 110, the time-domain interleaved analog-to-digital converter synchronizing device is in the second state.
  • the device provided in the embodiment of the present application can determine the delay error value in the second state.
  • the switch module 140 may include a switch and a control terminal, such as the control terminal CO of the waveform generator 130, and the control terminal CO controls the switch to be connected to the signal input terminal Ain, or connected to the signal input terminal Ain.
  • the first output terminal VO of the waveform generator module 130 is connected.
  • the switch includes a first end, a second end and a third end, the first end of the switch is connected to the time-domain interleaved analog-to-digital conversion module 110, and the second end of the switch is controlled by the control terminal CO to connect to the signal
  • the time-domain interleaving analog-to-digital converter synchronizing device is in the first state.
  • the third terminal of the switching switch controlled by the control terminal CO is connected to the signal input terminal Ain, the time domain interleaving analog-to-digital converter synchronizing device is in the second state.
  • the calibration module 120 may include: a demultiplexer (deMux) unit, the deMux unit is used to multiplex the data transmitted from the time-domain interleaving analog-to-digital conversion module 110 Demultiplexing to obtain multi-channel analog digital signals or multi-channel target digital signals.
  • deMux demultiplexer
  • the calibration module 120 includes: a data delay module and a waveform recovery module, as shown in FIG. 2 , the input end of the data delay module is connected to the output end of the analog-to-digital conversion module, The output end of the data delay module is connected to the input end of the waveform recovery module, and the data delay module is used to perform a correction on the multiple delay error values corresponding to multiple channels in the first state.
  • the delay adjustment of the target digital signal of the channel can specifically provide the delay adjustment of each data bit to adjust all the existing data misalignment. Multiple delay error values are shown in the parameters C1, C2, ..., CN in the figure .
  • the waveform restoration module is used to restore the multi-channel target digital signal to a synchronous multi-channel calibration digital signal, and the multi-channel calibration digital signal contains the waveform of the target analog signal.
  • the waveform recovery module detects whether the data contains a normal waveform in the waveform generator, and if not, adjusts the adjustment terminal of each data delay module so that the data output terminal outputs the waveform sent by the waveform generator.
  • the specific method can be to calculate the phase value of the waveform, and finally require that the phase difference of all adjacent waveforms is 1/fs, where fs is the total sampling rate of the time-domain interleaved analog-to-digital conversion module, which means that the minimum interval of sampling is 1 /fs. If the discrete Fourier transform (DFT) algorithm is used to calculate the phase relationship, the period of the output signal of the waveform generator is required to be an integer multiple of the sampling period, so that digital processing is more convenient.
  • DFT discrete Fourier transform
  • the delay error value is determined according to a reference analog signal and a synchronization control signal in the second state, wherein the reference analog signal and the The time-domain interleaved analog-to-digital conversion module is clock-synchronized, and the synchronization control signal is phase-synchronized with the reference analog signal; in the first state, the multi-channel target digital signal is calibrated according to the delay error value to obtain a multi-channel calibration digital signal , wherein the multi-channel target digital signal is obtained by interleaving and sampling the target analog signal through a plurality of sub-analog-to-digital conversion modules in the first state by the time-domain interleaving analog-to-digital conversion module in the device, which can solve the problem of time-domain interleaving mode
  • the problem of asynchronous data transmission of the digital converter is solved, and the data synchronization of the time-domain interleaved analog-to
  • Fig. 3 shows a method for synchronizing a time-domain interleaved analog-to-digital converter provided by an embodiment of the present invention.
  • the method can be executed by the time-domain interleaved analog-to-digital converter synchronization device in any of the above-mentioned device embodiments.
  • the method can be executed by software or hardware installed in the above-mentioned time-domain interleaved analog-to-digital converter synchronization device.
  • the method includes the following steps:
  • S301 In the second state, determine a delay error value according to the reference analog signal and the synchronous control signal.
  • the reference analog signal is clock-synchronized with the time-domain interleaving analog-to-digital conversion module, and the synchronization control signal is phase-synchronous with the reference analog signal.
  • S302 In the first state, calibrate the multi-channel target digital signal according to the delay error value, so as to obtain the multi-channel calibration digital signal.
  • the target analog signal is received, and the target analog signal is interleaved and sampled by a plurality of sub-analog-digital conversion modules in the time-domain interleaved analog-to-digital conversion module to obtain a multi-channel target digital signal.
  • the sampling clock will be frequency-divided to generate a data output clock signal, and the output of the frequency divider will have a phase uncertainty problem if it is not synchronized. There is a data out-of-sync problem in the channel target digital signal.
  • the calibration module calibrates the multi-channel target digital signal, the finally output multi-channel calibration digital signal is synchronous.
  • the delay error value is determined according to a reference analog signal and a synchronization control signal in the second state, wherein the reference analog signal and the The time-domain interleaved analog-to-digital conversion module is clock-synchronized, and the synchronization control signal is phase-synchronized with the reference analog signal; in the first state, the multi-channel target digital signal is calibrated according to the delay error value to obtain a multi-channel calibration digital signal , wherein the multi-channel target digital signal is obtained by interleaving and sampling the target analog signal through a plurality of sub-analog-to-digital conversion modules in the first state by the time-domain interleaving analog-to-digital conversion module in the device, which can solve the problem of time-domain interleaving mode
  • the problem of asynchronous data transmission of the digital converter is solved, and the data synchronization of the time-domain interleaved analog-to
  • FIG. 4 shows another method for synchronizing a time-domain interleaved analog-to-digital converter provided by an embodiment of the present invention.
  • the method can be executed by the time-domain interleaved analog-to-digital converter synchronization device in any of the above-mentioned device embodiments.
  • the method can be executed by software or hardware installed in the above-mentioned time-domain interleaved analog-to-digital converter synchronization device.
  • the method includes the following steps:
  • the multi-channel reference digital signal is obtained by interleaving and sampling the reference analog signal through a plurality of sub-analog-digital conversion modules in the second state by the time-domain interleaved analog-to-digital conversion module, and the reference analog signal and the synchronous control signal are obtained by Outputted by the waveform generator module, the reference analog signal is synchronized with the clock of the time-domain interleaving analog-to-digital conversion module, and the synchronization control signal is phase-synchronous with the reference analog signal.
  • a signal synchronized with the clock of the time-domain interleaved analog-to-digital conversion module may be determined as the reference analog signal.
  • a signal that is phase-synchronized with the reference analog signal may be determined as the synchronization control signal.
  • a reference analog signal with a certain amplitude and a certain frequency output by the waveform generator module is received, wherein the reference analog signal is synchronized with the clock of the time-domain interleaving analog-to-digital conversion module, and the time-domain interleaving
  • the clock of the analog-to-digital conversion module is the sampling clock
  • the clock of the data output of the multiple sub-analog-to-digital conversion modules is 1/N of the sampling clock, where N is the number of sub-analog-to-digital conversion modules in the time-domain interleaved analog-to-digital converter
  • the reference analog signal is interleaved and sampled by the N sub-analog-to-digital conversion modules, and the reference digital signal of N channels is obtained.
  • the reference of the N channels Digital signals are not synchronized. receiving the synchronous control signal output by the waveform generator module that is phase-synchronous with the reference analog signal, comparing the reference digital signal of each channel in the reference digital signals of the N channels with the synchronous control signal, and determining the corresponding N delay error values for N channels.
  • S402 In the first state, calibrate the multi-channel target digital signal according to the multiple delay error values to obtain a multi-channel calibration digital signal.
  • the multi-channel target digital signal is obtained by interleaving and sampling the target analog signal by the time-domain interleaving analog-to-digital conversion module in the device in the first state through a plurality of sub-analog-to-digital conversion modules.
  • the delay adjustments are respectively performed on the target digital signals of N channels output by the N sub-analog-to-digital conversion modules, so as to obtain synchronous multi-channel calibration digital signals.
  • a method for synchronizing a time-domain interleaved analog-to-digital converter provided by an embodiment of the present invention, by comparing the reference digital signal of each channel in the multi-channel reference digital signal with the synchronization control signal in the second state, the A plurality of delay error values respectively corresponding to a plurality of channels, wherein the multi-channel reference digital signal is interleaved by the time-domain interleaving analog-to-digital conversion module through a plurality of sub-analog-to-digital conversion modules in the second state Obtained by sampling, the reference analog signal and the synchronous control signal are synchronous with the clock of the time-domain interleaving analog-to-digital conversion module output by the reference analog signal output by the waveform generator module, and the synchronous control signal is synchronized with the reference The phase of the analog signal is synchronized.
  • the multi-channel target digital signal is calibrated according to the delay error value to obtain a multi-channel calibration digital signal, wherein the multi-channel target digital signal is interleaved by the time domain in the device.
  • the conversion module interleaves and samples the target analog signal through multiple sub-analog-to-digital conversion modules, which solves the problem of asynchronous data transmission of the time-domain interleaved analog-to-digital converter and realizes data synchronization of the time-domain interleaved analog-to-digital converter .
  • the analog reference signal with a certain amplitude and a certain frequency output by the waveform generator module may be a sine wave or a square wave.
  • the method further includes: controlling the time-domain interleaving analog-to-digital converter synchronizing device to switch between the first state and the second state through a switching module. Specifically, control the input end of the time-domain interleaved analog-to-digital conversion module to pass through the switching module, connect the signal input end, and make the synchronization device of the time-domain interleaved analog-to-digital converter be in the first state; or control the waveform generator module to pass through the switching The module is connected to the input terminal of the time-domain interleaving analog-to-digital conversion module, so that the synchronization device of the time-domain interleaving analog-to-digital converter is in the second state.
  • time-domain interleaving analog-to-digital conversion synchronization method in this specification is based on the same inventive concept as the embodiment of the time-domain interleaving analog-to-digital conversion synchronization device in this specification, so the specific implementation of this embodiment can be found in The implementation of the above-mentioned corresponding time-domain interleaving analog-to-digital conversion synchronization device will not be repeated.
  • one or more embodiments of this specification also provide an electronic device, which is used to perform the above-mentioned time-domain interleaving mode Number conversion synchronization method.
  • the electronic device includes a processor, a communication interface, a memory, and a communication bus; wherein, the processor, the communication interface, and the memory complete communication with each other through the bus; the memory uses The computer program is stored; the processor is used to execute the program stored in the memory to realize the above-mentioned time-domain interleaving analog-to-digital conversion synchronization method.
  • one or more embodiments of this specification also provide a computer-readable storage medium for storing computer programs, a specific
  • the storage medium may be a USB flash drive, an optical disk, a hard disk, etc.
  • the computer program stored in the storage medium implements the above-mentioned time-domain interleaving analog-to-digital conversion synchronization method when executed by the processor.
  • the embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Accordingly, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
  • the electronic device includes one or more processors (CPUs), input/output interfaces, network interfaces and memory.
  • processors CPUs
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • Memory may include non-permanent storage in computer readable media, in the form of random access memory (RAM) and/or nonvolatile memory such as read-only memory (ROM) or flash RAM. Memory is an example of computer readable media.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash random access memory
  • Computer-readable media including both permanent and non-permanent, removable and non-removable media, can be implemented by any method or technology for storage of information.
  • Information may be computer readable instructions, data structures, modules of a program, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory or other memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridge, tape disk storage or other magnetic storage device or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
  • computer-readable media excludes transitory computer-readable media, such as modulated data signals and carrier waves.
  • the embodiment of the present application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to realize the above-mentioned time-domain interleaved analog-to-digital conversion
  • the chip includes a processor and a communication interface
  • the communication interface is coupled to the processor
  • the processor is used to run programs or instructions to realize the above-mentioned time-domain interleaved analog-to-digital conversion
  • chips mentioned in the embodiments of the present application may also be called system-on-chip, system-on-chip, system-on-a-chip, or system-on-a-chip.

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本申请公开了一种时域交织模数转换器同步装置及方法，属于控制系统领域。该装置包括：时域交织模数转换模块，在第一状态下其输入端连接信号输入端，通过多个子模数转换模块对目标模拟信号进行交织采样，输出多通道目标数字信号；校准模块，其输入端与时域交织模数转换模块连接，在第一状态下根据延时误差值校准多通道目标数字信号，获得多通道校准数字信号，延时误差值是在第二状态下，根据参考模拟信号和同步控制信号确定的，参考模拟信号与时域交织模数转换模块时钟同步，同步控制信号与参考模拟信号相位同步；波形发生器模块，在第二状态下，与所述时域交织模数转换模块连接，也与校准模块连接，用于输出参考模拟信号和同步控制信号。

Description

一种时域交织模数转换器同步装置及方法 技术领域
本申请属于控制系统领域，具体涉及一种时域交织模数转换器同步装置及方法。
背景技术
模数转换器(Analog-to-Digital Converter，ADC)电路是指将模拟信号变为数字信号的电路，具有非常广泛的运用。由奈奎斯特定理可知，为了提高ADC的带宽，首先得提高其采样率。提高采样率的方法有许多种，其中简单有效的办法是将多颗ADC并联使用，使他们在不同时刻采集同一个信号，最后在输出端将采集到的信号按顺序拼接，最终输出更高采样率的数据，这样的ADC就是时域交织ADC。
一般时域交织ADC数据输出的时钟是采样时钟的1/N，N和交织ADC的核心数量有关，所以在电路设计中一般都会将采样时钟分频而产生数据输出时钟信号，而分频器输出在未同步情况下会出现相位不确定性，如2分频出现两种相位0°和180°，4分频会出现四种相位0°、90°、180°和270°，这种相位不确定性会导致数据接收端在接收多颗ADC数据时出现数据不同步的问题。
发明内容
本申请实施例的目的是提供一种时域交织模数转换器同步装置及方法，能够解决时域交织模数转换器数据传输不同步的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种时域交织模数转换器同步装置，所述装置包括：时域交织模数转换模块，在第一状态下，所述时域交织模数转 换模块的输入端连接信号输入端，通过多个子模数转换模块对目标模拟信号进行交织采样，输出多通道目标数字信号；校准模块，所述校准模块的输入端与所述时域交织模数转换模块的输出端连接，用于在所述第一状态下根据延时误差值校准所述多通道目标数字信号，获得多通道校准数字信号，其中，所述延时误差值是在第二状态下，根据参考模拟信号和同步控制信号确定的，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；波形发生器模块，在所述第二状态下，所述波形发生器模块与所述时域交织模数转换模块连接，所述波形发生器模块与所述校准模块连接，用于输出所述参考模拟信号和所述同步控制信号。
第二方面，本申请实施例提供了一种时域交织模数转换器同步方法，所述方法应用于上述第一方面所述的时域交织模数转换器同步装置，所述方法包括：在第二状态下，根据参考模拟信号和同步控制信号，确定延时误差值，其中所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；在第一状态下，根据所述延时误差值校准多通道目标数字信号，获得多通道校准数字信号，其中，所述多通道目标数字信号由所述装置中的时域交织模数转换模块在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样得到。
第三方面，本申请实施例提供了一种电子设备，该电子设备包括处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如第二方面所述的时域交织模数转换器同步方法的步骤。
第四方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第二面所述的时域交织模数转换器同步方法的步骤。
第五方面，本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令， 实现如第二面所述的时域交织模数转换器同步方法的步骤。
在本申请实施例中，通过时域交织模数转换模块，在第一状态下，所述时域交织模数转换模块的输入端连接信号输入端，通过多个子模数转换模块对目标模拟信号进行交织采样，输出多通道目标数字信号；校准模块，所述校准模块的输入端与所述时域交织模数转换模块的输出端连接，用于在所述第一状态下根据延时误差值校准所述多通道目标数字信号，获得多通道校准数字信号，其中，所述延时误差值是在第二状态下，根据参考模拟信号和同步控制信号确定的，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；波形发生器模块，在所述第二状态下，所述波形发生器模块与所述时域交织模数转换模块连接，所述波形发生器模块与所述校准模块连接，用于输出所述参考模拟信号和所述同步控制信号，能够解决时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
附图说明
图1是本申请实施例提供的一种时域交织模数转换器同步装置的结构示意图；
图2是本申请实施例提供的又一种时域交织模数转换器同步装置中校准模块的结构示意图；
图3是本申请实施例提供的一种时域交织模数转换器同步方法的示意性流程图；
图4是本申请实施例提供的另一种时域交织模数转换器同步方法的示意性流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的一种时域交织模数转换器同步装置进行详细地说明。
图1示出了本发明实施例提供的一种时域交织模数转换器同步装置。所述时域交织模数转换器同步装置包括：时域交织模数转换模块110、校准模块120和波形发生器模块130。
时域交织模数转换模块110，在第一状态下，所述时域交织模数转换模块110的输入端连接信号输入端，用于在第一状态下接收目标模拟信号，如图1中模拟输入信号(Analog input signal,Ain)，并通过多个子模数转换模块对所述目标模拟信号进行交织采样，获得多通道目标数字信号，如图1中的D1、D2、……、DN。由于在多个子模块对目标模拟信号同时交织采样时，会将采样时钟分频而产生数据输出时钟信号，而分频器输出在未同步情况下会出现相位不确定性问题，这种相位不确定性会导致输出端得到的多通道目标数字信号存在数据不同步的问题。
校准模块120，所述校准模块的输入端与所述时域交织模数转换模块的输出端连接，用于接收时域交织模数转换模块110输出的不同步的多通道目标数字信号，并在所述第一状态下，根据延时误差值校准所述多通道目标数 字信号，获得多通道校准数字信号，如图1中的Do1、Do2、……、DoN，其中，所述延时误差值是在第二状态下，根据参考模拟信号和同步控制信号确定的，所述参考模拟信号与所述时域交织模数转换模块110时钟同步，所述同步控制信号与所述参考模拟信号相位同步，最终解决了由相位不确定导致的时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。换言之，根据参考模拟信号和同步控制信号确定延时误差值，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步，来克服相位不确定性导致的数据不同步。
波形发生器模块130，在所述第二状态下，所述波形发生器模块130与所述时域交织模数转换模块110的输入端连接，用于输出参考模拟信号和同步控制信号。波形发生器模块130例如可以是图1所示的波形发生器。
经过校准模块120对所述多通道目标数字信号进行校准，最后输出的多通道校准数字信号是同步的。
在一种作为比较例的实现数据同步的方案中，可以通过每个子模数转换模块接收同步信号分别进行复位，其特点是同步信号可以为时钟信号，其时序要求高，并且同步信号始终存在，同步信号频率会落在信号带宽以内，干扰到模拟信号，降低信号完整性。
与之相比，本发明实施例电路连接简单，不需要用时序要求高的同步信号复位多个子模数转换模块，同时也避免了同步信号始终存在，同步信号频率落在信号带宽以内，会干扰到模拟信号，降低了系统的信号完整性的问题，最终解决了时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
本发明实施例提供的一种时域交织模数转换器同步装置，通过时域交织模数转换模块，用于在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样，输出多通道目标数字信号；校准模块，所述校准模块的输入端与所述时域交织模数转换模块的输出端连接，用于在所述第一状态下根据 延时误差值校准所述多通道目标数字信号，获得多通道校准数字信号，其中，所述延时误差值是是在第二状态下根据参考模拟信号和同步控制信号确定的，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步，能够解决时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
在一种实现方式中，再次参见图1，在第二状态下，波形发生器模块130的第一输出端VO与所述时域交织模数转换模块110的输入端连接，用于输出与所述时域交织模数转换模块110时钟同步的参考模拟信号。所述波形发生器模块130的第二输出端与所述校准模块120的控制端连接，用于输出与所述参考模拟信号相位同步的同步控制信号(Synchronous Control Signal)，该同步控制信号输入至校准模块120，如图1中的信号SYNCin。
时域交织模数转换模块110，用于在第二状态下接收波形发生器模块130输出的参考模拟信号，其中所述参考模拟信号与所述时域交织模数转换模块110的时钟是同步的。所述时域交织模数转换模块110通过多个子模数转换模块对所述参考模拟信号进行交织采样，获得多通道参考数字信号，由于上述说明的相位不确定性问题，所述多通道参考数字信号是不同步的。
校准模块120，用于在第二状态下接收时域交织模数转换模块110输出的不同步的多通道参考数字信号，并根据所述多通道参考数字信号和波形发生器模块130输出的同步控制信号，确定对应于多个通道的多个延时误差值。
本发明实施例通过在第二状态下所述波形发生器模块130输出具有一定幅度一定频率的参考模拟信号，其中所述参考模拟信号与所述时域交织模数转换模块110的时钟同步，如图1中的CLK1和CLK2，所述时域交织模数转换模块110的时钟即采样时钟，多个子模数转换模块数据输出的时钟是所述采样时钟的1/N，其中N为时域交织模数转换器中子模数转换模块的数量，并通过所述N个子模数转换模块对所述参考模拟信号进行交织采样，获得的N个通道的参考数字信号，通过所述波形发生器模块130输出与所述参考模 拟信号相位同步的同步控制信号，如图1中的信号SYNCin，确定对应于N个通道的N个延时误差值，所述N个延时误差值分别用于在所述第一状态下对N个子模数转换模块输出的N个通道目标数字信号进行延时调节，得到同步的多通道校准数字信号。即所述延时误差值是根据参考模拟信号和同步控制信号确定的，具体可以包括：根据参考模拟信号确定多通道参考数字信号，进而根据多通道参考数字信号和同步控制信号确定延时误差值。
本发明实施例提供的一种时域交织模数转换器同步装置，在第二状态下，所述波形发生器模块的第一输出端与所述时域交织模数转换模块的输入端连接，用于输出与所述时域交织模数转换模块时钟同步的参考模拟信号；所述波形发生器模块的第二输出端与所述校准模块的控制端连接，还用于输出与所述参考模拟信号相位同步的同步控制信号；所述时域交织模数转换模块还用于在所述第二状态下通过多个子模数转换模块对所述参考模拟信号进行交织采样，输出多通道参考数字信号；所述校准模块，还用于在所述第二状态下，根据所述多通道参考数字信号和所述同步控制信号，确定所述延时误差值，能够解决时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
在一种实现方式中所述波形发生器模块输出的具有一定幅度一定频率的模拟参考信号，可以是正弦波或方波。
在一种实现方式中，所述校准模块根据所述多通道参考数字信号和所述同步控制信号，确定所述延时误差值，包括：将所述多通道参考数字信号中每个通道的参考数字信号与所述同步控制信号比较，获得分别对应于多个通道的多个延时误差值。
在一种实现方式中，所述时域交织模数转换器同步装置还包括：切换模块140，所述切换模块140分别与所述时域交织模数转换模块110和所述波形发生器模块130连接，用于控制所述装置在所述第一状态和所述第二状态之间切换。
在一种实现方式中，如图1所示，切换模块140可以包括切换(Switch，SW)开关，切换开关连接所述时域交织模数转换模块110的输入端与所述信号输入端Ain时，所述时域交织模数转换器同步装置处于所述第一状态，本申请实施例提供的装置可以在第一状态下，根据延时误差值校准所述多通道目标数字信号，获得多通道校准数字信号。切换开关连接所述波形发生器模块130与所述时域交织模数转换模块110的输入端时，所述时域交织模数转换器同步装置处于所述第二状态。本申请实施例提供的装置可以在第二状态下确定延时误差值。
在一种实现方式中，如图1所示，切换模块140可以包括切换开关和控制端，例如波形发生器130的控制端CO，通过控制端CO控制切换开关与信号输入端Ain连接，或与波形发生器模块130的第一输出端VO连接。具体来讲，切换开关包括第一端、第二端和第三端，切换开关的第一端与时域交织模数转换模块110连接，在通过控制端CO控制切换开关的第二端与信号输入端Ain连接时，所述时域交织模数转换器同步装置处于所述第一状态。在通过控制端CO控制切换开关的第三端与信号输入端Ain连接时，所述时域交织模数转换器同步装置处于所述第二状态。
在一种可能的实现方式中，所述校准模块120可以包括：解复用(demultiplexer，deMux)单元，所述deMux单元用于将所述时域交织模数转换模块110传输过来的多路数据解复用，得到多通道模拟数字信号或多通道目标数字信号。
在一种实现方式中，所述校准模块120包括：数据延时模块和波形恢复模块，如图2所示，所述数据延时模块的输入端与所述模数转换模块的输出端连接，所述数据延时模块的输出端与所述波形恢复模块的输入端连接，所述数据延时模块用于在第一状态下根据对应于多个通道的多个延时误差值对所述多通道目标数字信号进行延时调节，具体可以提供每个数据位的延时调节，以对存在的所有数据错位进行调整，多个延时误差值如图中参数C1、 C2、…、CN所示。所述波形恢复模块用于将所述多通道目标数字信号恢复为同步的多通道校准数字信号，所述多通道校准数字信号含有目标模拟信号的波形。例如，波形恢复模块检测数据是否含有正常的波形发生器中的波形，若不正常，则调整每个数据延时模块调整端，使得数据输出端输出波形发生器发出的波形。可选的，具体方法可以是计算波形的相位值，最后要求所有相邻波形相位相差是1/fs，其中fs是时域交织模数转换模块的总采样率，意思是采样的最小间隔是1/fs。计算相位关系若使用离散傅里叶变换(Discrete Fourier Transform，DFT)算法，则要求波形发生器的输出信号的周期是采样周期的整数倍，这样数字处理起来较为方便。
本发明实施例提供的一种时域交织模数转换器同步方法，通过在第二状态下，根据参考模拟信号和同步控制信号，确定延时误差值，其中，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；在第一状态下，根据所述延时误差值校准多通道目标数字信号，获得多通道校准数字信号，其中，所述多通道目标数字信号由所述装置中的时域交织模数转换模块在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样得到，能够解决时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的一种时域交织模数转换器同步方法进行详细地说明。
图3示出了本发明实施例提供的一种时域交织模数转换器同步方法。该方法可以由上述任一装置实施例中的时域交织模数转换器同步装置执行，换言之，该方法可以由安装在上述时域交织模数转换器同步装置中的软件或硬件来执行，该方法包括如下步骤：
S301：在第二状态下，根据参考模拟信号和同步控制信号，确定延时误差值。
其中，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述 同步控制信号与所述参考模拟信号相位同步。S302：在第一状态下，根据延时误差值校准多通道目标数字信号，以获得多通道校准数字信号。
在第一状态下接收目标模拟信号，并通过时域交织模数转换模块中的多个子模数转换模块对目标模拟信号进行交织采样，获得多通道目标数字信号，由于在多个子模块对目标模拟信号同步交织采样时，会将采样时钟分频而产生数据输出时钟信号，而分频器输出在未同步情况下会出现相位不确定性问题，这种相位不确定性会导致输出端得到的多通道目标数字信号存在数据不同步的问题。
在第一状态下接收所述时域交织模数转换模块输出的不同步的多通道目标数字信号，并根据多个延时误差值校准所述多通道目标数字信号，获得多通道校准数字信号，经过校准模块对所述多通道目标数字信号校准，最后输出的多通道校准数字信号是同步的。
本发明实施例提供的一种时域交织模数转换器同步方法，通过在第二状态下，根据参考模拟信号和同步控制信号，确定延时误差值，其中，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；在第一状态下，根据所述延时误差值校准多通道目标数字信号，获得多通道校准数字信号，其中，所述多通道目标数字信号由所述装置中的时域交织模数转换模块在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样得到，能够解决时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
图4示出了本发明实施例提供的另一种时域交织模数转换器同步方法。该方法可以由上述任一装置实施例中的时域交织模数转换器同步装置执行，换言之，该方法可以由安装在上述时域交织模数转换器同步装置中的软件或硬件来执行，该方法包括如下步骤：
S401：在第二状态下，将多通道参考数字信号中每个通道的参考数字信号与同步控制信号比较，获得分别对应于多个通道的多个延时误差值。
其中所述多通道参考数字信号由所述时域交织模数转换模块在第二状态下通过多个子模数转换模块对参考模拟信号进行交织采样得到，所述参考模拟信号和同步控制信号是由波形发生器模块输出的,所述参考模拟信号与所述时域交织模数转换模块的时钟是同步的,所述同步控制信号与所述参考模拟信号相位同步。可选的，可以将与所述时域交织模数转换模块时钟同步的信号，确定为所述参考模拟信号。可选的，可以将与所述参考模拟信号相位同步的信号确定为所述同步控制信号。
在第二状态下，接收所述波形发生器模块输出的具有一定幅度一定频率的参考模拟信号，其中所述参考模拟信号与所述时域交织模数转换模块的时钟同步，所述时域交织模数转换模块的时钟即采样时钟，多个子模数转换模块数据输出的时钟是所述采样时钟的1/N，其中N为时域交织模数转换器中子模数转换模块的数量，并通过所述N个子模数转换模块对所述参考模拟信号进行交织采样，获得的N个通道的参考数字信号，由与上述实施例中的步骤S301相似的说明可知，所述N个通道的参考数字信号是不同步的。接收所述波形发生器模块输出的与所述参考模拟信号相位同步的同步控制信号，将所述N个通道的参考数字信号中每个通道的参考数字信号与所述同步控制信号比较，确定对应于N个通道的N个延时误差值。
S402：在第一状态下，根据所述多个延时误差值校准多通道目标数字信号，获得多通道校准数字信号。
其中，所述多通道目标数字信号由所述装置中的时域交织模数转换模块在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样得到。
在第一状态下，根据所述N个延时误差值分别对N个子模数转换模块输出的N个通道的目标数字信号进行延时调节，得到同步的多通道校准数字信号。
本发明实施例提供的一种时域交织模数转换器同步方法，通过在第二状态下，将所述多通道参考数字信号中每个通道的参考数字信号与所述同步控 制信号比较，获得分别对应于多个通道的多个延时误差值，其中所述多通道参考数字信号由所述时域交织模数转换模块在第二状态下通过多个子模数转换模块对参考模拟信号进行交织采样得到，所述参考模拟信号和同步控制信号是由波形发生器模块输出的所述参考模拟信号与所述时域交织模数转换模块的时钟是同步的,所述同步控制信号与所述参考模拟信号相位同步，在第一状态下，根据延时误差值校准多通道目标数字信号，获得多通道校准数字信号，其中，所述多通道目标数字信号由所述装置中的时域交织模数转换模块在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样得到，解决时域交织模数转换器数据传输不同步的问题，实现对时域交织模数转换器的数据同步。
在一种实现方式中，所述波形发生器模块输出的具有一定幅度一定频率的模拟参考信号，可以是正弦波或方波。
在一种实现方式中，在步骤S401之前，所述方法还包括：通过切换模块控制所述时域交织模数转换器同步装置在所述第一状态和所述第二状态之间切换。具体地，控制时域交织模数转换模块的输入端通过切换模块，连接信号输入端，使时域交织模数转换器同步装置处于所述第一状态；或者控制波形发生器模块通过所述切换模块，连接时域交织模数转换模块的输入端，使时域交织模数转换器同步装置处于所述第二状态。
需要说明的是，本说明书中关于时域交织模数转换同步方法的实施例与本说明书中关于时域交织模数转换同步装置的实施例基于同一发明构思，因此该实施例的具体实施可以参见前述对应的时域交织模数转换同步装置的实施，重复之处不再赘述。
进一步地，对应上述描述的时域交织模数转换同步方法，基于相同的技术构思，本说明书一个或多个实施例还提供了一种电子设备，该电子设备用于执行上述的时域交织模数转换同步方法。
具体在本实施例中，电子设备包括有处理器、通信接口、存储器和通信 总线；其中，所述处理器、所述通信接口以及所述存储器通过总线完成相互间的通信；所述存储器，用于存放计算机程序；所述处理器，用于执行所述存储器上所存放的程序，实现上述的时域交织模数转换同步方法。
需要说明的是，本说明书中关于电子设备的实施例与本说明书中关于时域交织模数转换同步方法的实施例基于同一发明构思，因此该实施例的具体实施可以参见前述对应的时域交织模数转换同步方法的实施，重复之处不再赘述。
进一步地，对应上述描述的时域交织模数转换同步方法，基于相同的技术构思，本说明书一个或多个实施例还提供了一种计算机可读存储介质，用于存储计算机程序，一个具体的实施例中，该存储介质可以为U盘、光盘、硬盘等，该存储介质存储的计算机程序在被处理器执行时，实现上述的时域交织模数转换同步方法。
需要说明的是，本说明书中关于存储介质的实施例与本说明书中关于时域交织模数转换同步方法的实施例基于同一发明构思，因此该实施例的具体实施可以参见前述对应的时域交织模数转换同步方法的实施，重复之处不再赘述。
本领域内的技术人员应明白，本发明的实施例可提供为方法、装置、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算 机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，电子设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所 述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现上述时域交织模数转换同步方法实施例的各个过程，或实现上述时域交织模数转换同步装置实施例的各模块的功能，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (10)

  1. 一种时域交织模数转换器同步装置，其特征在于，所述装置包括：
    时域交织模数转换模块，在第一状态下，所述时域交织模数转换模块的输入端连接信号输入端，通过多个子模数转换模块对目标模拟信号进行交织采样，输出多通道目标数字信号；
    校准模块，所述校准模块的输入端与所述时域交织模数转换模块的输出端连接，用于在所述第一状态下根据延时误差值校准所述多通道目标数字信号，获得多通道校准数字信号，其中，所述延时误差值是在第二状态下，根据参考模拟信号和同步控制信号确定的，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；
    波形发生器模块，在所述第二状态下，所述波形发生器模块与所述时域交织模数转换模块连接，所述波形发生器模块与所述校准模块连接，用于输出所述参考模拟信号和所述同步控制信号。
  2. 根据权利要求1所述的装置，其特征在于，所述波形发生器模块，在所述第二状态下，所述波形发生器模块与所述时域交织模数转换模块连接，所述波形发生器模块与所述校准模块连接，用于输出所述参考模拟信号和所述同步控制信号，包括：在第二状态下，所述波形发生器模块的第一输出端与所述时域交织模数转换模块的输入端连接，用于输出与所述时域交织模数转换模块时钟同步的参考模拟信号；所述波形发生器模块的第二输出端与所述校准模块的控制端连接，还用于输出与所述参考模拟信号相位同步的同步控制信号；
    所述时域交织模数转换模块还用于在所述第二状态下通过多个子模数转换模块对所述参考模拟信号进行交织采样，输出多通道参考数字信号；
    所述校准模块，用于在所述第二状态下，根据所述多通道参考数字信号 和所述同步控制信号，确定所述延时误差值。
  3. 根据权利要求2所述的装置，其特征在于，所述根据所述多通道参考数字信号和所述同步控制信号，确定所述延时误差值，包括：
    将所述多通道参考数字信号中每个通道的参考数字信号与所述同步控制信号比较，获得分别对应于多个通道的多个延时误差值。
  4. 根据权利要求1所述的装置，其特征在于，所述装置还包括：
    切换模块，所述时域交织模数转换模块的输入端通过所述切换模块连接所述信号输入端时，所述时域交织模数转换器同步装置处于所述第一状态；所述波形发生器模块通过所述切换模块连接所述时域交织模数转换模块的输入端时，所述时域交织模数转换器同步装置处于所述第二状态。
  5. 一种时域交织模数转换器同步方法，其特征在于，所述方法应用于如权利要求1-4中任一项所述的时域交织模数转换器同步装置，所述方法包括：
    在第二状态下，根据参考模拟信号和同步控制信号，确定延时误差值，其中，所述参考模拟信号与所述时域交织模数转换模块时钟同步，所述同步控制信号与所述参考模拟信号相位同步；在第一状态下，根据所述延时误差值校准多通道目标数字信号，获得多通道校准数字信号，其中，所述多通道目标数字信号由所述装置中的时域交织模数转换模块在第一状态下通过多个子模数转换模块对目标模拟信号进行交织采样得到。
  6. 根据权利要求5所述的方法，其特征在于，所述在第二状态下，根据参考模拟信号和同步控制信号，确定延时误差值，包括：
    在第二状态下，根据多通道参考数字信号和同步控制信号，确定所述延时误差值，其中所述多通道参考数字信号由所述时域交织模数转换模块在第 二状态下通过多个子模数转换模块对参考模拟信号进行交织采样得到，所述参考模拟信号和同步控制信号是由波形发生器模块输出的。
  7. 根据权利要求5所述的方法，其特征在于，在所述根据参考模拟信号和同步控制信号，确定延时误差值之前，所述方法还包括：
    将与所述时域交织模数转换模块时钟同步的信号，确定为所述参考模拟信号。
  8. 根据权利要求5所述的方法，其特征在于，在所述根据参考模拟信号和同步控制信号，确定延时误差值之前，所述方法还包括：
    将与所述参考模拟信号相位同步的信号确定为所述同步控制信号。
  9. 根据权利要求5所述的方法，其特征在于，所述根据参考模拟信号和同步控制信号，确定延时误差值，包括：
    将所述多通道参考数字信号中每个通道的参考数字信号与所述同步控制信号比较，获得分别对应于多个通道的多个延时误差值。
  10. 根据权利要求5所述的方法，其特征在于，在所述获得多通道校准数字信号之前，还包括：
    控制所述时域交织模数转换模块的输入端通过切换模块，连接信号输入端，使所述时域交织模数转换器同步装置处于所述第一状态；或者
    控制所述波形发生器模块通过切换模块，连接所述时域交织模数转换模块的输入端，使所述时域交织模数转换器同步装置处于所述第二状态。
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