WO2023130550A1 - 一种半导体结构及制造方法 - Google Patents

一种半导体结构及制造方法 Download PDF

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Publication number
WO2023130550A1
WO2023130550A1 PCT/CN2022/078509 CN2022078509W WO2023130550A1 WO 2023130550 A1 WO2023130550 A1 WO 2023130550A1 CN 2022078509 W CN2022078509 W CN 2022078509W WO 2023130550 A1 WO2023130550 A1 WO 2023130550A1
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Prior art keywords
semiconductor
layer
word line
bit line
channel
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PCT/CN2022/078509
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English (en)
French (fr)
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张魁
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长鑫存储技术有限公司
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Priority to US17/777,522 priority Critical patent/US20240121946A1/en
Publication of WO2023130550A1 publication Critical patent/WO2023130550A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method.
  • Semiconductor storage structures usually include word lines and bit lines.
  • the embedded word line structure or GAA (Gate-All-Around , surrounding the gate) structure.
  • GAA Gate-All-Around , surrounding the gate
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method, which at least help to solve the problem of too weak electrical conductivity between the bit line structure and the active structure.
  • an embodiment of the present disclosure provides a semiconductor structure on the one hand, including: a substrate having bit lines extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doped layer, The semiconductor doped layer is located on the side of the bit line, the top surface of the semiconductor doped layer is in contact with the semiconductor channel; the word line extending along the second direction, the word line surrounds part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line ; The word line dielectric layer, the word line dielectric layer is located between the word line and the semiconductor channel; the isolation layer, the isolation layer is located between the word line and the bit line and between the word line and the semiconductor doped layer.
  • the bit line has at least two rows of semiconductor channels arranged at intervals, and the semiconductor doped layer is located on both sides of the bit line.
  • bit lines there are at least two bit lines, and the semiconductor doped layer is located on one side of the bit lines.
  • the semiconductor doped layers of the two adjacent bit lines are located on different sides.
  • the material of the bit line includes metal;
  • the semiconductor structure further includes: a dielectric layer, the dielectric layer is located on the top surface of the bit line, and the semiconductor doped layer is also located on the side of the dielectric layer, the The semiconductor channel is located on the surface of the medium layer.
  • the base is a semiconductor substrate; the semiconductor structure further includes: a barrier layer, the barrier layer is located in the base and protrudes above the base, and the semiconductor channel is located on the top surface of the barrier layer .
  • the isolation layer is also located on the top surface of the barrier layer exposed by the semiconductor channel, and the isolation layer is located between the word line and the barrier layer.
  • the word line is located on the top surface of the barrier layer exposed by the semiconductor channel.
  • the width of the bit line is 2 times to 3.5 times the maximum width of the semiconductor channel.
  • the maximum width of the semiconductor channel ranges from 10 nm to 20 nm.
  • the semiconductor doped layer has N-type ions or P-type ions;
  • the semiconductor channel includes: a channel region, the region of the semiconductor channel facing the word line is used as the channel region, the The channel region is doped with N-type ions or P-type ions; the doped region, the region of the semiconductor channel outside the channel region is used as the doped region, and the doped ions in the doped region
  • the type is the same as that of the doping ions in the semiconductor doped layer.
  • the type of dopant ions in the channel region is different from the type of dopant ions in the semiconductor doped layer.
  • the area of the orthographic projection of the bit line on the substrate ranges from 0.5 times to 0.8 times the area of the orthographic projection of the semiconductor channel on the substrate.
  • the material of the semiconductor channel is the same as that of the semiconductor doped layer; the material of the semiconductor channel includes silicon, germanium or silicon germanium.
  • the word lines include word lines arranged at intervals
  • the semiconductor structure further includes: a first isolation layer, the first isolation layer is located between adjacent word lines; a second isolation layer, the The second isolation layer is located on the word line and on the first isolation layer, and the second isolation layer is also located on a side of the semiconductor channel away from the word line.
  • another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate having bit lines extending along a first direction; forming a semiconductor doped layer and a semiconductor channel, the semiconductor channel is located on the bit line, the semiconductor doped layer is located on the side of the bit line, and the top surface of the semiconductor doped layer is in contact with the semiconductor channel; forming a channel extending along the second direction a word line and a word line dielectric layer, the word line surrounds part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line, the word line dielectric layer is located between the word line and the Between the semiconductor channels; forming an isolation layer, the isolation layer is located between the word line and the bit line and between the word line and the semiconductor doped layer.
  • the process step of forming the semiconductor doped layer and the semiconductor channel includes: providing a stacked initial semiconductor substrate and a first doped layer, and the first doped layer is doped with N-type ions or P Type ions, and the first doped layer has a bit line; forming a semiconductor layer on the top surface of the first doped layer and the bit line; patterning the semiconductor layer and the first doped layer , remaining the semiconductor layer as the semiconductor channel, and remaining the first doped layer as the semiconductor doped layer.
  • a second doped layer is formed by using a selective epitaxy process, and a groove is formed in the second doped layer; before patterning the semiconductor layer and the first doped layer, it also includes: forming a sacrificial layer layer, the sacrificial layer fills the groove; after patterning the semiconductor layer and the first doped layer, the sacrificial layer is removed.
  • the word line after forming the word line, it also includes: performing doping treatment on the semiconductor channel higher than the top surface of the word line, and the type of doping ions in the doping treatment is the same as that of the semiconductor doping
  • the dopant ions in the layers are of the same type.
  • the semiconductor channel is located on the bit line and the semiconductor doped layer is located on the side of the bit line, which increases the contact area between the bit line structure and the active structure, which is conducive to improving the bit line structure.
  • the problem of weak conductivity between the structure and the active structure is beneficial to improve the stability of the semiconductor structure;
  • the word line surrounds part of the semiconductor channel, that is, the semiconductor structure is a GAA structure, and the GAA structure can realize the channel region of the gate to the semiconductor
  • the four-sided wrapping can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, and reduces the occupied area of the word line in the vertical direction, which is conducive to enhancing gate control. performance and increased integration of semiconductor structures.
  • the bit line there are at least two rows of semiconductor channels arranged at intervals on the bit line, which is beneficial to enhance the control performance of the bit line; since the word line surrounds part of the semiconductor channel, it is equivalent to two word lines being controlled by the same bit line , can enhance the control ability of the bit line to the word line, and further improve the stability of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure.
  • 4 to 14 are structural schematic diagrams corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 15 to 24 are top views corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 25 to 36 are structural schematic diagrams corresponding to each step in the method for forming a semiconductor structure provided by another embodiment of the present disclosure.
  • 37 to 49 are top views corresponding to each step in the method for forming a semiconductor structure provided by another embodiment of the present disclosure.
  • the current semiconductor structure has the problem of too weak electrical conductivity between the bit line structure and the active structure.
  • the current DRAM structure is mainly based on the embedded word line structure or GAA structure.
  • the word line structure surrounds the active structure, and the word line structure is located on the bit line structure, resulting in a too small contact area between the bit line structure and the active structure, which in turn leads to the conduction between the bit line structure and the active structure in the semiconductor structure.
  • the problem of undercapacity In order to improve the integration of integrated circuits, while increasing the working speed of DRAM and reducing its power consumption, the current DRAM structure is mainly based on the embedded word line structure or GAA structure.
  • the word line structure surrounds the active structure, and the word line structure is located on the bit line structure, resulting in a too small contact area between the bit line structure and the active structure, which in turn leads to the conduction between the bit line structure and the active structure in the semiconductor structure.
  • the problem of undercapacity In order to improve the integration of integrated circuits, while increasing the working speed of DRAM and reducing its power consumption, the current DRAM structure is mainly based
  • the implementation of the present disclosure provides a semiconductor structure, including: a substrate with a bit line extending along a first direction; a semiconductor channel, the semiconductor channel is located on the bit line; a semiconductor doped layer, the semiconductor doped layer is located on the side of the bit line, The top surface of the semiconductor doped layer is in contact with the semiconductor channel; the word line extending along the second direction, the word line surrounds part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; the word line dielectric layer, the word line dielectric layer Located between the word line and the semiconductor channel; the isolation layer, the isolation layer is located between the word line and the bit line and between the word line and the semiconductor doped layer, the semiconductor channel and the semiconductor doped layer are used as the active structure, that is, the semiconductor doped layer As the source and drain of the semiconductor structure, the semiconductor channel is located on the bit line and the semiconductor doped layer is located on the side of the bit line, which increases the contact area between the bit line structure and the active structure, which is conduc
  • the word line surrounds part of the semiconductor channel, that is, the semiconductor structure is a GAA structure, and the GAA structure can realize the four-sided wrapping of the gate to the semiconductor channel region, which can To a large extent, it solves the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, reduces the occupied area of the word line in the vertical direction, and is conducive to enhancing the gate control performance and improving the semiconductor structure. level of integration.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of the semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 100 with a bit line 104 extending along a first direction; a semiconductor channel 110 located on the bit line 104; a semiconductor doped layer 101 located on the side of the bit line 104 , the top surface of the semiconductor doped layer 101 is in contact with the semiconductor channel 110; the word line 130 extending along the second direction, the word line 130 surrounds part of the semiconductor channel 110, and the bottom surface of the word line 130 is higher than the top surface of the bit line 104;
  • the line dielectric layer 131, the word line dielectric layer 131 is located between the word line 130 and the semiconductor channel 110; the isolation layer 120, the isolation layer 120 is located between the word line 130 and the bit line 104 and between the word line 130 and the semiconductor doped layer 101 .
  • base 100 is a semiconductor substrate.
  • the semiconductor substrate may include, but is not limited to, any one of a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate.
  • the word line 130 surrounds part of the semiconductor channel 110
  • the semiconductor doped layer 101 is located on both sides of the bit line 104
  • the material of the bit line 104 includes metal, and the metal can specifically be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.
  • the contact resistance can effectively avoid the problem of leakage current, which is beneficial to improve the conductivity between the bit line 104 and the semiconductor doped layer 101; the bit line 104 can be a single layer structure or a stacked layer structure.
  • the material of the bit line is the same as that of the substrate, and the bit line has the same type of doping ions as the doping ions in the semiconductor doped layer, and the doping ions serve as carriers, which can improve the performance of the bit line Migration and diffusion between the inner layer and the semiconductor doped layer are beneficial to improve the conductivity of the bit line and the semiconductor doped layer, and the material of the bit line is the same as that of the substrate, and the bit line can be regarded as an extension of the substrate, so that Simplifying the process flow can also avoid interface defects caused by contact with different media.
  • the semiconductor structure further includes: a barrier layer 103, the barrier layer 103 is located in the substrate 100 and protrudes above the substrate 100, the semiconductor channel 110 is located on a part of the top surface of the barrier layer 103, and the barrier layer 103 is used to block the bit line 104 Ion diffusion between the substrate 100, the ions include dopant ions or metal ions, the barrier layer 103 is located in the substrate 100 and protrudes above the substrate 100, which means that the bottom surface of the bit line 104 in contact with the barrier layer 103 is higher than the substrate 100 and The top surface in contact with the semiconductor doped layer 101 can effectively prevent the metal ions or dopant ions of the bit line 104 from diffusing into the substrate 100, which is conducive to improving the conductivity of the bit line 104 and the semiconductor doped layer 101; the barrier layer 103
  • the material is silicon nitride.
  • the material of the barrier layer may be silicon dioxide or other materials with a high dielectric constant.
  • the semiconductor structure further includes: a dielectric layer 105, the dielectric layer 105 is located on the top surface of the bit line 104, and the semiconductor doped layer 101 is also located on the side of the dielectric layer 105, the semiconductor channel 110 is located on the surface of the dielectric layer 105, and the dielectric layer 105
  • the upper surface in contact with the semiconductor channel 110 is not higher than the upper surface of the semiconductor doped layer 101 in contact with the semiconductor channel 110, which is conducive to the formation of the semiconductor channel 110, thereby improving the integrity of the semiconductor channel 110, which is conducive to improving the semiconductor channel 110.
  • Conductive properties of channel 110 are not higher than the upper surface of the semiconductor doped layer 101 in contact with the semiconductor channel 110, which is conducive to the formation of the semiconductor channel 110, thereby improving the integrity of the semiconductor channel 110, which is conducive to improving the semiconductor channel 110.
  • the upper surface of the dielectric layer 105 in contact with the semiconductor channel 110 is lower than the upper surface of the semiconductor doped layer 101 in contact with the semiconductor channel 110; the dielectric layer 105 is used to prevent the diffusion of metal ions in the bit line 104,
  • the dielectric layer 105 can also be regarded as a part of the bit line 104, and the material of the dielectric layer 105 can include but not limited to any one of titanium nitride or other nitrogen-containing metal materials.
  • the upper surface of the dielectric layer in contact with the semiconductor channel is flush with the upper surface of the semiconductor doped layer in contact with the semiconductor channel.
  • the width of the bit line 104 is 2 to 3.5 times the maximum width of the semiconductor channel 110, specifically 2 times, 2.8 times, 3.3 times or 3.5 times. If the width of 104 is less than twice the maximum width of the semiconductor channel 110, the width of the word line 130 between adjacent semiconductor channels 110 is relatively small, because the word line 130 does not have enough area to play a role, thereby reducing the word line 130. Control capability: the width of the bit line 104 is greater than 3.5 times the maximum width of the semiconductor channel 110, which is equivalent to increasing the width of the semiconductor structure in the second direction, thereby reducing the integration level of the semiconductor device.
  • the maximum width of the semiconductor channel 110 ranges from 10 nm to 20 nm, specifically 10 nm, 13 nm, 15 nm or 20 nm; the range of the orthographic projection area of the bit line 104 on the substrate 100 It is 0.5 times to 0.8 times the orthographic projection area of the semiconductor channel 110 on the substrate 100, specifically 0.5 times, 0.6 times, 0.7 times or 0.8 times, which ensures the contact area between the bit line 104 and the semiconductor channel 110, which is conducive to improving
  • the problem of too weak conductivity between the bit line structure and the active structure is beneficial to improve the stability of the semiconductor structure.
  • the material of the semiconductor channel 110 and the material of the semiconductor doped layer 101 may be the same, specifically silicon, germanium or silicon germanium, so as to improve the interface performance between the semiconductor channel 110 and the semiconductor doped layer 101, It is beneficial to improve the interface state defects, thereby improving the electrical performance of the semiconductor structure.
  • the material of the semiconductor channel and the material of the semiconductor doped layer may be different.
  • the semiconductor channel 110 may include: a channel region 111, the region of the semiconductor channel 110 facing the word line 130 serves as the channel region 111, and the channel region 111 is doped with N-type ions or P-type ions
  • the doped region 112, the region of the semiconductor channel 110 other than the channel region 111 is used as the doped region 112, and the type of doped ions in the doped region 112 is the same as the type of doped ions in the semiconductor doped layer 101.
  • the type of dopant ions in the channel region 111 is different from the type of dopant ions in the semiconductor doped layer 101, which is equivalent to a junction transistor, where "junction" refers to a PN junction , that is, there is a PN junction in the transistor formed by the semiconductor channel 110, which is a device in which the majority carrier is used as a conduction device, so the problem of storage and diffusion of minority carriers can be avoided, and the velocity of the majority carrier is high, which is conducive to improving the semiconductor channel 110. electrical conductivity.
  • the type of dopant ions in the channel region is the same as the type of dopant ions in the semiconductor doped layer, which means that the semiconductor structure is a junctionless transistor, and "junctionless” here means no PN junction, that is, there is no PN junction in a transistor composed of a semiconductor channel.
  • the additional doping here refers to the doping performed to make the doping ion type of the doping region different from the doping ion type of the channel region.
  • the dopant ions are N-type ions or P-type ions
  • the N-type ions may be phosphorus ions, arsenic ions or antimony ions
  • the P-type ions may be boron ions, indium ions or boron fluoride ions.
  • the material of the semiconductor doped layer 101 and the material of the substrate 100 can be the same, specifically silicon, germanium or silicon germanium, the semiconductor doped layer 101 and the substrate 100 can be formed from the same initial substrate, and the semiconductor doped layer 101 can be formed from the same initial substrate.
  • the layer 101 and the substrate 100 have an integrated structure, so as to improve the interface performance between the substrate 100 and the semiconductor doped layer 101, which is beneficial to improve the interface state defects, and further improve the electrical performance of the semiconductor structure.
  • the material of the semiconductor doped layer and the material of the semiconductor channel may be different.
  • the material of the doped semiconductor layer and the material of the bit line can be the same as the material of the base, so that the doped semiconductor layer, the bit line and the base can be formed from the same initial base, and the doped semiconductor layer, the bit line and the substrate as an integrated structure, thereby improving the interface performance between the bit line and the semiconductor doped layer, which is beneficial to improving the interface state defects, and further improving the electrical performance of the semiconductor structure.
  • the material of the isolation layer 120 includes, but is not limited to, any one or more of silicon oxide, silicon nitride, or silicon oxynitride; the isolation layer 120 may be a single-layer structure or a stacked layer structure.
  • the word line 130 includes word lines arranged at intervals; the material of the word line 130 includes but not limited to one or more of polysilicon, titanium nitride, tantalum nitride, copper, tungsten or aluminum;
  • the line 130 can be a single-layer structure or a stacked structure; the word line dielectric layer 131 is used to isolate the word line 130 from the semiconductor channel 110 to form electrical insulation; the material of the word line dielectric layer 131 includes but is not limited to silicon oxide, silicon nitride or One or more of silicon oxynitride; the word line dielectric layer 131 can be a single layer structure or a stacked layer structure.
  • the bottom surface of the word line 130 is higher than the top surface of the bit line 104, that is, there is an isolation layer 120 between the word line 130 and the bit line 104, which can ensure that the word line 130 is electrically isolated from the bit line 104, and at the same time can Avoiding leakage current and capacitive effects is beneficial to improving the stability of the semiconductor structure.
  • the semiconductor structure further includes: a first isolation layer (not shown in the figure), the first isolation layer is located between the adjacent word lines 130; a second isolation layer 142, the second isolation layer 142 is located between the word lines line 130 and the first isolation layer, and the second isolation layer 142 is also located on the side of the semiconductor channel 110 away from the word line 130 .
  • the first isolation layer and the second isolation layer 142 are integrally formed.
  • the process flow can be simplified; on the other hand, the interface performance between the first isolation layer 141 and the second isolation layer 142 can be improved. It is beneficial to improve the interface state defects, and further improve the electrical performance of the semiconductor structure; the materials of the first isolation layer and the second isolation layer 142 include but are not limited to one or more of silicon oxide, silicon nitride or silicon oxynitride;
  • the first isolation layer and the second isolation layer 142 can be a single layer structure or a stacked layer structure.
  • the semiconductor channel 110 is located on the bit line 104 and the semiconductor doped layer 101 is located on the side of the bit line 104, which increases the contact area between the bit line structure and the active structure, and has It is beneficial to improve the problem of too weak electrical conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure;
  • the word line 130 surrounds part of the semiconductor channel 110, that is, the semiconductor structure is a GAA structure, and the GAA structure can realize gate
  • the four-sided wrapping of the channel region of the semiconductor can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, and reduce the occupied area of the word line 130 in the vertical direction , which is beneficial to enhancing the control performance of the gate and improving the integration degree of the semiconductor structure.
  • the bit line 104 there are at least two rows of semiconductor channels 110 arranged at intervals on the bit line 104, which is beneficial to enhance the electrical contact performance between the bit line 104 and the semiconductor channels 110, and further improve the stability of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a semiconductor structure.
  • the semiconductor structure provided by another embodiment of the present disclosure is substantially the same as the semiconductor structure provided by the foregoing embodiment.
  • the main difference is that there are at least two bit lines, and the semiconductor doped layer is located on the side.
  • FIG. 3 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure.
  • the semiconductor structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with FIG. 3 . Do not go into details.
  • the semiconductor structure includes: a substrate 200 with a bit line 204 extending along a first direction; a semiconductor channel 210, and the semiconductor channel 210 is located on the bit line 204; a semiconductor doped layer 201, and the semiconductor doped layer 201 is located at the bit line
  • the side surface of the line 204, the top surface of the semiconductor doped layer 201 is in contact with the semiconductor channel 210; the word line 230 extending along the second direction, the word line 230 surrounds part of the semiconductor channel 210, and the bottom surface of the word line 230 is higher than that of the bit line 204 Top surface; word line dielectric layer 231, word line dielectric layer 231 is located between word line 230 and semiconductor channel 210; isolation layer 220, isolation layer 220 is located between word line 230 and bit line 204 and word line 230 and semiconductor doping Between layers 201.
  • the semiconductor doped layer 201 is located on one side of the bit line 204, and the semiconductor doped layers 201 of two adjacent bit lines 204 are located on different sides; the isolation layer 220 is also located on the semiconductor The top surface of the barrier layer 203 exposed by the channel 210 , and the isolation layer 220 is located between the word line 230 and the barrier layer 203 ; the word line 230 is located on the top surface of the barrier layer 203 exposed by the semiconductor channel 110 .
  • the semiconductor channel 210 is located on the bit line 204 and the semiconductor doped layer 201 is located on the side of the bit line 204, which increases the contact area between the bit line structure and the active structure, and has It is beneficial to improve the problem of too weak electrical conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure;
  • the word line 230 surrounds part of the semiconductor channel 210, that is, the semiconductor structure is a GAA structure, and the GAA structure can realize gate
  • the four-sided wrapping of the channel region of the semiconductor can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, and reduce the occupied area of the word line 230 in the vertical direction , which is beneficial to enhancing the control performance of the gate and improving the integration degree of the semiconductor structure.
  • an embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.
  • FIGS. 15 to 24 are top views corresponding to each step in the manufacturing method of a semiconductor structure provided by an embodiment of the present invention , the method for manufacturing the semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings.
  • a substrate 100 is provided, on which a bit line 104 extending along a first direction is provided; a semiconductor doped layer 101 and a semiconductor channel 110 are formed, and the semiconductor channel 110 is located on the bit line 104 , the semiconductor doped layer 101 is located on the side of the bit line 104 , and the top surface of the semiconductor doped layer 101 is in contact with the semiconductor channel 110 .
  • the process steps of forming the semiconductor doped layer 101 and the semiconductor channel 110 include: providing a stacked initial semiconductor substrate 108 and a first doped layer 109, the first doped layer 109 is doped with N-type ions or P Type ions, and the first doped layer 109 has a bit line 104; a semiconductor layer is formed on the top surface of the first doped layer 109 and the bit line 104; the semiconductor layer and the first doped layer 109 are patterned, and the remaining semiconductor layer is used as In the semiconductor channel 110 , the first doped layer 109 is left as the semiconductor doped layer 101 .
  • an initial semiconductor substrate is provided, and a partial thickness of the initial semiconductor substrate is doped, and the dopant ions of the doping treatment are N-type ions or P-type ions, then the partial thickness of the initial semiconductor substrate is used as The first doped layer 109 , and the initial semiconductor substrate other than the first doped layer 109 is used as the initial semiconductor substrate 108 .
  • the material of the initial semiconductor substrate is a semiconductor material.
  • the semiconductor material may be any one of silicon, germanium, silicon germanium or silicon carbide.
  • the doping treatment is to make the first doped layer 109 have dopant ions through an ion implantation process, wherein the dopant ions are N-type ions or P-type ions, and the N-type ions can specifically be phosphorus ions, Arsenic ions or antimony ions, and the P-type ions may specifically be boron ions, indium ions or boron fluoride ions.
  • the first doped layer 109 and the initial semiconductor substrate 108 are patterned to form a first trench 102 in the initial semiconductor substrate 108 .
  • the sidewall of the first trench 102 exposes part of the side surface of the initial semiconductor substrate 108.
  • it can prevent the ions in the subsequently formed bit line from diffusing into the initial semiconductor substrate 108, thereby reducing the concentration of ions in the bit line, and further It is beneficial to improve the conductivity of the bit line; on the other hand, it can ensure that the area of the subsequently formed bit line structure increases, thereby improving the conductivity of the bit line.
  • the first doped layer is patterned to form a first trench, and the bottom of the first trench exposes the surface of the initial semiconductor substrate.
  • the width of the first trench 102 is 2 to 3.5 times the maximum width of the subsequently formed semiconductor channel, specifically 2 times, 2.8 times, 3.3 times or 3.5 times.
  • the subsequently formed bit line is located in the first trench 102, which means that the width of the first trench 102 is equal to the width of the subsequently formed bit line, and in the subsequently formed semiconductor structure, the width of the bit line is less than 2 times the maximum width of the semiconductor channel.
  • the width of the word line between adjacent semiconductor channels is small, because the word line does not have enough area to play a role, thereby reducing the control ability of the word line; the width of the bit line is greater than 3.5 times the maximum width of the semiconductor channel , which is equivalent to increasing the width of the semiconductor structure in the second direction, thereby reducing the integration degree of the semiconductor device.
  • a stacked barrier layer 103, a bit line 104, and a dielectric layer 105 are sequentially formed on the initial semiconductor substrate 108, and the stacked barrier layer 103, bit line 104, and dielectric layer 105 are also located in the first trench 102. Inside.
  • the barrier layer 103 is used to prevent ion diffusion between the bit line 104 and the initial semiconductor substrate 108, and the ions include dopant ions or metal ions, and the bottom surface of the bit line 104 in contact with the barrier layer 103 is higher than the initial semiconductor substrate.
  • the top surface of the substrate 108 in contact with the first doped layer 109 can effectively prevent the metal ions or dopant ions of the bit line 104 from diffusing into the initial semiconductor substrate 108, which is beneficial to improve the contact between the bit line 104 and the first doped layer.
  • the bottom surface of the bit line in contact with the barrier layer is flush with the top surface of the original semiconductor substrate in contact with the first doped layer; the material of the barrier layer can be silicon dioxide or other materials with high dielectric constant Material.
  • the opposite sides of the bit line 104 have the first doped layer 109, which increases the contact area between the bit line 104 and the first doped layer 109. It is beneficial to improve the problem of too weak electrical conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure.
  • the material of the bit line 104 includes metal, and the metal can specifically be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.
  • the resistance of the metal itself is small, which reduces the contact between the bit line 104 and the first doped layer 109
  • the contact resistance can effectively avoid the problem of leakage current, which is beneficial to improve the conductivity between the bit line 104 and the semiconductor doped layer 101; the bit line 104 can be a single layer structure or a stacked layer structure.
  • the material of the bit line is the same as that of the substrate, and the bit line has the same type of doping ions as the doping ions in the semiconductor doped layer, and the doping ions serve as carriers, which can improve the performance of the bit line
  • the migration and diffusion between the first doped layer and the first doped layer are beneficial to improve the conductivity of the bit line and the first doped layer, and the material of the bit line is the same as that of the substrate.
  • the first doped layer, the bit line The line and the initial semiconductor substrate can be formed from the same initial base, and the first doped layer, the bit line and the initial semiconductor substrate are integrated, thereby improving the interface performance between the bit line and the first doped layer, which is conducive to improving the interface state defects, thereby further improving the electrical properties of the semiconductor structure; on the other hand, it can simplify the process flow.
  • the surface of the dielectric layer 105 is lower than the surface of the first doped layer 109, which effectively avoids the phenomenon that the subsequent formation of the semiconductor channel has lattice defects, thereby helping to improve the conductivity of the semiconductor channel; the dielectric layer 105 is used for To prevent the diffusion of metal ions in the bit line 104, the dielectric layer 105 can also be regarded as a part of the bit line 104, and the material of the dielectric layer 105 can include but not limited to any one of titanium nitride or other nitrogen-containing metal materials.
  • the surface of the dielectric layer is flush with the surface of the first doped layer, on the one hand, the area of the bit line can be increased, and on the other hand, the contact area between the first doped layer and the bit line can be increased, It is beneficial to improve the conductivity of the bit line, and further helps to improve the conductivity of the semiconductor structure.
  • the second doped layer 106 is formed by using a selective epitaxial process, and the second doped layer 106 has a trench 122 therein.
  • the second doped layer 106 is a semiconductor layer, and there are dopant ions in the second doped layer 106, and the type of doped ions in the second doped layer 106 is the same as that of the first doped layer 109
  • the types of ions are different, that is, the semiconductor structure formed by the second doped layer 106 and the first doped layer 109 is a junction transistor, where "junction" refers to a PN junction, that is, a semiconductor channel formed subsequently There is a PN junction in the transistor, which is a device in which the majority of carriers are used as a conductive device, so it can avoid the problem of no minority carrier storage and diffusion, and the speed of the majority of carriers is high, which is conducive to improving the conductivity of the semiconductor channel.
  • the type of dopant ions in the second doped layer is the same as the type of dopant ions in the first doped layer, that is, the semiconductor structure formed by the second doped layer and the first doped layer is Junction transistors, "junctionless” here refers to no PN junction, that is, there is no PN junction in a transistor composed of a semiconductor channel.
  • the doped region is additionally doped, the doped
  • the impurity concentration is more difficult to control; on the other hand, because the device is a junction-free transistor, it is beneficial to avoid the ultra-steep source-drain concentration gradient doping process and the phenomenon of making an ultra-steep PN junction in the nanoscale range, so that the doping mutation can be avoided
  • the resulting threshold voltage drift and leakage current increase are beneficial to suppress the short channel effect, and can still work in the scale of a few nanometers, thus helping to further improve the integration density and electrical performance of semiconductor structures.
  • N-type ions are doped in situ.
  • P-type ions are doped in situ.
  • the source material used in the selective epitaxial growth process includes source gas, etching gas hydrogen chloride, and doping ion source gas.
  • the doping ion source gas is used to provide doping ions.
  • the source gas can be silicon source gas , the silicon source gas may specifically be silane, disilane, dichlorosilane or trichlorosilane.
  • the source gas may also be a germanium source gas, and the germanium source gas may specifically be germane.
  • the dopant ion source gas is an N-type ion source gas, and the N-type ion source gas may specifically be phosphine, arsine or antimony hydride.
  • the dopant ion source gas is a P-type ion source gas, and the P-type ion source gas may specifically be borane, boron trifluoride or diborane.
  • the material of the second doped layer 106 is the same as that of the initial semiconductor substrate 108, specifically silicon, germanium or silicon germanium.
  • the process flow can be simplified; on the other hand, the material is the same, Then the lattice mismatch factor is 0, which effectively avoids the problems of lattice defects inside the second doped layer 106 and the increase of internal resistance, and is beneficial to improve the conductivity of the second doped layer 106 .
  • the material of the second doped layer may be different from that of the original semiconductor substrate.
  • a sacrificial layer 107 is formed, and the sacrificial layer 107 fills the trench 122 .
  • the second doped layer 106, the first doped layer 109 and the initial semiconductor substrate 108 are patterned, the second doped layer 106 is left as the semiconductor channel 110, and the first doped layer 109 is left as the semiconductor channel 110.
  • the doped layer 101, the remaining initial semiconductor substrate 108 is used as the base 100, and the sacrificial layer 107 is removed.
  • the subsequently formed word line surrounds part of the semiconductor channels 110, and the semiconductor doped layer 101 is located on both sides of the bit line 104.
  • the contact area between the bit line 104 and the semiconductor doped layer 101 is increased, which is beneficial to improve the problem of too weak electrical conductivity between the bit line structure and the active structure, and further helps to improve the stability of the semiconductor structure.
  • the maximum width of the semiconductor channel 110 ranges from 10nm to 20nm, specifically 10nm, 13nm, 15nm or 20nm; It is 0.5 times to 0.8 times the orthographic projection area of the semiconductor channel 110 on the substrate 100, specifically 0.5 times, 0.6 times, 0.7 times or 0.8 times, which ensures the contact area between the bit line 104 and the semiconductor channel 110, which is conducive to improving The problem of too weak conductivity between the bit line structure and the active structure is beneficial to improve the stability of the semiconductor structure.
  • an isolation layer 120 is formed, and the isolation layer 120 is located on the side of the bit line 104 and the side of the semiconductor doped layer 101 away from the bit line 104 .
  • the material of the isolation layer 120 includes, but is not limited to, any one or more of silicon oxide, silicon nitride, or silicon oxynitride; the isolation layer 120 may be a single-layer structure or a stacked layer structure.
  • the word line 130 and the word line dielectric layer 131 extending along the second direction are formed, the word line 130 and the word line dielectric layer 131 are located on the isolation layer 120, and the word line 130 surrounds the part The semiconductor channel 110 , and the bottom surface of the word line 130 is higher than the top surface of the bit line 104 , and the word line dielectric layer 131 is located between the word line 130 and the semiconductor channel 110 .
  • a word line dielectric layer 131 and a gate conductive layer 132 are formed on the isolation layer 120, the word line dielectric layer 131 is located on the side of the semiconductor channel 110 with a partial thickness and surrounds the semiconductor channel 110; the gate conductive layer 132 The semi-thick semiconductor channel 110 is located on the side of the gate dielectric layer 131 corresponding to and surrounds the gate dielectric layer 131 .
  • the material of the gate conductive layer 132 includes but is not limited to one or more of polysilicon, titanium nitride, tantalum nitride, copper, tungsten or aluminum; the gate conductive layer 132 can be a single-layer structure or a stacked Layer structure; the word line dielectric layer 131 is used to isolate the word line 130 from the semiconductor channel 110 to form electrical insulation; the material of the word line dielectric layer 131 includes but is not limited to one or more of silicon oxide, silicon nitride or silicon oxynitride The word line dielectric layer 131 can be a single layer structure or a stacked layer structure.
  • the gate conductive layer 132 is patterned, and the remaining gate conductive layer 132 is used as the word line 130 .
  • the bottom surface of the word line 130 is higher than the top surface of the bit line 104, that is, there is an isolation layer 120 between the word line 130 and the bit line 104, which can ensure that the word line 130 is electrically isolated from the bit line 104, and at the same time can Avoiding leakage current and capacitive effects is beneficial to improving the stability of the semiconductor structure.
  • a substrate is provided, on which there are bit lines extending along a first direction; a semiconductor doped layer and an isolation layer are sequentially formed on the substrate, the semiconductor doped layer is located on the side of the bit line, and the isolation layer is also located on the side of the bit line.
  • the word line and the word line dielectric layer extending along the second direction, the word line and the word line dielectric layer are located on the isolation layer, the word line surrounds the word line dielectric layer, and the bottom surface of the word line is higher than the top of the bit line surface; form a second trench, the sidewall of the second trench exposes the word line dielectric layer and the isolation layer, and the bottom of the second trench exposes the semiconductor doped layer and the bit line; forms a semiconductor channel, and the semiconductor channel is located in the second trench Inside, the semiconductor channel is located on the bit line, and the top surface of the semiconductor doped layer is in contact with the semiconductor channel.
  • a first isolation layer (not shown) and a second isolation layer 142 are formed, the first isolation layer is located between adjacent word lines 130; the second isolation layer 142 is located on the word line 130 and on the first isolation layer, and the second isolation layer 142 is also located on the side of the semiconductor channel 110 away from the word line 130 .
  • the first isolation layer and the second isolation layer 142 are integrally formed, on the one hand, the process flow can be simplified; on the other hand, the interface performance between the first isolation layer and the second isolation layer 142 is improved, which is beneficial Improve the interface state defects, and further improve the electrical performance of the semiconductor structure;
  • the materials of the first isolation layer and the second isolation layer 142 include but are not limited to one or more of silicon oxide, silicon nitride or silicon oxynitride; the first The isolation layer and the second isolation layer 142 can be a single layer structure or a stacked layer structure.
  • doping treatment is performed on the semiconductor channel 110 higher than the top surface of the word line 130 , and the type of doping ions in the doping treatment is the same as that in the semiconductor doping layer 101 .
  • the semiconductor channel 110 includes: a channel region 111, the region of the semiconductor channel 110 facing the word line 130 serves as the channel region 111, and the channel region 111 is doped with N-type ions or P-type ions; In the doped region 112 , the region of the semiconductor channel 110 other than the channel region 111 is used as the doped region 112 , and the type of doping ions in the doped region 112 is the same as that in the semiconductor doped layer 101 .
  • the type of dopant ions in the channel region 111 is different from the type of dopant ions in the semiconductor doped layer 101, which is equivalent to a junction transistor, where "junction" refers to a PN junction , that is, there is a PN junction in the transistor formed by the semiconductor channel 110, which is a device in which the majority carrier is used as a conduction device, so the problem of storage and diffusion of minority carriers can be avoided, and the velocity of the majority carrier is high, which is conducive to improving the semiconductor channel 110. electrical conductivity.
  • the type of dopant ions in the channel region is the same as the type of dopant ions in the semiconductor doped layer, which means that the semiconductor structure is a junctionless transistor, and "junctionless” here means no PN junction, that is, there is no PN junction in a transistor composed of a semiconductor channel.
  • the doped region is additionally doped, the doped
  • the impurity concentration is more difficult to control; on the other hand, because the device is a junction-free transistor, it is beneficial to avoid the ultra-steep source-drain concentration gradient doping process and the phenomenon of making an ultra-steep PN junction in the nanoscale range, so that the doping mutation can be avoided
  • the resulting threshold voltage drift and leakage current increase are beneficial to suppress the short channel effect, and can still work in the scale of a few nanometers, thus helping to further improve the integration density and electrical performance of semiconductor structures.
  • the dopant ions are N-type ions or P-type ions
  • the N-type ions may be phosphorus ions, arsenic ions or antimony ions
  • the P-type ions may be boron ions, indium ions or boron fluoride ions.
  • the semiconductor channel 110 is located on the bit line 104 and the semiconductor doped layer 101 is located on the side of the bit line 104, which increases the contact area between the bit line structure and the active structure, and has It is beneficial to improve the problem of too weak electrical conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure;
  • the word line 130 surrounds part of the semiconductor channel 110, that is, the semiconductor structure is a GAA structure, and the GAA structure can realize gate
  • the four-sided wrapping of the channel region of the semiconductor can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, and reduce the occupied area of the word line 110 in the vertical direction , which is beneficial to enhancing the control performance of the gate and improving the integration degree of the semiconductor structure.
  • the bit line there are at least two rows of semiconductor channels arranged at intervals on the bit line, which is beneficial to enhance the control performance of the bit line; since the word line surrounds part of the semiconductor channel, it is equivalent to two word lines being controlled by the same bit line , can enhance the control ability of the bit line to the word line, and further improve the stability of the semiconductor structure.
  • FIGS. 37 to 49 are schematic diagrams corresponding to each step in the method for preparing a semiconductor structure provided by another embodiment of the present disclosure.
  • the parts that are the same as or corresponding to those of the above-mentioned embodiments will not be described in detail below.
  • a substrate 200 is provided, on which there is a bit line 204 extending along a first direction, and a semiconductor doped layer 201 and a semiconductor channel 210 are formed, and the semiconductor channel 210 is located on the bit line 204 , the semiconductor doped layer 201 is located on the side of the bit line 204 , and the top surface of the semiconductor doped layer 201 is in contact with the semiconductor channel 210 .
  • the process steps of forming the semiconductor doped layer 201 and the semiconductor channel 210 include: providing a stacked initial semiconductor substrate 208 and a first doped layer 209, the first doped layer 209 is doped with N-type ions or P type ions, and the first doped layer 209 has a bit line 204; a semiconductor layer is formed on the top surface of the first doped layer 209 and the bit line 204; the semiconductor layer and the first doped layer 209 are patterned, and the remaining semiconductor layer is used as In the semiconductor channel 210 , the remaining first doped layer 209 is used as the semiconductor doped layer 201 .
  • an initial semiconductor substrate is provided, and a partial thickness of the initial semiconductor substrate is doped, and the dopant ions of the doping treatment are N-type ions or P-type ions, and the partial thickness of the initial semiconductor substrate is used as the first doping treatment.
  • layer 209 the initial semiconductor substrate other than the first doped layer 209 serves as the initial semiconductor substrate 208 .
  • the first doped layer 209 and the initial semiconductor substrate 208 are patterned to form a first trench 202 in the initial semiconductor substrate 208 .
  • a stacked first barrier layer 213, a conductive layer 214, and a dielectric layer 205 are sequentially formed on the initial semiconductor substrate 208, and the stacked first barrier layer 213, conductive layer 214, and dielectric layer 205 are also located on the first Inside a trench 202 .
  • the material of the conductive layer 214 includes metal, and the metal can specifically be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.
  • the resistance of the metal itself is small, which reduces the contact between the conductive layer 214 and the first doped layer 209
  • the contact resistance can effectively avoid the problem of leakage current, which is beneficial to improve the conductivity of the conductive layer 214 and the first doped layer 209; the conductive layer 214 can be a single-layer structure or a stacked layer structure.
  • the first barrier layer 213 is used to block metal ion diffusion between the conductive layer 214 and the initial semiconductor substrate 208; the bottom surface of the conductive layer 214 in contact with the first barrier layer 213 is higher than the initial semiconductor substrate 208 and The top surface in contact with the first doped layer 209 can effectively prevent the metal ions of the conductive layer 214 from diffusing into the initial semiconductor substrate 208, which is conducive to improving the conductivity of the conductive layer 214 and the first doped layer 209; the first barrier The material of layer 213 is silicon nitride. In other embodiments, the material of the first barrier layer may be silicon dioxide or other materials with a high dielectric constant.
  • a third trench 252 is formed through the conductive layer 214 and the dielectric layer 205 , the bottom of the third trench exposes the first barrier layer 213 , and the remaining conductive layer 214 serves as the bit line 104 .
  • the third trench 252 is located in the first barrier layer 213 , so that the conductive layer 214 forms an open circuit, so as to be electrically isolated, and prevent two adjacent bit lines from forming a path, which is equivalent to forming two transistors.
  • the bottom surface of the third trench is flush with the top surface of the first barrier layer.
  • the second barrier layer 223 is formed, the second barrier layer 223 fills the third trench 252 , and the second barrier layer 223 and the first barrier layer 213 constitute the barrier layer 203 .
  • the second barrier layer 223 is used to prevent the diffusion of metal ions between adjacent bit lines 204, and the material of the second barrier layer 223 is the same as that of the first barrier layer 213, thereby improving the second barrier layer 223.
  • the performance of the interface with the first barrier layer 213 is beneficial to improve the interface state defects, thereby improving the electrical performance of the semiconductor structure.
  • the material of the second barrier layer may be different from that of the first barrier layer.
  • a third barrier layer is formed on the initial semiconductor substrate, and the third barrier layer is also located in the trench to form a fourth trench, the sidewall of the fourth trench exposes the surface of the first doped layer, And the bottom surface of the fourth trench is higher than the bottom surface of the first doped layer, the stacked bit lines and the dielectric layer are sequentially formed on the initial semiconductor substrate, the stacked bit lines and the dielectric layer are still located in the fourth trench, and the remaining The third barrier layer acts as a barrier layer.
  • the method for forming the subsequent semiconductor structure corresponding to each step in Figure 30 to Figure 36 is the same as or similar to the method for forming the structure diagram corresponding to each step in Figure 7 to Figure 14 in the previous embodiment , so the subsequent semiconductor structure formation methods corresponding to the respective steps in FIG. 30 to FIG. 36 will not be described in detail.
  • the semiconductor doped layer 201 is located on one side of the bit line 204, and the semiconductor doped layers 201 of two adjacent bit lines 204 are located on different sides; the isolation layer 220 is also located on the semiconductor The top surface of the barrier layer 203 exposed by the channel 210 , and the isolation layer 220 is located between the word line 230 and the barrier layer 203 ; the word line 230 is located on the top surface of the barrier layer 203 exposed by the semiconductor channel 110 .
  • the semiconductor channel 210 is located on the bit line 204 and the semiconductor doped layer 201 is located on the side of the bit line 204, which increases the contact area between the bit line structure and the active structure, and has It is beneficial to improve the problem of too weak electrical conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure;
  • the word line 230 surrounds part of the semiconductor channel 210, that is, the semiconductor structure is a GAA structure, and the GAA structure can realize gate
  • the four-sided wrapping of the channel region of the semiconductor can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, and reduce the occupied area of the word line 230 in the vertical direction , which is beneficial to enhancing the control performance of the gate and improving the integration degree of the semiconductor structure.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及制造方法，半导体结构包括：基底（100），基底（100）上具有沿第一方向延伸的位线（104）；半导体通道（110），半导体通道（110）位于位线（104）上；半导体掺杂层（101），半导体掺杂层（101）位于位线（104）的侧面，半导体掺杂层（101）顶面与半导体通道（100）接触；沿第二方向延伸的字线（130），字线（130）环绕部分半导体通道（100），且字线（130）的底表面高于位线（104）的顶表面；字线介质层（131），字线介质层（131）位于字线（130）与半导体通道（100）之间；隔离层（120），隔离层（120）位于字线（130）与位线（104）之间以及字线（130）与半导体掺杂层（101）之间。本公开实施例提供的半导体结构及制造方法至少有利于解决位线结构与有源结构之间导电能力过弱的问题。

Description

一种半导体结构及制造方法
交叉引用
本申请要求于2022年01月06日递交的名称为“一种半导体结构及制造方法”、申请号为202210010264.X的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及制造方法。
背景技术
半导体存储结构中通常包括字线和位线，为了提高集成电路的集成度，同时提升存储结构的工作速度和降低它的功耗，逐步采用埋入式字线结构或者GAA(Gate-All-Around，环绕栅极)结构。在采用这些字线结构时，如何改善位线结构与有源结构之间导电能力过弱的情况，提高半导体结构的稳定性，已成为本领域技术人员亟待解决的一个重要问题。
发明内容
本公开实施例提供一种半导体结构及制造方法，至少有利于解决位线结构与有源结构之间导电能力过弱的问题。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底，基底上具有沿第一方向延伸的位线；半导体通道，半导体通道位于位线上；半导体掺杂层，半导体掺杂层位于位线的侧面，半导体掺杂层顶面与半导体通道接触；沿第二方向延伸的字线，字线环绕部分半导体通道，且字线的底表面高于位线的顶表面；字线介质层，字线介质层位于字线与半导体通道之间；隔离层，隔离层位于字线与位线之间以及字线与半导体掺杂层之间。
另外，在所述第一方向上，所述位线上具有至少两列间隔排布的半导体通道，所述半导体掺杂层位于所述位线的两侧。
另外，所述位线至少两条，所述半导体掺杂层位于所述位线的一侧。
另外，相邻的所述两条位线的所述半导体掺杂层位于不同侧。
另外，所述位线的材料包括金属；所述半导体结构还包括：介质层，所述介质层位于所述位线顶面，且所述半导体掺杂层还位于所述介质层侧面，所述半导体通道位于所述介质层表面。
另外，所述基底为半导体衬底；所述半导体结构还包括：阻挡层，所述阻挡层位于所述基底内且凸出于所述基底上方，所述半导体通道位于所述阻挡层部分顶面。
另外，所述隔离层还位于所述半导体通道露出的所述阻挡层顶面，且所述隔离层位于所述字线与所述阻挡层之间。
另外，所述字线位于所述半导体通道露出的所述阻挡层顶面。
另外，在平行于所述第二方向上，所述位线的宽度为所述半导体通道的最大宽度的2倍～3.5倍。
另外，在平行于所述第二方向上，所述半导体通道的最大宽度的范围为10nm～20nm。
另外，所述半导体掺杂层具有N型离子或P型离子；所述半导体通道包括：沟道区，与所述字线正对的所述半导体通道的区域作为所述沟道区，所述沟道区内掺杂有N型离子或者P型离子；掺杂区，所述沟道区以外的所述半导体通道的区域作为所述掺杂区，所述掺杂区内的掺杂离子的类型与所述半导体掺杂层内掺杂离子的类型相同。
另外，所述沟道区内的掺杂离子的类型与所述半导体掺杂层内掺杂离子的类型不同。
另外，所述位线在所述基底上的正投影面积范围为所述半导体通道在所述基底上的正投影面积的0.5倍～0.8倍。
另外，所述半导体通道的材料与所述半导体掺杂层的材料相同；所述半导体通道的材料包括硅、锗或者锗化硅。
另外，所述字线包括间隔排布的字线，所述半导体结构还包括：第一隔离层，所述第一隔离层位于相邻的所述字线之间；第二隔离层，所述第二隔离层位于所述字线上以及所述第一隔离层上，且所述第二隔离层还位于远离所述字线的所述半导体通道的侧面。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，包括：提供基底，所述基底上具有沿第一方向延伸的位线；形成半导体掺杂层以及半导体通道，所述半导体通道位于所述位线上，所述半导体掺杂层位于所述位线的侧面，所述半导体掺杂层顶面与所述半导体通道相接触；形成沿第二方向延伸的字线以及字线介质层，所述字线环绕部分所述半导体通道，且所述字线的底表面高于所述位线的顶表面，所述字线介质层位于所述字线与所述半导体通道之间；形成隔离层，所述隔离层位于所述字线与所述位线之间以及所述字线与所述半导体掺杂层之间。
另外，形成所述半导体掺杂层以及所述半导体通道的工艺步骤包括：提供层叠设置的初始半导体衬底以及第一掺杂层，所述第一掺杂层内掺杂有N型离子或者P型离子，且所述第一掺杂层内具有位线；在所述第一掺杂层顶面以及所述位线上形成半导体层；图形化所述半导体层以及所述第一掺杂层，剩余所述半导体层作为所述半导体通道，剩余所述第一掺杂层作为所述半导体掺杂层。
另外，采用选择性外延工艺，形成第二掺杂层，且所述第二掺杂层内具有沟槽；在图形化所述半导体层以及所述第一掺杂层之前，还包括：形成牺牲层，所述牺牲层填充满所述沟槽；在图形化所述半导体层以及所述第一掺杂层之后，去除所述牺牲层。
另外，在形成所述字线之后，还包括：对高于所述字线顶面的所述半导体通道进行掺杂处理，且所述掺杂处理的掺杂离子的类型与所述半导体掺杂层中的掺杂离子的类型相同。
本公开实施例提供的技术方案至少具有以下优点：
本公开实施例提供的一种半导体结构的技术方案中，半导体通道位于位线上以及半导体掺杂层位于位线的侧面增大了位线结构与有源结构的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性；字线环绕部分半导体通道，即半导体结构为GAA结构，GAA结构可以实现栅极对半导体的沟道区的四面包裹，可以很大程度上解决栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等问题，减少了字线在垂直方向上的占用面积，有利于增强栅极控制性能以及提高半导体结构的 集成度。
此外，在第一方向上，位线上具有至少两列间隔排布的半导体通道，有利于增强位线控制性能；由于字线环绕部分半导体通道，相当于两条字线由同一条位线控制，可以增强位线对字线的控制能力，进一步提高半导体结构的稳定性。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的半导体结构的一种结构示意图；
图2为本公开一实施例提供的半导体结构的一种俯视图；
图3为本公开另一实施例提供的半导体结构的一种结构示意图；
图4～图14为本公开一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图；
图15～图24为本公开一实施例提供的半导体结构的形成方法中各步骤对应的俯视图；
图25～图36为本公开另一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图；
图37～图49为本公开另一实施例提供的半导体结构的形成方法中各步骤对应的俯视图。
具体实施方式
由背景技术可知，目前半导体结构存在位线结构与有源结构之间导电能 力过弱的问题。
分析发现，导致上述问题的主要原因包括：为了提高集成电路的集成度，同时提升DRAM的工作速度和降低它的功耗，因此，目前DRAM结构主要以埋入式字线结构或者GAA结构为主。其中，GAA结构中字线结构环绕有源结构，字线结构位于位线结构上，导致位线结构与有源结构的接触面积过小，进而导致半导体结构存在位线结构与有源结构之间导电能力过弱的问题。
本公开实施提供一种半导体结构，包括：基底，基底上具有沿第一方向延伸的位线；半导体通道，半导体通道位于位线上；半导体掺杂层，半导体掺杂层位于位线的侧面，半导体掺杂层顶面与半导体通道接触；沿第二方向延伸的字线，字线环绕部分半导体通道，且字线的底表面高于位线的顶表面；字线介质层，字线介质层位于字线与半导体通道之间；隔离层，隔离层位于字线与位线之间以及字线与半导体掺杂层之间，半导体通道与半导体掺杂层作为有源结构，即半导体掺杂层作为半导体结构的源极与漏极，半导体通道位于位线上以及半导体掺杂层位于位线的侧面增大了位线结构与有源结构的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性；字线环绕部分半导体通道，即半导体结构为GAA结构，GAA结构可以实现栅极对半导体的沟道区的四面包裹，可以很大程度上解决栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等问题，减少了字线在垂直方向上的占用面积，有利于增强栅极控制性能以及提高半导体结构的集成度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图1以及图2，图1为本公开一实施例提供的半导体结构的一种结构示意图，图2为本公开一实施例提供的半导体结构的一种俯视图。半导体结构包括：基底100，基底上具有沿第一方向延伸的位线104；半导体通道110，半导体通道110位于位线104上；半导体掺杂层101，半导体掺杂层101位于位线104的侧面，半导体掺杂层101顶面与半导体通道110接触；沿第二方向延伸的字线130，字线130环绕部分半导体通道110，且字线130的底表面高于位线104 的顶表面；字线介质层131，字线介质层131位于字线130与半导体通道110之间；隔离层120，隔离层120位于字线130与位线104之间以及字线130与半导体掺杂层101之间。
在一些实施例中，基底100为半导体衬底。具体地，半导体衬底可以包括但不限于硅衬底、锗衬底、锗硅衬底或碳化硅衬底的任一种。
在一些实施例中，在第一方向上，位线104上具有至少两列间隔排布的半导体通道110，字线130环绕部分半导体通道110，半导体掺杂层101位于位线104的两侧，增大了位线104与半导体掺杂层101的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性。
在一些实施例中，位线104的材料包括金属，金属具体可以为钴、镍、钼、钛、钨、钽或者铂，金属自身的电阻小，降低了位线104与半导体掺杂层101的接触电阻，有效避免漏电流的问题，有利于提高位线104与半导体掺杂层101的导电能力；位线104可以为单层结构或者叠层结构。在另一些实施例中，位线的材料与基底的材料相同，且位线内具有与半导体掺杂层内掺杂离子类型相同的掺杂离子，掺杂离子作为载流子，可以提高位线内与半导体掺杂层之间的迁移和扩散，有利于提高位线与半导体掺杂层的导电能力，而且位线的材料与基底的材料相同，位线可以视为基底的延伸部分，从而可以简化工艺流程，也可以避免不同介质接触导致的界面缺陷。
在一些实施例中，半导体结构还包括：阻挡层103，阻挡层103位于基底100内且凸出于基底100上方，半导体通道110位于阻挡层103部分顶面，阻挡层103用于阻挡位线104与基底100之间离子扩散，离子包括掺杂离子或金属离子，阻挡层103位于基底100内且凸出于基底100上方，相当于位线104与阻挡层103相接触的底面高于基底100与半导体掺杂层101相接触的顶面，可以有效避免位线104的金属离子或者掺杂离子扩散到基底100中，有利于提高位线104与半导体掺杂层101的导电性能；阻挡层103的材料为氮化硅。在另一些实施例中，阻挡层的材料可以为二氧化硅或者其他介质常数高的材料。
在一些实施例中，半导体结构还包括：介质层105，介质层105位于位线104顶面，且半导体掺杂层101还位于介质层105侧面，半导体通道110位于介 质层105表面，介质层105与半导体通道110相接触的上表面不高于半导体掺杂层101与半导体通道110相接触的上表面，有利于半导体通道110的形成，从而提高形成半导体通道110的完整性，进而有利于提高半导体通道110的导电性能。
在一些实施例中，介质层105与半导体通道110相接触的上表面低于半导体掺杂层101与半导体通道110相接触的上表面；介质层105用于防止位线104内的金属离子扩散，介质层105也可以视为位线104的一部分，介质层105的材料可以包括但不限于氮化钛或其他含氮金属材料的任意一种。在另一些实施例中，介质层与半导体通道接触的上表面与半导体掺杂层与半导体通道相接触的上表面齐平。
在一些实施例中，在平行于第二方向上，位线104的宽度为半导体通道110的最大宽度的2倍～3.5倍，具体可以为2倍、2.8倍、3.3倍或3.5倍，位线104的宽度小于半导体通道110的最大宽度的2倍，则相邻的半导体通道110之间的字线130的宽度较小，由于字线130没有足够的区域发挥作用，从而降低了字线130的控制能力；位线104的宽度大于半导体通道110的最大宽度的3.5倍，相当于增大了半导体结构在第二方向的宽度，从而降低半导体器件的集成度。
在一些实施例中，在平行于第二方向上，半导体通道110的最大宽度的范围为10nm～20nm，具体可以为10nm、13nm、15nm或者20nm；位线104在基底100上的正投影面积范围为半导体通道110在基底100上的正投影面积的0.5倍～0.8倍，具体可以为0.5倍、0.6倍、0.7倍或者0.8倍，保证了位线104与半导体通道110的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性。
在一些实施例中，半导体通道110的材料与半导体掺杂层101的材料可以相同，具体可以为硅、锗或者锗化硅，从而改善半导体通道110与半导体掺杂层101之间的界面性能，有利于改善界面态缺陷，进而改善半导体结构的电学性能。在另一些实施例中，半导体通道的材料与半导体掺杂层的材料可以不相同。
在一些实施例中，半导体通道110可以包括：沟道区111，与字线130正 对的半导体通道110的区域作为沟道区111，沟道区111内掺杂有N型离子或者P型离子；掺杂区112，沟道区111以外的半导体通道110的区域作为掺杂区112，掺杂区112内的掺杂离子的类型与半导体掺杂层101内掺杂离子的类型相同。
在一些实施例中，沟道区111内的掺杂离子的类型与半导体掺杂层101内掺杂离子的类型不同，相当于有结晶体管，此处的“有结”指的是有PN结，即半导体通道110构成的晶体管中有PN结，是多数载流子作为导电的器件，因而可以避免无少数载流子存储与扩散问题，而且多数载流子速度高，有利于提高半导体通道110的导电性能。
在另一些实施例中，沟道区内的掺杂离子的类型与半导体掺杂层内掺杂离子的类型相同，相当于半导体结构为无结晶体管，此处的“无结”指的是无PN结，即半导体通道构成的晶体管中没有PN结。一方面，无需对掺杂区进行额外的掺杂，从而避免了对掺杂区的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对掺杂区进行掺杂，掺杂浓度更加难以控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。可以理解的是，此处额外的掺杂指的是，为了让掺杂区的掺杂离子类型与沟道区的掺杂离子类型不同而进行的掺杂。
在一些实施例中，掺杂离子为N型离子或者P型离子，N型离子具体可以为磷离子、砷离子或者锑离子，P型离子具体可以为硼离子、铟离子或者氟化硼离子。
在一些实施例中，半导体掺杂层101的材料与基底100的材料可以相同，具体可以为硅、锗或者锗化硅，半导体掺杂层101以及基底100可以由同一初始基底形成，半导体掺杂层101以及基底100为一体结构，从而改善基底100与半导体掺杂层101之间的界面性能，有利于改善界面态缺陷，进而进一步改善半导体结构的电学性能。在另一些实施例中，半导体掺杂层的材料与半导体通道的材料可以不相同。
在另一些实施例中，半导体掺杂层的材料以及位线的材料与基底的材料 可以相同，这样，半导体掺杂层、位线和基底可以由同一初始基底形成，半导体掺杂层、位线以及基底为一体结构，从而改善位线与半导体掺杂层之间的界面性能，有利于改善界面态缺陷，进而进一步改善半导体结构的电学性能。
在一些实施例中，隔离层120的材料包括但不限于氧化硅、氮化硅或者氮氧化硅中的任意一种或多种；隔离层120可以为单层结构或叠层结构。
在一些实施例中，字线130包括间隔排布的字线；字线130的材料包括但不限于多晶硅、氮化钛、氮化钽、铜、钨或者铝中的一种或多种；字线130可以为单层结构或叠层结构；字线介质层131用于将字线130与半导体通道110隔离形成电绝缘；字线介质层131的材料包括但不限于氧化硅、氮化硅或者氮氧化硅中的一种或多种；字线介质层131可以为单层结构或叠层结构。
在一些实施例中，字线130的底表面高于位线104的顶表面，即字线130与位线104之间具有隔离层120，可以保证字线130与位线104电绝缘，同时可以避免漏电流以及电容效应，有利于提高半导体结构的稳定性。
在一些实施例中，半导体结构还包括：第一隔离层(图中未示出)，第一隔离层位于相邻的字线130之间；第二隔离层142，第二隔离层142位于字线130上以及第一隔离层上，且第二隔离层142还位于远离字线130的半导体通道110的侧面。
在一些实施例中，第一隔离层与第二隔离层142为一体成型结构，一方面，可以简化工艺流程；另一方面，改善第一隔离层141与第二隔离层142的界面性能，有利于改善界面态缺陷，进而进一步改善半导体结构的电学性能；第一隔离层以及第二隔离层142的材料包括但不限于氧化硅、氮化硅或者氮氧化硅中的一种或多种；第一隔离层以及第二隔离层142可以为单层结构或叠层结构。
本公开实施例提供的一种半导体结构的技术方案中，半导体通道110位于位线104上以及半导体掺杂层101位于位线104的侧面增大了位线结构与有源结构的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性；字线130环绕部分半导体通道110，即半导体结构为GAA结构，GAA结构可以实现栅极对半导体的沟道区的四面包裹，可以很大程度上解决栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道 效应等问题，减少了字线130在垂直方向上的占用面积，有利于增强栅极控制性能以及提高半导体结构的集成度。
此外，在第一方向上，位线104上具有至少两列间隔排布的半导体通道110，有利于增强位线104与半导体通道110的电接触性能，进一步提高半导体结构的稳定性。
本公开另一实施例还提供一种半导体结构，本公开另一实施例提供的半导体结构与前述实施例提供的半导体结构大致相同，主要区别包括位线至少两条，半导体掺杂层位于位线的一侧。
图3为本公开另一实施例提供的半导体结构的一种结构示意图，以下将结合图3对本公开另一实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图3，半导体结构包括：基底200，基底上具有沿第一方向延伸的位线204；半导体通道210，半导体通道210位于位线204上；半导体掺杂层201，半导体掺杂层201位于位线204的侧面，半导体掺杂层201顶面与半导体通道210接触；沿第二方向延伸的字线230，字线230环绕部分半导体通道210，且字线230的底表面高于位线204的顶表面；字线介质层231，字线介质层231位于字线230与半导体通道210之间；隔离层220，隔离层220位于字线230与位线204之间以及字线230与半导体掺杂层201之间。
在一些实施例中，位线204至少两条，半导体掺杂层201位于位线204的一侧，相邻的两条位线204的半导体掺杂层201位于不同侧；隔离层220还位于半导体通道210露出的阻挡层203顶面，且隔离层220位于字线230与阻挡层203之间；字线230位于半导体通道110露出的阻挡层203顶面。
本公开实施例提供的一种半导体结构的技术方案中，半导体通道210位于位线204上以及半导体掺杂层201位于位线204的侧面增大了位线结构与有源结构的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性；字线230环绕部分半导体通道210，即半导体结构为GAA结构，GAA结构可以实现栅极对半导体的沟道区的四面包裹，可以很大程度上解决栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等问题，减少了字线230在垂直方向上的占用面积，有利于增强栅极控制 性能以及提高半导体结构的集成度。
相应地，本发明一实施例提供一种半导体结构的制造方法，可用于形成上述半导体结构。
图4至图14为本发明一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图，图15至图24为本发明一实施例提供的半导体结构的制造方法中各步骤对应的俯视图，以下将结合附图对本实施例提供的半导体结构的制造方法进行详细说明。
参考图4至图9以及图15至图19，提供基底100，基底100上具有沿第一方向延伸的位线104；形成半导体掺杂层101以及半导体通道110，半导体通道110位于位线104上，半导体掺杂层101位于位线104的侧面，半导体掺杂层101顶面与半导体通道110相接触。
具体地，形成半导体掺杂层101以及半导体通道110的工艺步骤包括：提供层叠设置的初始半导体衬底108以及第一掺杂层109，第一掺杂层109内掺杂有N型离子或者P型离子，且第一掺杂层109内具有位线104；在第一掺杂层109顶面以及位线104上形成半导体层；图形化半导体层以及第一掺杂层109，剩余半导体层作为半导体通道110，剩余第一掺杂层109作为半导体掺杂层101。
更具体地，参考图4，提供初始半导体基底，对部分厚度的初始半导体基底进行掺杂处理，且掺杂处理的掺杂离子为N型离子或者P型离子，则部分厚度的初始半导体基底作为第一掺杂层109，第一掺杂层109以外的初始半导体基底作为初始半导体衬底108。
在一些实施例中，初始半导体基底的材料为半导体材料。半导体材料具体可以为硅、锗、锗硅或碳化硅的任意一种。
在一些实施例中，掺杂处理为通过离子注入工艺使第一掺杂层109内具有掺杂离子，其中，掺杂离子为N型离子或者P型离子，N型离子具体可以为磷离子、砷离子或者锑离子，P型离子具体可以为硼离子、铟离子或者氟化硼离子。
参考图5以及图15，图形化第一掺杂层109以及初始半导体衬底108，在初始半导体衬底108内形成第一沟槽102。第一沟槽102的侧壁暴露出部分初 始半导体衬底108的侧面，一方面可以避免后续形成的位线内的离子扩散到初始半导体衬底108内，从而降低位线内离子的浓度，进一步有利于提高位线的导电性能；另一方面，可以保证后续形成的位线结构的面积增大，从而提高位线的导电性能。在另一些实施例中，图形化第一掺杂层，形成第一沟槽，第一沟槽底部暴露出初始半导体衬底表面。
在一些实施例中，在平行于后续形成字线的延伸方向上，第一沟槽102的宽度为后续形成的半导体通道的最大宽度的2倍～3.5倍，具体可以为2倍、2.8倍、3.3倍或3.5倍。后续形成的位线位于第一沟槽102内，相当于第一沟槽102的宽度等于后续形成的位线的宽度，后续形成的半导体结构中，位线的宽度小于半导体通道的最大宽度的2倍，则相邻的半导体通道之间的字线的宽度较小，由于字线没有足够的区域发挥作用，从而降低了字线的控制能力；位线的宽度大于半导体通道的最大宽度的3.5倍，相当于增大了半导体结构在第二方向的宽度，从而降低半导体器件的集成度。
参考图6以及图16，在初始半导体衬底108上依次形成层叠的阻挡层103、位线104以及介质层105，层叠的阻挡层103、位线104以及介质层105还位于第一沟槽102内。
在一些实施例中，阻挡层103用于阻挡位线104与初始半导体衬底108之间离子扩散，离子包括掺杂离子或金属离子，位线104与阻挡层103相接触的底面高于初始半导体衬底108与第一掺杂层109相接触的顶面，可以有效避免位线104的金属离子或者掺杂离子扩散到初始半导体衬底108中，有利于提高位线104与第一掺杂层109的导电性能；阻挡层103的材料为氮化硅。在另一些实施例中，位线与阻挡层相接触的底面与初始半导体衬底与第一掺杂层相接触的顶面齐平；阻挡层的材料可以为二氧化硅或者其他介质常数高的材料。
在一些实施例中，在沿后续形成字线的延伸方向上，位线104相对的侧面均具有第一掺杂层109，增大了位线104与第一掺杂层109的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性。
在一些实施例中，位线104的材料包括金属，金属具体可以为钴、镍、钼、钛、钨、钽或者铂，金属自身的电阻小，降低了位线104与第一掺杂层109 的接触电阻，有效避免漏电流的问题，有利于提高位线104与半导体掺杂层101的导电能力；位线104可以为单层结构或者叠层结构。在另一些实施例中，位线的材料与基底的材料相同，且位线内具有与半导体掺杂层内掺杂离子类型相同的掺杂离子，掺杂离子作为载流子，可以提高位线内与第一掺杂层之间的迁移和扩散，有利于提高位线与第一掺杂层的导电能力，而且位线的材料与基底的材料相同，一方面，第一掺杂层、位线和初始半导体衬底可以由同一初始基底形成，第一掺杂层、位线以及初始半导体衬底为一体结构，从而改善位线与第一掺杂层之间的界面性能，有利于改善界面态缺陷，进而进一步改善半导体结构的电学性能；另一方面，可以简化工艺流程。
在一些实施例中，介质层105的表面低于第一掺杂层109的表面，有效避免后续形成半导体通道具有晶格缺陷的现象，进而有利于提高半导体通道的导电性；介质层105用于防止位线104内的金属离子扩散，介质层105也可以视为位线104的一部分，介质层105的材料可以包括但不限于氮化钛或其他含氮金属材料的任意一种。在另一些实施例中，介质层的表面与第一掺杂层表面齐平，一方面可以增大位线的面积，另一方面，可以增大第一掺杂层与位线的接触面积，有利于提高位线的导电能力，进一步有利于提高半导体结构的导电性。
参考图7以及图17，采用选择性外延工艺，形成第二掺杂层106，且第二掺杂层106内具有沟槽122。
在一些实施例中，第二掺杂层106为半导体层，第二掺杂层106内有掺杂离子，第二掺杂层106内掺杂离子的类型与第一掺杂层109内掺杂离子的类型不同，即第二掺杂层106与第一掺杂层109形成的半导体结构为有结晶体管，此处的“有结”指的是有PN结，即后续形成的半导体通道构成的晶体管中有PN结，是多数载流子作为导电的器件，因而可以避免无少数载流子存储与扩散问题，而且多数载流子速度高，有利于提高半导体通道的导电性能。在另一些实施例中，第二掺杂层内掺杂离子的类型与第一掺杂层内掺杂离子的类型相同，即第二掺杂层与第一掺杂层形成的半导体结构为无结晶体管，此处的“无结”指的是无PN结，即半导体通道构成的晶体管中没有PN结。一方面，无需对掺杂区进行额外的掺杂，从而避免了对掺杂区的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对掺杂区进行掺杂，掺杂浓度更加难以 控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。
在一些实施例中，形成第二掺杂层106的工艺步骤中，原位掺杂N型离子。在另一些实施例中，形成第二掺杂层的工艺步骤中，原位掺杂P型离子。
在一些实施例中，选择性外延生长工艺采用的源材料包括源气体、刻蚀性气体氯化氢以及掺杂离子源气体，掺杂离子源气体用于提供掺杂离子，源气体可以为硅源气体，硅源气体具体可以为硅烷、乙硅烷、二氯甲硅烷或者三氯甲硅烷。在另一些实施例中，源气体还可以为锗源气体，锗源气体具体可以为锗烷。
在一些实施例中，掺杂离子源气体为N型离子源气体，N型离子源气体具体可以为磷烷、砷烷或者氢化锑。在另一些实施例中，掺杂离子源气体为P型离子源气体，P型离子源气体具体可以为硼烷、三氟化硼或者乙硼烷。
在一些实施例中，第二掺杂层106的材料与初始半导体衬底108的材料相同，具体可以为硅、锗或者锗化硅，一方面，可以简化工艺流程；另一方面，材料相同，则晶格失配因子为0，有效避免第二掺杂层106内部具有晶格缺陷以及内部电阻增大的问题，有利于提高第二掺杂层106的导电性能。在另一些实施例中，第二掺杂层的材料与初始半导体衬底的材料可以不相同。
参考图8以及图18，形成牺牲层107，牺牲层107填充满沟槽122。
参考图9以及图19，图形化第二掺杂层106、第一掺杂层109以及初始半导体衬底108，剩余第二掺杂层106作为半导体通道110，剩余第一掺杂层109作为半导体掺杂层101，剩余的初始半导体衬底108作为基底100，去除所述牺牲层107。
在一些实施例中，在第一方向上，位线104上具有至少两列间隔排布的半导体通道110，后续形成的字线环绕部分半导体通道110，半导体掺杂层101位于位线104的两侧，增大了位线104与半导体掺杂层101的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体 结构的稳定性。
在一些实施例中，在平行于第二方向上，半导体通道110的最大宽度的范围为10nm～20nm，具体可以为10nm、13nm、15nm或者20nm；位线104在基底100上的正投影面积范围为半导体通道110在基底100上的正投影面积的0.5倍～0.8倍，具体可以为0.5倍、0.6倍、0.7倍或者0.8倍，保证了位线104与半导体通道110的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性。
参考图10以及图20，形成隔离层120，隔离层120位于位线104的侧面以及半导体掺杂层101远离位线104的侧面。
在一些实施例中，隔离层120的材料包括但不限于氧化硅、氮化硅或者氮氧化硅中的任意一种或多种；隔离层120可以为单层结构或叠层结构。
参考图11、图12以及图21、图22，形成沿第二方向延伸的字线130以及字线介质层131，字线130以及字线介质层131位于隔离层120上，字线130环绕部分半导体通道110，且字线130的底表面高于位线104的顶表面，字线介质层131位于字线130与半导体通道110之间。
具体地，参考图11以及图21，在隔离层120上形成字线介质层131以及栅导电层132，字线介质层131位于部分厚度的半导体通道110侧面且环绕半导体通道110；栅导电层132位于部分厚度的半导体通道110对应的栅介质层131的侧面且环绕栅介质层131。
在一些实施例中，栅导电层132的材料包括但不限于多晶硅、氮化钛、氮化钽、铜、钨或者铝中的一种或多种；栅导电层132可以为单层结构或叠层结构；字线介质层131用于将字线130与半导体通道110隔离形成电绝缘；字线介质层131的材料包括但不限于氧化硅、氮化硅或者氮氧化硅中的一种或多种；字线介质层131可以为单层结构或叠层结构。
参考图12以及图22，图形化栅导电层132，剩余的栅导电层132作为字线130。
在一些实施例中，字线130的底表面高于位线104的顶表面，即字线130与位线104之间具有隔离层120，可以保证字线130与位线104电绝缘，同时可 以避免漏电流以及电容效应，有利于提高半导体结构的稳定性。
在另一些实施例中，提供基底，基底上具有沿第一方向延伸的位线；在基底上依次形成半导体掺杂层以及隔离层，半导体掺杂层位于位线的侧面，隔离层还位于位线上；形成沿第二方向延伸的字线以及字线介质层，字线以及字线介质层位于隔离层上，字线环绕字线介质层，且字线的底表面高于位线的顶表面；形成第二沟槽，第二沟槽侧壁暴露出字线介质层以及隔离层，第二沟槽底部暴露出半导体掺杂层以及位线；形成半导体通道，半导体通道位于第二沟槽内，半导体通道位于位线上，且半导体掺杂层顶面与半导体通道相接触。
参考图13以及图23，形成第一隔离层(图中未示出)以及第二隔离层142，第一隔离层位于相邻的字线130之间；第二隔离层142位于字线130上以及第一隔离层上，且第二隔离层142还位于远离字线130的半导体通道110的侧面。
在一些实施例中，第一隔离层与第二隔离层142为一体成型结构，一方面，可以简化工艺流程；另一方面，改善第一隔离层与第二隔离层142的界面性能，有利于改善界面态缺陷，进而进一步改善半导体结构的电学性能；第一隔离层以及第二隔离层142的材料包括但不限于氧化硅、氮化硅或者氮氧化硅中的一种或多种；第一隔离层以及第二隔离层142可以为单层结构或叠层结构。
参考图14以及图24，对高于字线130顶面的半导体通道110进行掺杂处理，且掺杂处理的掺杂离子的类型与半导体掺杂层101中的掺杂离子的类型相同。
在一些实施例中，半导体通道110包括：沟道区111，与字线130正对的半导体通道110的区域作为沟道区111，沟道区111内掺杂有N型离子或者P型离子；掺杂区112，沟道区111以外的半导体通道110的区域作为掺杂区112，掺杂区112内的掺杂离子的类型与半导体掺杂层101内掺杂离子的类型相同。
在一些实施例中，沟道区111内的掺杂离子的类型与半导体掺杂层101内掺杂离子的类型不同，相当于有结晶体管，此处的“有结”指的是有PN结，即半导体通道110构成的晶体管中有PN结，是多数载流子作为导电的器件，因而可以避免无少数载流子存储与扩散问题，而且多数载流子速度高，有利于提 高半导体通道110的导电性能。
在另一些实施例中，沟道区内的掺杂离子的类型与半导体掺杂层内掺杂离子的类型相同，相当于半导体结构为无结晶体管，此处的“无结”指的是无PN结，即半导体通道构成的晶体管中没有PN结。一方面，无需对掺杂区进行额外的掺杂，从而避免了对掺杂区的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对掺杂区进行掺杂，掺杂浓度更加难以控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。
在一些实施例中，掺杂离子为N型离子或者P型离子，N型离子具体可以为磷离子、砷离子或者锑离子，P型离子具体可以为硼离子、铟离子或者氟化硼离子。
本公开实施例提供的一种半导体结构的技术方案中，半导体通道110位于位线104上以及半导体掺杂层101位于位线104的侧面增大了位线结构与有源结构的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性；字线130环绕部分半导体通道110，即半导体结构为GAA结构，GAA结构可以实现栅极对半导体的沟道区的四面包裹，可以很大程度上解决栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等问题，减少了字线110在垂直方向上的占用面积，有利于增强栅极控制性能以及提高半导体结构的集成度。
此外，在第一方向上，位线上具有至少两列间隔排布的半导体通道，有利于增强位线控制性能；由于字线环绕部分半导体通道，相当于两条字线由同一条位线控制，可以增强位线对字线的控制能力，进一步提高半导体结构的稳定性。
图25至图36为本公开另一实施例提供的半导体结构的制备方法中各步骤对应的结构示意图，图37至图49为本公开另一实施例提供的半导体结构的制备方法中各步骤对应的俯视图，与上述实施例相同或相应的部分，以下将 不做详细赘述。
参考图25至图33以及图37至图44，提供基底200，基底200上具有沿第一方向延伸的位线204，形成半导体掺杂层201以及半导体通道210，半导体通道210位于位线204上，半导体掺杂层201位于位线204的侧面，半导体掺杂层201顶面与半导体通道210相接触。
具体地，形成半导体掺杂层201以及半导体通道210的工艺步骤包括：提供层叠设置的初始半导体衬底208以及第一掺杂层209，第一掺杂层209内掺杂有N型离子或者P型离子，且第一掺杂层209内具有位线204；在第一掺杂层209顶面以及位线204上形成半导体层；图形化半导体层以及第一掺杂层209，剩余半导体层作为半导体通道210，剩余第一掺杂层209作为半导体掺杂层201。
参考图25，提供初始半导体基底，对部分厚度的初始半导体基底进行掺杂处理，且掺杂处理的掺杂离子为N型离子或者P型离子，则部分厚度的初始半导体基底作为第一掺杂层209，第一掺杂层209以外的初始半导体基底作为初始半导体衬底208。
参考图26以及图37，图形化第一掺杂层209以及初始半导体衬底208，在初始半导体衬底208内形成第一沟槽202。
参考图27以及图38，在初始半导体衬底208上依次形成层叠的第一阻挡层213、导电层214以及介质层205，层叠的第一阻挡层213、导电层214以及介质层205还位于第一沟槽202内。
在一些实施例中，导电层214的材料包括金属，金属具体可以为钴、镍、钼、钛、钨、钽或者铂，金属自身的电阻小，降低了导电层214与第一掺杂层209的接触电阻，有效避免漏电流的问题，有利于提高导电层214与第一掺杂层209的导电能力；导电层214可以为单层结构或者叠层结构。
在一些实施例中，第一阻挡层213用于阻挡导电层214与初始半导体衬底208之间金属离子扩散；导电层214与第一阻挡层213相接触的底面高于初始半导体衬底208与第一掺杂层209相接触的顶面，可以有效避免导电层214的金属离子扩散到初始半导体衬底208中，有利于提高导电层214与第一掺杂层209的导电性能；第一阻挡层213的材料为氮化硅。在另一些实施例中，第一阻挡层的材料可以为二氧化硅或者其他介质常数高的材料。
参考图28以及图39，形成贯穿导电层214以及介质层205的第三沟槽252，第三沟槽底部暴露出第一阻挡层213，剩余的导电层214作为位线104。
在一些实施例中，第三沟槽252位于第一阻挡层213内，以使导电层214形成断路，从而电绝缘，避免两个相邻的位线形成通路，相当于形成两个晶体管。在另一些实施例中，第三沟槽的底面与第一阻挡层的顶面齐平。
参考图29以及图40，形成第二阻挡层223，第二阻挡层223填充满第三沟槽252，第二阻挡层223与第一阻挡层213构成阻挡层203。
在一些实施例中，第二阻挡层223用于阻挡相邻的位线204之间金属离子扩散，第二阻挡层223的材料与第一阻挡层213的材料相同，从而改善第二阻挡层223与第一阻挡层213之间的界面性能，有利于改善界面态缺陷，进而改善半导体结构的电学性能。在另一些实施例中，第二阻挡层的材料与第一阻挡层的材料可以不相同。
在另一些实施例中，在初始半导体衬底上形成第三阻挡层，第三阻挡层还位于沟槽内，形成第四沟槽，第四沟槽侧壁暴露出第一掺杂层表面，且第四沟槽的底面高于第一掺杂层的底面，在初始半导体衬底上依次形成层叠的位线以及介质层，层叠的位线以及介质层还位于第四沟槽内，剩余的第三阻挡层作为阻挡层。
在一些实施例中，后续的半导体结构如图30至图36中各步骤对应的结构示意图的形成方法与上一实施例中图7至图14中各步骤对应的结构示意图的形成方法相同或类似，故后续的半导体结构如图30至图36中各步骤对应的结构示意图的形成方法不做详细赘述。
在一些实施例中，位线204至少两条，半导体掺杂层201位于位线204的一侧，相邻的两条位线204的半导体掺杂层201位于不同侧；隔离层220还位于半导体通道210露出的阻挡层203顶面，且隔离层220位于字线230与阻挡层203之间；字线230位于半导体通道110露出的阻挡层203顶面。
本公开实施例提供的一种半导体结构的技术方案中，半导体通道210位于位线204上以及半导体掺杂层201位于位线204的侧面增大了位线结构与有源结构的接触面积，有利于改善位线结构与有源结构之间导电能力过弱的问题，进而有利于提高半导体结构的稳定性；字线230环绕部分半导体通道210， 即半导体结构为GAA结构，GAA结构可以实现栅极对半导体的沟道区的四面包裹，可以很大程度上解决栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等问题，减少了字线230在垂直方向上的占用面积，有利于增强栅极控制性能以及提高半导体结构的集成度。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    基底，所述基底上具有沿第一方向延伸的位线；
    半导体通道，所述半导体通道位于所述位线上；
    半导体掺杂层，所述半导体掺杂层位于所述位线的侧面，所述半导体掺杂层顶面与所述半导体通道接触；
    沿第二方向延伸的字线，所述字线环绕部分所述半导体通道，且所述字线的底表面高于所述位线的顶表面；
    字线介质层，所述字线介质层位于所述字线与所述半导体通道之间；
    隔离层，所述隔离层位于所述字线与所述位线之间以及所述字线与所述半导体掺杂层之间。
  2. 如权利要求1所述的半导体结构，其特征在于，在所述第一方向上，所述位线上具有至少两列间隔排布的所述半导体通道，所述半导体掺杂层位于所述位线的两侧。
  3. 如权利要求1所述的半导体结构，其特征在于，所述位线至少两条，所述半导体掺杂层位于所述位线的一侧。
  4. 如权利要求3所述的半导体结构，其特征在于，相邻的所述两条位线的所述半导体掺杂层位于不同侧。
  5. 如权利要求1所述的半导体结构，其特征在于，所述位线的材料包括金属；所述半导体结构还包括：介质层，所述介质层位于所述位线顶面，且所述半导体掺杂层还位于所述介质层侧面，所述半导体通道位于所述介质层表面。
  6. 如权利要求1所述的半导体结构，其特征在于，所述基底为半导体衬底；所述半导体结构还包括：阻挡层，所述阻挡层位于所述基底内且凸出于所述基底上方，所述半导体通道位于所述阻挡层部分顶面。
  7. 如权利要求6所述的半导体结构，其特征在于，所述隔离层还位于所述半导体通道露出的所述阻挡层顶面，且所述隔离层位于所述字线与所述阻挡层之间。
  8. 如权利要求6所述的半导体结构，其特征在于，所述字线位于所述半导体通道露出的所述阻挡层顶面。
  9. 如权利要求1所述的半导体结构，其特征在于，在平行于所述第二方向上，所述位线的宽度为所述半导体通道的最大宽度的2倍～3.5倍。
  10. 如权利要求9所述的半导体结构，其特征在于，在平行于所述第二方向上，所述半导体通道的最大宽度的范围为10nm～20nm。
  11. 如权利要求1所述的半导体结构，其特征在于，所述半导体掺杂层具有N型离子或P型离子；所述半导体通道包括：
    沟道区，与所述字线正对的所述半导体通道的区域作为所述沟道区，所述沟道区内掺杂有N型离子或者P型离子；
    掺杂区，所述沟道区以外的所述半导体通道的区域作为所述掺杂区，所述掺杂区内的掺杂离子的类型与所述半导体掺杂层内掺杂离子的类型相同。
  12. 如权利要求11所述的半导体结构，其特征在于，所述沟道区内的掺杂离子的类型与所述半导体掺杂层内掺杂离子的类型不同。
  13. 如权利要求1所述的半导体结构，其特征在于，所述位线在所述基底上的正投影面积范围为所述半导体通道在所述基底上的正投影面积的0.5倍～0.8倍。
  14. 如权利要求1所述的半导体结构，其特征在于，所述半导体通道的材料与所述半导体掺杂层的材料相同；所述半导体通道的材料包括硅、锗或者锗化硅。
  15. 如权利要求1所述的半导体结构，其特征在于，所述字线包括间隔排布的字线，所述半导体结构还包括：
    第一隔离层，所述第一隔离层位于相邻的所述字线之间；
    第二隔离层，所述第二隔离层位于所述字线上以及所述第一隔离层上，且所述第二隔离层还位于远离所述字线的所述半导体通道的侧面。
  16. 一种半导体结构的制造方法，其特征在于，包括：
    提供基底，所述基底上具有沿第一方向延伸的位线；
    形成半导体掺杂层以及半导体通道，所述半导体通道位于所述位线上，所述半导体掺杂层位于所述位线的侧面，所述半导体掺杂层顶面与所述半导体通道相接触；
    形成沿第二方向延伸的字线以及字线介质层，所述字线环绕部分所述半导体通道，且所述字线的底表面高于所述位线的顶表面，所述字线介质层位于所述字线与所述半导体通道之间；
    形成隔离层，所述隔离层位于所述字线与所述位线之间以及所述字线与所述半导体掺杂层之间。
  17. 如权利要求16所述的半导体结构的制造方法，其特征在于，形成所述半导体掺杂层以及所述半导体通道的工艺步骤包括：
    提供层叠设置的初始半导体衬底以及第一掺杂层，所述第一掺杂层内掺杂有N型离子或者P型离子，且所述第一掺杂层内具有位线；
    在所述第一掺杂层顶面以及所述位线上形成半导体层；
    图形化所述半导体层以及所述第一掺杂层，剩余所述半导体层作为所述半导体通道，剩余所述第一掺杂层作为所述半导体掺杂层。
  18. 如权利要求17所述的半导体结构的制造方法，其特征在于，采用选择性外延工艺，形成第二掺杂层，且所述第二掺杂层内具有沟槽；在图形化所述半导体层以及所述第一掺杂层之前，还包括：形成牺牲层，所述牺牲层填充满所述沟槽；在图形化所述半导体层以及所述第一掺杂层之后，去除所述牺牲层。
  19. 如权利要求16所述的半导体结构的制造方法，其特征在于，在形成所述字线之后，还包括：对高于所述字线顶面的所述半导体通道进行掺杂处理，且所述掺杂处理的掺杂离子的类型与所述半导体掺杂层中的掺杂离子的类型相同。
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