WO2023130369A1 - 显示基板、显示装置及显示基板的裂纹检测方法 - Google Patents

显示基板、显示装置及显示基板的裂纹检测方法 Download PDF

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Publication number
WO2023130369A1
WO2023130369A1 PCT/CN2022/070787 CN2022070787W WO2023130369A1 WO 2023130369 A1 WO2023130369 A1 WO 2023130369A1 CN 2022070787 W CN2022070787 W CN 2022070787W WO 2023130369 A1 WO2023130369 A1 WO 2023130369A1
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Prior art keywords
area
layer
display
substrate
conductive layer
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PCT/CN2022/070787
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English (en)
French (fr)
Inventor
刘庭良
徐元杰
龙跃
王思雨
楚雨格
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/026,517 priority Critical patent/US20240298485A1/en
Priority to PCT/CN2022/070787 priority patent/WO2023130369A1/zh
Priority to CN202280000009.5A priority patent/CN116868049A/zh
Publication of WO2023130369A1 publication Critical patent/WO2023130369A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
    • G01N27/22—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
    • G01N27/24—Investigating the presence of flaws
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods

Definitions

  • the present application relates to the field of display technology, and in particular to a display substrate, a display device, and a crack detection method for a display substrate.
  • a display substrate includes a display area and a frame area located at least on one side of the display area, and the frame area includes a crack detection area;
  • the display substrate includes a substrate, detection wiring on the substrate, and a conductive layer on the side of the detection wiring away from the substrate; the conductive layer is located in the frame area; the detection wiring The line is located in the crack detection area; at least part of the orthographic projection of the detection wiring on the substrate falls within the orthographic projection of the conductive layer on the substrate.
  • the conductive layer is connected to a constant electrical signal; the conductive layer covers at least part of the crack detection area.
  • the frame area further includes a crack prevention area located on the side of the crack detection area away from the display area, and the display substrate further includes a patterned conductive material layer located in the crack prevention area;
  • the conductive material layer is located between the conductive layer and the substrate; an orthographic projection of the conductive material layer on the substrate falls at least partially within an orthographic projection of the conductive layer on the substrate .
  • the conductive material layer has a network structure.
  • the layer of conductive material is electrically connected to the conductive layer.
  • the display substrate includes a plurality of inorganic layers, and the plurality of inorganic layers are located in a region outside the crack prevention region.
  • the frame area further includes a power signal line area located between the crack detection area and the display area
  • the display substrate further includes a low-level power signal line area located in the power signal line area.
  • At least part of the orthographic projection of the low-level power signal line on the substrate falls within the orthographic projection of the conductive layer on the substrate, or the conductive layer on the substrate.
  • the edge of the orthographic projection close to the display area coincides with the edge of the orthographic projection of the low-level power signal line on the substrate away from the display area.
  • the display substrate includes a touch layer on the substrate, the touch layer includes a plurality of touch electrodes, and the touch layer is at least partially located in the display area; the conductive The layer is set in the same layer as the touch electrode.
  • the display substrate includes a pixel circuit layer on the substrate, the pixel circuit layer is at least partially located in the display area; the pixel circuit layer includes a plurality of conductive film layers, and the conductive layer and at least one conductive film layer of the pixel circuit layer are arranged in the same layer.
  • the pixel circuit layer includes a pixel circuit, the pixel circuit includes a thin film transistor and a capacitor, the thin film transistor includes a source electrode and a gate electrode, and the capacitor includes a first capacitor plate and a second capacitor electrode plate, the first capacitive plate is set on the same layer as the gate electrode;
  • the plurality of conductive film layers include the gate electrode, the source electrode and the second capacitive plate; the conductive layer and the source electrode are arranged on the same layer.
  • At least part of the detection wiring is provided on the same layer as at least one of the gate electrode and the second capacitive plate.
  • the frame area further includes a power signal line area located between the crack detection area and the display area
  • the display substrate further includes a low-level power signal line area located in the power signal line area. line; the conductive layer is set on the same layer as the low-level power signal line.
  • the conductive layer is connected to the low-level power signal line; or, the conductive layer is connected to the low-level power signal line with different signals.
  • the frame area further includes a crack prevention area located on the side of the crack detection area away from the display area, and a cutting reserve area located on the side of the crack prevention area away from the crack detection area,
  • the conductive layer covers at least part of the cut-retention area.
  • the conductive layer is connected to a ground signal, or, the conductive layer is connected to a low-level power signal.
  • the frame area further includes a gate drive area located between the display area and the crack detection area, the gate drive area is provided with a gate drive circuit; the conductive layer is located in the area outside the gate drive area.
  • a display device includes the above-mentioned display substrate.
  • a crack detection method for a display substrate is provided.
  • the crack detection method is used for a display substrate, and the display substrate includes a display area and a frame area at least on one side of the display area, and the frame area includes a crack detection area;
  • the detection wiring on the substrate and the conductive layer located on the side of the detection wiring away from the substrate;
  • the conductive layer is located in the frame area;
  • the detection wiring is located in the crack detection area;
  • the detection At least part of the orthographic projection of the trace on the substrate falls within the orthographic projection of the conductive layer on the substrate;
  • the conductive layer is connected to a constant electrical signal;
  • the crack detection method includes:
  • the first capacitance value is the sum of capacitance values between the detection wiring and other conductive structures of the display substrate, where the other conductive structures include the conductive layer;
  • the crack detection method further includes:
  • the location where the detection wire is broken is determined according to the first capacitance value.
  • the thickness and width of the detection trace are the same everywhere; the determining the location where the detection trace is broken according to the first capacitance value includes:
  • the trace length is calculated using the following formula:
  • Cx is the first capacitance value
  • C0 is the second capacitance value
  • the second capacitance value is the sum of capacitance values between the detection wiring and other conductive structures not including the conductive layer
  • C1 is the third capacitance value
  • the second capacitance value is the third capacitance value between the detection wiring and other conductive structures of the display substrate when the detection wiring is not broken, and the other conductive structures
  • the structure includes the conductive layer
  • L is the total length of the detection wiring
  • Lx is the wiring length between the location where the detection wiring is broken and the starting end of the detection wiring.
  • the conductive layer in the display substrate located on the side of the detection line away from the substrate is connected to a constant electrical signal, and the detection line is positive on the substrate. If the projection falls within the orthographic projection of the conductive layer on the substrate, the conductive layer can prevent the static charge accumulated on the surface of the display substrate from being conducted to the direction close to the substrate, effectively preventing the static charge from being conducted to the pixel circuit layer of the display substrate, and improving the static charge. The problem of shifting the characteristics of the thin film transistors in the pixel circuit layer is caused, and the display effect of the display panel is improved.
  • FIG. 1 is a schematic structural view of a display substrate provided by an exemplary embodiment of the present application
  • Fig. 2 is a partial cross-sectional view of a display substrate provided by an exemplary embodiment of the present application
  • Fig. 3 is a partial cross-sectional view of a display substrate provided by another exemplary embodiment of the present application.
  • Fig. 4A is a partial cross-sectional view of a display substrate provided by another exemplary embodiment of the present application.
  • Fig. 4B is a partial cross-sectional view of a display substrate provided by another exemplary embodiment of the present application.
  • Fig. 4C is a partial cross-sectional view of a display substrate provided by another exemplary embodiment of the present application.
  • FIG. 4D is a schematic diagram of a partial structure of a display substrate provided by an exemplary embodiment of the present application.
  • FIG. 5 is a schematic diagram of a partial structure of a display substrate provided by another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a partial structure of the display substrate shown in FIG. 3;
  • FIG. 7 is a schematic diagram of a partial structure of the display substrate shown in FIG. 4A .
  • first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word “if” as used herein may be interpreted as “at” or “when” or “in response to a determination.”
  • Embodiments of the present application provide a display substrate, a display device, and a crack detection method for a display substrate.
  • the display substrate, the display device, and the crack detection method for the display substrate in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the case of no conflict, the features in the following embodiments may complement each other or be combined with each other.
  • the embodiment of the present application provides a display substrate.
  • the display substrate 100 includes a display area 101 and a frame area 102 at least on one side of the display area 101 .
  • the frame area 102 includes a crack detection area 1021 .
  • the display substrate 100 includes a substrate 10 , a detection wiring 82 on the substrate 10 , and a conductive layer 30 on a side of the detection wiring 82 away from the substrate 10 .
  • the detection wiring 82 is located in the crack detection area 1021 .
  • the orthographic projection of the detection wiring 82 on the substrate 10 falls within the orthographic projection of the conductive layer 30 on the substrate 10 .
  • the conductive layer 30 is located on the side of the detection trace 82 away from the substrate 10, and the orthographic projection of the detection trace 82 on the substrate 10 falls on the orthographic projection of the conductive layer 30 on the substrate.
  • the conductive layer 30 can prevent the static charge accumulated on the surface of the display substrate from being conducted to the direction close to the substrate, effectively avoiding the conduction of the static charge to the pixel circuit layer of the display substrate, and improving the characteristic deviation of the thin film transistor of the pixel circuit layer caused by the static charge. problem, improve the display effect of the display panel.
  • the conductive layer 30 is connected to a constant electrical signal. In this way, the conductive layer 30 can effectively prevent the electrostatic charge accumulated on the surface of the display substrate from conducting toward the direction close to the substrate 10.
  • the frame region 102 of the display substrate 100 includes a left frame, an upper frame and a right frame of the display substrate.
  • the frame area 102 of the display substrate may further include a lower frame.
  • the lower side frame may be a side frame of the display substrate for binding the driver chip; the upper side frame is the opposite side of the lower side frame; the left side frame is opposite to the right side frame.
  • the frame area 102 of the display substrate 100 further includes a gate drive area 1022 located between the display area 101 and the crack detection area 1021, and a gate drive area 1022 located between the gate drive area 1022 and the crack detection area.
  • the sum of the widths of the crack detection area 1021 and the crack prevention area 1024 ranges from 162 ⁇ m to 198 ⁇ m.
  • the sum of the widths of the crack detection area 1021 and the crack prevention area 1024 may be 162 ⁇ m, 170 ⁇ m, 175 ⁇ m, 180 ⁇ m, 185 ⁇ m, 190 ⁇ m, 198 ⁇ m, etc.
  • display substrates are generally produced in batches, and multiple display substrates share a common substrate. After the film layer structure of the display substrate is fabricated, the common substrate needs to be cut to obtain multiple independent display substrates. , the substrate of each display substrate is a part of the common substrate.
  • the frame area 102 of the display substrate Before cutting the common substrate, the frame area 102 of the display substrate further includes a cutting area located on the side of the crack prevention area 1024 facing away from the display area 101 , and the width of the cutting area ranges from 108 ⁇ m to 132 ⁇ m. In some embodiments, the width of the cutting area may be 108 ⁇ m, 110 ⁇ m, 115 ⁇ m, 120 ⁇ m, 125 ⁇ m, 132 ⁇ m, etc.
  • the frame area 102 also includes a cutting reserved area 1025 located on the side of the crack prevention area 1024 away from the display area 101 .
  • the gate driving region 1022 is provided with a gate driving circuit 90 ; the conductive layer 30 is located outside the gate driving region 1022 .
  • the gate drive circuit consists of transistors and capacitors.
  • the display substrate further includes a low-level power signal line 81 located in the power signal line region 1023 .
  • the low-level power signal line 81 is configured to connect a low-level power signal.
  • the display substrate further includes a patterned conductive material layer 83 located in the crack prevention area 1024; the conductive material layer 83 is located between the conductive layer 30 and Between the substrates 10, the conductive material layer 83 is connected to a constant electrical signal; the orthographic projection of the conductive material layer 83 on the substrate 10 at least partially falls on the conductive layer 30 on the substrate. within the orthographic projection on 10.
  • the conductive material layer 83 can prevent the crack from extending to the display area, preventing the crack from continuing to extend toward the display area 101 and causing gate cracks.
  • the gate drive circuit in the electrode drive area or the pixel circuit in the display area is damaged, which causes some sub-pixels of the display panel to fail to emit light normally, which helps to improve the display reliability of the display panel; since the conductive material layer 83 is connected to the constant If the electric signal is received, the conductive material layer 83 can play a role of shielding the static charge, further preventing the static charge from being conducted to the display area 101, and further ensuring the display effect of the display substrate.
  • the conductive material layer 83 has a network structure. In this way, when the common substrate is cut, the conductive material layer 83 can more effectively prevent cracks from extending to the display area.
  • the conductive material layer 83 includes a plurality of first wires 831 extending in the same direction and second wires 832 located between adjacent first wires 831 , and adjacent first wires 831 can be arranged before There are a plurality of second traces 832 , and adjacent first traces 831 are connected through the second traces 832 , so that the wire material layer 83 as a whole has a mesh structure.
  • the conductive material layer 83 is electrically connected to the conductive layer 30 . Since the conductive layer 30 is connected to a stable electrical signal and the conductive material layer 83 is electrically connected to the conductive layer 30 , the conductive material layer 83 and the conductive layer are connected to the same stable electrical signal. Wherein, in the embodiment shown in Figure 2 and Figure 3, the conductive material layer 83 is in direct contact with the conductive layer 30; in the embodiment shown in Figure 4A, an insulating layer is provided between the conductive material layer 83 and the conductive layer 30, and the conductive The material layer 83 is electrically connected to the conductive layer 30 through vias penetrating the insulating layer therebetween.
  • the display substrate further includes a pixel circuit layer 40 on the substrate 10, a light emitting layer 50 on the side of the pixel circuit layer 40 away from the substrate 10,
  • the encapsulation layer 60 on the side of the light emitting layer 50 away from the substrate 10
  • the touch layer 70 on the side of the encapsulation layer 60 away from the substrate 10 .
  • the pixel circuit layer 40 is at least partially located in the display area 101
  • the light emitting layer 50 is located in the display area 101 .
  • the encapsulation layer 60 is located in the display area 101 and the frame area 102 , and the encapsulation layer 60 can cover the gate driving area 1022 , the power signal line area 1023 , the crack detection area 1021 and the crack prevention area 1024 of the frame area 102 .
  • the light-emitting layer 50 includes a plurality of sub-pixels 501, and the sub-pixels 501 include a first electrode 51, an organic light-emitting layer 52 located on the side of the first electrode 51 facing away from the substrate 10, and an organic light-emitting layer 52 located on the side away from the organic light-emitting layer 52.
  • the second electrode 53 on one side of the substrate 10 .
  • the first electrode 51 may be an anode
  • the second electrode 53 may be a cathode.
  • the second electrode 53 of each sub-pixel 501 of the light emitting layer 50 may be a connected surface electrode.
  • the cathode of the sub-pixel can be electrically connected to the low-level power signal line 81, and the low-level power signal line 81 provides the cathode with a low-level power signal.
  • the low-level power signal connected to the cathode of the sub-pixel is a constant electrical signal, and in the display area 101 , the cathode of the sub-pixel can prevent static charges from being conducted to the pixel circuit.
  • the light emitting layer 50 further includes a pixel defining layer 54 , and the pixel defining layer 54 is provided with pixel openings corresponding to the sub-pixels one by one.
  • the first electrode 51 is located between the pixel defining layer 54 and the pixel circuit layer 40 , and the pixel opening exposes at least part of the corresponding first electrode 51 .
  • the pixel circuit layer 40 includes a plurality of pixel circuits, the pixel circuits may correspond to the sub-pixels 501 one by one, and the pixel circuits drive the corresponding sub-pixels 501 .
  • the pixel circuit includes a thin film transistor 401 and a capacitor 402 .
  • the thin film transistor 401 includes an active layer 41 , a gate electrode 42 , a first electrode 43 and a second electrode 44 .
  • One of the first electrode 43 and the second electrode 44 is a source electrode, and the other is a drain electrode.
  • the capacitor 402 includes a first capacitor plate 45 and a second capacitor plate 46 located on the side of the first capacitor plate 45 facing away from the substrate 10 .
  • the pixel circuit layer 40 may further include a gate insulating layer 403 , a capacitor insulating layer 404 , an interlayer dielectric layer 405 and a planarization layer 406 .
  • the gate insulating layer 403 is located between the active layer 41 and the gate electrode 42
  • the capacitor insulating layer 404 is located between the first capacitor plate 45 and the second capacitor plate 46
  • the interlayer dielectric layer 405 is located between the second capacitor plate 46 and the planarization layer 406 .
  • Parts of the first pole 43 and the second pole 44 are located between the interlayer dielectric layer 405 and the planarization layer, and the other part passes through the through hole penetrating the interlayer dielectric layer 405, the capacitor insulating layer 404 and the gate insulating layer 403 and has The source layer 41 is electrically connected.
  • the first electrode 51 of the sub-pixel 501 is electrically connected to the first electrode 43 of the thin film transistor 401 through the through hole penetrating the planarization layer 406 .
  • the first pole 43 is a source; when the thin film transistor 401 is a p-type transistor, the first pole 43 is a drain.
  • the pixel circuit layer 40 includes a plurality of conductive film layers, and the multiple conductive film layers include the gate electrode 42 of the thin film transistor 401, the thin film transistor The source electrode of 401 and the second capacitor plate 46 of the capacitor 402 .
  • the pixel circuit layer 40 further includes a transfer portion 47
  • the planarization layer 406 includes a first sub-planarization layer 4061 and the first sub-planarization layer 4061 is located away from the substrate 10
  • the second sub-planarization layer 4062 on one side, the transfer portion 47 is located between the first sub-planarization layer 4061 and the second sub-planarization layer 4062 .
  • the first electrode 51 is electrically connected to the first pole 43 of the thin film transistor 401 through the transfer portion 47 .
  • the plurality of conductive film layers of the pixel circuit layer 40 also includes a transfer portion 47 .
  • the detection wiring 82 is provided on the same layer as the gate electrode or the second capacitive plate 46 . In this way, the detection wiring 82 can be formed simultaneously with the gate electrode or the second capacitor plate 46, and the formation of the detection wiring 82 does not require a separate process step, which helps to simplify the manufacturing process of the display substrate.
  • a part of the detection wiring 82 is provided on the same layer as the gate electrode, another part is provided on the same layer as the second capacitor plate, and the part provided on the same layer as the gate electrode and the part provided on the same layer as the second capacitor plate Parts are electrically connected through vias penetrating the capacitive insulating layer.
  • all parts of the detection wiring 82 are located on the same layer, the detection wiring 82 is arranged on the same layer as the gate electrode, or the detection wiring 82 is arranged on the same layer as the second capacitive plate 46 . In the embodiments shown in FIG. 2 to FIG. 4C , the detection wiring 82 is arranged on the same layer as the gate electrode.
  • the conductive material layer 83 is disposed on the same layer as the gate electrode or the second capacitive plate 46 . In this way, the conductive material layer 83 can be formed simultaneously with the gate electrode or the second capacitor plate 46, and the formation of the conductive material layer 83 does not require a separate process step, which helps to simplify the manufacturing process of the display substrate.
  • a part of the conductive material layer 83 is provided on the same layer as the gate electrode, another part is provided on the same layer as the second capacitor plate, and the part provided on the same layer as the gate electrode and the part provided on the same layer as the second capacitor plate Parts are electrically connected through vias penetrating the capacitive insulating layer.
  • all parts of the conductive material layer 83 are located on the same layer, the conductive material layer 83 is set on the same layer as the gate electrode, or the detection wiring 82 is set on the same layer as the second capacitive plate 46 .
  • the conductive material layer 83 and the second capacitive plate 46 are arranged in the same layer.
  • the encapsulation layer 60 is a thin film encapsulation layer.
  • the thin film encapsulation layer may include alternately arranged organic layers and inorganic layers.
  • the thin film encapsulation layer includes two inorganic layers and an organic layer located between the two inorganic layers.
  • the touch layer 70 includes a plurality of touch electrodes 71 arranged at intervals.
  • the touch electrodes 71 may be located in the display area 101 , or the touch electrodes 71 may be partially located in the display area 101 and partially extend to the frame area 102 .
  • the touch electrode 71 includes a touch grid pattern 300 ; each touch grid of the touch grid pattern 300 is arranged around at least one sub-pixel 501 .
  • multiple sub-pixels of the display substrate are divided into multiple pixel units, and the pixel units may include red sub-pixels 210 , green sub-pixels 220 and blue sub-pixels 230 .
  • the pixel units may include red sub-pixels 210 , green sub-pixels 220 and blue sub-pixels 230 .
  • the display substrate further includes a touch signal line 410 located outside the touch electrode 71 , and the touch signal line 410 is electrically connected to the touch grid pattern 300 in the touch layer.
  • the touch signal line 410 may be a TX line (transmission signal line) or an RX line (reception signal line).
  • the orthographic projection of the conductive layer 30 on the substrate 10 is located outside the orthographic projection of the touch signal line 410 on the substrate 10, that is, the touch signal line 410 is located
  • the orthographic projection on the substrate 10 is on the side facing away from the display area.
  • the display substrate includes a plurality of inorganic layers, and the plurality of inorganic layers are located outside the crack prevention area 1024 . That is, the inorganic layer of the display substrate is not disposed in the crack stop area 1024 .
  • the plurality of inorganic layers of the display substrate may include a gate insulating layer 403 , a capacitor insulating layer 404 , an interlayer dielectric layer 405 , and an inorganic layer of the encapsulation layer 60 . As shown in FIG. 2 to FIG.
  • the crack prevention area 1024 is not provided with an inorganic layer, but only has a planarization layer 406, a pixel definition layer 54, and an encapsulation layer 60, wherein the encapsulation layer 60 located in the crack prevention area 1024 only includes an encapsulation layer
  • the organic layer of the encapsulation layer 60 and the inorganic layer of the encapsulation layer 60 are not disposed in the crack prevention area 1024 .
  • the cracks are easy to extend along the inorganic layer, by setting the inorganic layer of the display substrate in the area outside the crack prevention area 1024, it is more helpful to improve the effect of the crack prevention area 1024 in preventing cracks from extending to the display area 101, and further improve the performance of the display panel. Show reliability.
  • the conductive layer 30 is connected to a ground signal, or, the conductive layer is connected to a low-level power signal. Both the ground signal and the low-level power signal are constant electrical signals.
  • the conductive layer 30 covers at least part of the crack detection area.
  • the conductive layer 30 is a patterned film layer.
  • the orthographic projection of the conductive layer 30 on the substrate 10 and the orthographic projection of the detection trace 82 on the substrate 10 may substantially coincide.
  • the orthographic projection of the conductive layer 30 on the substrate 10 roughly coincides with the orthographic projection of the detection wiring 82 on the substrate 10, which means that the orthographic projection of the conductive layer 30 on the substrate covers the detection wiring 82 on the substrate.
  • the orthographic projection on the substrate 10, or the orthographic projection of the conductive layer 30 on the substrate and the orthographic projection of the detection wiring 82 on the substrate 10 mostly overlap, and the edge of the orthographic projection of the conductive layer 30 on the substrate overlaps with the detection wiring 82.
  • the edge of the orthographic projection of 82 on the substrate 10 has at least a partially non-overlapping area, or the conductive layer 30 is a patterned film layer, and the orthographic projection of the hollow area on the substrate has at least part of the exposed detection wiring The area where the orthographic projection of 82 on the substrate 10 is located.
  • the conductive layer 30 covers the crack detection area 1021 .
  • the part of the conductive layer 30 located in the crack detection area 1021 may be a continuous film layer without patterning, covering the crack detection area 1021 .
  • the conductive layer 30 has a better shielding effect on static charges, and can more effectively prevent static charges from being transmitted to the thin film transistors of the pixel circuit layer 40 .
  • the conductive layer 30 is disposed on the same layer as at least one conductive film layer of the pixel circuit layer 40 . In this way, the conductive layer 30 and at least one conductive film layer of the pixel circuit layer 40 are formed simultaneously in one patterning process, which helps to simplify the manufacturing process of the display substrate.
  • the conductive layer 30 is set on the same layer as the low-level power signal line 81 .
  • the conductive layer 30 and the low-level power signal line 81 can be formed in one patterning process, which further simplifies the manufacturing process.
  • the conductive layer 30 and the source electrode of the thin film transistor 401 are disposed on the same layer.
  • the static charge is shielded by the conductive layer 30 when it is conducted to the conductive layer 30, and cannot continue to conduct downward through the conductive layer 30, while the gate electrode,
  • Both the active layer and the capacitor are located on the side of the conductive layer 30 close to the substrate, the probability of electrostatic charge conduction to the gate electrode, the active layer, and the capacitor is greatly reduced, and the conductive layer 30 can better avoid the influence of static charge on the pixel circuit.
  • the conductive material layer 83 is provided on the same layer as the gate electrode of the thin film transistor or the second capacitor plate of the capacitor, and when no inorganic layer is provided in the crack prevention region 1024, the conductive layer 30 is in direct contact with the conductive material layer, Thus the conductive layer 30 is electrically connected to the conductive material layer.
  • the conductive layer 30 is connected to the low-level power signal line 81 .
  • the conductive layer 30 and the low-level power signal line 81 may be located on the same layer, and the conductive layer 30 is continuous with the low-level power signal line 81 . In this way, both the conductive layer 30 and the low-level power signal line 81 are connected to the low-level power signal, and there is no need to arrange the wiring for connecting the conductive layer 30 to the low-level power signal, which helps to simplify the wiring complexity of the display substrate.
  • the conductive layer 30 is spaced apart from the level power signal line 81 , and the conductive layer 30 and the low level power signal line 81 can be connected to different signals.
  • the conductive layer 30 is connected to a ground signal
  • the low-level power signal line 81 is connected to a low-level power signal.
  • the conductive layer 30 is located on a side of the low-level power signal line 81 away from the substrate. At least part of the orthographic projection of the low-level power signal line 81 on the substrate 10 falls within the orthographic projection of the conductive layer 30 on the substrate 10, or, the conductive layer 30 is in the The edge of the orthographic projection on the substrate 10 close to the display area 101 coincides with the edge of the orthographic projection of the low-level power signal line 81 on the substrate 10 away from the display area 101 .
  • the low-level power supply signal line 81 is connected to the low-level power supply signal, and the low-level power supply signal is a constant electrical signal, the low-level power supply signal line 81 can play the role of shielding static charges, which can prevent static charges from moving along the low-level power supply signal.
  • the flat power supply signal line 81 is conducted to the display area 101; the orthographic projection of the conductive layer 30 on the substrate 10 is close to the edge of the display area 101 and the orthographic projection of the low-level power signal line 81 on the substrate 10 is away from the display area 101 , or at least part of the orthographic projection of the low-level power signal line 81 on the substrate 10 falls within the orthographic projection of the conductive layer 30 on the substrate 10, then the static charge cannot be conducted downward through the crack detection region 1021 , and cannot be conducted downward through the power signal line area 1023 , which is more helpful to avoid electrostatic charges from being conducted to the thin film transistors of the pixel circuit, and to ensure the display reliability of the display substrate.
  • the orthographic projection of the low-level power signal line 81 on the substrate 10 falls within the orthographic projection of the conductive layer 30 on the substrate 10.
  • the orthographic projection of the conductive layer 30 on the substrate covers a part of the orthographic projection of the low-level power signal line 81 on the substrate. In this way, the shielding effect of the conductive layer 30 and the low-level power signal line 81 on static charges is better.
  • the low-level power signal line 81 surrounds the display area 101 and overlaps with the cathodes of the sub-pixels.
  • the low-level power signal line 81 may include a first film layer, a second film layer located on the side of the first film layer away from the substrate 10, and a film layer located on the side of the second film layer away from the substrate.
  • the ITO layer close to the substrate in the anode is on the same layer.
  • the conductive layer 30 and the touch electrode 71 are disposed on the same layer. That is, the conductive layer 30 and the touch electrodes 71 are formed in one patterning process.
  • the conductive material layer 83 is arranged on the same layer as the gate electrode of the thin film transistor or the second capacitor plate of the capacitor, the conductive material layer 83 and the conductive layer 30 are electrically connected through the through hole penetrating the organic layer between them. connect.
  • a planarization layer 406, a pixel defining layer 54, and an organic layer of the encapsulation layer 60 are arranged between the conductive layer 30 and the conductive material layer 83.
  • the conductive layer 30 passes through the planarization layer 406, the pixel
  • the via holes of the organic layers defining the layer 54 and the encapsulation layer 60 are electrically connected to the conductive material layer 83 .
  • the conductive layer 30 is not overlapped with the conductive material layer 83 . That is, the conductive layer 30 is not electrically connected to the conductive material layer 83 through the via hole.
  • the conductive layer 30 and the conductive material layer 83 can be connected to the same constant electrical signal through different traces, or the conductive layer 30 and the conductive material layer 83 can be electrically connected together through different traces first, and then connected to the same constant electrical signal. electric signal.
  • the width of the conductive layer 30 ranges from 225 ⁇ m to 275 ⁇ m.
  • the width of the conductive layer 30 is, for example, 225 ⁇ m, 230 ⁇ m, 235 ⁇ m, 240 ⁇ m, 245 ⁇ m, 250 ⁇ m, 255 ⁇ m, 260 ⁇ m, 265 ⁇ m, 270 ⁇ m, 275 ⁇ m or the like.
  • the conductive layer 30 covers at least part of the cutting reserved area 1025. In this way, when the electrostatic charge is conducted downward through the film layer of the cutting reserved area 1025 , the part of the conductive layer 30 located in the cutting reserved area 1025 can block the electrostatic charge, further improving the display reliability of the display substrate.
  • the conductive layer 30 is a continuous film layer without patterning. In the embodiment shown in FIG. 5 , the conductive layer 30 covers the crack detection area 1021 and part of the crack prevention area 1024 , and the conductive layer 30 is spaced apart from the low-level power signal line 81 . In the embodiment shown in FIG.
  • the conductive layer 30 covers the crack detection area 1021 and part of the crack prevention area 1024 , and the conductive layer 30 is continuous with the low-level power signal line 81 .
  • the conductive layer 30 covers the crack detection area 1021 , the crack prevention area 1024 , the cutting reserved area 1025 and part of the power signal line area 1023 .
  • Embodiments of the present application further provide a display device, the display device comprising the display substrate described in any one of the above embodiments.
  • the display device is a display panel
  • the display panel further includes a polarizer on a side of the touch layer 70 away from the substrate and a cover plate on a side of the polarizer away from the substrate.
  • the display panel also includes optical glue between the polarizer and the cover.
  • the cover can be a glass cover.
  • the display device includes a casing and a display panel, and the display panel is arranged in the casing.
  • the display device provided in the embodiment of the present application may be, for example, any device with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, and a vehicle-mounted device.
  • the embodiment of the present application also provides a crack detection method of a display substrate.
  • the crack detection method is used for the display substrate described in any one of the above embodiments.
  • the crack detection method includes the following processes:
  • the first capacitance value is the sum of capacitance values between the detection wiring and other conductive structures of the display substrate, where the other conductive structures include the conductive layer;
  • the other conductive structures of the display substrate refer to all other conductive structures of the display substrate except the detection wiring, such as capacitor plates of pixel circuits, conductive structures of thin film transistors, etc.
  • the capacitance threshold range is the range of the capacitance value between the detection line and other conductive structures of the display substrate when the detection line is not broken, and the capacitance threshold range is a known value range.
  • a voltage signal can be written into the conductive layer, and then the voltage change of the detection wiring is detected, and the chip determines the first capacitance value according to the voltage change of the detection wiring.
  • the crack detection method further includes: determining the location where the detection wire is broken according to the first capacitance value.
  • the thickness and width of the detection trace are the same everywhere; the determining the location where the detection trace is broken according to the first capacitance value includes:
  • the location where the detected wire is broken is determined according to the length of the wire.
  • the trace length is calculated using the following formula:
  • Cx is the first capacitance value
  • C0 is the second capacitance value
  • the second capacitance value is the sum of capacitance values between the detection wiring and other conductive structures not including the conductive layer
  • C1 is the third capacitance value
  • the second capacitance value is the third capacitance value between the detection wiring and other conductive structures of the display substrate when the detection wiring is not broken, and the other conductive structures
  • the structure includes the conductive layer
  • L is the total length of the detection wiring
  • Lx is the wiring length between the location where the detection wiring is broken and the starting end of the detection wiring.
  • the starting end of the detection line is the end of the detection line close to the chip.

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Abstract

一种显示基板（100）、显示装置及显示基板（100）的裂纹检测方法。显示基板（100）包括显示区（101）和至少位于显示区（101）一侧的边框区（102），边框区（102）包括裂纹检测区（1021）。显示基板（100）包括衬底（10）、位于衬底（10）上的检测走线（82）及位于检测走线（82）背离衬底（10）一侧的导电层（30）；导电层（30）位于边框区（102）；检测走线（82）位于裂纹检测区（1021）；检测走线（82）在衬底（10）上的正投影的至少部分落在导电层（30）在衬底（10）上的正投影内。显示装置包括显示面板。

Description

显示基板、显示装置及显示基板的裂纹检测方法 技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板、显示装置及显示基板的裂纹检测方法。
背景技术
随着科学技术的不断发展，越来越多的显示设备被广泛地应用到人们的日常生活以及工作当中，成为人们不可缺少的重要工具。
显示设备在制作及使用过程中，不可避免的会产生静电荷，静电荷传导至显示面板的像素电路的薄膜晶体管时，会导致薄膜晶体管的特性偏移，进而影响显示面板的显示效果。
发明内容
根据本申请实施例的第一方面，提供了一种显示基板。所述显示基板包括显示区和至少位于所述显示区一侧的边框区，所述边框区包括裂纹检测区；
所述显示基板包括衬底、位于所述衬底上的检测走线及位于所述检测走线背离所述衬底一侧的导电层；所述导电层位于所述边框区；所述检测走线位于所述裂纹检测区；所述检测走线在所述衬底上的正投影的至少部分落在所述导电层在所述衬底上的正投影内。
在一个实施例中，所述导电层连接恒定的电信号；所述导电层至少覆盖部分所述裂纹检测区。
在一个实施例中，所述边框区还包括位于所述裂纹检测区背离所述显示区一侧的裂纹阻止区，所述显示基板还包括位于所述裂纹阻止区的图形化的导电材料层；所述导电材料层位于所述导电层与所述衬底之间；所述导电 材料层在所述衬底上的正投影至少部分落在所述导电层在所述衬底上的正投影内。
在一个实施例中，所述导电材料层呈网状结构。
在一个实施例中，所述导电材料层与所述导电层电连接。
在一个实施例中，所述显示基板包括多个无机层，所述多个无机层位于所述裂纹阻止区之外的区域。
在一个实施例中，所述边框区还包括位于所述裂纹检测区与所述显示区之间的电源信号线区，所述显示基板还包括位于所述电源信号线区的低电平电源信号线；
所述低电平电源信号线在所述衬底上的正投影的至少部分落在所述导电层在所述衬底上的正投影内，或者，所述导电层在所述衬底上的正投影靠近显示区的边缘与所述低电平电源信号线在所述衬底上的正投影背离所述显示区的边缘重合。
在一个实施例中，所述显示基板包括位于所述衬底上的触控层，所述触控层包括多个触控电极，所述触控层至少部分位于所述显示区；所述导电层与所述触控电极同层设置。
在一个实施例中，所述显示基板包括位于所述衬底上的像素电路层，所述像素电路层至少部分位于所述显示区；所述像素电路层包括多个导电膜层，所述导电层与所述像素电路层的至少一个所述导电膜层同层设置。
在一个实施例中，所述像素电路层包括像素电路，所述像素电路包括薄膜晶体管和电容，所述薄膜晶体管包括源电极和栅电极，所述电容包括第一电容极板和第二电容极板，所述第一电容极板与所述栅电极同层设置；
所述多个导电膜层包括所述栅电极、所述源电极及所述第二电容极板；所述导电层与所述源电极同层设置。
在一个实施例中，所述检测走线的至少部分与所述栅电极和所述第二电容极板的至少之一同层设置。
在一个实施例中，所述边框区还包括位于所述裂纹检测区与所述显示区之间的电源信号线区，所述显示基板还包括位于所述电源信号线区的低电平电源信号线；所述导电层与所述低电平电源信号线同层设置。
在一个实施例中，所述导电层与所述低电平电源信号线相连；或者，所述导电层与所述低电平电源信号线连接不同的信号。
在一个实施例中，所述边框区还包括位于所述裂纹检测区背离所述显示区一侧的裂纹阻止区、及位于所述裂纹阻止区背离所述裂纹检测区一侧的切割保留区，所述导电层覆盖至少部分所述切割保留区。
在一个实施例中，所述导电层连接接地信号，或者，所述导电层连接低电平电源信号。
在一个实施例中，所述边框区还包括位于所述显示区与所述裂纹检测区之间的栅极驱动区，所述栅极驱动区设有栅极驱动电路；所述导电层位于所述栅极驱动区之外的区域。
根据本申请实施例的第二方面，提供了一种显示装置。所述显示装置包括上述的显示基板。
根据本申请实施例的第三方面，提供了一种显示基板的裂纹检测方法。所述裂纹检测方法用于显示基板，所述显示基板包括显示区和至少位于所述显示区一侧的边框区，所述边框区包括裂纹检测区；所述显示基板包括衬底、位于所述衬底上的检测走线及位于所述检测走线背离所述衬底一侧的导电层；所述导电层位于所述边框区；所述检测走线位于所述裂纹检测区；所述检测走线在所述衬底上的正投影的至少部分落在所述导电层在所述衬底上的正投影内；所述导电层连接恒定的电信号；
所述裂纹检测方法包括：
检测第一电容值，所述第一电容值为所述检测走线与所述显示基板的其他导电结构之间的电容值之和，所述其他导电结构包括所述导电层；
若所述第一电容值不在电容阈值范围内，确定所述检测走线发生断裂。
在一个实施例中，所述确定所述检测走线发生断裂之后，所述裂纹检测方法还包括：
根据所述第一电容值确定所述检测走线发生断裂的位置。
在一个实施例中，所述检测走线各处的厚度及宽度均相同；所述根据所述第一电容值确定所述检测走线发生断裂的位置，包括：
计算所述检测走线发生断裂的位置与所述检测走线的起始端之间的走线长度，
根据所述走线长度确定所述检测走线发生断裂的位置；
所述走线长度采用如下计算公式计算：
Lx＝(Cx-C0)*L/(C1-C0)
式中，Cx为所述第一电容值；C0为第二电容值，所述第二电容值为所述检测走线与不包括所述导电层的其他导电结构之间的电容值之和；C1为第三电容值，所述第二电容值为所述检测走线未发生断裂时，所述检测走线与所述显示基板的其他导电结构之间的第三电容值，所述其他导电结构包括所述导电层；L为所述检测走线的总长，Lx为所述检测走线发生断裂的位置与所述检测走线的起始端之间的走线长度。
本申请实施例所达到的主要技术效果是：
本申请实施例提供的显示基板、显示装置及显示基板的裂纹检测方法，显示基板中位于检测走线背离衬底一侧的导电层连接恒定的电信号，且检测走线在衬底上的正投影落在导电层在衬底上的正投影内，则导电层可阻止显示基板表面积累的静电荷向靠近衬底的方向传导，有效避免静电荷传导至显 示基板的像素电路层，改善静电荷导致像素电路层的薄膜晶体管的特性偏移的问题，改善显示面板的显示效果。
附图说明
图1是本申请一示例性实施例提供的显示基板的结构示意图；
图2是本申请一示例性实施例提供的显示基板的局部剖视图；
图3是本申请另一示例性实施例提供的显示基板的局部剖视图；
图4A是本申请再一示例性实施例提供的显示基板的局部剖视图；
图4B是本申请又一示例性实施例提供的显示基板的局部剖视图；
图4C是本申请又一示例性实施例提供的显示基板的局部剖视图；
图4D是本申请一示例性实施例提供的显示基板的局部结构示意图；
图5是本申请又一实施例提供的显示基板的局部结构示意图；
图6是图3所示的显示基板的局部结构示意图；
图7是图4A所示的显示基板的局部结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本申请相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解， 本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
本申请实施例提供了一种显示基板、显示装置及显示基板的裂纹检测方法。下面结合附图，对本申请实施例中的显示基板、显示装置及显示基板的裂纹检测方法进行详细说明。在不冲突的情况下，下述的实施例中的特征可以相互补充或相互组合。
本申请实施例提供了一种显示基板。参见图1，所述显示基板100包括显示区101和至少位于所述显示区101一侧的边框区102。所述边框区102包括裂纹检测区1021。
参见图2至图4A，所述显示基板100包括衬底10、位于所述衬底10上的检测走线82及位于所述检测走线82背离所述衬底10一侧的导电层30。所述检测走线82位于所述裂纹检测区1021。所述检测走线82在所述衬底10上的正投影落在所述导电层30在所述衬底10上的正投影内。
本申请实施例提供的显示基板，导电层30位于检测走线82背离衬底10的一侧，且检测走线82在衬底10上的正投影落在导电层30在衬底上的正投影内，则导电层30可阻止显示基板表面积累的静电荷向靠近衬底的方向传导，有效避免静电荷传导至显示基板的像素电路层，改善静电荷导致像素电路层的薄膜晶体管的特性偏移的问题，改善显示面板的显示效果。
在一个实施例中，所述导电层30连接恒定的电信号。如此设置，导电 层30可有效阻止显示基板表面积累的静电荷向靠近衬底10的方向传导。
在一个实施例中，再次参见图1，显示基板100的边框区102包括包括显示基板的左侧边框、上侧边框和右侧边框。显示基板的边框区102还可包括下侧边框。所述下侧边框，可以是显示基板的用于绑定驱动芯片的一侧边框；所述上侧边框为下侧边框的相对侧；左侧边框与右侧边框相对。
在一个实施例中，所述显示基板100的边框区102还包括位于显示区101与所述裂纹检测区1021之间的栅极驱动区1022、位于所述栅极驱动区1022与所述裂纹检测区1021之间的电源信号线区1023、以及位于所述裂纹检测区1021背离显示区101一侧的裂纹阻止区1024。裂纹检测区1021与裂纹阻止区1024的宽度之和的范围为162μm～198μm。在一些实施例中，所述裂纹检测区1021与裂纹阻止区1024的宽度之和可为162μm、170μm、175μm、180μm、185μm、190μm、198μm等。
在一些实施例中，显示基板一般是批量制作的，多个显示基板共用公共衬底，在显示基板的膜层结构制作完成后，需要对公共衬底进行切割，以得到多个独立的显示基板，每一显示基板的衬底为公共衬底的一部分。在对公共衬底进行切割之前，显示基板的边框区102还包括位于所述裂纹阻止区1024背离显示区101一侧的切割区，切割区的宽度范围为108μm～132μm。在一些实施例中，切割区的宽度可为108μm、110μm、115μm、120μm、125μm、132μm等。理想的切割情况下，在对显示基板进行切割之后，切割区全部被切掉，显示基板的衬底边缘与裂纹阻止区1024的边缘齐平。但是由于切割误差的存在，进行切割后得到的显示基板的切割区可能会有部分被保留，边框区102还包括位于所述裂纹阻止区1024背离显示区101一侧的切割保留区1025。
在一个实施例中，如图1至图4C所示，所述栅极驱动区1022设有栅极驱动电路90；所述导电层30位于所述栅极驱动区1022之外的区域。栅极驱动电路包括晶体管和电容。通过设置导电层30位于栅极驱动区1022之外 的区域，可避免导电层30与栅极驱动区1022内的导电结构之间形成耦合电容，而对栅极驱动电路产生信号干扰，有助于保证显示基板的显示效果。
在一个实施例中，如图2至图4C所示，所述显示基板还包括位于所述电源信号线区1023的低电平电源信号线81。低电平电源信号线81被配置为连接低电平电源信号。
在一个实施例中，如图2至图4C所示，所述显示基板还包括位于所述裂纹阻止区1024的图形化的导电材料层83；所述导电材料层83位于所述导电层30与所述衬底10之间，所述导电材料层83连接恒定的电信号；所述导电材料层83在所述衬底10上的正投影至少部分落在所述导电层30在所述衬底10上的正投影内。
通过在裂纹阻止区1024设置图形化的导电材料层83，在对公共衬底进行切割时，导电材料层83可阻止裂纹向显示区延伸，避免裂纹继续向朝向显示区101的方向延伸而导致栅极驱动区的栅极驱动电路或者显示区的像素电路被破坏，进而造成显示面板的一些子像素无法正常发光的情况，有助于提升显示面板的显示可靠性；由于导电材料层83连接恒定的电信号，则导电材料层83可起到屏蔽静电荷的作用，进一步防止静电荷向显示区101传导，可进一步保证显示基板的显示效果。
进一步地，所述导电材料层83呈网状结构。如此设置，在对公共衬底进行切割时，导电材料层83可更有效地阻止裂纹向显示区延伸。如图5所示，导电材料层83包括多个同向延伸的第一走线831及位于相邻第一走线831之间的第二走线832，相邻第一走线831之前可设有多个第二走线832，相邻第一走线831通过第二走线832相连，从而使导线材料层83整体呈网状结构。
进一步地，如图2至图4C所示，所述导电材料层83与所述导电层30电连接。由于导电层30连接稳定的电信号，导电材料层83与导电层30电连接，则导电材料层83与导电层连接至同一稳定的电信号。其中，图2及图3 所示的实施例中，导电材料层83与导电层30直接接触；图4A所示的实施例中，导电材料层83与导电层30之间设有绝缘层，导电材料层83与导电层30通过穿透它们之间的绝缘层的通孔电连接。
在一个实施例中，参见图2至图4C，所述显示基板还包括位于所述衬底10上的像素电路层40、位于所述像素电路层40背离衬底10一侧的发光层50、位于所述发光层50背离衬底10一侧的封装层60、以及位于所述封装层60背离衬底10一侧的触控层70。所述像素电路层40至少部分位于所述显示区101，所述发光层50位于显示区101。封装层60位于显示区101及边框区102，封装层60可覆盖边框区102的栅极驱动区1022、电源信号线区1023、裂纹检测区1021及裂纹阻止区1024。
在一个实施例中，所述发光层50包括多个子像素501，子像素501包括第一电极51、位于第一电极51背离衬底10一侧的有机发光层52、及位于有机发光层52背离衬底10一侧的第二电极53。第一电极51可以是阳极，第二电极53可以是阴极。发光层50的各子像素501的第二电极53可以是连成一片的面电极。子像素的阴极可与低电平电源信号线81电连接，低电平电源信号线81为阴极提供低电平电源信号。子像素的阴极连接的低电平电源信号为恒定的电信号，则在显示区101，子像素的阴极可阻止静电荷传导至像素电路。
发光层50还包括像素限定层54，像素限定层54设有与子像素一一对应的像素开口。第一电极51位于像素限定层54与像素电路层40之间，像素开口暴露对应的第一电极51的至少部分。
在一个实施例中，所述像素电路层40包括多个像素电路，像素电路可与子像素501一一对应，像素电路驱动对应的子像素501。
在一个实施例中，像素电路包括薄膜晶体管401和电容402。薄膜晶体管401包括有源层41、栅电极42、第一极43和第二极44。第一极43与第二 极44中的一个为源电极，另一个为漏电极。电容402包括第一电容极板45和位于第一电容极板45背离衬底10一侧的第二电容极板46。其中，栅电极42与第一电容极板45可同层设置；第一极43与第二极44可同层设置。两个结构同层设置指的是，两个结构位于同一层且材料相同，可在一次构图工艺中同时形成。
像素电路层40还可包括栅极绝缘层403、电容绝缘层404、层间介质层405及平坦化层406。栅极绝缘层403位于有源层41与栅电极42之间，电容绝缘层404位于第一电容极板45与第二电容极板46之间，层间介质层405位于第二电容极板46与平坦化层406之间。第一极43与第二极44的一部分位于层间介质层405与平坦化层之间，另一部分通过穿透层间介质层405、电容绝缘层404及栅极绝缘层403的通孔与有源层41电连接。子像素501的第一电极51通过穿透平坦化层406的通孔与薄膜晶体管401的第一极43电连接。薄膜晶体管401为n型晶体管时，第一极43为源极；薄膜晶体管401为p型晶体管时，第一极43为漏极。
在一些实施例中，如图2至图4B所示，所述像素电路层40包括多个导电膜层，所述多个导电膜层包括所述薄膜晶体管401的栅电极42、所述薄膜晶体管401的源电极及所述电容402的第二电容极板46。
在一个实施例中，如图4C所示，像素电路层40还包括转接部47，所述平坦化层406包括第一子平坦化层4061及位于第一子平坦化层4061背离衬底10一侧的第二子平坦化层4062，所述转接部47位于第一子平坦化层4061与第二子平坦化层4062之间。所述第一电极51通过转接部47与薄膜晶体管401的第一极43电连接。所述像素电路层40的多个导电膜层还包括转接部47。
在一个实施例中，所述检测走线82的至少部分与所述栅电极或所述第二电容极板46同层设置。如此设置，检测走线82可与栅电极或第二电容极板46可同时形成，检测走线82的形成不需要单独的工艺步骤，有助于简化 显示基板的制备工艺。
在一些实施例中，检测走线82的一部分与栅电极同层设置，另一部分与第二电容极板同层设置，与栅电极同层设置的部分及与第二电容极板同层设置的部分通过穿透电容绝缘层的通孔电连接。在另一些实施例中，检测走线82的各部分均位于同一层，检测走线82与栅电极同层设置，或者检测走线82与第二电容极板46同层设置。图2至图4C所示的实施例中，检测走线82与栅电极同层设置。
在一个实施例中，所述导电材料层83的至少部分与所述栅电极或所述第二电容极板46同层设置。如此设置，导电材料层83可与栅电极或第二电容极板46可同时形成，导电材料层83的形成不需要单独的工艺步骤，有助于简化显示基板的制备工艺。
在一些实施例中，导电材料层83的一部分与栅电极同层设置，另一部分与第二电容极板同层设置，与栅电极同层设置的部分及与第二电容极板同层设置的部分通过穿透电容绝缘层的通孔电连接。在另一些实施例中，导电材料层83各部分均位于同一层，导电材料层83与栅电极同层设置，或者检测走线82与第二电容极板46同层设置。图2至图4C所示的实施例中，导电材料层83与第二电容极板46同层设置。
在一个实施例中，封装层60为薄膜封装层，薄膜封装层可包括交替排布的有机层和无机层，例如薄膜封装层包括两层无机层及位于两层无机层之间的有机层。
在一个实施例中，触控层70包括多个间隔排布的触控电极71。触控电极71可位于显示区101，或者触控电极71部分位于显示区101，部分延伸至边框区102。
如图4D所示，所述触控电极71包括触控网格图案300；所述触控网格图案300的每个触控网格围绕至少一个子像素501设置。
如图4D所示，显示基板的多个子像素被划分为多个像素单元，像素单元可以包括红色子像素210、绿色子像素220和蓝色子像素230。图4C所示的实施例中，一个像素单元中，绿色子像素220有两个，每个颜色子像素501分别对应一触控网格。
如图4D所示，所述显示基板还包括位于所述触控电极71外侧的触控信号线410，触控信号线410与触控层中的触控网格图案300电连接。所述触控信号线410可以是TX线(发射信号线)或RX线(接收信号线)。
在一个实施例中，所述导电层30在衬底10上的正投影位于所述触控信号线410在衬底10上的正投影的外侧，也即是位于所述触控信号线410在衬底10上的正投影背离显示区的一侧。
在一个实施例中，所述显示基板包括多个无机层，所述多个无机层位于所述裂纹阻止区1024之外的区域。也即是，显示基板的无机层未设置在裂纹阻止区1024。显示基板的多个无机层可包括栅极绝缘层403、电容绝缘层404、层间介质层405、以及封装层60的无机层。如图2至图4C所示，裂纹阻止区1024未设置有无机层，仅设有平坦化层406、像素限定层54及封装层60，其中位于裂纹阻止区1024的封装层60只包括封装层60的有机层，封装层60的无机层未设置在裂纹阻止区1024。
由于裂纹易于沿着无机层延伸，通过设置显示基板的无机层位于裂纹阻止区1024之外的区域，更有助于提升裂纹阻止区1024阻止裂纹向显示区101延伸的效果，进一步提升显示面板的显示可靠性。
在一个实施例中，所述导电层30连接接地信号，或者，所述导电层连接低电平电源信号。接地信号与低电平电源信号均为恒定的电信号。
在一个实施例中，所述导电层30至少覆盖部分所述裂纹检测区。
在一个实施例中，如图2所示，所述导电层30为图形化的膜层。导电层30在衬底10上的正投影与检测走线82在衬底10上的正投影可大致重合。 其中，导电层30在衬底10上的正投影与检测走线82在衬底10上的正投影大致重合，指的是导电层30在衬底上的正投影覆盖检测走线82在衬底10上的正投影，或者导电层30在衬底上的正投影与检测走线82在衬底10上的正投影大部分重叠，导电层30在衬底上的正投影的边缘与检测走线82在衬底10上的正投影的边缘具有至少部分不重叠的区域，再或者导电层30为图形化的膜层，其具有的镂空区域在衬底上的正投影至少部分的暴露检测走线82在衬底10上的正投影所在的区域。
在另一实施例中，如图3至图7所示，所述导电层30覆盖所述裂纹检测区1021。导电层30位于裂纹检测区1021的部分可为连续的膜层，未进行图形化，覆盖裂纹检测区1021。如此设置，导电层30对静电荷的屏蔽效果更好，可更有效地避免静电荷传输至像素电路层40的薄膜晶体管。
在一个实施例中，所述导电层30与所述像素电路层40的至少一个所述导电膜层同层设置。如此设置，导电层30与像素电路层40的至少一个导电膜层在一次构图工艺中同时形成，有助于简化显示基板的制备工艺。
进一步地，所述导电层30与所述低电平电源信号线81同层设置。如此设置，导电层30与低电平电源信号线81可在一次构图工艺中形成，可进一步简化制备工艺。
在一些实施例中，如图2及图3所示，所述导电层30与所述薄膜晶体管401的源电极同层设置。如此设置，静电荷在裂纹阻止区1024朝靠近衬底的方向传导的过程中，静电荷传导至导电层30时即被导电层30屏蔽，无法通过导电层30继续向下传导，而栅电极、有源层以及电容均位于导电层30靠近衬底的一侧，静电荷传导至栅电极、有源层以及电容的概率大大减小，导电层30更能避免静电荷对像素电路的影响。
在该实施例中，导电材料层83与薄膜晶体管的栅电极或电容的第二电容极板同层设置，且在裂纹阻止区1024未设置无机层时，导电层30与导电 材料层直接接触，从而导电层30与导电材料层电连接。
在一个实施例中，如图3所示，所述导电层30与所述低电平电源信号线81相连。导电层30与低电平电源信号线81可位于同一层，且导电层30与低电平电源信号线81连续。如此，导电层30与低电平电源信号线81均连接低电平电源信号，无需设置将导电层30连接至低电平电源信号的走线，有助于简化显示基板的走线复杂度。
在另一实施例中，如图2所示，导电层30与电平电源信号线81间隔设置，所述导电层30与所述低电平电源信号线81可连接不同的信号。例如，所述导电层30连接接地信号，所述低电平电源信号线81连接低电平电源信号。
在一个实施例中，如图4A所示，所述导电层30位于所述低电平电源信号线81背离所述衬底的一侧。所述低电平电源信号线81在所述衬底10上的正投影的至少部分落在所述导电层30在所述衬底10上的正投影内，或者，所述导电层30在所述衬底10上的正投影靠近显示区101的边缘与所述低电平电源信号线81在所述衬底10上的正投影背离所述显示区101的边缘重合。
由于低电平电源信号线81连接低电平电源信号，低电平电源信号为恒定的电信号，则低电平电源信号线81可起到屏蔽静电荷的作用，可防止静电荷沿低电平电源信号线81传导至显示区101；通过设置导电层30在衬底10上的正投影靠近显示区101的边缘与低电平电源信号线81在衬底10上的正投影背离显示区101的边缘重合，或者低电平电源信号线81在衬底10上的正投影的至少部分落在导电层30在衬底10上的正投影内，则静电荷无法通过裂纹检测区1021向下传导，也不能通过电源信号线区1023向下传导，更有助于避免静电荷传导至像素电路的薄膜晶体管，保证显示基板的显示可靠性。
优选的，所述低电平电源信号线81在所述衬底10上的正投影的至少 部分落在所述导电层30在所述衬底10上的正投影内。如图4A所示，导电层30在衬底上的正投影覆盖低电平电源信号线81在衬底上的正投影的一部分。如此设置，导电层30与低电平电源信号线81对静电荷的屏蔽效果更好。
在一些实施例中，所述低电平电源信号线81环绕所述显示区101，且与子像素的阴极搭接。所述低电平电源信号线81可包括第一膜层、位于第一膜层背离所述衬底10一侧的第二膜层、及位于所述第二膜层背离所述衬底一侧的第三膜层；其中所述第一膜层与所述转接部位于同一层，所述第二膜层与所述源电极位于同一层，所述第三膜层与所述子像素的阳极中靠近衬底的ITO层位于同一层。
在一个实施例中，如图4A所示，导电层30与触控电极71同层设置。也即是，导电层30与触控电极71在一次构图工艺中形成。在该实施例中，导电材料层83与薄膜晶体管的栅电极或电容的第二电容极板同层设置时，导电材料层83与导电层30通过穿透它们之间的有机层的通孔电连接。图4A所示的实施例中，导电层30与导电材料层83之间设有平坦化层406、像素限定层54及封装层60的有机层，导电层30通过穿透平坦化层406、像素限定层54及封装层60的有机层的通孔，与导电材料层83电连接。
在另一个实施例中，如图4B所示，所述导电层30与所述导电材料层83未搭接。也即是，导电层30与导电材料层83未通过过孔电连接。导电层30与导电材料层83可通过不同的走线连接至同一恒定的电信号，或者导电层30与导电材料层83可首先通过不同的走线电连接在一起，之后再连接至同一恒定的电信号。
进一步地，所述导电层30的宽度范围为225μm～275μm。导电层30的宽度例如为225μm、230μm、235μm、240μm、245μm、250μm、255μm、260μm、265μm、270μm、275μm等。
在一个实施例中，如图4A及图7所示，所述导电层30覆盖至少部分 所述切割保留区1025。如此设置，静电荷通过切割保留区1025的膜层向下传导时，导电层30位于切割保留区1025内的部分可阻挡静电荷，进一步提升显示基板的显示可靠性。在一些实施例中，如图5至图7所示，导电层30为连续的膜层，未进行图形化。图5所示的实施例中，导电层30覆盖裂纹检测区1021和部分裂纹阻止区1024，导电层30与低电平电源信号线81间隔设置。图6所示的实施例中，导电层30覆盖裂纹检测区1021和部分裂纹阻止区1024，导电层30与低电平电源信号线81连续。图7所示的实施例中，导电层30覆盖裂纹检测区1021、裂纹阻止区1024、切割保留区1025以及部分电源信号线区1023。
本申请实施例还提供了一种显示装置，所述显示装置包括上述任一实施例所述的显示基板。
在一个实施例中，所述显示装置为显示面板，所述显示面板还包括位于所述触控层70背离衬底一侧的偏光片以及位于偏光片背离衬底一侧的盖板。显示面板还包括位于偏光片与盖板之间的光学胶。盖板可以是玻璃盖板。
在一个实施例中，所述显示装置包括壳体和显示面板，所述显示面板设置在所述壳体内。
本申请实施例提供的显示装置例如可以为手机、平板电脑、电视机、笔记本电脑、车载设备等任何具有显示功能的设备。
本申请实施例还提供了一种显示基板的裂纹检测方法。所述裂纹检测方法用于上述任一实施例所述的显示基板。所述裂纹检测方法包括如下过程：
首先，检测第一电容值，所述第一电容值为所述检测走线与所述显示基板的其他导电结构之间的电容值之和，所述其他导电结构包括所述导电层；
随后，若所述第一电容值不在电容阈值范围内，确定所述检测走线发生断裂。
其中，所述显示基板的其他导电结构指的是显示基板除检测走线之外 的其他所有导电结构，例如像素电路的电容极板、薄膜晶体管的各导电结构等。电容阈值范围为检测走线未发生断裂时检测走线与所述显示基板的其他导电结构之间的电容值的范围，电容阈值范围为已知的数值范围。
在一个实施例中，可向所述导电层写入电压信号，随后检测检测走线的电压变化，芯片根据检测走线的电压变化确定第一电容值。
在一个实施例中，所述确定所述检测走线发生断裂之后，所述裂纹检测方法还包括：根据所述第一电容值确定所述检测走线发生断裂的位置。
进一步地，所述检测走线各处的厚度及宽度均相同；所述根据所述第一电容值确定所述检测走线发生断裂的位置，包括：
计算所述检测走线发生断裂的位置与所述检测走线的起始端之间的走线长度，
根据所述走线长度确定所述检测走线发生断裂的位置。
所述走线长度采用如下计算公式计算：
Lx＝(Cx-C0)*L/(C1-C0)
式中，Cx为所述第一电容值；C0为第二电容值，所述第二电容值为所述检测走线与不包括所述导电层的其他导电结构之间的电容值之和；C1为第三电容值，所述第二电容值为所述检测走线未发生断裂时，所述检测走线与所述显示基板的其他导电结构之间的第三电容值，所述其他导电结构包括所述导电层；L为所述检测走线的总长，Lx为所述检测走线发生断裂的位置与所述检测走线的起始端之间的走线长度。
其中，检测走线的起始端为检测走线靠近芯片的端部。
可知，采用本申请实施例提供的裂纹检测方法，相对于通过检测走线的电阻来进行裂纹检测的方案来说，可确定检测走线发生断裂的位置，裂纹检测精度更高。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种显示基板，其特征在于，所述显示基板包括显示区和至少位于所述显示区一侧的边框区，所述边框区包括裂纹检测区；
    所述显示基板包括衬底、位于所述衬底上的检测走线及位于所述检测走线背离所述衬底一侧的导电层；所述导电层位于所述边框区；所述检测走线位于所述裂纹检测区；所述检测走线在所述衬底上的正投影的至少部分落在所述导电层在所述衬底上的正投影内。
  2. 根据权利要求1所述的显示基板，其特征在于，所述导电层连接恒定的电信号；所述导电层至少覆盖部分所述裂纹检测区。
  3. 根据权利要求1所述的显示基板，其特征在于，所述边框区还包括位于所述裂纹检测区背离所述显示区一侧的裂纹阻止区，所述显示基板还包括位于所述裂纹阻止区的图形化的导电材料层；所述导电材料层位于所述导电层与所述衬底之间；所述导电材料层在所述衬底上的正投影至少部分落在所述导电层在所述衬底上的正投影内。
  4. 根据权利要求3所述的显示基板，其特征在于，所述导电材料层呈网状结构。
  5. 根据权利要求3所述的显示基板，其特征在于，所述导电材料层与所述导电层电连接。
  6. 根据权利要求3所述的显示基板，其特征在于，所述显示基板包括多个无机层，所述多个无机层位于所述裂纹阻止区之外的区域。
  7. 根据权利要求1所述的显示基板，其特征在于，所述边框区还包括位于所述裂纹检测区与所述显示区之间的电源信号线区，所述显示基板还包括位于所述电源信号线区的低电平电源信号线；
    所述低电平电源信号线在所述衬底上的正投影的至少部分落在所述导电层在所述衬底上的正投影内，或者，所述导电层在所述衬底上的正投影靠近显示区的边缘与所述低电平电源信号线在所述衬底上的正投影 背离所述显示区的边缘重合。
  8. 根据权利要求1所述的显示基板，其特征在于，所述显示基板包括位于所述衬底上的触控层，所述触控层包括多个触控电极，所述触控层至少部分位于所述显示区；所述导电层与所述触控电极同层设置。
  9. 根据权利要求1所述的显示基板，其特征在于，所述显示基板包括位于所述衬底上的像素电路层，所述像素电路层至少部分位于所述显示区；所述像素电路层包括多个导电膜层，所述导电层与所述像素电路层的至少一个所述导电膜层同层设置。
  10. 根据权利要求9所述的显示基板，其特征在于，所述像素电路层包括像素电路，所述像素电路包括薄膜晶体管和电容，所述薄膜晶体管包括源电极和栅电极，所述电容包括第一电容极板和第二电容极板，所述第一电容极板与所述栅电极同层设置；
    所述多个导电膜层包括所述栅电极、所述源电极及所述第二电容极板；所述导电层与所述源电极同层设置。
  11. 根据权利要求10所述的显示基板，其特征在于，所述检测走线的至少部分与所述栅电极和所述第二电容极板的至少之一同层设置。
  12. 根据权利要求1所述的显示基板，其特征在于，所述边框区还包括位于所述裂纹检测区与所述显示区之间的电源信号线区，所述显示基板还包括位于所述电源信号线区的低电平电源信号线；所述导电层与所述低电平电源信号线同层设置。
  13. 根据权利要求12所述的显示基板，其特征在于，所述导电层与所述低电平电源信号线相连；或者，所述导电层与所述低电平电源信号线连接不同的信号。
  14. 根据权利要求1所述的显示基板，其特征在于，所述边框区还包括位于所述裂纹检测区背离所述显示区一侧的裂纹阻止区、及位于所述裂纹阻止区背离所述裂纹检测区一侧的切割保留区，所述导电层覆盖至少部分所述切割保留区。
  15. 根据权利要求1所述的显示基板，其特征在于，所述导电层连接接地信号，或者，所述导电层连接低电平电源信号。
  16. 根据权利要求1至15任一项所述的显示基板，其特征在于，所述边框区还包括位于所述显示区与所述裂纹检测区之间的栅极驱动区，所述栅极驱动区设有栅极驱动电路；所述导电层位于所述栅极驱动区之外的区域。
  17. 一种显示装置，其特征在于，所述显示装置包括权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的裂纹检测方法，其特征在于，所述裂纹检测方法用于显示基板，所述显示基板包括显示区和至少位于所述显示区一侧的边框区，所述边框区包括裂纹检测区；所述显示基板包括衬底、位于所述衬底上的检测走线及位于所述检测走线背离所述衬底一侧的导电层；所述导电层位于所述边框区；所述检测走线位于所述裂纹检测区；所述检测走线在所述衬底上的正投影的至少部分落在所述导电层在所述衬底上的正投影内；所述导电层连接恒定的电信号；
    所述裂纹检测方法包括：
    检测第一电容值，所述第一电容值为所述检测走线与所述显示基板的其他导电结构之间的电容值之和，所述其他导电结构包括所述导电层；
    若所述第一电容值不在电容阈值范围内，确定所述检测走线发生断裂。
  19. 根据权利要求18所述的裂纹检测方法，其特征在于，所述确定所述检测走线发生断裂之后，所述裂纹检测方法还包括：
    根据所述第一电容值确定所述检测走线发生断裂的位置。
  20. 根据权利要求19所述的裂纹检测方法，其特征在于，所述检测走线各处的厚度及宽度均相同；所述根据所述第一电容值确定所述检测走线发生断裂的位置，包括：
    计算所述检测走线发生断裂的位置与所述检测走线的起始端之间的 走线长度，
    根据所述走线长度确定所述检测走线发生断裂的位置；
    所述走线长度采用如下计算公式计算：
    Lx＝(Cx-C0)*L/(C1-C0)
    式中，Cx为所述第一电容值；C0为第二电容值，所述第二电容值为所述检测走线与不包括所述导电层的其他导电结构之间的电容值之和；C1为第三电容值，所述第二电容值为所述检测走线未发生断裂时，所述检测走线与所述显示基板的其他导电结构之间的第三电容值，所述其他导电结构包括所述导电层；L为所述检测走线的总长，Lx为所述检测走线发生断裂的位置与所述检测走线的起始端之间的走线长度。
PCT/CN2022/070787 2022-01-07 2022-01-07 显示基板、显示装置及显示基板的裂纹检测方法 WO2023130369A1 (zh)

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CN109752421A (zh) * 2019-01-31 2019-05-14 厦门天马微电子有限公司 显示面板和显示装置
CN111366619A (zh) * 2020-03-18 2020-07-03 京东方科技集团股份有限公司 显示面板及其裂纹检测方法、显示装置
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CN112669737A (zh) * 2020-12-22 2021-04-16 上海天马有机发光显示技术有限公司 显示面板及其裂纹检测方法、显示装置
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JP2007123793A (ja) * 2005-10-24 2007-05-17 Chunghwa Picture Tubes Ltd 薄膜トランジスタアレイ基板と液晶ディスプレイ
US20080198287A1 (en) * 2007-02-20 2008-08-21 Hyun-Young Kim Display panel, method for manufacturing the same, motherboard for manufacturing the same and method for manufacturing a display substrate for the same
CN109752421A (zh) * 2019-01-31 2019-05-14 厦门天马微电子有限公司 显示面板和显示装置
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