WO2022160807A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2022160807A1
WO2022160807A1 PCT/CN2021/126115 CN2021126115W WO2022160807A1 WO 2022160807 A1 WO2022160807 A1 WO 2022160807A1 CN 2021126115 W CN2021126115 W CN 2021126115W WO 2022160807 A1 WO2022160807 A1 WO 2022160807A1
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Prior art keywords
layer
metal layer
base substrate
gate metal
source
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PCT/CN2021/126115
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English (en)
French (fr)
Inventor
尚庭华
张毅
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/796,706 priority Critical patent/US20240224620A1/en
Publication of WO2022160807A1 publication Critical patent/WO2022160807A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • Active-matrix organic light-emitting diode active-matrix organic light-emitting diode, AMOLED
  • AMOLED active-matrix organic light-emitting diode
  • an AMOLED display panel includes: a base substrate, and a gate metal layer, an inorganic insulating layer and a source-drain metal layer which are located on one side of the base substrate and are stacked in sequence.
  • the orthographic projection of the gate metal layer on the base substrate overlaps with the orthographic projection of the source and drain metal layers on the base substrate.
  • Embodiments of the present disclosure provide a display panel, a method for manufacturing the same, and a display device.
  • a display panel comprising:
  • a gate metal layer and a source-drain metal layer that are located on one side of the base substrate and stacked in sequence;
  • an inorganic insulating layer and an organic flat layer that are located between the gate metal layer and the source-drain metal layer and stacked in sequence;
  • the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate have overlapping portions, and the organic flat layer is on the substrate The orthographic projection on the substrate overlaps the overlapping portion.
  • the gate metal layer and the source/drain metal layer are sequentially stacked along a direction away from the base substrate.
  • the inorganic insulating layer and the organic flat layer are sequentially stacked along a direction away from the base substrate.
  • the base substrate has a display area and a non-display area surrounding the display area;
  • the organic flat layer is located in the display area
  • Each of the source-drain metal layer, the gate metal layer and the inorganic insulating layer is located in the display area and the non-display area, respectively.
  • the orthographic projection of the organic flat layer on the base substrate covers the overlapping portion.
  • the dielectric constant of the material of the organic flat layer is greater than or equal to 3 and less than or equal to 4.
  • the gate metal layer includes: a first gate metal layer and a second gate metal layer stacked in sequence along a direction away from the base substrate;
  • the inorganic insulating layer includes:
  • the display panel further includes:
  • an inorganic layer base an active layer and a second gate insulating layer that are located between the gate metal layer and the base substrate and are stacked in sequence along a direction away from the base substrate;
  • the source-drain metal layer is connected to the active layer through a via hole passing through the organic flat layer, the inorganic insulating layer and the second gate insulating layer.
  • the via hole includes: a first via hole penetrating the organic flat layer, and a second via hole penetrating the inorganic insulating layer and the second gate insulating layer;
  • the orthographic projection of the opening of the first via close to the base substrate on the base substrate is different from the orthographic projection of the opening of the second via far away from the base substrate on the base substrate. Orthographic coincidence.
  • a method for manufacturing a display panel comprising:
  • the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate have overlapping portions, and the organic flat layer is on the substrate The orthographic projection on the substrate overlaps the overlapping portion.
  • forming a gate metal layer and a source-drain metal layer stacked in sequence on one side of the base substrate includes:
  • a source-drain metal layer is formed on a side of the gate metal layer away from the base substrate.
  • forming a sequentially stacked inorganic insulating layer and an organic flat layer between the gate metal layer and the source-drain metal layer includes:
  • the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the second via hole on the base substrate.
  • forming a sequentially stacked inorganic insulating layer and an organic flat layer between the gate metal layer and the source-drain metal layer includes:
  • the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the second via hole on the base substrate.
  • a display device comprising: a drive circuit, and the display panel as described in the above aspect;
  • the driving circuit is connected to the display panel and used for driving the display panel to display.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure
  • FIG. 7 is a flowchart of a method for manufacturing a gate metal layer and a source-drain metal layer according to an embodiment of the present disclosure
  • FIG. 8 is a partial schematic diagram of a manufacturing process flow diagram provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a method for manufacturing an inorganic insulating layer and an organic flat layer provided by an embodiment of the present disclosure.
  • FIG. 10 is another partial schematic diagram of a manufacturing process flow diagram provided by an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of another method for manufacturing an inorganic insulating layer and an organic flat layer provided by an embodiment of the present disclosure
  • FIG. 12 is another partial schematic diagram of a manufacturing process flow diagram provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of another part of a manufacturing process flow diagram provided by an embodiment of the present disclosure.
  • 15 is a schematic diagram of another part of a manufacturing process flow diagram provided by an embodiment of the present disclosure.
  • 16 is a partial film layer layout of another display panel provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the signal here refers to a data signal for charging the pixel.
  • driver IC driver integrated circuit
  • the load on the signal line transmitting the data signal can affect the signal switching speed.
  • the loads on the signal lines include multiple types, one of which is: capacitive loads caused by overlapping capacitances formed by overlapping gate metal layers and source-drain metal layers.
  • the capacitance value of the overlapping capacitor is large, and the capacitive load brought by the overlapping capacitor is large, which in turn leads to a slow signal switching speed and a large power consumption of the driving circuit, which is disadvantageous to the realization of a high refresh frequency. influences.
  • Embodiments of the present disclosure provide a display panel. Compared with the related art, the capacitance value of the overlapping capacitor formed by the gate metal layer and the source-drain metal layer included in the display panel is smaller, and correspondingly, the capacitance load generated by the overlapping capacitor is smaller. In this way, the signal switching speed is improved, the power consumption of the driving circuit is reduced, and the design of high refresh frequency is favorable.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in Figure 1, the display panel may include:
  • gate gate metal layer
  • source & drain source & drain
  • the orthographic projection of the gate metal layer 01 on the base substrate 00, the orthographic projection of the source/drain metal layer 02 on the base substrate 00, and the orthographic projection of the organic flat layer 04 on the base substrate 00 at least partially overlap. In this way, the newly added organic flat layer 04 can increase the distance between the gate metal layer 01 and the source-drain metal layer 02.
  • the capacitance value of the overlap capacitor formed by the stacked two film layers is negatively correlated with the distance between the two film layers. It can be known that: in the embodiment of the present disclosure, by increasing the gate metal layer 01 and the source and drain The spacing between the electrode metal layers 02 can effectively reduce the capacitance of the overlap capacitor formed by the gate metal layer 01 and the source-drain metal layer 02 .
  • the purpose of reducing the capacitive load can be achieved on the premise of reducing the capacitance value. Furthermore, the power consumption of the driving circuit can be reduced on the premise of facilitating the design of a high refresh rate.
  • the embodiments of the present disclosure provide a display panel.
  • the display panel includes a gate metal layer and a source-drain metal layer that are located on one side of a base substrate and are sequentially stacked, and an inorganic insulating layer and an organic flat layer that are located between the gate metal layer and the source-drain metal layer and are sequentially stacked .
  • the display panel further includes an organic flat layer
  • the orthographic projection of the organic flat layer on the base substrate overlaps with the overlapping portion of the orthographic projections of the gate metal layer and the source-drain metal layer on the base substrate
  • the increase The distance between the gate metal layer and the source-drain metal layer is reduced, and correspondingly, the capacitance value of the overlap capacitor formed by the gate metal layer and the source-drain metal layer is reduced. In this way, the capacitive load caused by the overlapping capacitors is small, and the power consumption of the driving circuit for driving the display panel to display is low.
  • the gate metal layer 01 and the source and drain metal layers 02 may be stacked in sequence along the direction away from the base substrate 00 . That is, the display panel described in the embodiments of the present disclosure may have a bottom gate structure. Of course, in some embodiments, the display panel may also have a top-gate structure, that is, the source-drain metal layer 02 and the gate metal layer 01 are sequentially stacked along a direction away from the base substrate 00 .
  • the inorganic insulating layer 03 and the organic flat layer 04 may be stacked in sequence along the direction away from the base substrate 00 . That is, in the embodiment of the present disclosure, the organic flat layer 04 may be far away from the base substrate 00 relative to the inorganic insulating layer 03 .
  • the gate metal layer 01 , the inorganic insulating layer 03 , the organic flat layer 04 and the source-drain metal layer 02 may be sequentially stacked along the direction away from the base substrate 00 .
  • other film structures eg, an encapsulation layer
  • other film structures are generally disposed on the side of the source-drain metal layer 02 away from the base substrate 00 . Therefore, by disposing the organic flat layer 04 close to One side of the source-drain metal layer 02 can ensure good flatness of other film layer structures, thereby ensuring good yield of the display panel.
  • the organic planarization layer 04 may be close to the base substrate 00 relative to the inorganic insulating layer 03 . That is, the organic flat layer 04 and the inorganic insulating layer 03 may be sequentially stacked in a direction away from the base substrate 00 .
  • the orthographic projection of the organic flat layer 04 on the base substrate 00 may cover the overlapping portion of the gate metal layer 01 and the source-drain metal layer 02 .
  • the distance between any overlapping parts of the gate metal layer 01 and the source-drain metal layer 02 can be made smaller, which further effectively reduces the capacitance of the overlapped capacitance formed by the gate metal layer 01 and the source-drain metal layer 02 .
  • the capacitive load caused by the overlapping capacitor can be further effectively reduced, and the power consumption of the driving circuit can be reduced.
  • the dielectric constant of the material of the organic flat layer 04 described in the embodiments of the present disclosure may be greater than or equal to 3 and less than or equal to 4.
  • the material of the organic flat layer 04 may include: polyimide.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • the base substrate 00 may have a display area A1 and a non-display area A2 surrounding the display area A1.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. 2 and 3, it can be seen that the organic flat layer 04 described in the embodiment of the present disclosure may only be located in the display area A1, and each film in the source-drain metal layer 02, the gate metal layer 01 and the inorganic insulating layer 03 The layers may all be located in the display area A1 and the non-display area A2, respectively.
  • FIG. 3 only shows part of the display area A1 and part of the display area A2.
  • the display area A1 may include a plurality of pixels arranged in an array, and each pixel may include a pixel circuit and a light-emitting element.
  • the pixel circuit can be respectively connected with the gate line, the data line and the light emitting element, and the pixel circuit is used to transmit the data signal from the data line to the light emitting element under the control of the gate driving signal provided by the gate line to drive the light emitting element to emit light.
  • the pixel circuit generally includes a driving transistor.
  • the gate driving circuit for transmitting the gate driving signal to the gate line may be disposed on the base substrate 00 and may be located in the non-display area A2. Therefore, the non-display area A2 described in the embodiments of the present disclosure may include: a GOA area for setting the GOA circuit, and other areas. Also, along the direction away from the display area A1, the GOA area and other areas may be sequentially arranged. Also, the gate driving circuit generally includes a plurality of thin film transistors.
  • the gate metal layer 01 and the source-drain metal layer 02 located in the display area A1 may constitute the transistor in the pixel circuit described above.
  • the gate metal layer 01 and the source-drain metal layer 02 located in the non-display area A2 can constitute the thin film transistor in the GOA circuit described above. Because the data signal is generally only provided to the light-emitting element by the pixel circuit located in the display area A1, and not provided to the circuit structure located in the non-display area A2.
  • adding an organic flat layer 04 between the gate metal layer 01 and the source-drain metal layer 02 in the non-display area A2 has a significant effect on reducing the power consumption of the driving circuit.
  • the benefit is not great, so by only adding the organic flat layer 04 in the display area A1, the power consumption of the driving circuit can be effectively reduced, the structure of the display panel can be simplified, and the manufacturing cost can be reduced.
  • the organic flat layer 04 may also be located in the non-display area A2.
  • FIG. 4 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure.
  • the gate metal layer 01 may include: a first gate metal layer 011 and a second gate metal layer stacked in sequence along a direction away from the base substrate 00 012.
  • the inorganic insulating layer 03 may include: a first gate insulating layer (GI) 031 located between the first gate metal layer 011 and the second gate metal layer 012 .
  • an interlayer dielectric (ILD) 032 located between the second gate metal layer 012 and the source-drain metal layer 02.
  • the dielectric constant of the first gate insulating layer 031 may be about seven.
  • the dielectric constant of the material of the interlayer interposition layer 032 may be equal to or greater than 3 and less than or equal to 4.
  • the materials of the first gate insulating layer 031 and the interlayer interlayer 032 may include at least one of silicon nitride (SiN), silicon oxide (SiO) and silicon oxynitride (SiNO).
  • the display panel described in the embodiment of the present disclosure may further include: located between the gate metal layer 01 and the base substrate 00 and in a direction away from the base substrate 00 An inorganic layer base 05, an active (poly) layer 06 and a second gate insulating layer 07 are sequentially stacked. And, a target flat layer 08 , a pixel electrode 09 and a pixel definition layer (PDL) 10 are located on the side of the source-drain metal layer 02 away from the base substrate 00 and stacked in sequence.
  • PDL pixel definition layer
  • the pixel electrode 09 may be an anode (anode) or a cathode (cathode), and the embodiment of the present disclosure is described by taking the pixel electrode 09 as an anode as an example.
  • the inorganic layer substrate 05 , the active layer 06 , the second gate insulating layer 07 , the target planarization layer 08 and the respective film layers included in the pixel definition layer 10 may be located in the display area A1 and the non-display area A2 , respectively.
  • the pixel electrode 09 may be located only in the display area A1.
  • the source-drain metal layer 02 may be connected to the active layer 06 through a via hole K1 penetrating the organic flat layer 04 , the inorganic insulating layer 03 and the second gate insulating layer 07 .
  • the via hole K1 can be divided into a first via hole K11 penetrating the organic planarization layer 04 and a second via hole K12 penetrating the inorganic insulating layer 03 and the second gate insulating layer 07 .
  • the first via K11 is close to the orthographic projection of the opening of the base substrate 00 on the base substrate 00
  • the second via K12 is far from the opening of the base substrate 00 on the base substrate 00
  • the orthographic projections on the substrate 00 may be coincident. That is, at the intersection of the first via hole K11 and the second via hole K12, the size of the openings of the two via holes may be the same.
  • this setting can reduce the amount of other film layers (eg, effect of the flatness of the pixel electrode). Further, adverse effects on pixel light emission are avoided.
  • the orthographic projection of the opening of the first via hole K11 close to the base substrate 00 on the base substrate 00 may cover the second via hole K12 away from the base substrate 00
  • the orthographic projection of the opening on the base substrate 00 at the intersection of the first via hole K11 and the second via hole K12 , the size of the opening of the first via hole K11 is relatively large, and the size of the opening of the second via hole K12 is relatively small.
  • the second via hole K12 penetrating the inorganic insulating layer 03 and the second gate insulating layer 07 can be reliably etched, thereby ensuring a reliable connection between the source-drain metal layer 02 and the active layer 06 .
  • the source-drain metal layer 02 can pass through the inorganic insulating layer 03 and the second gate insulating layer.
  • the via hole of 07 ie, the second via hole K12 ) is reliably connected to the active layer 06 .
  • FIGS. 4 and 5 respectively use different ways to identify each film layer.
  • the embodiments of the present disclosure provide a display panel.
  • the display panel includes a gate metal layer and a source-drain metal layer that are located on one side of a base substrate and are sequentially stacked, and an inorganic insulating layer and an organic flat layer that are located between the gate metal layer and the source-drain metal layer and are sequentially stacked .
  • the display panel further includes an organic flat layer
  • the orthographic projection of the organic flat layer on the base substrate overlaps with the overlapping portion of the orthographic projections of the gate metal layer and the source-drain metal layer on the base substrate
  • the increase The distance between the gate metal layer and the source-drain metal layer is reduced, and correspondingly, the capacitance value of the overlap capacitor formed by the gate metal layer and the source-drain metal layer is reduced. In this way, the capacitive load caused by the overlapping capacitors is small, and the power consumption of the driving circuit for driving the display panel to display is low.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure, and the method can be used to manufacture the display panel as described in any one of FIGS. 1 to 5 . As shown in Figure 6, the method may include:
  • Step 601 providing a base substrate.
  • the base substrate may be a flexible substrate made of a flexible material, or may also be a glass substrate.
  • Step 602 forming a gate metal layer and a source-drain metal layer stacked in sequence on one side of the base substrate.
  • Step 603 forming an inorganic insulating layer and an organic flat layer sequentially stacked between the gate metal layer and the source and drain metal layers.
  • the embodiments of the present disclosure provide a method for manufacturing a display panel.
  • an organic flat layer is also included between the gate metal layer and the source and drain metal layers, and the orthographic projection of the organic flat layer on the base substrate is different from the gate metal layer and the source and drain layers.
  • the overlapping portion of the orthographic projection of the electrode metal layer on the base substrate overlaps, so the distance between the gate metal layer and the source and drain metal layers is increased, and correspondingly, the distance between the gate metal layer and the source and drain metal layers is reduced. Capacitance of the overlap capacitor. In this way, the load brought by the overlapping capacitor is small, and the power consumption of the driving circuit for driving the display panel to display is low.
  • the foregoing step 602 may include:
  • Step 6021 forming a gate metal layer on one side of the base substrate.
  • Step 6022 forming a source-drain metal layer on the side of the gate metal layer away from the base substrate.
  • the display panel formed by the manufacturing sequence corresponding to the method shown in FIG. 7 is the display panel with the bottom gate structure shown in FIG. 1 to FIG. 5 .
  • the sequence of step 6021 and step 6022 may be reversed.
  • the inorganic layer base 05 is first formed in the display area A1 and the non-display area A2 included in the base substrate 00 .
  • the active layer 06 is formed on the side of the inorganic layer base 05 away from the base substrate 00 . Wherein, an active layer 06 may be formed in the display area A1 and the non-display area A2 respectively.
  • a second gate insulating layer 07 is formed on the side of the active layer 06 away from the inorganic layer substrate 05, where the second gate insulating layer 07 has not been etched, that is, does not have via holes.
  • the first gate metal layer 011 ie, a part of the gate metal layer 01
  • the first gate metal layer 011 may be formed in the display area A1 and the non-display area A2 respectively.
  • the first gate insulating layer 031 ie, a part of the inorganic insulating layer 03
  • the first gate insulating layer 031 is formed on the side of the first gate metal layer 011 away from the second gate insulating layer 07 .
  • the first gate insulating layer 031 has not been etched, that is, it does not yet have the second via hole K12.
  • a second gate metal layer 012 is formed on the side of the first gate insulating layer 031 away from the first gate metal layer 011 (that is, another part of the gate metal layer 01). 8 only shows the second gate metal layer 012 formed in the display area A1.
  • interlayer interlayer 032 of the inorganic insulating layer 03 can be formed through the following process, and the second via K12 penetrating the inorganic insulating layer 03 and the second gate insulating layer can be obtained by etching.
  • the foregoing step 603 may include:
  • Step 6031A forming an inorganic material layer on the side of the gate metal layer away from the base substrate.
  • the inorganic material layer here may include: an inorganic material layer for forming the interlayer intervening layer 032 , and an inorganic material layer for forming the first gate insulating layer 031 layer of inorganic materials.
  • the inorganic material layer may be formed by deposition.
  • Step 6032A forming an organic flat layer with a first via hole on the side of the inorganic material layer away from the gate metal layer.
  • an organic flat layer having a first via hole K11 may be formed only in the display area A1.
  • the organic planarization layer 04 may be formed by a mask-related patterning process.
  • a photolithography can be formed on the side of the inorganic material layer away from the gate metal layer 01 in the non-display area A2.
  • the photoresist pattern M1 may have via holes.
  • the photoresist pattern M1 with via holes can be formed by a mask-related patterning process.
  • Step 6033A etching the inorganic material layer by using the organic flat layer as a protective layer to form an inorganic insulating layer with a second via hole.
  • the organic flat layer 04 may be used as a protective layer, and the inorganic material layer may be etched by means of etch, thereby obtaining the inorganic insulating layer having the second via hole K12 . And the etching of the second gate insulating layer 07 can be continued until the active layer 06 is exposed.
  • etching can also be used, but the inorganic material layer and the second gate insulating layer 07 are etched using the formed photoresist pattern M1 as a protective layer, so that the active layer 06 is exposed. .
  • the above-mentioned step 6022 is: forming a source-drain metal layer on the side of the organic flat layer away from the base substrate.
  • the structure shown in FIG. 4 can be obtained by etching. Display panel. That is, in the obtained display panel, the orthographic projection of the first via hole K11 on the base substrate 00 may overlap with the orthographic projection of the second via hole K12 on the base substrate 00 . In other words, the size of the opening at the intersection of the first via hole K11 and the second via hole K12 is the same. In this way, the influence of the first via hole K11 penetrating through the organic flat layer 04 on the flatness of other film layers (eg, pixel electrodes) disposed thereon can be reduced. Further, adverse effects on pixel light emission are avoided.
  • other film layers eg, pixel electrodes
  • the foregoing step 603 may include:
  • Step 6031B forming an inorganic material layer on the side of the gate metal layer away from the base substrate.
  • step 6031A For this step, reference may be made to the above-mentioned step 6031A, which will not be repeated here.
  • Step 6032B forming a photoresist pattern on the side of the inorganic material layer away from the gate metal layer.
  • a photoresist pattern can be formed directly on the side of the inorganic material layer away from the gate metal layer, and the photoresist pattern is located in the display area A1 and the non-display area A2 , and has vias.
  • the photoresist pattern M1 with via holes may be formed by a mask-related patterning process.
  • Step 6033B etching the inorganic material layer with the photoresist pattern as a protective layer to form an inorganic insulating layer having a second via hole.
  • the photoresist pattern can be used as a protective layer, and the inorganic material layer can be etched by means of etching to form an inorganic insulating layer having second via holes K12 .
  • the etching of the second gate insulating layer 07 may be continued until the active layer 06 is exposed.
  • the display area A1 and the non-display area A2 are the same, and will not be introduced and described one by one here.
  • Step 6034B peeling off the photoresist pattern.
  • the photoresist pattern may be stripped off by a related process of stripping (eg, laser stripping) in combination with the process flow chart shown in FIG. 12 .
  • stripping eg, laser stripping
  • Step 6035B forming an organic flat layer having a first via hole on the side of the inorganic insulating layer away from the gate metal layer.
  • the organic flat layer 04 having the first via hole is formed on the side of the inorganic insulating layer 03 having the second via hole K12 away from the base substrate 00 .
  • the organic flat layer 04 may be formed by a mask-related patterning process.
  • the inorganic insulating layer 03 and the second gate insulating layer 07 are etched first, and then the organic planarization layer 04 is formed. Therefore, it is necessary to consider the first via K11 penetrating the organic planarizing layer 04 and the holes penetrating the inorganic insulating layer 03
  • the alignment accuracy of the second via hole K12 ensures that the source-drain metal layer 02 formed on the organic flat layer 04 can reliably establish connection with the active layer 06 through the first via hole K11 and the second via hole K12. In this way, referring to the structures shown in FIGS. 5 and 12 , at the junction of the first via hole K11 and the second via hole K12 , the opening size of the first via hole K11 is larger than that of the second via hole K12 .
  • the manufacturing method may further include:
  • a source-drain metal layer 02 is formed on the side of the organic flat layer 04 away from the base substrate 00 , and the source-drain metal layer 02 is connected to the active layer 06 through via holes.
  • the source and drain metal layers 02 can be formed in the display area A1 and the non-display area A2 respectively, and the source and drain metal layers 02 located in the display area A1 can extend to the active area through the first via K11 and the second via K12 layer 06 and connected to the active layer 06.
  • the source-drain metal layer 02 located in the non-display area A2 may extend to the active layer 06 through the second via hole K12 and be connected to the active layer 06 .
  • a target flat layer 08 is formed on the side of the source-drain metal layer 02 away from the base substrate 00 .
  • the target flat layer 08 may be formed in both the display area A1 and the non-display area A2.
  • the pixel electrode 09 is formed on the side of the target flat layer 08 away from the base substrate 00 .
  • the pixel electrode 09 is formed only in the display area A1.
  • the pixel definition layer 10 is formed on the side of the pixel electrode 09 away from the base substrate 00 . Wherein, the pixel definition layer 10 may be formed in both the display area A1 and the non-display area A2.
  • FIG. 13 is a manufacturing process continued after the manufacturing process shown in FIG. 9 and FIG. 10 .
  • FIG. 15 is a manufacturing process continued after the manufacturing process shown in FIGS. 11 and 12 . Comparing FIG. 13 and FIG. 15 , it can be seen that due to the different manufacturing processes in step 603 , the sizes of the finally formed first via hole K11 and the second via hole K12 are different.
  • FIG. 14 and FIG. 16 respectively show the structural layout of the display panel corresponding to FIG. 4 and FIG. 5 . Comparing FIG. 14 and FIG. 16 , it can be seen that the sizes of the first via hole K11 and the second via hole K12 formed by different manufacturing methods are different.
  • the embodiments of the present disclosure provide a method for manufacturing a display panel.
  • an organic flat layer is also included between the gate metal layer and the source and drain metal layers, and the orthographic projection of the organic flat layer on the base substrate is different from the gate metal layer and the source and drain layers.
  • the overlapping portion of the orthographic projection of the electrode metal layer on the base substrate overlaps, so the distance between the gate metal layer and the source and drain metal layers is increased, and correspondingly, the distance between the gate metal layer and the source and drain metal layers is reduced. Capacitance of the overlap capacitor. In this way, the load brought by the overlapping capacitor is small, and the power consumption of the driving circuit for driving the display panel to display is low.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include: a driving circuit 100 and a display panel 200 as shown in any one of FIGS. 1 to 5 .
  • the driving circuit 100 can be connected to the display panel 200 and can be used to drive the display panel 200 to display.
  • the display device including the display module may be any product or component with a display function, such as an AMOLED display device, a liquid crystal display device, a mobile phone, a tablet computer, a television, a monitor, or a notebook computer.
  • a display function such as an AMOLED display device, a liquid crystal display device, a mobile phone, a tablet computer, a television, a monitor, or a notebook computer.

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Abstract

本公开提供了一种显示面板及其制造方法、显示装置，属于显示技术领域。其中，该显示面板包括位于衬底基板一侧且依次层叠的栅极金属层和源漏极金属层，以及位于栅极金属层和源漏极金属层之间且依次层叠的无机绝缘层和有机平坦层。由于该显示面板还包括有机平坦层，且该有机平坦层在衬底基板上的正投影，与栅极金属层和源漏极金属层在衬底基板上的正投影的重叠部分重叠，因此增加了栅极金属层和源漏极金属层的间距，相应的，减小了栅极金属层和源漏极金属层形成的交叠电容的容值。如此，该交叠电容带来的负载较小，驱动该显示面板显示的驱动电路的功耗较低。

Description

显示面板及其制造方法、显示装置
本公开要求于2021年1月28日提交的申请号为202110116496.9、发明名称为“显示面板及其制造方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及其制造方法、显示装置。
背景技术
有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AM OLED)显示面板因其自发光和响应速度快等优点被广泛应用于显示领域中。
相关技术中，AMOLED显示面板包括：衬底基板，以及位于衬底基板一侧且依次层叠的栅极金属层、无机绝缘层和源漏极金属层。其中，栅极金属层在衬底基板上的正投影与源漏极金属层在衬底基板上的正投影重叠。
但是，相关技术中显示面板所包括的栅极金属层和源漏极金属层之间会形成较大容值的交叠电容，该电容带来的较大负载会导致驱动显示面板显示的驱动电路的功耗较大。
发明内容
本公开实施例提供了一种显示面板及其制造方法、显示装置。
所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板；
位于所述衬底基板一侧且依次层叠的栅极金属层和源漏极金属层；
以及，位于所述栅极金属层和所述源漏极金属层之间且依次层叠的无机绝缘层和有机平坦层；
其中，所述栅极金属层在所述衬底基板上的正投影与所述源漏极金属层在 所述衬底基板上的正投影存在重叠部分，所述有机平坦层在所述衬底基板上的正投影与所述重叠部分重叠。
可选的，所述栅极金属层和所述源漏极金属层沿远离所述衬底基板的方向依次层叠。
可选的，所述无机绝缘层和所述有机平坦层沿远离所述衬底基板的方向依次层叠。
可选的，所述衬底基板具有显示区，以及围绕所述显示区的非显示区；
其中，所述有机平坦层位于所述显示区；
所述源漏极金属层、所述栅极金属层和所述无机绝缘层中的每个膜层均分别位于所述显示区和所述非显示区。
可选的，所述有机平坦层在所述衬底基板上的正投影覆盖所述重叠部分。
可选的，所述有机平坦层的材料的介电常数大于等于3，且小于等于4。
可选的，所述栅极金属层包括：沿远离所述衬底基板的方向依次层叠的第一栅极金属层和第二栅极金属层；所述无机绝缘层包括：
位于所述第一栅极金属层和所述第二栅极金属层之间的第一栅绝缘层；
以及，位于所述第二栅极金属层和所述源漏极金属层之间的层间介定层。
可选的，所述显示面板还包括：
位于所述栅极金属层和所述衬底基板之间，且沿远离所述衬底基板的方向依次层叠的无机层基底、有源层和第二栅绝缘层；
以及，位于所述源漏极金属层远离所述衬底基板的一侧，且依次层叠的目标平坦层、像素电极和像素定义层；
其中，所述源漏极金属层通过贯穿所述有机平坦层、所述无机绝缘层和所述第二栅绝缘层的过孔与所述有源层连接。
可选的，所述过孔包括：贯穿所述有机平坦层的第一过孔，以及贯穿所述无机绝缘层和所述第二栅绝缘层的第二过孔；
其中，所述第一过孔靠近所述衬底基板的开口在所述衬底基板上的正投影，与所述第二过孔远离所述衬底基板的开口在所述衬底基板上的正投影重合。
另一方面，提供了一种显示面板的制造方法，所述方法包括：
提供衬底基板；
在所述衬底基板的一侧形成依次层叠的栅极金属层和源漏极金属层；
以及，在所述栅极金属层和所述源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层；
其中，所述栅极金属层在所述衬底基板上的正投影与所述源漏极金属层在所述衬底基板上的正投影存在重叠部分，所述有机平坦层在所述衬底基板上的正投影与所述重叠部分重叠。
可选的，所述在所述衬底基板的一侧形成依次层叠的栅极金属层和源漏极金属层，包括：
在所述衬底基板的一侧形成栅极金属层；
在所述栅极金属层远离所述衬底基板的一侧形成源漏极金属层。
可选的，所述在所述栅极金属层和所述源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层，包括：
在所述栅极金属层远离所述衬底基板的一侧形成无机材料层；
在所述无机材料层远离所述栅极金属层的一侧形成具有第一过孔的有机平坦层；
以所述有机平坦层作为保护层刻蚀所述无机材料层，形成具有第二过孔的无机绝缘层；
其中，所述第一过孔在所述衬底基板上的正投影，与所述第二过孔在所述衬底基板上的正投影重叠。
可选的，所述在所述栅极金属层和所述源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层，包括：
在所述栅极金属层远离所述衬底基板的一侧形成无机材料层；
在所述无机材料层远离所述栅极金属层的一侧形成光刻胶图案；
以所述光刻胶图案作为保护层刻蚀所述无机材料层，形成具有第二过孔的无机绝缘层；
剥离所述光刻胶图案；
在所述无机绝缘层远离所述栅极金属层的一侧形成具有第一过孔的有机平坦层；
其中，所述第一过孔在所述衬底基板上的正投影，与所述第二过孔在所述衬底基板上的正投影重叠。
又一方面，提供了一种显示装置，所示显示装置包括：驱动电路，以及如 上述方面所述的显示面板；
所述驱动电路与所述显示面板连接，且用于驱动所述显示面板显示。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示面板的结构示意图；
图2是本公开实施例提供的另一种显示面板的结构示意图；
图3是本公开实施例提供的又一种显示面板的结构示意图；
图4是本公开实施例提供的再一种显示面板的结构示意图；
图5是本公开实施例提供的再一种显示面板的结构示意图；
图6是本公开实施例提供的一种显示面板的制造方法流程图；
图7是本公开实施例提供的一种栅极金属层和源漏极金属层的制造方法流程图；
图8是本公开实施例提供的一种制造工艺流程图的一部分示意图；
图9是本公开实施例提供的一种无机绝缘层和有机平坦层的制造方法流程图；
图10是本公开实施例提供的一种制造工艺流程图的另一部分示意图；
图11是本公开实施例提供的另一种无机绝缘层和有机平坦层的制造方法流程图；
图12是本公开实施例提供的一种制造工艺流程图的另一部分示意图；
图13是本公开实施例提供的一种制造工艺流程图的又一部分示意图；
图14是本公开实施例提供的一种显示面板的部分膜层版图；
图15是本公开实施例提供的一种制造工艺流程图的再一部分示意图；
图16是本公开实施例提供的另一种显示面板的部分膜层版图；
图17是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
近年来，具有高刷新频率的显示产品层出不穷。若要达到较高的刷新频率，则对于逐行驱动的显示面板而言，留给每行像素的刷新时间较短。如此，即需要较快的信号切换速度。此处的信号是指：用于给像素充电的数据(data)信号。相应的，对提供数据信号的驱动电路(driver integrated circuit，driver IC)的驱动能力要求也越来越高，驱动电路的功耗随之上升。
此外，经研究发现，传输数据信号的信号线上的负载会影响信号切换速度。负载越大，导致信号切换速度越慢，进一步导致驱动电路的功耗变大，影响驱动电路的使用寿命，最终影响显示面板的显示效果。可选的，信号线上的负载包括多种，其中一种是：层叠设置的栅极金属层和源漏极金属层交叠所形成的交叠电容带来的电容负载。相关技术中，该交叠电容的容值较大，该交叠电容所带来的电容负载较大，进而导致信号切换速度较慢，驱动电路功耗较大，对实现高刷新频率带来不利影响。
本公开实施例提供了一种显示面板。相对于相关技术，该显示面板所包括的栅极金属层和源漏极金属层形成的交叠电容的容值较小，相应的，该交叠电容产生的电容负载较小。如此，提升了信号切换速度，降低了驱动电路的功耗，有利于高刷新频率的设计。
图1是本公开实施例提供的一种显示面板的结构示意图。如图1所示，该显示面板可以包括：
衬底基板00，位于衬底基板00一侧且依次层叠的栅极金属层(gate)01和源漏极金属层(source&drain，SD)02，以及位于栅极金属层01和源漏极金属层02之间且依次层叠的无机绝缘层03和有机平坦层(planarization，PLN)04。
其中，栅极金属层01在衬底基板00上的正投影与源漏极金属层02在衬底基板00上的正投影存在重叠部分，且有机平坦层04在衬底基板00上的正投影与该重叠部分重叠。即参考图1，栅极金属层01在衬底基板00上的正投影，源漏极金属层02在衬底基板00上的正投影，以及有机平坦层04在衬底基板00上的正投影至少部分重叠。如此，该新增的有机平坦层04即可以使得栅极金属 层01和源漏极金属层02之间的间距增大。
基于层叠的两层膜层之间的间距越小，该两层膜层形成的交叠电容的容值越大，两层膜层之间的间距越大，该两层膜层形成的交叠电容的容值越小。即，层叠的两层膜层形成的交叠电容的容值，与该两层膜层之间的间距负相关的原理可知：在本公开实施例中，通过增加栅极金属层01和源漏极金属层02之间的间距，可以有效降低栅极金属层01和源漏极金属层02形成的交叠电容的容值。再基于上述实施例记载可知，在降低容值的前提下，即可以达到减小电容负载的目的。进而，可以在利于高刷新率设计的前提下，降低驱动电路的功耗。
综上所述，本公开实施例提供了一种显示面板。该显示面板包括位于衬底基板一侧且依次层叠的栅极金属层和源漏极金属层，以及位于栅极金属层和源漏极金属层之间且依次层叠的无机绝缘层和有机平坦层。由于该显示面板还包括有机平坦层，且该有机平坦层在衬底基板上的正投影，与栅极金属层和源漏极金属层在衬底基板上的正投影的重叠部分重叠，因此增加了栅极金属层和源漏极金属层的间距，相应的，减小了栅极金属层和源漏极金属层形成的交叠电容的容值。如此，该交叠电容带来的电容负载较小，驱动该显示面板显示的驱动电路的功耗较低。
可选的，参考图1所示显示面板，栅极金属层01和源漏极金属层02可以沿远离衬底基板00的方向依次层叠。即，本公开实施例记载的显示面板可以为底栅结构。当然，在一些实施例中，显示面板也可以为顶栅结构，即，源漏极金属层02和栅极金属层01沿远离衬底基板00的方向依次层叠。
可选的，继续参考图1所示显示面板，无机绝缘层03和有机平坦层04可以沿远离衬底基板00的方向依次层叠。即，在本公开实施例中，有机平坦层04相对于无机绝缘层03可以远离衬底基板00。
对于图1所示结构的显示面板，也即是，栅极金属层01、无机绝缘层03、有机平坦层04和源漏极金属层02可以沿远离衬底基板00的方向依次层叠。
再结合图1所示显示面板，因在源漏极金属层02远离衬底基板00的一侧一般会再设置其他膜层结构(如，封装层)，故通过将有机平坦层04设置于靠近源漏极金属层02的一侧，可以确保其他膜层结构的平坦度较好，进而确保显示面板的良率较好。
在一些实施例中，有机平坦层04相对于无机绝缘层03可以靠近衬底基板00。即有机平坦层04和无机绝缘层03可以沿远离衬底基板00的方向依次层叠。
可选的，依然参考图1，在本公开实施例中，有机平坦层04在衬底基板00上的正投影可以覆盖栅极金属层01和源漏极金属层02的重叠部分。如此，可以使得栅极金属层01和源漏极金属层02重叠的任一部分的间距均较小，进一步有效降低栅极金属层01和源漏极金属层02形成的交叠电容的容值。相应的，可以进一步有效降低该交叠电容带来的电容负载，降低驱动电路的功耗。
可选的，本公开实施例记载的有机平坦层04的材料的介电常数可以大于等于3，且小于等于4。例如，该有机平坦层04的材料可以包括：聚酰亚胺。
可选的，图2是本公开实施例提供的另一种显示面板的结构示意图。如图2所示，该衬底基板00可以具有显示区A1，以及围绕显示区A1的非显示区A2。
可选的，图3是本公开实施例提供的又一种显示面板的结构示意图。结合图2和图3可以看出，本公开实施例记载的有机平坦层04可以仅位于显示区A1，且源漏极金属层02、栅极金属层01和无机绝缘层03中的每个膜层可以均分别位于显示区A1和非显示区A2。图3仅示出部分显示区A1和部分显示区A2。
需要说明的是，显示区A1可以包括阵列排布的多个像素，每个像素可以包括像素电路和发光元件。其中，像素电路可以分别与栅线、数据线和发光元件连接，像素电路用于在栅线提供的栅极驱动信号控制下，向发光元件传输来自数据线的数据信号，以驱动发光元件发光。且，像素电路一般包括驱动晶体管。
还需要说明的是，向栅线传输栅极驱动信号的栅极驱动电路，简称GOA电路可以设置于衬底基板00上，且可以位于非显示区A2。故，本公开实施例记载的非显示区A2可以包括：用于设置GOA电路的GOA区，以及其他区域。且，沿远离显示区A1的方向，GOA区和其他区域可以依次排布。且，栅极驱动电路一般包括多个薄膜晶体管。
可选的，结合图3，位于显示区A1的栅极金属层01和源漏极金属层02可以构成上述记载的像素电路中的晶体管。位于非显示区A2的栅极金属层01和源漏极金属层02可以构成上述记载的GOA电路中的薄膜晶体管。因数据信号一般仅由位于显示区A1的像素电路提供至发光元件，而不会提供至位于非显示区A2的电路结构。故，结合上述实施例对信号切换速度的介绍可知，在非显示区A2内的栅极金属层01和源漏极金属层02之间新增有机平坦层04，对降低 驱动电路的功耗的受益不大，故通过仅在显示区A1内新增有机平坦层04，可以在有效降低驱动电路功耗的同时，简化显示面板结构，降低制造成本。
当然，在一些实施例中，有机平坦层04也可以位于非显示区A2内。
可选的，图4是本公开实施例提供的再一种显示面板的结构示意图。图5是本公开实施例提供的再一种显示面板的结构示意图。
参考图4和图5可以看出，在本公开实施例中，栅极金属层01可以包括：沿远离衬底基板00的方向依次层叠的第一栅极金属层011和第二栅极金属层012。相应的，无机绝缘层03可以包括：位于第一栅极金属层011和第二栅极金属层012之间的第一栅绝缘层(gate insulator，GI)031。以及，位于第二栅极金属层012和源漏极金属层02之间的层间介定层(inter layer dielectric，ILD)032。
通过在每相邻两层导电膜层之间均设置绝缘层，可以有效避免信号相互影响，确保显示面板的显示效果。
可选的，第一栅绝缘层031的介电常数可以约为7。层间介定层032的材料的介电常数可以于等于3，且小于等于4。
可选的，第一栅绝缘层031和层间介定层032的材料可以包括：氮化硅(S iN)、氧化硅(SiO)和氮氧化硅(SiNO)中的至少一种。
可选的，继续参考图4和图5可以看出，本公开实施例记载的显示面板还可以包括：位于栅极金属层01和衬底基板00之间，且沿远离衬底基板00的方向依次层叠的无机层基底05、有源(poly)层06和第二栅绝缘层07。以及，位于源漏极金属层02远离衬底基板00的一侧，且依次层叠的目标平坦层08、像素电极09和像素定义层(pixel definition layer，PDL)10。
可选的，像素电极09可以为阳极(anode)或阴极(cathode)，本公开实施例以该像素电极09为阳极为例进行说明。无机层基底05、有源层06、第二栅绝缘层07、目标平坦层08以及像素定义层10所包括的各个膜层可以分别位于显示区A1和非显示区A2中。像素电极09可以仅位于显示区A1中。
其中，源漏极金属层02可以通过贯穿有机平坦层04、无机绝缘层03和第二栅绝缘层07的过孔K1与有源层06连接。如此，参考图4和图5，可以将过孔K1划分为贯穿有机平坦层04的第一过孔K11，以及贯穿无机绝缘层03和第二栅绝缘层07的第二过孔K12。
可选的，参考图4所示显示面板，第一过孔K11靠近衬底基板00的开口在衬底基板00上的正投影，与第二过孔K12远离衬底基板00的开口在衬底基板00上的正投影可以重合。即，第一过孔K11与第二过孔K12交接处，两个过孔的开口的尺寸可以相同。
经试验测试，如此设置，可以在确保源漏极金属层02与有源层06可靠连接的前提下，降低贯穿有机平坦层04的第一过孔K11对其上设置的其他膜层(如，像素电极)的平坦性的影响。进而，避免对像素发光产生不利影响。
当然，在一些实施例中，参考图5所示显示面板，第一过孔K11靠近衬底基板00的开口在衬底基板00上的正投影，可以覆盖第二过孔K12远离衬底基板00的开口在衬底基板00上的正投影。即，第一过孔K11与第二过孔K12交接处，第一过孔K11的开口的尺寸相对较大，第二过孔K12的开口的尺寸相对较小。如此，可以确保可靠刻蚀贯穿无机绝缘层03和第二栅绝缘层07的第二过孔K12，进而确保源漏极金属层02与有源层06的可靠连接。
需要说明的是，对于未新增有机平坦层04的区域(如图4和图5所示的非显示区A2)，源漏极金属层02可以通过贯穿无机绝缘层03和第二栅绝缘层07的过孔(即，第二过孔K12)与有源层06可靠连接。
另外，图4和图5分别采用不同的方式标识各个膜层。
综上所述，本公开实施例提供了一种显示面板。该显示面板包括位于衬底基板一侧且依次层叠的栅极金属层和源漏极金属层，以及位于栅极金属层和源漏极金属层之间且依次层叠的无机绝缘层和有机平坦层。由于该显示面板还包括有机平坦层，且该有机平坦层在衬底基板上的正投影，与栅极金属层和源漏极金属层在衬底基板上的正投影的重叠部分重叠，因此增加了栅极金属层和源漏极金属层的间距，相应的，减小了栅极金属层和源漏极金属层形成的交叠电容的容值。如此，该交叠电容带来的电容负载较小，驱动该显示面板显示的驱动电路的功耗较低。
图6是本公开实施例提供的一种显示面板的制造方法流程图，该方法可以用于制造如图1至图5任一所述的显示面板。如图6所示，该方法可以包括：
步骤601、提供衬底基板。
可选的，该衬底基板可以为由柔性材料制成的柔性基板，或者，也可以为 玻璃基板。
步骤602、在衬底基板的一侧形成依次层叠的栅极金属层和源漏极金属层。
步骤603、在栅极金属层和源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层。
其中，栅极金属层在衬底基板上的正投影与源漏极金属层在衬底基板上的正投影存在重叠部分，且有机平坦层在衬底基板上的正投影与重叠部分重叠。
综上所述，本公开实施例提供了一种显示面板的制造方法。由于该方法制成的显示面板中，栅极金属层和源漏极金属层之间还包括有机平坦层，且该有机平坦层在衬底基板上的正投影，与栅极金属层和源漏极金属层在衬底基板上的正投影的重叠部分重叠，因此增加了栅极金属层和源漏极金属层的间距，相应的，减小了栅极金属层和源漏极金属层形成的交叠电容的容值。如此，该交叠电容带来的负载较小，驱动该显示面板显示的驱动电路的功耗较低。
可选的，如图7所示，上述步骤602可以包括：
步骤6021、在衬底基板的一侧形成栅极金属层。
步骤6022、在栅极金属层远离衬底基板的一侧形成源漏极金属层。
采用图7所示方法对应的制造顺序形成的显示面板即为上述图1至图5所示的底栅结构的显示面板。当然，若要形成顶栅结构的显示面板，则调换步骤6021和步骤6022的顺序即可。
此外，无论是形成图4还是图5所示结构的显示面板，结合图8所示的部分工艺流程图可以看出，在提供衬底基板00之后，均会先执行下述方法：
(1)在衬底基板00所包括的显示区A1和非显示区A2中先形成无机层基底05。(2)在无机层基底05远离衬底基板00的一侧形成有源层06。其中，可以在显示区A1和非显示区A2分别形成一有源层06。(3)在有源层06远离无机层基底05的一侧形成第二栅绝缘层07，此处的第二栅绝缘层07还未被刻蚀，即还不具有过孔。(4)在第二栅绝缘层07远离有源层06的一侧形成第一栅极金属层011(即，栅极金属层01的一部分)。其中，可以在显示区A1和非显示区A2分别形成第一栅极金属层011。(5)在第一栅极金属层011远离第二栅绝缘层07的一侧形成第一栅绝缘层031(即，无机绝缘层03的一部分)。此处的第一栅绝缘层031还未被刻蚀，即还不具有第二过孔K12。(6)在第一栅绝缘层031远离第一栅极金属层011的一侧形成第二栅极金属层012(即，栅 极金属层01的另一部分)。其中，图8仅示出了形成于显示区A1的第二栅极金属层012。然后，可以再通过下述工艺，形成无机绝缘层03的另一部分层间介定层032，以及刻蚀得到贯穿无机绝缘层03和第二栅绝缘层的第二过孔K12。
作为一种可选的实现方式，以形成图4所示显示面板为例，如图9所示，上述步骤603可以包括：
步骤6031A、在栅极金属层远离衬底基板的一侧形成无机材料层。
可选的，结合图8和图10所示工艺流程图可知，此处的无机材料层可以包括：用于形成层间介定层032的无机材料层，以及用于形成第一栅绝缘层031的无机材料层。此外，可以采用沉积的方式形成该无机材料层。
步骤6032A、在无机材料层远离栅极金属层的一侧形成具有第一过孔的有机平坦层。
可选的，结合图10，可以仅在显示区A1形成具有第一过孔K11的有机平坦层。此外，可以采用掩膜版(mask)相关构图工艺形成该有机平坦层04。
然后，因非显示区A2中的源漏极金属层02也需要与有源层06连接，故可以再在非显示区A2中，在无机材料层远离栅极金属层01的一侧形成光刻胶图案M1。该光刻胶图案M1可以具有过孔。可以采用mask相关构图工艺形成该具有过孔的光刻胶图案M1。
步骤6033A、以有机平坦层作为保护层刻蚀无机材料层，形成具有第二过孔的无机绝缘层。
可选的，结合图10，在显示区A1中，可以以有机平坦层04作为保护层，通过刻蚀(etch)的方式刻蚀无机材料层，从而得到具有第二过孔K12的无机绝缘层。且可以继续刻蚀第二栅绝缘层07，直至刻蚀到有源层06露出为止。
此外，对于非显示区A2，同样可以采用刻蚀的方式，只是是以形成的光刻胶图案M1为保护层进行刻蚀无机材料层以及第二栅绝缘层07，以使得有源层06露出。如此，上述步骤6022即为：在有机平坦层远离衬底基板的一侧形成源漏极金属层。
采用上述图9所示制造流程，无需考虑贯穿有机平坦层04的第一过孔K11，以及贯穿无机绝缘层03的第二过孔K12的对位精度，可以刻蚀得到图4所示结构的显示面板。即，得到的显示面板中，第一过孔K11在衬底基板00上的正投影，与第二过孔K12在衬底基板00上的正投影可以重叠。换言之，第一过孔K 11和第二过孔K12交接处的开口尺寸相同。如此，可以降低贯穿有机平坦层04的第一过孔K11对其上设置的其他膜层(如，像素电极)的平坦性的影响。进而，避免对像素发光产生不利影响。
作为另一种可选的实现方式，以形成图5所示显示面板为例，如图11所示，上述步骤603可以包括：
步骤6031B、在栅极金属层远离衬底基板的一侧形成无机材料层。
该步骤的可以参考上述步骤6031A，在此不再赘述。
步骤6032B、在无机材料层远离栅极金属层的一侧形成光刻胶图案。
结合图12所示工艺流程图，在形成无机材料层之后，可以直接在无机材料层远离栅极金属层的一侧形成光刻胶图案，该光刻胶图案位于显示区A1和非显示区A2，且具有过孔。
可选的，可以采用mask相关构图工艺形成该具有过孔的光刻胶图案M1。
步骤6033B、以光刻胶图案作为保护层刻蚀无机材料层，形成具有第二过孔的无机绝缘层。
继续参考图12，可以以该光刻胶图案作为保护层，通过刻蚀的方式刻蚀无机材料层，形成具有第二过孔K12的无机绝缘层。此外，可以继续刻蚀第二栅绝缘层07，直至有源层06露出为止。显示区A1和非显示区A2同理，此处不一一进行介绍说明。
步骤6034B、剥离光刻胶图案。
在刻蚀得到第二过孔K12后，结合图12所示工艺流程图，可以通过剥离相关工艺(如，激光剥离)，剥离该光刻胶图案。
步骤6035B、在无机绝缘层远离栅极金属层的一侧形成具有第一过孔的有机平坦层。
然后，再接着在具有第二过孔K12的无机绝缘层03远离衬底基板00的一侧形成具有第一过孔的有机平坦层04。可选的，可以采用掩膜版(mask)相关构图工艺形成该有机平坦层04。
由于该制造方式中，是先刻蚀无机绝缘层03和第二栅绝缘层07，再形成有机平坦层04，故需要考虑贯穿有机平坦层04的第一过孔K11，以及贯穿无机绝缘层03的第二过孔K12的对位精度的问题，从而确保有机平坦层04上形成的源漏金属层02可以通过第一过孔K11和第二过孔K12，与有源层06可靠建立 连接。如此，参考图5和图12所示结构，第一过孔K11和第二过孔K12的交接处，第一过孔K11的开口尺寸要大于第二过孔K12的开口尺寸。
可选的，为形成图4或图5所示显示面板，在执行完上述步骤603之后，再结合图13和图15所示工艺流程图，制造方法还可以包括：
(1)在有机平坦层04远离衬底基板00的一侧形成源漏极金属层02，且设置源漏极金属层02通过过孔与有源层06连接。其中，可以在显示区A1和非显示区A2分别形成源漏极金属层02，且位于显示区A1的源漏极金属层02可以通过第一过孔K11和第二过孔K12延伸至有源层06，并与有源层06连接。位于非显示区A2的源漏极金属层02可以通过第二过孔K12延伸至有源层06，并与有源层06连接。此外，对于图10所示流程图，在形成源漏极金属层02之前，还会执行剥离形成于非显示区A2的光刻胶图案M1的操作。(2)在源漏极金属层02远离衬底基板00的一侧形成目标平坦层08。其中，可以在显示区A1和非显示区A2中均形成该目标平坦层08。(3)在目标平坦层08远离衬底基板00的一侧形成像素电极09。且仅在显示区A1中形成该像素电极09。(4)在像素电极09远离衬底基板00的一侧形成像素定义层10。其中，可以在显示区A1和非显示区A2中均形成像素定义层10。
其中，图13是在图9和图10所示制造工艺后继续执行的制造工艺。图15是在图11和图12所示制造工艺后继续执行的制造工艺。对比图13和图15可以看出，因步骤603的制造工艺不同，最终形成的第一过孔K11和第二过孔K12的尺寸不同。为体现该尺寸不同，图14和图16分别示出了图4和图5对应的显示面板结构版图。对比图14和图16可以看出，采用不同制造方法形成的第一过孔K11和第二过孔K12的尺寸不同。
综上所述，本公开实施例提供了一种显示面板的制造方法。由于该方法制成的显示面板中，栅极金属层和源漏极金属层之间还包括有机平坦层，且该有机平坦层在衬底基板上的正投影，与栅极金属层和源漏极金属层在衬底基板上的正投影的重叠部分重叠，因此增加了栅极金属层和源漏极金属层的间距，相应的，减小了栅极金属层和源漏极金属层形成的交叠电容的容值。如此，该交叠电容带来的负载较小，驱动该显示面板显示的驱动电路的功耗较低。
图17是本公开实施例提供的一种显示装置的结构示意图。如图17所示， 该显示装置可以包括：驱动电路100，以及如图1至图5任一所示的显示面板200。其中，该驱动电路100可以与显示面板200连接，且可以用于驱动显示面板200显示。
可选的，包括该显示模组的显示装置可以为：AMOLED显示装置、液晶显示装置、手机、平板电脑、电视机、显示器或笔记本电脑等任何具有显示功能的产品或部件。
应当理解的是，本公开实施例说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，例如能够根据本申请实施例图示或描述中给出那些以外的顺序实施。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种显示面板，所述显示面板包括：
    衬底基板；
    位于所述衬底基板一侧且依次层叠的栅极金属层和源漏极金属层；
    以及，位于所述栅极金属层和所述源漏极金属层之间且依次层叠的无机绝缘层和有机平坦层；
    其中，所述栅极金属层在所述衬底基板上的正投影与所述源漏极金属层在所述衬底基板上的正投影存在重叠部分，所述有机平坦层在所述衬底基板上的正投影与所述重叠部分重叠。
  2. 根据权利要求1所述的显示面板，其中，所述栅极金属层和所述源漏极金属层沿远离所述衬底基板的方向依次层叠。
  3. 根据权利要求2所述的显示面板，其中，所述无机绝缘层和所述有机平坦层沿远离所述衬底基板的方向依次层叠。
  4. 根据权利要求1至3任一所述的显示面板，其中，所述衬底基板具有显示区，以及围绕所述显示区的非显示区；
    其中，所述有机平坦层位于所述显示区；
    所述源漏极金属层、所述栅极金属层和所述无机绝缘层中的每个膜层均分别位于所述显示区和所述非显示区。
  5. 根据权利要求1至4任一所述的显示面板，其中，所述有机平坦层在所述衬底基板上的正投影覆盖所述重叠部分。
  6. 根据权利要求1至5任一所述的显示面板，其中，所述有机平坦层的材料的介电常数大于等于3，且小于等于4。
  7. 根据权利要求1至6任一所述的显示面板，其中，所述栅极金属层包括： 沿远离所述衬底基板的方向依次层叠的第一栅极金属层和第二栅极金属层；所述无机绝缘层包括：
    位于所述第一栅极金属层和所述第二栅极金属层之间的第一栅绝缘层；
    以及，位于所述第二栅极金属层和所述源漏极金属层之间的层间介定层。
  8. 根据权利要求1至7任一所述的显示面板，其中，所述显示面板还包括：
    位于所述栅极金属层和所述衬底基板之间，且沿远离所述衬底基板的方向依次层叠的无机层基底、有源层和第二栅绝缘层；
    以及，位于所述源漏极金属层远离所述衬底基板的一侧，且依次层叠的目标平坦层、像素电极和像素定义层；
    其中，所述源漏极金属层通过贯穿所述有机平坦层、所述无机绝缘层和所述第二栅绝缘层的过孔与所述有源层连接。
  9. 根据权利要求8所述的显示面板，其中，所述过孔包括：贯穿所述有机平坦层的第一过孔，以及贯穿所述无机绝缘层和所述第二栅绝缘层的第二过孔；
    其中，所述第一过孔靠近所述衬底基板的开口在所述衬底基板上的正投影，与所述第二过孔远离所述衬底基板的开口在所述衬底基板上的正投影重合。
  10. 根据权利要求9所述的显示面板，其中，所述衬底基板具有显示区，以及围绕所述显示区的非显示区；所述有机平坦层位于所述显示区；所述源漏极金属层、所述栅极金属层和所述无机绝缘层中的每个膜层均分别位于所述显示区和所述非显示区；
    所述有机平坦层在所述衬底基板上的正投影覆盖所述重叠部分；
    所述有机平坦层的材料的介电常数大于等于3，且小于等于4；
    所述栅极金属层包括：沿远离所述衬底基板的方向依次层叠的第一栅极金属层和第二栅极金属层；所述无机绝缘层包括：位于所述第一栅极金属层和所述第二栅极金属层之间的第一栅绝缘层；以及，位于所述第二栅极金属层和所述源漏极金属层之间的层间介定层。
  11. 一种显示面板的制造方法，所述方法包括：
    提供衬底基板；
    在所述衬底基板的一侧形成依次层叠的栅极金属层和源漏极金属层；
    以及，在所述栅极金属层和所述源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层；
    其中，所述栅极金属层在所述衬底基板上的正投影与所述源漏极金属层在所述衬底基板上的正投影存在重叠部分，所述有机平坦层在所述衬底基板上的正投影与所述重叠部分重叠。
  12. 根据权利要求11所述的方法，其中，所述在所述衬底基板的一侧形成依次层叠的栅极金属层和源漏极金属层，包括：
    在所述衬底基板的一侧形成栅极金属层；
    在所述栅极金属层远离所述衬底基板的一侧形成源漏极金属层。
  13. 根据权利要求12所述的方法，其中，所述在所述栅极金属层和所述源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层，包括：
    在所述栅极金属层远离所述衬底基板的一侧形成无机材料层；
    在所述无机材料层远离所述栅极金属层的一侧形成具有第一过孔的有机平坦层；
    以所述有机平坦层作为保护层刻蚀所述无机材料层，形成具有第二过孔的无机绝缘层；
    其中，所述第一过孔在所述衬底基板上的正投影，与所述第二过孔在所述衬底基板上的正投影重叠。
  14. 根据权利要求12所述的方法，其中，所述在所述栅极金属层和所述源漏极金属层之间形成依次层叠的无机绝缘层和有机平坦层，包括：
    在所述栅极金属层远离所述衬底基板的一侧形成无机材料层；
    在所述无机材料层远离所述栅极金属层的一侧形成光刻胶图案；
    以所述光刻胶图案作为保护层刻蚀所述无机材料层，形成具有第二过孔的无机绝缘层；
    剥离所述光刻胶图案；
    在所述无机绝缘层远离所述栅极金属层的一侧形成具有第一过孔的有机平坦层；
    其中，所述第一过孔在所述衬底基板上的正投影，与所述第二过孔在所述衬底基板上的正投影重叠。
  15. 一种显示装置，所示显示装置包括：驱动电路，以及如权利要求1至10任一所述的显示面板；
    所述驱动电路与所述显示面板连接，且用于驱动所述显示面板显示。
PCT/CN2021/126115 2021-01-28 2021-10-25 显示面板及其制造方法、显示装置 WO2022160807A1 (zh)

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