WO2023126741A1 - 半導体装置、記憶装置、及び半導体装置の作製方法 - Google Patents

半導体装置、記憶装置、及び半導体装置の作製方法 Download PDF

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WO2023126741A1
WO2023126741A1 PCT/IB2022/062263 IB2022062263W WO2023126741A1 WO 2023126741 A1 WO2023126741 A1 WO 2023126741A1 IB 2022062263 W IB2022062263 W IB 2022062263W WO 2023126741 A1 WO2023126741 A1 WO 2023126741A1
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Prior art keywords
insulator
conductor
oxide
oxygen
opening
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
方堂涼太
大貫達也
加藤清
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2023570483A priority Critical patent/JPWO2023126741A1/ja
Priority to US18/723,731 priority patent/US20250056786A1/en
Priority to KR1020247025040A priority patent/KR20240129192A/ko
Priority to CN202280082899.9A priority patent/CN118402329A/zh
Publication of WO2023126741A1 publication Critical patent/WO2023126741A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Definitions

  • One aspect of the present invention relates to a method for producing a metal oxide.
  • one embodiment of the present invention relates to transistors, semiconductor devices, and electronic devices.
  • one embodiment of the present invention relates to a method for manufacturing a semiconductor device.
  • one aspect of the present invention relates to semiconductor wafers and modules.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices.
  • a display device (such as a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to include a semiconductor device in some cases.
  • One aspect of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method.
  • One aspect of the invention also relates to a process, machine, manufacture, or composition of matter.
  • a CPU is an assembly of semiconductor elements that are processed from a semiconductor wafer, have semiconductor integrated circuits (at least transistors and memories) that are chipped, and have electrodes that are connection terminals.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.
  • transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • Patent Document 1 discloses a low-power-consumption CPU and the like that utilize a characteristic that a transistor including an oxide semiconductor has a small leakage current.
  • Patent Document 2 discloses a memory device or the like that can retain stored data for a long period of time by utilizing the characteristic that a transistor including an oxide semiconductor has low leakage current.
  • One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes an oxide, a first conductor and a second conductor over the oxide, and a first conductor. a first insulator disposed on the conductor and the second conductor and having a first opening and a second opening; and a second insulator within the first opening of the first insulator. and a third conductor on the second insulator, the first opening having the first insulator having a region overlapping the oxide, the third conductor comprising: , a region overlapping with the oxide with the second insulator interposed therebetween, and the second insulator is in contact with the top surface of the oxide and the sidewall of the first opening included in the first insulator.
  • the capacitive element has a second conductor, a third insulator over the second conductor, and a fourth conductor over the third insulator, the third insulator, and the fourth conductor are arranged in the second opening, and the distance between the first conductor and the second conductor in a cross-sectional view in the channel length direction of the transistor is equal to the width of the first opening. It is a smaller semiconductor device.
  • the second opening included in the first insulator has a region overlapping with the second conductor, and the fourth conductor is connected to the second conductor with the third insulator interposed therebetween. It is preferable that the third insulator has a region that overlaps with the conductor, and that the third insulator has regions that are in contact with the top surface of the second conductor and the sidewall of the first opening of the first insulator.
  • the second insulator includes the fourth insulator, the fifth insulator over the fourth insulator, and the sixth insulator over the fifth insulator.
  • the third insulator has a seventh insulator; an eighth insulator on the seventh insulator; a ninth insulator on the eighth insulator;
  • the thickness of the insulator 4 has a region smaller than the thickness of the fifth insulator, the sixth insulator is less permeable to oxygen than the fifth insulator, and the seventh insulator has a region smaller than the thickness of the eighth insulator, and the ninth insulator is less permeable to oxygen than the eighth insulator.
  • the fourth insulator has the same insulating material as the seventh insulator, and the fifth insulator has the same insulating material as the eighth insulator.
  • the sixth insulator has the same insulating material as the ninth insulator, and the third conductor has the same conductive material as the fourth conductor.
  • a tenth insulator is provided between the first conductor, the second conductor, and the first insulator, and the tenth insulator is located between the first opening and the first insulator.
  • the tenth insulator has a third opening that overlaps with the second opening and a fourth opening that overlaps with the second opening.
  • the insulator 10 has regions in contact with the side surface of the oxide, the side surface of the first conductor, and the side surface of the second conductor. and the second conductor is preferably less than the width of the third opening.
  • the first conductor includes a fifth conductor and a sixth conductor on the fifth conductor
  • the second conductor includes a seventh conductor. and an eighth conductor on the seventh conductor
  • the distance between the fifth conductor and the seventh conductor in a cross-sectional view in the channel length direction of the transistor is equal to the distance between the fifth conductor and the seventh conductor. is preferably less than the distance between the first conductor and the eighth conductor.
  • mutually facing side surfaces of the first conductor and the second conductor are substantially perpendicular to the upper surface of the oxide.
  • the oxide preferably contains indium, zinc, and one or more selected from gallium, aluminum, and tin.
  • the oxide preferably has crystals, and the c-axis of the crystals is substantially perpendicular to the surface of the oxide or the surface on which the oxide is formed.
  • a ninth conductor be provided under the oxide, and the ninth conductor overlap with the oxide and the third conductor.
  • Another aspect of the present invention has a plurality of layers each including a memory array provided with the above semiconductor device, and each layer includes a first wiring electrically connected to a first conductor and a third wiring. and a third wire electrically connected to the fourth conductor, wherein the upper ninth conductor in the continuous layer is , is electrically connected to the third wiring in the lower layer, and the second wiring in the lower layer is provided at a position overlapping with the third wiring in the upper layer in the continuous layers.
  • the first wirings of the odd-numbered layers are electrically connected to each other, and the first wirings of the even-numbered layers are electrically connected to each other.
  • a driver circuit be provided, and the plurality of layers be provided over the driver circuit.
  • One embodiment of the present invention includes a transistor and a capacitor, and the transistor includes an oxide, first to third conductors, a first insulator, and a second insulator. and the capacitor includes a second conductor, a third insulator, and a fourth conductor.
  • a first insulator is formed over the conductive layer, and first and second openings are formed in the first insulator to expose top and side surfaces of the conductive layer and side surfaces of the oxide.
  • the mask layer having a third opening overlapping with a part of the first opening, and in a cross-sectional view in the channel length direction of the transistor , the width of the third opening is less than the width of the first opening, the mask layer is used to etch the conductive layer to form the first conductor and the second conductor, the first insulator is , an insulating film is formed to cover the first opening and the second opening, a conductive film is formed on the insulating film, and the insulating film and the conductive film are formed from the first opening and the second opening. removing the exposed portions to form a second insulator and a third conductor in the first opening and forming a third insulator and a fourth conductor in the second opening; This is a method for manufacturing a semiconductor device.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with high operation speed can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with little variation in electrical characteristics of transistors can be provided.
  • a semiconductor device with favorable electrical characteristics can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a method for manufacturing a semiconductor device in which the number of steps is reduced can be provided.
  • FIG. 1A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 1B to 1D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • 2A and 2B are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
  • 3A and 3B are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
  • FIG. 4A is a top view of a semiconductor device which is one embodiment of the present invention.
  • 4B to 4D are cross-sectional views of semiconductor devices that are embodiments of the present invention.
  • FIG. 5A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 13A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 14A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 15A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 16A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device which is one embodiment of the present invention.
  • FIG. 18 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention.
  • FIG. 19 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.
  • FIG. 20 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.
  • FIG. 21 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.
  • FIG. 22A is a plan view of a semiconductor device according to one embodiment of the present invention.
  • 22B and 22C are cross-sectional views of a semiconductor device that is one embodiment of the present invention.
  • FIG. 23A is a plan view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 23B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 24 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • 25A to 25C are a block diagram, a schematic diagram, and a circuit diagram illustrating the structure of a memory device according to one embodiment of the present invention.
  • 26A and 26B are schematic diagrams illustrating the structure of a memory device according to one embodiment of the present invention.
  • 27A and 27B are a schematic diagram and a circuit diagram illustrating the structure of a memory device according to one embodiment of the present invention.
  • FIG. 28 is a schematic diagram illustrating the structure of a memory device according to one embodiment of the present invention.
  • 29A and 29B are layout diagrams illustrating the structure of a memory device according to one embodiment of the present invention.
  • 30A and 30B are a layout diagram and a cross-sectional schematic diagram for explaining the structure of a memory device according to one embodiment of the present invention.
  • FIG. 31 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 32 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 33 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • 34A and 34B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
  • 35A and 35B are diagrams illustrating an example of an electronic component.
  • 36A to 36E are schematic diagrams of a memory device according to one embodiment of the present invention.
  • 37A to 37H are diagrams illustrating electronic devices according to one embodiment of the present invention.
  • FIG. 38 is a diagram showing an example of space equipment.
  • top views also referred to as “plan views”
  • perspective views also referred to as “plan views”.
  • description of some hidden lines may be omitted.
  • the ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, “first” can be appropriately replaced with “second” or “third”. Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected means that X and Y are electrically connected.
  • X and Y are electrically connected means an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) between X and Y. ) is present, the connection through which electrical signals can be transmitted between X and Y.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • the fact that X and Y are directly connected means that an electric signal is transmitted between X and Y via a wiring (or electrode) or the like between X and Y without passing through the object.
  • a direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a region in which a channel is formed (hereinafter also referred to as a channel formation region) is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode).
  • a current can flow between the source and the drain through the formation region.
  • a channel formation region means a region where current mainly flows.
  • the function of the source or drain may be switched when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably in some cases.
  • the channel length is, for example, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) overlaps with a gate electrode in a top view of a transistor, or the source length in a channel formation region.
  • channel lengths in one transistor do not always have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the channel forming region.
  • the channel width is, for example, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) overlaps with a gate electrode in a top view of a transistor, or a channel formation region in the channel length direction.
  • a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and a channel width shown in a top view of a transistor ( hereinafter also referred to as “apparent channel width”) may be different.
  • the effective channel width becomes larger than the apparent channel width, and its influence cannot be ignored.
  • the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to the apparent channel width.
  • channel width may refer to the effective channel width.
  • the channel length, channel width, effective channel width, or apparent channel width can be determined by analyzing cross-sectional TEM images, for example.
  • impurities in a semiconductor refer to, for example, substances other than the main components that constitute the semiconductor.
  • an element whose concentration is less than 0.1 atomic percent can be said to be an impurity.
  • the inclusion of impurities may cause, for example, an increase in the defect level density of the semiconductor, a decrease in crystallinity, and the like.
  • impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, and oxide semiconductors.
  • transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V 2 O 3
  • silicon oxynitride contains more oxygen than nitrogen as its composition.
  • Silicon nitride oxide contains more nitrogen than oxygen in its composition.
  • aluminum oxynitride has a higher content of oxygen than nitrogen as its composition.
  • aluminum oxynitride has a composition in which the content of nitrogen is higher than that of oxygen.
  • hafnium oxynitride has a higher content of oxygen than nitrogen as its composition.
  • hafnium oxynitride has a composition in which the content of nitrogen is higher than that of oxygen.
  • insulator can be replaced with an insulating film or an insulating layer.
  • conductor can be replaced with a conductive film or a conductive layer.
  • semiconductor can be interchanged with a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of ⁇ 5 degrees or more and 5 degrees or less is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially perpendicular means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a metal oxide is a metal oxide in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like.
  • oxide semiconductors also referred to as oxide semiconductors or simply OSs
  • an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.
  • the term “normally-off” means that the drain current per 1 ⁇ m of the channel width flowing through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate is 1 ⁇ 10 ⁇ 1 at room temperature. 20 A or less, 1 ⁇ 10 ⁇ 18 A or less at 85° C., or 1 ⁇ 10 ⁇ 16 A or less at 125° C.
  • Voltage is a potential difference from a reference potential.
  • the reference potential is ground potential
  • “voltage” can be replaced with “potential”. Note that the ground potential does not necessarily mean 0V.
  • the potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit etc. also change.
  • the heights are the same or approximately the same” refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • planarization processing typically CMP processing
  • CMP processing may expose the surface of a single layer or multiple layers.
  • the surfaces to be CMP-processed have the same height from the reference surface.
  • the heights of the layers may differ depending on the processing equipment, processing method, or material of the surface to be processed during the CMP processing. In this specification and the like, this case is also treated as "the height matches or roughly matches".
  • the height of the top surface of the first layer and the height of the second layer A case where the height difference from the upper surface is 20 nm or less is also referred to as "matching or substantially matching heights".
  • the ends match or roughly match means that at least part of the outline overlaps between the laminated layers when viewed from the top.
  • the upper layer and the lower layer may be processed with the same mask pattern, or partially with the same mask pattern.
  • the contours do not overlap, and the upper contour may be positioned inside the lower contour, or the upper contour may be positioned outside the lower contour. “match or approximate match”.
  • a semiconductor device which is one embodiment of the present invention includes a transistor and a capacitor.
  • FIG. 1A to 1D are top and cross-sectional views of a semiconductor device having a transistor 200 and a capacitor 100.
  • FIG. FIG. 1A is a top view of the semiconductor device.
  • 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 and the capacitor 100 in the channel length direction.
  • FIG. 1C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG.
  • 1A is also a cross-sectional view of the transistor 200 in the channel width direction.
  • 1D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view of the capacitive element 100 in the channel width direction. Note that some elements are omitted in the top view of FIG. 1A for clarity of illustration.
  • a semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212 , a transistor 200 and a capacitor 100 over the insulator 214 , and the transistor 200 .
  • Insulator 280 on insulator 275 and insulator 271 (insulators 271a and 271b), insulator 282 on insulator 280, insulator 283 on insulator 282, and insulator 283 on insulator 280 274 and an insulator 285 on insulator 283 and on insulator 274 .
  • the insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, the insulator 285, the insulator 274, and the insulator 285 function as interlayer films. Also, the insulator 283 is in contact with part of the top surface of the insulator 214 , the side surfaces of the insulator 280 , and the side surfaces and top surface of the insulator 282 . As shown in FIG. 1 , the transistor 200 and the capacitive element 100 are at least partially embedded in the insulator 280 .
  • the transistor 200 includes an oxide 230 functioning as a semiconductor layer, a conductor 260 functioning as a first gate, a conductor 205 functioning as a second gate, and a conductor functioning as either a source or a drain. It has a body 242a and a conductor 242b that functions as the other of the source or drain.
  • an insulator 252, an insulator 250, and an insulator 254 functioning as a first gate insulating film are included.
  • insulators 222 and 224 functioning as second gate insulating films are included.
  • the first gate and first gate insulating film of the transistor 200 are arranged in the openings 258 formed in the insulators 280 , 275 and 271 . That is, conductor 260 , insulator 252 , insulator 250 , and insulator 254 are positioned within opening 258 .
  • the capacitive element 100 also includes a conductor 242b functioning as a lower electrode, insulators 152, 150, and 154 functioning as dielectrics, and a conductor 160 functioning as an upper electrode. That is, the capacitive element 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.
  • the conductor 242b can also serve as the lower electrode of the capacitor 100 and the other of the source and drain of the transistor 200 . Therefore, part of the manufacturing process of the transistor 200 can be used in the manufacturing process of the capacitor 100, so that the semiconductor device can be manufactured with high productivity.
  • the upper electrode and dielectric of the capacitive element 100 are arranged in the openings 158 formed in the insulators 280 , 275 and 271 . That is, conductor 160 , insulator 152 , insulator 150 , and insulator 154 are positioned within opening 158 .
  • the semiconductor device of one embodiment of the present invention also includes a conductor 240 that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 is provided in contact with the side surface of the conductor 240 . Also, the conductor 240 is electrically connected to the conductor 242a. A conductor 246 that is electrically connected to the conductor 240 and functions as a wiring is provided over the insulator 285 and the conductor 240 .
  • the conductors 240 and 246 are circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals, and plugs or wirings for electrically connecting the transistor 200. function as
  • a semiconductor device including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device.
  • the conductor 246 may be electrically connected to the sense amplifier.
  • transistor 200 and capacitive element 100 are both formed on oxide 230, as shown in FIG. 1A. Therefore, in plan view, the capacitive element 100 can be provided without greatly increasing the occupied area, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
  • the transistor 200 includes an insulator 216 over an insulator 214, conductors 205 (a conductor 205a and a conductor 205b) embedded in the insulator 216, Insulator 222 over insulator 216 and over conductor 205, insulator 224 over insulator 222, oxide 230a over insulator 224, oxide 230b over oxide 230a, and oxide 230b conductor 242a, insulator 271a over conductor 242a, conductor 242b over oxide 230b, insulator 271b over conductor 242b, insulator 252 over oxide 230b, and insulator 252 over oxide 230b.
  • insulator 252 includes a top surface of insulator 222, sides of insulator 224, sides of oxide 230a, sides and top of oxide 230b, conductor 242a and conductor 242 b , the insulators 271 a and 271 b , the insulator 275 , the insulator 280 , and the bottom surface of the insulator 250 .
  • the top surface of the conductor 260 is arranged so that the top surface of the insulator 254 , the top surface of the insulator 250 , the top surface of the insulator 252 , and the top surface of the insulator 280 are substantially flush with each other.
  • the insulator 282 is in contact with at least part of the upper surface of each of the conductor 260 , the insulator 252 , the insulator 250 , the insulator 254 , and the insulator 280 .
  • the oxide 230a and the oxide 230b are collectively referred to as the oxide 230 in some cases.
  • the conductor 242a and the conductor 242b are collectively referred to as the conductor 242 in some cases.
  • the insulator 271a and the insulator 271b are collectively referred to as the insulator 271 .
  • the insulator 280, the insulator 271 and the insulator 275 are provided with openings 258 reaching the oxide 230b. That is, it can be said that the opening 258 has a region that overlaps with the oxide 230b. In addition, it can be said that the insulator 275 has an opening that overlaps with the opening 258 of the insulator 280 .
  • Insulator 252 , insulator 250 , insulator 254 , and conductor 260 are also disposed within opening 258 . That is, the conductor 260 has a region overlapping with the oxide 230b with the insulators 252, 250, and 254 interposed therebetween.
  • a conductor 260, an insulator 252, an insulator 250, and an insulator 254 are provided between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b.
  • the insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260 . Note that opening 258 reaches insulator 222 in areas that do not overlap oxide 230, as shown in FIG. 1C.
  • the oxide 230 preferably has an oxide 230a overlying the insulator 224 and an oxide 230b overlying the oxide 230a.
  • the oxide 230 has a structure in which two layers of the oxide 230a and the oxide 230b are stacked; however, the present invention is not limited to this.
  • a single layer of the oxide 230b or a layered structure of three or more layers may be provided, or each of the oxides 230a and 230b may have a layered structure.
  • the conductor 260 functions as a first gate (also called top gate) electrode, and the conductor 205 functions as a second gate (also called back gate) electrode.
  • insulators 252, 250, and 254 function as a first gate insulator, and insulators 222 and 224 function as a second gate insulator.
  • the gate insulator is sometimes called a gate insulating layer or a gate insulating film.
  • the conductor 242a functions as one of the source and the drain, and the conductor 242b functions as the other of the source and the drain. At least part of the region of the oxide 230 overlapping with the conductor 260 functions as a channel formation region.
  • FIG. 2A shows an enlarged view of the vicinity of the channel forming region in FIG. 1B.
  • the distance L2 between the conductors 242a and 242b is preferably smaller than the width of the opening 258.
  • the width of the opening 258 is the distance L1 between the interface of the insulator 280 and the insulator 252 on the conductor 242a side and the interface of the insulator 280 and the insulator 252 on the conductor 242b side shown in FIG. 2A. handle.
  • channel etching of the conductors 242a and 242b is performed after the opening 258 is formed in this embodiment mode.
  • the distance L2 between the conductor 242a and the conductor 242b can be relatively easily adjusted to a very fine structure (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less). , or 10 nm or less, and 1 nm or more, or 5 nm or more).
  • the opening 258 has the insulator 222 as a bottom surface and the insulators 280, 275, and 271 as side surfaces.
  • 230 and the conductor 242 can be regarded as a shape in which a part of the structure is protruded. Further, in the structure including the insulator 224, the oxide 230, and the conductor 242, it can be considered that the region of the oxide 230 between the conductors 242a and 242b is exposed.
  • an insulator 252 is provided in contact with the bottom and inner walls of the opening 258 .
  • the insulator 252 is formed on the top surface of the insulator 222, the side surfaces of the insulator 224, the side surfaces of the oxide 230a, the top surface and side surfaces of the oxide 230b, part of the top surface and side surfaces of the conductor 242a, and the top surface of the conductor 242b. It is in contact with a part and a side surface, a side surface of the insulator 271 a , a side surface of the insulator 271 b , a side surface of the insulator 275 , and a side surface of the insulator 280 .
  • An insulator 250 , an insulator 254 , and a conductor 260 are stacked over the insulator 252 . Therefore, an insulator 252 , an insulator 250 , an insulator 254 , and a conductor 260 are provided to cover the conductors 242 a and 242 b partially protruding into the opening 258 .
  • the channel formation region of the transistor 200 has a very fine structure. As a result, the ON current of the transistor 200 is increased, and the frequency characteristics can be improved.
  • the oxide 230b includes a region 230bc functioning as a channel formation region of the transistor 200, and regions 230ba and 230bb functioning as a source region or a drain region and provided to sandwich the region 230bc. have. At least a portion of the region 230bc overlaps the conductor 260 . In other words, the region 230bc is provided in a region between the conductors 242a and 242b. The region 230ba is provided so as to overlap with the conductor 242a, and the region 230bb is provided so as to overlap with the conductor 242b.
  • region 230bc functioning as a channel forming region is a high-resistance region with a lower carrier concentration because it has less oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb.
  • region 230bc can be said to be i-type (intrinsic) or substantially i-type.
  • the region 230ba and the region 230bb functioning as a source region or a drain region have many oxygen vacancies or have a high impurity concentration such as hydrogen, nitrogen, or a metal element, so that the carrier concentration is increased and the resistance is lowered.
  • the regions 230ba and 230bb are n-type regions having a higher carrier concentration and a lower resistance than the region 230bc.
  • the opposing sides of the conductors 242a and 242b are preferably substantially perpendicular to the top surface of the oxide 230b.
  • the side end portion of the region 230ba formed under the conductor 242a on the side of the region 230bc is prevented from excessively receding from the side end portion of the conductor 242a on the side of the region 230bc. can do.
  • the frequency characteristics of the transistor 200 can be improved, and the operation speed of the semiconductor device according to one embodiment of the present invention can be improved.
  • the semiconductor device according to one embodiment of the present invention is used as a memory cell of a memory device, the writing speed and the reading speed can be improved.
  • the carrier concentration of the region 230bc functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , and 1 ⁇ 10 16 cm ⁇ 3 . It is more preferably less than 3 , more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 12 cm ⁇ 3 . Also, the lower limit of the carrier concentration of the region 230bc functioning as a channel formation region is not particularly limited, but can be set to 1 ⁇ 10 ⁇ 9 cm ⁇ 3 , for example.
  • the carrier concentration is equal to or lower than the carrier concentration of the region 230ba and the region 230bb, and equal to or higher than the carrier concentration of the region 230bc.
  • a region may be formed. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb.
  • the bonding region may have a hydrogen concentration equal to or lower than that of the regions 230ba and 230bb and equal to or higher than that of the region 230bc.
  • the bonding region may have oxygen vacancies equal to or less than those of the regions 230ba and 230bb and equal to or greater than those of the region 230bc.
  • FIG. 2A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b
  • the present invention is not limited to this.
  • each of the above regions may be formed up to oxide 230a as well as oxide 230b.
  • the concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes for each region, and may change continuously within each region. In other words, the closer the region is to the channel formation region, the lower the concentrations of the metal elements and the impurity elements such as hydrogen and nitrogen.
  • metal oxides functioning as semiconductors are preferably used for the oxides 230 (the oxides 230a and 230b) including a channel formation region.
  • the bandgap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more.
  • the off-state current of the transistor can be reduced by using a metal oxide with a large bandgap.
  • an In-M-Zn oxide containing indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium).
  • element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.
  • an In--Ga oxide, an In--Zn oxide, or an indium oxide may be used.
  • the oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions.
  • the atomic ratio of the element M to the main component metal element is the same as the atomic ratio of the element M to the main component metal element in the metal oxide used for the oxide 230b. Larger is preferable.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. With this structure, diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b can be suppressed.
  • the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the transistor 200 can have high on-state current and high frequency characteristics.
  • the oxides 230a and 230b have a common element other than oxygen as a main component, the defect level density at the interface between the oxides 230a and 230b can be reduced.
  • the defect level density at the interface between oxide 230a and oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • the neighboring composition includes a range of ⁇ 30% of the desired atomic number ratio.
  • the element M it is preferable to use gallium.
  • a metal oxide that can be used for the oxide 230a may be used as the oxide 230b.
  • the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and the atomic ratio of the sputtering target used for the deposition of the metal oxide. may be
  • the oxide 230b preferably has crystallinity.
  • CAAC-OS c-axis aligned crystal oxide semiconductor
  • CAAC-OS is a metal oxide that has a dense structure with high crystallinity and few impurities and defects (such as oxygen vacancies).
  • heat treatment is performed at a temperature at which the metal oxide is not polycrystallized (for example, 400° C. or more and 600° C. or less), so that the CAAC-OS has a dense structure with higher crystallinity.
  • a temperature at which the metal oxide is not polycrystallized for example, 400° C. or more and 600° C. or less
  • the oxide 230b by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Accordingly, extraction of oxygen from the oxide 230b can be reduced even if heat treatment is performed, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • a transistor including an oxide semiconductor if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded.
  • hydrogen in the vicinity of oxygen vacancies may form defects in which hydrogen enters oxygen vacancies (hereinafter sometimes referred to as V OH ) to generate electrons serving as carriers. Therefore, if oxygen vacancies are included in the region where the channel is formed in the oxide semiconductor, the transistor has normally-on characteristics (a channel exists even if no voltage is applied to the gate electrode, and current flows through the transistor). flow characteristics). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in a region where a channel is formed in the oxide semiconductor. In other words, the region in which the channel is formed in the oxide semiconductor preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.
  • an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor, and heat treatment is performed so that the oxide semiconductor is converted from the insulator.
  • Oxygen can be supplied and oxygen vacancies and VOH can be reduced.
  • the on-state current or the field-effect mobility of the transistor 200 might decrease.
  • variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface cause variations in the characteristics of the semiconductor device having transistors.
  • oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor is oxidized and the conductivity is impaired. It may adversely affect the electrical characteristics and reliability of the transistor.
  • the region 230bc functioning as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type.
  • Region 230bb has a high carrier concentration and is preferably n-type.
  • the semiconductor device is configured to efficiently supply oxygen to the region 230bc and suppress oxidation of the conductors 242a, 242b, and 260.
  • the insulator 250 In order to supply oxygen to the region 230bc, it is preferable to use an insulator that easily transmits oxygen as the insulator 250 .
  • An insulator containing excess oxygen is preferably used as the insulator 280 . With this structure, oxygen contained in the insulator 280 can be supplied to the region 230bc through the insulator 250 .
  • an insulator having a function of suppressing diffusion of oxygen is provided near each of the conductors 242a, 242b, and 260. It is preferable to provide In the semiconductor device described in this embodiment, the insulators are the insulators 252, 254, and 275, for example.
  • the insulator 252 preferably has a barrier property against oxygen.
  • the insulator 252 is provided between the insulator 250 and the conductor 242a and between the insulator 250 and the conductor 242b. Therefore, oxygen contained in the insulator 250 can be prevented from diffusing into the conductors 242a and 242b, and oxidation of the conductors 242a and 242b can be suppressed. Alternatively, the amount of oxygen contained in the insulator 250 that diffuses into the conductors 242a and 242b is reduced, so that the oxide layers formed on the side surfaces of the conductors 242a and 242b can be thin. Further, the insulator 252 is provided between the insulator 250 and the oxide 230b. Therefore, when heat treatment or the like is performed, desorption of oxygen from the region 230bc of the oxide 230b can be suppressed.
  • the film thickness of the insulator 252 is preferably thin.
  • the thickness of the insulator 252 preferably has a region smaller than the thickness of the insulator 250 .
  • Insulator 250 has a region that contacts the top surface of oxide 230b.
  • oxygen contained in the insulator 250 can be supplied to the region 230bc of the oxide 230b, and excessive supply of oxygen contained in the insulator 250 can be suppressed.
  • the insulator 252 is provided between the insulators 280 and 250 and has a region in contact with the sidewall of the opening of the insulator 280 .
  • oxygen contained in the insulator 280 can be supplied to the insulator 250, and excessive supply of oxygen contained in the insulator 280 can be suppressed.
  • the insulator 254 preferably has a barrier property against oxygen. Insulator 254 is provided between insulator 250 and conductor 260 . Therefore, oxygen contained in the insulator 250 can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Note that the insulator 254 should be at least less permeable to oxygen than the insulator 250 .
  • the insulator 275 it is preferable to use an insulator having a function of suppressing permeation of oxygen.
  • the insulator 275 is provided between the insulator 280 and the conductors 242a and 242b. With this structure, diffusion of oxygen contained in the insulator 280 to the conductors 242a and 242b can be suppressed. Therefore, the oxygen contained in the insulator 280 can prevent the conductors 242a and 242b from being oxidized to increase the resistivity and reduce the on-current.
  • the insulator 275 should be at least less permeable to oxygen than the insulator 250 .
  • the region 230bc functioning as a channel forming region can be i-type or substantially i-type, and the regions 230ba and 230bb functioning as a source region or a drain region can be n-type.
  • a semiconductor device having electrical characteristics can be provided. Further, with the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. For example, good electrical characteristics can be obtained even if the distance L2 shown in FIG. 2A is 20 nm or less, 15 nm or less, 10 nm or less, or 7 nm or less, and is 2 nm or more, 3 nm or more, or 5 nm or more.
  • miniaturization of the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.
  • the cutoff frequency of the transistor can be, for example, 50 GHz or higher, or 100 GHz or higher in a room temperature environment.
  • a conductive material that is difficult to oxidize a conductive material that has a function of suppressing diffusion of oxygen, or the like is preferably used.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Accordingly, a decrease in the conductivity of the conductors 242a, 242b, and 260 can be suppressed.
  • the conductors 242a, 242b, and 260 are conductive materials containing at least metal and nitrogen. become a body.
  • any one or more of the conductors 242a, 242b, and 260 may have a laminated structure.
  • a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing diffusion of oxygen, or the like is used as a layer in contact with the oxide 230b. good.
  • the conductor 260a is made of a conductive material that is difficult to oxidize or has a function of suppressing the diffusion of oxygen. It is preferable to use a conductive material having
  • a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b.
  • a metal oxide that can be applied to the oxide 230 described above is preferably used.
  • CAAC-OS is an oxide having crystals, and the c-axis of the crystals is substantially perpendicular to the surface of the oxide or the formation surface. Accordingly, extraction of oxygen from the oxide 230b by the conductor 242a or the conductor 242b can be suppressed. In addition, it is possible to suppress a decrease in the conductivity of the conductors 242a and 242b.
  • the insulator 282 provided over the insulator 280 is preferably formed by a method by which oxygen can be added to the insulator 280 .
  • the insulator 280 can contain excess oxygen.
  • the semiconductor device in this embodiment mode has a structure in which entry of hydrogen into the transistor 200 is suppressed.
  • an insulator having a function of suppressing diffusion of hydrogen is provided so as to cover the transistor 200 .
  • the insulators are the insulators 212 and 283, for example.
  • An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 212 . Accordingly, diffusion of hydrogen into the transistor 200 from below the insulator 212 can be suppressed.
  • an insulator having a function of suppressing diffusion of hydrogen as the insulator 283 . Accordingly, diffusion of hydrogen from above the insulator 283 into the transistor 200 can be suppressed. In addition, diffusion of hydrogen contained in the insulator 274 to the transistor 200 can be suppressed.
  • microwave treatment is performed in an atmosphere containing oxygen in a state where the conductors 242a and 242b are provided over the oxide 230b, so that oxygen vacancies in the region 230bc and VOH are reduced.
  • the microwave treatment refers to treatment using an apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequencies such as RF, and the oxygen plasma can act. At this time, the region 230bc can also be irradiated with microwaves or high frequencies such as RF.
  • V OH in the region 230bc can be divided into oxygen vacancies and hydrogen, the hydrogen can be removed from the region 230bc, and the oxygen vacancies can be compensated with oxygen. Therefore, the hydrogen concentration, oxygen vacancies, and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
  • the effects of microwaves, high frequencies such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb.
  • the effects of oxygen plasma can be reduced by insulators 271 and 280 provided over oxide 230b and conductor 242 .
  • V 2 O 3 is reduced and an excessive amount of oxygen is not supplied in the regions 230ba and 230bb during the microwave treatment, so that a decrease in carrier concentration can be prevented.
  • microwave treatment is preferably performed in an oxygen-containing atmosphere.
  • an atmosphere containing oxygen By performing microwave treatment in an atmosphere containing oxygen through the insulator 252 or the insulator 250 in this manner, oxygen can be efficiently injected into the region 230bc.
  • the insulator 252 so as to be in contact with the side surface of the conductor 242 and the surface of the region 230bc, injection of more than a necessary amount of oxygen into the region 230bc is suppressed, and oxidation of the side surface of the conductor 242 is suppressed. be able to.
  • oxidation of the side surface of the conductor 242 can be suppressed when the insulating film to be the insulator 250 is formed.
  • the oxygen injected into the region 230bc has various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into the region 230bc may be one or more of the forms described above, and oxygen radicals are particularly preferable. In addition, since the film quality of the insulator 252 and the insulator 250 can be improved, the reliability of the transistor 200 is improved.
  • oxygen vacancies and V OH can be selectively removed from the oxide semiconductor region 230bc to make the region 230bc i-type or substantially i-type. Furthermore, excessive supply of oxygen to the regions 230ba and 230bb functioning as the source region or the drain region can be suppressed, and the state of the n-type region before the microwave treatment can be maintained. As a result, variations in the electrical characteristics of the transistor 200 can be suppressed, and variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.
  • a semiconductor device with little variation in transistor characteristics it is possible to provide a semiconductor device with little variation in transistor characteristics. Further, a semiconductor device with favorable frequency characteristics can be provided. In addition, a semiconductor device with high operating speed can be provided. Further, a highly reliable semiconductor device can be provided. Further, a semiconductor device having favorable electrical characteristics can be provided. Further, a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter also referred to as round shape).
  • the radius of curvature of the curved surface is preferably larger than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region without the curved surface.
  • the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and more preferably greater than or equal to 2 nm and less than or equal to 10 nm.
  • the interface between the oxide 230 and the insulator 252 and its vicinity can be Indium contained in the oxide 230 may be unevenly distributed.
  • the vicinity of the surface of the oxide 230 has an atomic ratio close to that of indium oxide or an atomic ratio close to that of In—Zn oxide.
  • At least one of the insulator 212 , the insulator 214 , the insulator 271 , the insulator 275 , the insulator 282 , the insulator 283 , and the insulator 285 is exposed to impurities such as water and hydrogen from the substrate side or the transistor 200 . It preferably functions as a barrier insulating film that suppresses diffusion from above into the transistor 200 .
  • At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.) and copper atoms (thus, the above impurities hardly permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (through which oxygen hardly permeates).
  • a barrier insulating film refers to an insulating film having barrier properties.
  • barrier property refers to the function of suppressing the diffusion of the corresponding substance (also referred to as “low permeability”).
  • the corresponding substance has the function of capturing and fixing (also called gettering).
  • the insulators 212, 214, 271, 275, 282, 283, and 285 are insulators having a function of suppressing diffusion of water, impurities such as hydrogen, and oxygen. is preferably used, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used.
  • the insulator 212, the insulator 275, and the insulator 283 are preferably made of silicon nitride or the like, which has a higher hydrogen barrier property.
  • the insulator 214, the insulator 271, the insulator 282, and the insulator 285 are preferably made of aluminum oxide, magnesium oxide, or the like, which has high functions of capturing and fixing hydrogen.
  • impurities such as water and hydrogen can be prevented from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214 .
  • impurities such as water and hydrogen can be prevented from diffusing to the transistor 200 side from the interlayer insulating film or the like provided outside the insulator 285 .
  • diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulators 212 and 214 can be suppressed.
  • oxygen contained in the insulator 280 or the like can be prevented from diffusing above the transistor 200 through the insulator 282 or the like.
  • the transistor 200 is formed of the insulators 212, 214, 271, 275, 282, 283, and 283, which have a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.
  • a structure surrounded by an insulator 285 is preferable.
  • the insulators 212, 214, 271, 275, 282, 283, and 285 are preferably oxides having an amorphous structure.
  • metal oxides such as AlO x (x is any number greater than 0) or MgO y (y is any number greater than 0).
  • Oxygen atoms in metal oxides having such an amorphous structure have dangling bonds, and the dangling bonds sometimes have the property of capturing or fixing hydrogen.
  • hydrogen contained in the transistor 200 or hydrogen existing around the transistor 200 is captured or fixed. be able to.
  • the transistor 200 and the semiconductor device with favorable characteristics and high reliability can be manufactured.
  • the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but part of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 has a polycrystalline structure. may be formed.
  • the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 are multilayers in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. It may be a structure. For example, a laminated structure in which a layer of polycrystalline structure is formed on a layer of amorphous structure may be used.
  • the insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited by sputtering, for example. Since the sputtering method does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentrations of the insulators 212, 214, 271, 275, 282, 283, and 285 are can be reduced.
  • the film formation method is not limited to the sputtering method, chemical vapor deposition (CVD) method, molecular beam epitaxy (MBE) method, pulsed laser deposition (PLD) method. ) method, Atomic Layer Deposition (ALD) method, or the like may be used as appropriate.
  • insulators 212, 275, and 283 It may also be desirable to reduce the resistivity of insulators 212, 275, and 283.
  • the resistivity of the insulator 212, the insulator 275, and the insulator 283 can be approximately 1 ⁇ 10 13 ⁇ cm, the insulator 212, the insulator 275, and the insulator 283 can be processed using plasma or the like in a manufacturing process of a semiconductor device. Insulator 283 can mitigate charge-up in conductor 205, conductor 242, conductor 260, or conductor 246 in some cases.
  • Each of the insulator 212, the insulator 275, and the insulator 283 preferably has a resistivity of 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 216, the insulator 274, the insulator 280, and the insulator 285 preferably have a lower dielectric constant than the insulator 214.
  • the parasitic capacitance generated between wirings can be reduced.
  • the insulator 216, the insulator 274, the insulator 280, and the insulator 285 include silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Silicon oxide having vacancies or the like may be used as appropriate.
  • the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260 .
  • the conductor 205 is preferably embedded in an opening formed in the insulator 216 . Also, part of the conductor 205 is embedded in the insulator 214 in some cases.
  • the conductor 205 has a conductor 205a and a conductor 205b.
  • the conductor 205a is provided in contact with the bottom and side walls of the opening.
  • the conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a.
  • the height of the top surface of the conductor 205b approximately matches the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216 .
  • the conductor 205a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N 2 O, NO, NO 2 ), and copper atoms. It is preferable to use a conductive material having a Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.
  • the conductor 205a When a conductive material having a function of reducing diffusion of hydrogen is used for the conductor 205a, impurities such as hydrogen contained in the conductor 205b enter the oxide 230 through the insulators 216, 224, and the like. You can prevent it from spreading. Further, by using a conductive material having a function of suppressing diffusion of oxygen for the conductor 205a, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 205b. As the conductive material having a function of suppressing diffusion of oxygen, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Therefore, the conductor 205a may be a single layer or a laminate of the above conductive materials. For example, the conductor 205a may be titanium nitride.
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 205b.
  • tungsten may be used for the conductor 205b.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 .
  • Vth of the transistor 200 can be increased and off-state current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.
  • the electric resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electric resistivity. Also, the thickness of the insulator 216 is almost the same as that of the conductor 205 . Here, it is preferable to reduce the film thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205 . By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that diffusion of the impurities into the oxide 230 can be reduced. .
  • the conductor 205 is preferably provided larger than a region of the oxide 230 that does not overlap with the conductors 242a and 242b, as shown in FIG. 1A.
  • the conductor 205 preferably extends also in regions outside the ends of the oxides 230a and 230b in the channel width direction.
  • the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the oxide 230 in the channel width direction.
  • the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode electrically surround the channel formation region of the oxide 230 .
  • a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.
  • a transistor with an S-channel structure represents a transistor structure in which a channel formation region is electrically surrounded by electric fields of one and the other of a pair of gate electrodes.
  • the S-channel structure disclosed in this specification and the like has a structure different from the Fin type structure and the planar type structure.
  • the S-channel structure disclosed in this specification etc. can also be regarded as a type of Fin structure.
  • a Fin structure indicates a structure in which a gate electrode is arranged so as to cover at least two sides (specifically, two sides, three sides, four sides, etc.) of a channel.
  • the channel formation region can be electrically surrounded. Since the S-channel structure is a structure that electrically surrounds the channel forming region, it is substantially equivalent to a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. It can also be said.
  • the transistor 200 has an S-channel structure, a GAA structure, or an LGAA structure, a channel formation region formed at or near the interface between the oxide 230 and the gate insulator is the entire bulk of the oxide 230. can be done. Therefore, since the density of the current flowing through the transistor can be increased, it can be expected that the on-state current of the transistor or the field-effect mobility of the transistor can be increased.
  • the conductor 205 is extended to function as wiring.
  • a structure in which a conductor functioning as a wiring is provided under the conductor 205 may be employed.
  • one conductor 205 does not necessarily have to be provided for each transistor.
  • the conductor 205 may be shared by a plurality of transistors.
  • the conductor 205 has a structure in which the conductor 205a and the conductor 205b are stacked; however, the present invention is not limited to this.
  • the conductor 205 may be provided as a single layer or a laminated structure of three or more layers.
  • the insulator 222 and the insulator 224 function as gate insulators.
  • the insulator 222 preferably has a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
  • hydrogen for example, at least one of hydrogen atoms and hydrogen molecules
  • oxygen eg, at least one of oxygen atoms and oxygen molecules
  • the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230 .
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • these insulators may be stacked with silicon oxide, silicon oxynitride, or silicon nitride.
  • the insulator 222 may be a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • thinning of gate insulators may cause problems such as leakage current.
  • a high-k material for an insulator that functions as a gate insulator it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a substance with a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr)TiO 3 (BST) may be used in some cases.
  • silicon oxide, silicon oxynitride, or the like may be used as appropriate.
  • the heat treatment may be performed at, for example, 100° C. to 600° C., more preferably 350° C. to 550° C.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide 230 to reduce oxygen vacancies.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen after the heat treatment is performed in a nitrogen gas or inert gas atmosphere. good.
  • heat treatment may be continuously performed in a nitrogen gas or inert gas atmosphere.
  • oxide 230 when the oxide 230 is subjected to oxygenation treatment, oxygen vacancies in the oxide 230 can be repaired with supplied oxygen. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230, so that the hydrogen can be removed as H 2 O (dehydrated). Accordingly, hydrogen remaining in the oxide 230 can be suppressed from being recombined with oxygen vacancies to form VOH .
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used.
  • the insulator 224 may be formed in an island shape so as to overlap with the oxide 230a. In this case, the insulator 275 is in contact with the side surface of the insulator 224 and the top surface of the insulator 222 .
  • an island shape indicates a state in which two or more layers using the same material formed in the same step are physically separated.
  • a conductor 242a and a conductor 242b are provided in contact with the top surface of the oxide 230b.
  • the conductors 242a and 242b function as the source and drain electrodes of the transistor 200, respectively.
  • Examples of the conductor 242 include nitride containing tantalum, nitride containing titanium, nitride containing molybdenum, nitride containing tungsten, nitride containing tantalum and aluminum, It is preferable to use a nitride or the like containing titanium and aluminum. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even after absorbing oxygen.
  • hydrogen contained in the oxide 230b and the like might diffuse into the conductor 242a or the conductor 242b.
  • hydrogen contained in the oxide 230b or the like easily diffuses into the conductor 242a or the conductor 242b, and the diffused hydrogen 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b or the like might be absorbed by the conductor 242a or the conductor 242b.
  • the conductor 242 without the curved surface, the cross-sectional area of the conductor 242 in the cross section in the channel width direction as shown in FIG. 1D can be increased. Accordingly, the conductivity of the conductor 242 can be increased, and the on current of the transistor 200 can be increased.
  • the sheet resistance of the oxide 230b in a region overlapping with the conductor 242a (the conductor 242b) is reduced.
  • the carrier concentration may increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a (the conductor 242b) can be reduced in a self-aligning manner.
  • the conductors 242a and 242b are preferably formed using a conductive film having compressive stress.
  • a strain expanding in the direction of tension (hereinafter sometimes referred to as tensile strain) can be formed in the regions 230ba and 230bb.
  • the compressive stress of the conductor 242a is the stress that tends to relax the compressed shape of the conductor 242a, and is the stress that has a vector in the direction from the center to the end of the conductor 242a. The same applies to the compressive stress of the conductor 242b.
  • the magnitude of the compressive stress of the conductor 242a is, for example, 500 MPa or more, preferably 1000 MPa or more, more preferably 1500 MPa or more, and even more preferably 2000 MPa or more. Note that the magnitude of the stress of the conductor 242a may be determined by measuring the stress of a sample obtained by forming a conductive film used for the conductor 242a over a substrate. The same applies to the magnitude of the compressive stress that the conductor 242b has.
  • Strains are formed in the regions 230ba and 230bb by the action of the compressive stresses of the conductors 242a and 242b.
  • the strain is a strain (tensile strain) expanded in the direction of tension by the action of the compressive stress of the conductors 242a and 242b.
  • the strain corresponds to stretching of the CAAC structure in a direction perpendicular to the c-axis.
  • oxygen vacancies are likely to be formed in the strain.
  • VOH since hydrogen is likely to be incorporated into the strain, VOH is likely to be formed. Therefore, in the strain, oxygen vacancies and VOH are likely to be formed, and these tend to have a stable structure.
  • the regions 230ba and 230bb become stable n-type regions with high carrier concentrations.
  • the present invention is not limited to this.
  • a similar strain may form in oxide 230a.
  • the conductors 242a and 242b are conductors containing tantalum or titanium and nitrogen.
  • the conductor 242 has a two-layer structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a conductor 242b1 and a conductor 242b1 on the conductor 242b1.
  • a two-layer structure including the conductor 242b2 may be used.
  • the conductor 242a1 and the conductor 242b1 are arranged on the side in contact with the oxide 230b.
  • the conductor 242a1 and the conductor 242b1 may be collectively referred to as the lower layer of the conductor 242. Further, the conductor 242a2 and the conductor 242b2 may be collectively referred to as an upper layer of the conductor 242 in some cases.
  • the lower layers of the conductor 242 are preferably made of a conductive material that is resistant to oxidation. Accordingly, it is possible to prevent the lower layer of the conductor 242 from being oxidized and the conductivity of the conductor 242 from decreasing. Note that the lower layer of the conductor 242 may have a property of easily absorbing (releasing) hydrogen. As a result, hydrogen in the oxide 230 diffuses into the lower layer of the conductor 242, so that the hydrogen concentration in the oxide 230 can be reduced. Therefore, the transistor 200 can have stable electrical characteristics.
  • the lower layer of the conductor 242 preferably has a large compressive stress as described above, and preferably has a larger compressive stress than the upper layer of the conductor 242 .
  • the regions 230ba and 230bb in contact with the lower layer of the conductor 242 can be made stable n-type regions with high carrier concentration.
  • the upper layers of the conductor 242 (the conductor 242a2 and the conductor 242b2) preferably have higher conductivity than the lower layers of the conductor 242 (the conductor 242a1 and the conductor 242b1).
  • the thickness of the upper layer of the conductor 242 may be larger than the thickness of the lower layer of the conductor 242 .
  • at least part of the upper layer of the conductor 242 may have a region with higher conductivity than the lower layer of the conductor 242 .
  • the upper layer of the conductor 242 is preferably made of a conductive material with a lower resistivity than the lower layer of the conductor 242 . Accordingly, a semiconductor device in which wiring delay is suppressed can be manufactured.
  • the upper layer of the conductor 242 may have the property of easily absorbing hydrogen. As a result, hydrogen absorbed in the lower layer of the conductor 242 diffuses into the upper layer of the conductor 242, so that the concentration of hydrogen in the oxide 230 can be further reduced. Therefore, the transistor 200 can have stable electrical characteristics.
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 are preferably made of conductive materials having the same constituent elements and different chemical compositions.
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 can be continuously formed without being exposed to the atmospheric environment.
  • impurities or moisture from the atmospheric environment can be prevented from adhering to the surface of the lower layer of the conductor 242, and the vicinity of the interface between the lower layer and the upper layer of the conductor 242 can be prevented. can be kept clean.
  • a nitride containing tantalum with a high nitrogen to tantalum atomic ratio is used for the lower layer of the conductor 242
  • a tantalum containing nitride with a low nitrogen to tantalum atomic ratio is used for the upper layer of the conductor 242 .
  • the lower layer of the conductor 242 tantalum with an atomic ratio of nitrogen to tantalum of 1.0 to 2.0, preferably 1.1 to 1.8, more preferably 1.2 to 1.5
  • the upper layer of the conductor 242 has an atomic ratio of nitrogen to tantalum of 0.3 to 1.5, preferably 0.5 to 1.3, more preferably 0.6 to 1.0. of tantalum-containing nitride is used.
  • the oxidation of the nitride containing tantalum can be suppressed.
  • the oxidation resistance of the nitride containing tantalum can be enhanced.
  • diffusion of oxygen into the nitride containing tantalum can be suppressed. Therefore, it is preferable to use a nitride containing tantalum, which has a high atomic ratio of nitrogen to tantalum, for the lower layer of the conductor 242 . This can prevent the formation of an oxide layer between the lower layer of the conductor 242 and the oxide 230 or reduce the thickness of the oxide layer.
  • a nitride containing tantalum by lowering the atomic ratio of nitrogen to tantalum, the resistivity of the nitride can be lowered. Therefore, it is preferable to use a nitride containing tantalum, which has a low atomic ratio of nitrogen to tantalum, for the top layer of the conductor 242 . Accordingly, a semiconductor device in which wiring delay is suppressed can be manufactured.
  • the concentrations of tantalum and nitrogen detected in each layer are not limited to stepwise changes in each layer, but are continuously changed in the region between the upper layer and the lower layer ( (also called gradation). That is, the closer the region of the conductor 242 to the oxide 230, the higher the atomic ratio of nitrogen to tantalum. Therefore, the atomic ratio of nitrogen to tantalum in the region below conductor 242 is preferably higher than the atomic ratio of nitrogen to tantalum in the region above conductor 242 .
  • the film thickness of the lower layer of the conductor 242 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less. In this case, at least a part of the lower layer of the conductor 242 should have a region having the film thickness as described above. In addition, the film thickness of the lower layer of the conductor 242 is preferably thinner than the film thickness of the upper layer of the conductor 242 . In this case, at least a portion of the lower layer of the conductor 242 may have a region thinner than the upper layer of the conductor 242 .
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 use the same element and have different chemical compositions of the conductive materials
  • the lower layer of the conductor 242 is not limited to this. and the upper layer of the conductor 242 may be formed using different conductive materials.
  • the lower layer of the conductor 242 and the upper layer of the conductor 242 may have different one or more selected from constituent elements, chemical compositions, and film formation conditions.
  • a nitride containing tantalum eg, tantalum nitride
  • a nitride containing titanium eg, titanium nitride
  • titanium nitride titanium nitride
  • titanium nitride can be more conductive than tantalum nitride
  • the top layer of conductor 242 can be more conductive than the bottom layer of conductor 242 . Therefore, since the contact resistance with the conductor 240 provided in contact with the upper surface of the conductor 242 can be reduced, a semiconductor device in which wiring delay is suppressed can be manufactured.
  • the distance between the conductors 242a2 and 242b2 substantially matches the distance L1 of the width of the opening 258 in the channel length direction.
  • the distance L2 between the conductors 242a1 and 242b1 is preferably smaller than the distance L1 between the conductors 242a2 and 242b2. .
  • the thickness of the portion of the conductor 242 (the conductor 242a1 and the conductor 242b1) sandwiched between the portion of the conductor 260 and the oxide 230b is reduced. and the oxide 230b can be made closer. This can increase the effect of the electric field of the conductor 260 on the oxide 230b.
  • the insulator 252 is in contact with part of the side surface and top surface of the conductor 242a1, part of the side surface and top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. .
  • the side surfaces of the conductor 242a1 and the conductor 242b1 facing each other have flat surfaces from the top to the bottom, and the flat surfaces are approximately the top surface of the oxide 230b.
  • the invention is not so limited.
  • the upper end portions of the opposing sides of the conductor 242a1 and the conductor 242b1 may be curved.
  • the side surfaces are preferably substantially perpendicular to the top surface of the oxide 230b.
  • the insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b.
  • the insulator 271 preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 271 preferably has a function of suppressing diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing diffusion of oxygen more than the insulator 280 does.
  • an insulator such as silicon nitride, aluminum oxide, or magnesium oxide may be used.
  • the insulator 275 is provided so as to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271. Specifically, the insulator 275 has regions in contact with the side surfaces of the oxide 230b, the conductor 242a, and the conductor 242b.
  • the insulator 275 preferably has a function of trapping hydrogen and fixing hydrogen.
  • the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide.
  • the insulator 275 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.
  • the conductor 242 can be wrapped with an insulator having a barrier property against oxygen.
  • oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242 . Accordingly, oxygen contained in the insulator 224 and the insulator 280 can suppress direct oxidation of the conductor 242 to increase the resistivity and reduce the on-current.
  • the insulator 252 functions as part of the gate insulator.
  • a barrier insulating film against oxygen is preferably used.
  • any of the insulators that can be used for the insulator 282 may be used.
  • an insulator containing oxides of one or both of aluminum and hafnium is preferably used.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used.
  • aluminum oxide is used as the insulator 252 .
  • the insulator 252 is an insulator containing at least oxygen and aluminum.
  • the insulator 252 is provided in contact with the top and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222, as shown in FIG. 1C. That is, regions of the oxides 230a and 230b, and the insulator 224 overlapping with the conductor 260 are covered with the insulator 252 in the cross section in the channel width direction.
  • the insulator 252 having a barrier property against oxygen can block oxygen from being released from the oxides 230a and 230b when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxides 230a and 230b can be reduced. Thereby, oxygen vacancies and VOH formed in the region 230bc can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
  • the insulator 280, the insulator 250, and the like contain an excessive amount of oxygen, excessive supply of the oxygen to the oxides 230a and 230b can be suppressed. Therefore, excessive oxidation of the regions 230ba and 230bb through the region 230bc can be suppressed from lowering the on current of the transistor 200 or lowering the field effect mobility.
  • the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280, respectively.
  • the insulator 252 is also in contact with part of the upper surface of the conductor 242 . Accordingly, the formation of an oxide film on part of the top surface and the side surfaces of the conductor 242 due to oxidation of the top surface and the side surfaces of the conductor 242 can be reduced. Accordingly, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.
  • the thickness of the insulator 252 is preferably thin.
  • the insulator 252 has a thickness of 0.1 nm to 5.0 nm, preferably 0.5 nm to 3.0 nm, more preferably 1.0 nm to less than 3.0 nm. In this case, at least part of the insulator 252 may have a region with the thickness as described above. Further, the thickness of the insulator 252 is preferably thinner than the thickness of the insulator 250 . In this case, at least part of the insulator 252 may have a region thinner than the insulator 250 .
  • the ALD method includes a thermal ALD (thermal ALD) method in which a precursor and a reactant react with only thermal energy, a PEALD (plasma enhanced ALD) method using a plasma-excited reactant, and the like.
  • thermal ALD thermal ALD
  • PEALD plasma enhanced ALD
  • film formation can be performed at a lower temperature by using plasma, which is preferable in some cases.
  • the ALD method can deposit atoms layer by layer, it is possible to deposit ultra-thin films, to deposit structures with high aspect ratios, to deposit films with few defects such as pinholes, and to improve coverage. There are effects such as excellent film formation and low temperature film formation. Therefore, the insulator 252 can be formed with a thin film thickness as described above with good coverage over the side surfaces of the opening formed in the insulator 280 and the like, the side ends of the conductor 242, and the like.
  • a film formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods.
  • quantification of impurities secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), or Auger electron spectroscopy (AES: Auger Electron Spectroscopy) can be performed using
  • the region 230bc can be formed. Oxygen vacancies and VOH that are formed can be reduced, and excessive oxidation of the regions 230ba and 230bb can be suppressed in some cases. In such a case, the structure without the insulator 252 can simplify the manufacturing process of the semiconductor device and improve productivity.
  • the insulator 250 functions as part of the gate insulator. Insulator 250 is preferably placed in contact with the top surface of insulator 252 .
  • the insulator 250 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.
  • the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen.
  • the thickness of the insulator 250 is preferably from 0.5 nm to 20 nm, more preferably from 0.5 nm to 15 nm.
  • the thickness of the insulator 250 is preferably 0.5 nm or more and 10 nm or less, more preferably 0.5 nm or more and 5 nm or less. is more preferred.
  • the insulator 250 may have at least a portion of the region with the film thickness as described above.
  • the insulator 250 may have a two-layer laminated structure of an insulator 250a and an insulator 250b on the insulator 250a.
  • the lower insulator 250a is formed using an insulator through which oxygen easily permeates
  • the upper insulator 250b is formed using an insulator through which oxygen diffuses.
  • the insulator 250a is preferably formed using the material that can be used for the insulator 250
  • the insulator 250b is preferably an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used.
  • hafnium oxide is used for the insulator 250b.
  • the insulator 250b is an insulator containing at least oxygen and hafnium.
  • the thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, more preferably 1.0 nm to 3.0 nm. In this case, at least a part of the insulator 250b may have a region with the thickness as described above.
  • an insulating material that is a high-k material with a high dielectric constant may be used for the insulator 250b.
  • the gate insulator has a stacked structure of the insulators 250a and 250b, the stacked structure can be stable against heat and have a high relative dielectric constant. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness of the gate insulator. Also, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced. Therefore, the withstand voltage of the insulator 250 can be increased.
  • EOT equivalent oxide thickness
  • the insulator 254 functions as part of the gate insulator.
  • a barrier insulating film against hydrogen is preferably used as the insulator 254 . Accordingly, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the insulator 250 and the oxide 230b.
  • an insulator that can be used for the insulator 283 described above may be used.
  • silicon nitride deposited by a PEALD method may be used as the insulator 254 .
  • the insulator 254 is an insulator containing at least nitrogen and silicon.
  • the insulator 254 may further have a barrier property against oxygen. Accordingly, diffusion of oxygen contained in the insulator 250 to the conductor 260 can be suppressed.
  • the thickness of the insulator 254 is preferably thin.
  • the insulator 254 has a thickness of 0.1 nm to 5.0 nm, preferably 0.5 nm to 3.0 nm, more preferably 1.0 nm to 3.0 nm. In this case, at least part of the insulator 254 may have a region with the thickness as described above. Further, the thickness of the insulator 254 is preferably thinner than the thickness of the insulator 250 . In this case, at least part of the insulator 254 may have a region thinner than the insulator 250 .
  • the insulator 250 has a two-layer structure as illustrated in FIG. 2B
  • an insulator such as hafnium oxide which has a function of suppressing permeation of impurities such as hydrogen and oxygen, such as hafnium oxide
  • the insulator 250b can also have the function of the insulator 254 .
  • the structure without the insulator 254 can simplify the manufacturing process of the semiconductor device and improve productivity.
  • a conductor 260 functions as a first gate electrode of the transistor 200 .
  • the conductor 260 preferably has a conductor 260a and a conductor 260b disposed over the conductor 260a.
  • conductor 260a is preferably arranged to wrap the bottom and side surfaces of conductor 260b.
  • the top surface of conductor 260 is substantially aligned with the top surface of insulator 250 .
  • the conductor 260 has a two-layer structure of conductors 260a and 260b, but may have a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a preferably uses a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
  • a conductive material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductor 260a has a function of suppressing the diffusion of oxygen
  • oxygen contained in the insulator 250 can suppress oxidation of the conductor 260b and a decrease in conductivity.
  • the conductive material having a function of suppressing diffusion of oxygen titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.
  • the conductor 260 is formed so as to fill the opening 258 provided extending in the channel width direction, and the conductor 260 is also provided extending in the channel width direction. Accordingly, when a plurality of transistors 200 are provided, the conductor 260 can also function as a wiring. In this case, along with the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are also provided to extend.
  • the conductor 260 since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity.
  • the conductor 260b can use a conductive material whose main component is tungsten, copper, or aluminum. Further, the conductor 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.
  • the conductor 260 is formed in a self-aligned manner so as to fill the opening 258 formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductors 242a and 242b without being aligned.
  • the height of the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap with each other is based on the bottom surface of the insulator 222 in the channel width direction of the transistor 200.
  • the height is preferably less than the height of the bottom surface of oxide 230b.
  • the conductor 260 functioning as a gate electrode covers the side surface and top surface of the channel formation region of the oxide 230b with the insulator 250 or the like interposed therebetween. Easier to work on the whole. Therefore, the on current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.
  • the insulator 280 is provided on the insulator 275, and openings are formed in regions where the insulator 250 and the conductor 260 are provided. Also, the upper surface of the insulator 280 may be flattened.
  • the insulator 280 functioning as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.
  • the insulator 280 is preferably provided using a material similar to that of the insulator 216, for example.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a material such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies is preferable because a region containing oxygen released by heating can be easily formed.
  • the insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 280 .
  • impurities such as water and hydrogen
  • an oxide containing silicon such as silicon oxide or silicon oxynitride may be used as appropriate for the insulator 280 .
  • the insulator 282 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses permeation of oxygen.
  • an insulator such as a metal oxide having an amorphous structure such as aluminum oxide may be used. In this case, the insulator 282 is an insulator containing at least oxygen and aluminum.
  • the insulator 282 having a function of trapping impurities such as hydrogen in contact with the insulator 280 in a region sandwiched between the insulator 212 and the insulator 283, hydrogen and the like contained in the insulator 280 and the like are provided. of impurities can be captured, and the amount of hydrogen in the region can be made constant.
  • the insulator 282 it is preferable to form an aluminum oxide film by a sputtering method, and it is more preferable to form an aluminum oxide film by a pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas.
  • a pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • RF (Radio Frequency) power may be applied to the substrate.
  • the amount of oxygen injected into layers below the insulator 282 can be controlled by the amount of RF power applied to the substrate.
  • the smaller the RF power the smaller the amount of oxygen injected into a layer below the insulator 282, and the oxygen amount is likely to be saturated even if the thickness of the insulator 282 is thin. Also, the amount of oxygen injected into the layer below the insulator 282 increases as the RF power increases.
  • RF power is, for example, 0 W/cm 2 or more and 1.86 W/cm 2 or less.
  • the amount of oxygen suitable for the characteristics of the transistor can be changed and implanted depending on the RF power when the insulator 282 is formed. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be implanted.
  • the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • 1A to 1D and the like show a structure in which the insulator 282 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers may be used.
  • the insulator 282 may have a laminated structure of two layers.
  • the upper and lower layers of insulator 282 may be formed of the same material by different methods.
  • the RF power applied to the substrate when forming the lower layer of the insulator 282 and the the RF power applied to the substrate when depositing the upper layer of the insulator 282 is preferably different, and the RF power applied to the substrate when depositing the lower layer of the insulator 282 is different from the RF power applied to the substrate when depositing the upper layer of the insulator 282. It is more preferably lower than the RF power applied to the substrate during film formation.
  • the lower layer of the insulator 282 is deposited with RF power applied to the substrate of 0 W/cm 2 or more and 0.62 W/cm 2 or less, and the RF power of the upper layer of the insulator 282 applied to the substrate is 1.0 W/cm 2 or more.
  • a film is formed at 86 W/cm 2 or less.
  • the lower layer of the insulator 282 is deposited with an RF power of 0 W/cm 2 applied to the substrate, and the upper layer of the insulator 282 is deposited with an RF power of 0.31 W/cm 2 applied to the substrate. do.
  • the insulator 282 can have an amorphous structure and the amount of oxygen supplied to the insulator 280 can be adjusted.
  • the RF power applied to the substrate when forming the lower layer of the insulator 282 may be higher than the RF power applied to the substrate when forming the upper layer of the insulator 282 .
  • the lower layer of the insulator 282 is deposited with RF power applied to the substrate of 1.86 W/cm 2 or less
  • the upper layer of the insulator 282 is deposited with the RF power applied to the substrate of 0 W/cm 2 or more.
  • a film is formed at 62 W/cm 2 or less.
  • the lower layer of the insulator 282 is deposited with an RF power of 1.86 W/cm 2 applied to the substrate, and the upper layer of the insulator 282 is deposited with an RF power of 0.62 W/cm 2 applied to the substrate. form a film.
  • the amount of oxygen supplied to the insulator 280 can be increased.
  • the thickness of the lower layer of the insulator 282 is 1 nm to 20 nm, preferably 1.5 nm to 15 nm, more preferably 2 nm to 10 nm, further preferably 3 nm to 8 nm.
  • the lower layer of the insulator 282 can have an amorphous structure regardless of RF power.
  • the upper layer of the insulator 282 tends to have an amorphous structure, and the insulator 282 can have an amorphous structure.
  • the lower layer of the insulator 282 and the upper layer of the insulator 282 have a laminated structure made of the same material, but the present invention is not limited to this.
  • the lower layer of the insulator 282 and the upper layer of the insulator 282 may be laminated structures made of different materials.
  • Insulator 283 is in contact with a portion of the top surface of insulator 214, the side surface of insulator 216, the side surface of insulator 222, the side surface of insulator 275, the side surface of insulator 280, and the side and top surface of insulator 282, respectively. .
  • the insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen into the insulator 280 from above. Insulator 283 is placed over insulator 282 .
  • a nitride containing silicon such as silicon nitride or silicon nitride oxide is preferably used.
  • silicon nitride deposited by a sputtering method may be used as the insulator 283 .
  • a silicon nitride film with high density can be formed.
  • silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method.
  • An insulator 241 is provided in contact with the inner wall of the opening of the insulator 280 , the insulator 282 , the insulator 283 , and the insulator 285 , and the conductor 240 is provided in contact with the side surface of the insulator 241 .
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 240 .
  • the conductor 240 may have a laminated structure.
  • the conductor 240 can have a structure in which the first conductor is provided in contact with the side surface of the insulator 241 and the second conductor is provided inside.
  • the first conductor provided near the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271 includes:
  • a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used.
  • the conductive material having a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or stacked layers.
  • impurities such as water and hydrogen contained in a layer above the insulator 283 can be prevented from entering the oxide 230 through the conductor 240 .
  • the transistor 200 shows the structure in which the first conductor and the second conductor are stacked as the conductor 240
  • the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.
  • the height of the top surface of the conductor 240 may be higher than the height of the top surface of the insulator 285 in the region overlapping with the conductor 246 .
  • a barrier insulating film that can be used for the insulator 275 or the like may be used as the insulator 241 .
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used as the insulator 241 . Since the insulator 241 is provided in contact with the insulator 283 , the insulator 282 , and the insulator 271 , impurities such as water and hydrogen contained in the insulator 280 and the like are prevented from entering the oxide 230 through the conductor 240 . can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen.
  • oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240 .
  • the first insulator such as the insulator 280 in contact with the inner wall of the opening and the second insulator inside the insulator 280 serve as a barrier insulating film against oxygen.
  • a barrier insulating film against hydrogen are preferably used in combination.
  • aluminum oxide deposited by the ALD method may be used as the first insulator, and silicon nitride deposited by the PEALD method may be used as the second insulator.
  • oxidization of the conductor 240 can be suppressed, and moreover, entry of hydrogen into the conductor 240 can be reduced.
  • the transistor 200 shows a structure in which the insulator 241 is formed by stacking the first insulator and the second insulator, the present invention is not limited to this.
  • the insulator 241 may be provided as a single layer or a stacked structure of three or more layers.
  • an ordinal number may be assigned in order of formation for distinction.
  • a conductor 246 functioning as wiring may be arranged in contact with the upper surface of the conductor 240 .
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 246 .
  • the conductor 246 may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials. Note that the conductor 246 may be formed so as to be embedded in an opening provided in the insulator.
  • the capacitor 100 has insulators 152 , 150 , 154 , conductors 160 a , and 160 b arranged in openings 158 provided in insulators 280 , 275 , and 271 .
  • Insulator 150 is provided over insulator 152
  • insulator 154 is provided over insulator 150
  • conductor 160a is provided over insulator 154
  • conductor 160b is provided over conductor 160a. Note that in this specification and the like, the conductor 160a and the conductor 160b may be collectively referred to as the conductor 160 in some cases.
  • the insulator 152, the insulator 150, the insulator 154, the conductor 160a, and the conductor 160b that constitute the capacitor 100 correspond to the insulators 252, 250, and 160b that constitute the transistor 200. It can be formed using the same material and the same process as the body 254, the conductors 260a, and the conductors 260b. Therefore, the insulator 152 preferably contains the same insulating material as the insulator 252, and the description of the insulator 252 can be referred to for details.
  • the insulator 150 preferably contains the same insulating material as the insulator 250, and the description of the insulator 250 can be referred to for details.
  • the insulator 154 preferably contains the same insulating material as the insulator 254, and the description of the insulator 254 can be referred to for details.
  • the conductor 160a preferably contains the same conductive material as the conductor 260a, and the description of the conductor 260a can be referred to for details.
  • the conductor 160b preferably contains the same conductive material as the conductor 260b, and the description of the conductor 260b can be referred to for details.
  • Insulator 152, insulator 150, insulator 154, conductor 160a, and conductor 160b are formed using the same material and in the same process as insulator 252, insulator 250, insulator 254, conductor 260a, and conductor 260b. By forming it, the number of steps in manufacturing a semiconductor device can be reduced.
  • the insulator 150 can also have a laminated structure. Insulators that include oxides of one or both of aluminum and hafnium, which can be used for insulator 250b, function as high-k materials. By using such a high-k material, the capacitance of the capacitor 100 can be sufficiently secured even when the insulators 152, 150, and 154 are thick. By increasing the thickness of the insulator 152, the insulator 150, and the insulator 154, leakage current generated between the conductor 242b and the conductor 160 can be suppressed.
  • the opening 158 is provided in the insulator 280, the insulator 271 and the insulator 275 so as to reach the conductor 242b and the insulator 222. That is, it can be said that the opening 158 has a region overlapping with the conductor 242b. In addition, it can be said that the insulator 275 has an opening that overlaps with the opening 158 of the insulator 280 .
  • a region where the conductor 160 in the opening 158 and the conductor 242b intersect functions as the capacitive element 100. As shown in FIG. This region overlaps with oxide 230 b that functions as transistor 200 . That is, the capacitor 100 can be provided without excessively increasing the area occupied by the transistor 200 . As a result, miniaturization or high integration of the semiconductor device can be achieved. For example, when the semiconductor device according to one embodiment of the present invention is used as a memory cell of a memory device, memory capacity per unit area can be increased.
  • the opening 158 has the insulator 222 as the bottom surface and the insulators 280, 275, and 271 as the side surfaces.
  • 230 and the conductor 242 can be regarded as a shape in which a part of the structure is protruded. Note that, unlike the opening 258, the top surface of the oxide 230b is not exposed in the opening 158 because the top surface of the oxide 230b is covered with the conductor 242b.
  • an insulator 152 is provided in contact with the bottom surface and inner walls of the opening 158 .
  • the insulator 152 includes a top surface of the insulator 222, side surfaces of the insulator 224, side surfaces of the oxide 230a, side surfaces of the oxide 230b, part of the top surface and side surfaces of the conductor 242b, side surfaces of the insulator 271b, and side surfaces of the insulator 271b. 275 as well as the insulator 280 side.
  • the insulator 150 is provided in contact with the top surface of the insulator 152
  • the insulator 154 is provided in contact with the top surface of the insulator 150
  • the conductor 160 is provided in contact with the top surface of the insulator 154 . is provided. Therefore, an insulator 152 , an insulator 150 , an insulator 154 , and a conductor 160 are provided to cover the conductor 242 b partially protruding into the opening 158 .
  • Conductors 160 are provided facing each other with insulators 152, 150, and 154 interposed therebetween. Accordingly, since the capacitive element 100 can be formed on the three surfaces of the conductor 242b, the capacitance per unit area of the capacitive element 100 can be increased. Therefore, miniaturization or high integration of the semiconductor device can be achieved.
  • the conductor 160 is formed to fill an opening 158 extending in the channel width direction of the transistor 200, and the conductor 160 is also provided extending in the channel width direction of the transistor 200. there is Accordingly, when a plurality of transistors 200 and capacitors 100 are provided, the conductor 160 can also function as a wiring. In this case, along with the conductor 160, the insulator 152, the insulator 150, and the insulator 154 are also provided to extend.
  • an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example.
  • insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates.
  • Semiconductor substrates include, for example, semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
  • SOI Silicon On Insulator
  • Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.
  • Insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. oxynitrides with silicon, or nitrides with silicon and hafnium.
  • Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and an empty silicon oxide. There are silicon oxide with pores, resin, and the like.
  • insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in stacks.
  • insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • An insulator that functions as a gate insulator preferably has a region containing oxygen that is released by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from among the above, an alloy containing the above-described metal elements as a component, or an alloy or the like in which the above-described metal elements are combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred. Also, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even after absorbing oxygen.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used.
  • a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined.
  • a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.
  • a stacked-layer structure in which the above-described material containing the metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.
  • a conductive material containing the metal element and nitrogen described above may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may also be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • a metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the oxide 230 .
  • Metal oxides applicable to the oxide 230 according to the present invention are described below.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.
  • the metal oxide is an In-M-Zn oxide having indium, the element M and zinc.
  • the element M is aluminum, gallium, yttrium, or tin.
  • Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
  • the element M there are cases where a plurality of the above elements may be combined.
  • the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) is preferably used for a semiconductor layer of a transistor.
  • an oxide containing indium (In), aluminum (Al), and zinc (Zn) also referred to as IAZO
  • IAZO indium (In), aluminum (Al), gallium (Ga), and zinc
  • IAGZO or IGAZO oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) may be used for the semiconductor layer.
  • nitrogen-containing metal oxides may also be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may also be referred to as a metal oxynitride.
  • oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) is sometimes called an In--Ga--Zn oxide.
  • Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal. (poly crystal) and the like.
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum.
  • XRD X-ray diffraction
  • it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement.
  • GIXD Gram-Incidence XRD
  • the GIXD method is also called a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement may be simply referred to as the XRD spectrum.
  • the shape of the peak of the XRD spectrum is almost bilaterally symmetrical.
  • the shape of the peak of the XRD spectrum is left-right asymmetric.
  • the asymmetric shape of the peaks in the XRD spectra demonstrates the presence of crystals in the film or substrate. In other words, the film or substrate cannot be said to be in an amorphous state unless the shape of the peaks in the XRD spectrum is symmetrical.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nano beam electron diffraction pattern) observed by nano beam electron diffraction (NBED).
  • a diffraction pattern also referred to as a nano beam electron diffraction pattern
  • NBED nano beam electron diffraction
  • a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state.
  • a spot-like pattern is observed instead of a halo. For this reason, it is presumed that it cannot be concluded that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state, neither single crystal nor polycrystal, nor amorphous state, and is in an amorphous state. be done.
  • oxide semiconductors may be classified differently from the above when their structures are focused. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor that includes a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the formation surface of the CAAC-OS film, or the normal direction to the surface of the CAAC-OS film.
  • a crystalline region is a region having periodicity in atomic arrangement. If the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement.
  • CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and has no obvious orientation in the ab plane direction.
  • each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystalline region is less than 10 nm.
  • the maximum diameter of the crystal region may be about several tens of nanometers.
  • the CAAC-OS includes a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (
  • In layer a layer containing indium (In) and oxygen
  • Ga gallium
  • Zn zinc
  • oxygen oxygen
  • it tends to have a layered crystal structure (also referred to as a layered structure) in which (Ga, Zn) layers are laminated.
  • the (Ga, Zn) layer may contain indium.
  • the In layer may contain gallium.
  • the In layer may contain zinc.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM (Transmission Electron Microscope) image.
  • a plurality of bright points are observed in the electron beam diffraction pattern of the CAAC-OS film.
  • a certain spot and another spot are observed at point-symmetrical positions with respect to the spot of the incident electron beam that has passed through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not always a regular hexagon and may be a non-regular hexagon. Moreover, the distortion may have a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, no clear crystal grain boundary can be observed even near the strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal atoms. it is conceivable that.
  • a crystal structure in which clear grain boundaries are confirmed is called a polycrystal.
  • a grain boundary becomes a recombination center, traps carriers, and is highly likely to cause a decrease in on-current of a transistor, a decrease in field-effect mobility, and the like. Therefore, a CAAC-OS in which no clear grain boundaries are observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
  • a structure containing Zn is preferable for forming a CAAC-OS.
  • In--Zn oxide and In--Ga--Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is less likely to occur in CAAC-OS.
  • CAAC-OS since the crystallinity of an oxide semiconductor may be deteriorated due to contamination of impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS is resistant to heat and has high reliability.
  • CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for a transistor including a metal oxide in a channel formation region (sometimes referred to as an OS transistor), the degree of freedom in the manufacturing process can be increased.
  • nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has minute crystals.
  • the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also called a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.
  • an nc-OS film is subjected to structural analysis using an XRD apparatus, out-of-plane XRD measurement using ⁇ /2 ⁇ scanning does not detect a peak indicating crystallinity.
  • an nc-OS film is subjected to electron beam diffraction (also referred to as selected area electron beam diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is obtained. Observed.
  • an electron beam diffraction pattern is obtained in which a plurality of spots are observed within a ring-shaped area centered on the spot.
  • An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.
  • An a-like OS has void or low density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. In addition, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
  • CAC-OS relates to material composition.
  • CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called mosaic or patch.
  • CAC-OS is a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). is called). That is, CAC-OS is a composite metal oxide in which the first region and the second region are mixed.
  • the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In--Ga--Zn oxide are denoted by [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region whose main component is indium oxide, indium zinc oxide, or the like.
  • the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Also, the second region can be rephrased as a region containing Ga as a main component.
  • a clear boundary between the first region and the second region may not be observed.
  • the CAC-OS in the In—Ga—Zn oxide means a region containing Ga as a main component and a region containing In as a main component in a material structure containing In, Ga, Zn, and O. Each region is a mosaic, and refers to a configuration in which these regions exist randomly. Therefore, CAC-OS is presumed to have a structure in which metal elements are unevenly distributed.
  • the CAC-OS can be formed, for example, by sputtering under the condition that the substrate is not heated.
  • an inert gas typically argon
  • oxygen gas oxygen gas
  • nitrogen gas may be used as the film forming gas. good.
  • the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is preferably as low as possible.
  • the flow ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is 0% or more and less than 30%, preferably 0% or more and 10% or less.
  • an EDX mapping obtained using energy dispersive X-ray spectroscopy shows that a region containing In as a main component It can be confirmed that the (first region) and the region (second region) containing Ga as the main component are unevenly distributed and have a mixed structure.
  • the first region is a region with higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is developed. Therefore, by distributing the first region in the form of a cloud in the metal oxide, a high field effect mobility ( ⁇ ) can be realized.
  • the second region is a region with higher insulation than the first region.
  • the leakage current can be suppressed by distributing the second region in the metal oxide.
  • CAC-OS when used for a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementarily to provide a switching function (on/off). functions) can be given to the CAC-OS.
  • a part of the material has a conductive function
  • a part of the material has an insulating function
  • the whole material has a semiconductor function.
  • CAC-OS is most suitable for various semiconductor devices including display devices.
  • Oxide semiconductors have a variety of structures, each with different characteristics.
  • An oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. may
  • an oxide semiconductor with low carrier concentration is preferably used for a transistor.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm ⁇ 3 or less, preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less . 3 or less, more preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor whose channel formation region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
  • the impurities in the oxide semiconductor refer to, for example, substances other than the main components of the oxide semiconductor. For example, an element whose concentration is less than 0.1 atomic percent can be said to be an impurity.
  • the concentration of silicon or carbon in the oxide semiconductor is 2 ⁇ 10 atoms/cm or less, preferably 2 ⁇ 10 17 atoms/cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms/cm 3 , preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less. , more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • the oxide semiconductor reacts with oxygen that bonds to a metal atom to form water, which may cause oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated.
  • part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, hydrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the hydrogen concentration in the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably 5 ⁇ 10 18 atoms/cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • Semiconductor materials that can be used for oxide 230 are not limited to the metal oxides described above.
  • a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used as the oxide 230 .
  • a layered substance that functions as a semiconductor as the semiconductor material it is preferable to use a layered substance that functions as a semiconductor as the semiconductor material.
  • a layered substance is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds such as van der Waals forces that are weaker than covalent or ionic bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Layered substances include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds that contain chalcogens.
  • Chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • the oxide 230 it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor.
  • a transition metal chalcogenide that functions as a semiconductor.
  • Specific examples of transition metal chalcogenides applicable as the oxide 230 include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ).
  • tungsten sulfide typically WS 2
  • tungsten selenide typically WSe 2
  • tungsten tellurium typically WTe 2
  • hafnium sulfide typically HfS 2
  • hafnium selenide typically HfSe 2
  • zirconium sulfide typically ZrS 2
  • zirconium selenide typically ZrSe 2
  • a in each figure shows a top view.
  • B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in A in each figure, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in A in each figure, and is also a cross-sectional view of the transistor 200 in the channel width direction.
  • D in each figure is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in A of each figure, which is also a cross-sectional view of the capacitor 100 in the channel width direction.
  • some elements are omitted for clarity of the drawing.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. etc. can be used as appropriate for film formation.
  • Sputtering methods include an RF sputtering method using a high-frequency power source as a power source for sputtering, a DC sputtering method using a DC power source, and a pulse DC sputtering method in which the voltage applied to the electrodes is changed in pulses.
  • the RF sputtering method is mainly used for forming an insulating film
  • the DC sputtering method is mainly used for forming a metal conductive film.
  • the pulse DC sputtering method is mainly used when forming a film of a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.
  • the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. Furthermore, it can be divided into a metal CVD (MCVD) method and an organic metal CVD (MOCVD) method depending on the raw material gas used.
  • PECVD plasma CVD
  • TCVD thermal CVD
  • Photo CVD photo CVD
  • MCVD metal CVD
  • MOCVD organic metal CVD
  • the plasma CVD method can obtain high-quality films at relatively low temperatures.
  • the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed.
  • wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device.
  • a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased.
  • the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the ALD method a thermal ALD method in which the precursor and the reactant react with only thermal energy, a PEALD method using a plasma-excited reactant, or the like can be used.
  • the CVD method and ALD method are different from the sputtering method, in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.
  • a film of any composition can be deposited depending on the flow rate ratio of the raw material gases.
  • the CVD method it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of source gases while forming a film.
  • the time required for film formation is reduced compared to film formation using a plurality of film formation chambers, as the time required for transportation or pressure adjustment is not required. can do. Therefore, productivity of semiconductor devices can be improved in some cases.
  • a film of any composition can be formed by simultaneously introducing different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 5A to 5D).
  • the insulator 212 is preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 212 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the film formation of the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
  • silicon nitride is deposited as the insulator 212 by a pulse DC sputtering method using a silicon target in an atmosphere containing nitrogen gas.
  • a pulse DC sputtering method generation of particles due to arcing on the target surface can be suppressed, so that the film thickness distribution can be made more uniform.
  • the rise and fall of the discharge can be steeper than the high-frequency voltage. As a result, power can be supplied to the electrodes more efficiently, and the sputtering rate and film quality can be improved.
  • an insulator such as silicon nitride By using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, diffusion of impurities such as water and hydrogen contained in a layer below the insulator 212 can be suppressed.
  • an insulator such as silicon nitride through which copper is difficult to permeate as the insulator 212 even if a metal such as copper that is easily diffused is used as a conductor in a layer (not shown) below the insulator 212, the metal does not easily pass through. Upward diffusion through the insulator 212 can be suppressed.
  • an insulator 214 is deposited over the insulator 212 (see FIGS. 5A to 5D).
  • the insulator 214 is preferably deposited by a sputtering method.
  • the hydrogen concentration in the insulator 214 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the film formation of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
  • aluminum oxide is deposited as the insulator 214 by a pulse DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas.
  • the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • RF power may now be applied to the substrate.
  • the amount of oxygen injected into layers below insulator 214 can be controlled by the amount of RF power applied to the substrate.
  • the RF power is 0 W/cm 2 or more and 1.86 W/cm 2 or less.
  • the amount of oxygen suitable for the characteristics of the transistor can be changed and implanted according to the RF power when the insulator 214 is formed. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be implanted.
  • the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • the insulator 214 it is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping and fixing hydrogen. Accordingly, hydrogen contained in the insulator 216 or the like can be captured or fixed, and diffusion of the hydrogen to the oxide 230 can be prevented.
  • a metal oxide having an amorphous structure such as aluminum oxide
  • aluminum oxide having an amorphous structure aluminum oxide having an amorphous structure as the insulator 214 because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor 200 and the semiconductor device with favorable characteristics and high reliability can be manufactured.
  • an insulator 216 is deposited on the insulator 214 .
  • the insulator 216 is preferably deposited by a sputtering method.
  • the hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the film formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
  • a silicon oxide film is formed as the insulator 216 by a pulse DC sputtering method using a silicon target in an atmosphere containing oxygen gas.
  • the pulse DC sputtering method the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • the insulators 212, 214, and 216 are preferably formed continuously without being exposed to the atmosphere.
  • a multi-chamber film deposition apparatus may be used.
  • the insulator 212, the insulator 214, and the insulator 216 are formed with reduced hydrogen in the films, and the entry of hydrogen into the films between the film formation steps can be reduced. can be done.
  • Openings include, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. Wet etching may be used to form the openings, but dry etching is preferable for fine processing.
  • the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214 .
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as a dry etching apparatus.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency voltage having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency voltages having different frequencies may be applied to parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • a dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus.
  • ICP inductively coupled plasma
  • the conductive film to be the conductor 205a preferably contains a conductor having a function of suppressing permeation of oxygen.
  • a conductor having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of a conductor having a function of suppressing permeation of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used.
  • a conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a titanium nitride film is formed as a conductive film to be the conductor 205a.
  • a metal nitride as a lower layer of the conductor 205b, oxidation of the conductor 205b by the insulator 216 or the like can be suppressed.
  • the metal can be prevented from diffusing out of the conductor 205a.
  • a conductive film to be the conductor 205b is formed.
  • a conductive film to be the conductor 205b tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used.
  • the conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, tungsten is deposited as the conductive film to be the conductor 205b.
  • CMP treatment is performed to remove part of the conductive film that will be the conductor 205a and the conductive film that will be the conductor 205b, thereby exposing the insulator 216 (see FIGS. 5A to 5D). As a result, conductors 205a and 205b remain only in the openings. Note that part of the insulator 216 is removed by the CMP treatment in some cases.
  • an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 6A to 6D).
  • an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited.
  • the insulator containing oxides of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • hafnium-zirconium oxide is preferably used.
  • Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, diffusion of hydrogen and water contained in structures provided around the transistor 200 into the transistor 200 through the insulator 222 is suppressed. , the generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the film formation of the insulator 222 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 222 is formed using hafnium oxide by an ALD method.
  • the heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas may be about 20%.
  • heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
  • the heat treatment after the insulator 222 is formed, treatment is performed at a temperature of 400° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1. Impurities such as water and hydrogen contained in the insulator 222 can be removed by the heat treatment. In the case where an oxide containing hafnium is used as the insulator 222, the insulator 222 may be partly crystallized by the heat treatment. Further, the heat treatment can be performed at a timing such as after the insulator 224 is formed.
  • an insulating film 224A is formed on the insulator 222 (see FIGS. 6A to 6D).
  • the insulating film 224A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulating film 224A by a sputtering method.
  • the hydrogen concentration in the insulating film 224A can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Since the insulating film 224A will be in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • an oxide film 230A and an oxide film 230B are formed in order on the insulating film 224A (see FIGS. 6A to 6D).
  • the oxide films 230A and 230B are preferably formed continuously without being exposed to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B. can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are preferably formed by using the ALD method because films with uniform thickness can be formed even in trenches or openings with a large aspect ratio.
  • the use of the PEALD method is preferable because the oxide films 230A and 230B can be formed at a lower temperature than the thermal ALD method.
  • the sputtering method is used to form the oxide films 230A and 230B.
  • the oxide film 230A and the oxide film 230B are formed by sputtering
  • oxygen or a mixed gas of oxygen and noble gas is used as the sputtering gas.
  • the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased.
  • the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used.
  • part of the oxygen contained in the sputtering gas may be supplied to the insulator 224 when forming the oxide film 230A. Therefore, the percentage of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B is formed by a sputtering method, if the percentage of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, oxygen-excess oxidation occurs. A material semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited to this.
  • an oxygen-deficient oxide semiconductor is formed by setting the oxygen content in the sputtering gas to 1% to 30%, preferably 5% to 20%. be.
  • a transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility.
  • the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
  • a film is formed using Note that each oxide film may be formed in accordance with the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and the atomic ratio.
  • the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably formed by a sputtering method without being exposed to the air.
  • a multi-chamber film deposition apparatus may be used.
  • the insulating film 224A, the oxide film 230A, and the oxide film 230B can be prevented from being mixed with hydrogen between the film formation steps.
  • the heat treatment may be performed within a temperature range in which the oxide films 230A and 230B are not polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas may be about 20%.
  • heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
  • the heat treatment is performed at a temperature of 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • Impurities such as carbon, water, and hydrogen in the oxide films 230A and 230B can be reduced by such heat treatment including oxygen gas.
  • the crystallinity of the oxide film 230B can be improved, and a denser structure can be obtained.
  • the crystal regions in the oxide films 230A and 230B can be increased, and the in-plane variation of the crystal regions in the oxide films 230A and 230B can be reduced. Therefore, in-plane variations in electrical characteristics of the transistor 200 can be reduced.
  • hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222.
  • hydrogen in insulator 216 , insulating film 224 A, oxide film 230 A, and oxide film 230 B diffuses into insulator 222 . Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentrations in the insulator 216, the insulating film 224A, the oxide films 230A, and the oxide films 230B decrease.
  • the insulating film 224A functions as a gate insulator of the transistor 200, and the oxide films 230A and 230B function as channel formation regions of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide films 230A, and the oxide films 230B with reduced hydrogen concentration is preferable because it has high reliability.
  • a conductive film 242A is formed on the oxide film 230B (see FIGS. 6A to 6D).
  • the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 242A may be formed using tantalum nitride by a sputtering method.
  • heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure to continuously form the conductive film 242A without exposure to the air.
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.
  • an insulating film 271A is formed on the conductive film 242A (see FIGS. 6A to 6D).
  • the insulating film 271A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 271A is preferably an insulating film having a function of suppressing permeation of oxygen.
  • an aluminum oxide film or a silicon nitride film may be formed by a sputtering method.
  • a silicon nitride film and a silicon oxide film over the silicon nitride film may be formed by sputtering as the insulating film 271A.
  • the conductive film 242A and the insulating film 271A are preferably formed by a sputtering method without being exposed to the air.
  • a multi-chamber film deposition apparatus may be used. Accordingly, the conductive film 242A and the insulating film 271A can be formed with reduced hydrogen in the films, and further, entry of hydrogen into the films between film formation steps can be reduced. Further, in the case of providing a hard mask over the insulating film 271A, a film to be the hard mask may be formed continuously without being exposed to the atmosphere.
  • the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into an island shape by a lithography method, so that the insulator 224, the oxide 230a, the oxide 230b, and the conductive film 224A are formed.
  • a layer 242B and an insulating layer 271B are formed (see FIGS. 7A-7D).
  • the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B are formed so as to overlap with the conductor 205 at least partially.
  • a dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for fine processing.
  • the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be processed under different
  • the resist is first exposed through a mask.
  • the exposed regions are then removed or left behind using a developer to form a resist mask.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching treatment through the resist mask.
  • a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.
  • a hard mask made of an insulator or conductor may be used under the resist mask.
  • an insulating film or a conductive film that serves as a hard mask material is formed over the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • the etching of the conductive film 242A or the like may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the conductive film 242A or the like.
  • the insulating layer 271B is used as a hard mask.
  • the conductive layer 242B does not have curved surfaces between the side surfaces and the top surface, as shown in FIGS. 7B to 7D.
  • the conductors 242a and 242b shown in FIGS. 1B and 1D have angular ends where the side surface and the top surface intersect. Since the end portion where the side surface and the top surface of the conductor 242 intersect is angular, the cross-sectional area of the conductor 242 is larger than when the end portion has a curved surface. Accordingly, the resistance of the conductor 242 is reduced, so that the on current of the transistor 200 can be increased.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface.
  • the angle formed by the inclined side surface and the substrate surface (hereinafter sometimes referred to as taper angle) is preferably less than 90°.
  • the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°.
  • the structure is not limited to the above, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be substantially perpendicular to the top surface of the insulator 222.
  • the area can be reduced and the density can be increased.
  • byproducts generated in the above etching step are formed in layers on side surfaces of the insulator 224, the oxides 230a and 230b, the conductive layer 242B, and the insulating layer 271B in some cases.
  • the layered byproduct is formed between the insulator 224 , the oxide 230 a , the oxide 230 b , the conductive layer 242 B, the insulating layer 271 B, and the insulator 275 . Therefore, the layered byproduct formed in contact with the top surface of the insulator 222 is preferably removed.
  • an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 8A to 8D).
  • insulator 275 is preferably in close contact with the top surface of insulator 222 and the side surface of insulator 224 .
  • the insulator 275 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • An insulating film having a function of suppressing permeation of oxygen is preferably used as the insulator 275 .
  • silicon nitride may be deposited by ALD.
  • aluminum oxide is deposited by a sputtering method, and silicon nitride is deposited thereover by a PEALD method.
  • the insulator 275 has such a stacked-layer structure, the function of suppressing diffusion of water, impurities such as hydrogen, and oxygen may be improved.
  • the oxides 230a, 230b, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have a function of suppressing diffusion of oxygen. Accordingly, direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B in a later step can be reduced.
  • an insulating film to be the insulator 280 is formed on the insulator 275 .
  • the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film may be formed by a sputtering method.
  • the insulator 280 containing excess oxygen can be formed.
  • the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Note that heat treatment may be performed before the insulating film is formed.
  • the heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air.
  • moisture and hydrogen adsorbed to the surface of the insulator 275 or the like are removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b and the insulator 224 are reduced. be able to.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the insulating film to be the insulator 280 is subjected to CMP treatment to form the insulator 280 with a flat upper surface (see FIGS. 8A to 8D).
  • CMP treatment to form the insulator 280 with a flat upper surface.
  • a silicon nitride film may be formed over the insulator 280 by a sputtering method, for example, and CMP treatment may be performed until the silicon nitride reaches the insulator 280 .
  • insulator 280 a portion of insulator 280, a portion of insulator 275, and a portion of insulator layer 271B are processed to form openings 258 and 158 that reach conductive layer 242B and insulator 222 (FIG. 9A). to FIG. 9D).
  • the sides of insulator 224, the sides of oxide 230a, the sides of oxide 230b, and the top and sides of conductive layer 242B are exposed in openings 258 and 158, respectively, as shown in FIGS. 9C and 9D.
  • Insulators 271a and 271b are also formed by forming the openings 258 .
  • the width of the opening 258 in the cross-sectional view in the channel length direction of the transistor is defined as the distance L1.
  • the opening 258 and the opening 158 are preferably configured to extend in the direction parallel to the straight line A3-A4 (transistor channel width direction).
  • the opening 258 and the opening 158 are preferably formed so as to overlap with the conductor 205 .
  • the sides of insulator 280, insulator 275, and insulator 271, which form the inner walls of opening 258 and opening 158, are generally vertical and preferably do not have a tapered shape. .
  • a dry etching method or a wet etching method can be used for processing part of the insulator 280, part of the insulator 275, and part of the insulating layer 271B. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280 may be processed by a dry etching method, and part of the insulator 275 and part of the insulating layer 271B may be processed by a wet etching method.
  • a mask layer 259 is formed covering the insulator 280 and the openings 158 (see FIGS. 10A to 10D).
  • Mask layer 259 has an opening 263 that overlaps a portion of opening 258 .
  • a resist may be used as the mask layer 259.
  • an organic coating film such as an SOG (Spin On Glass) film or an SOC (Spin On Carbon) film under the resist.
  • a hard mask made of an insulator or a conductor may be used under the resist.
  • the width of the opening 263 in the cross-sectional view in the channel length direction of the transistor is defined as the distance L2.
  • the distance L2 is shorter than the distance L1, and the opening 263 is formed inside the opening 258.
  • part of the lower surface of the mask layer 259 is in contact with the upper surface of the conductive layer 242B inside the opening 258 .
  • the width of the opening 263 is reflected in the distance between the conductors 242a and 242b, so the distance L2 is preferably minute.
  • the distance L2 is 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • a lithography method using short-wavelength light such as EUV light or an electron beam.
  • the opening 263 can be provided with a margin. This makes it possible to relatively easily form a channel with a fine structure.
  • Mask layer 259 is then used to remove portions of conductive layer 242B exposed from mask layer 259 to expose oxide 230b.
  • a conductor 242a and a conductor 242b can be formed (see FIGS. 11A to 11D).
  • a portion of the conductive layer 242B is preferably processed using anisotropic etching.
  • processing by dry etching is preferable because it is suitable for fine processing.
  • side surfaces of the conductors 242a and 242b facing each other can be formed so as to be substantially perpendicular to the top surface of the oxide 230b. can.
  • Such a structure can reduce the formation of so-called Loff regions between the regions 230ba and 230bc and between the regions 230bb and 230bc. Therefore, the frequency characteristics of the transistor 200 can be improved, and the operation speed of the semiconductor device according to one embodiment of the present invention can be improved.
  • the mask layer 259 may be removed after the conductors 242a and 242b are formed.
  • dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment can be performed to remove the mask.
  • Layer 259 can be removed.
  • the etching treatment may cause the impurities to adhere to or diffuse into the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, the side surfaces of the insulator 280, and the like. be.
  • a step of removing such impurities may be performed.
  • the dry etching may form a damaged region on the surface of the oxide 230b. Such damaged areas may be removed.
  • the impurities include components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in a member used in an apparatus used for forming the opening, It may be caused by components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.
  • impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, impurities such as aluminum and silicon are preferably removed from the surface of oxide 230b and its vicinity. Further, it is preferable that the concentration of the impurity is reduced.
  • the concentration of aluminum atoms on and near the surface of the oxide 230b may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, and 1.0 atomic % or less. Atom % or less is more preferable, and less than 0.3 atomic % is even more preferable.
  • the regions with low crystallinity of the oxide 230b are preferably reduced or removed.
  • the oxide 230b have a layered CAAC structure.
  • the conductor 242a or the conductor 242b and its vicinity function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this manner, even at the drain end portion, which significantly affects the drain breakdown voltage, the region with low crystallinity of the oxide 230b is removed and the CAAC structure is provided. can. In addition, reliability of the transistor 200 can be improved.
  • a cleaning process is performed to remove impurities adhered to the surface of the oxide 230b in the etching process.
  • a cleaning method there are wet cleaning using a cleaning solution (also referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate. Note that the cleaning process may deepen the groove.
  • Wet cleaning may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water, pure water, carbonated water, or the like.
  • aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water, pure water, carbonated water, or the like.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these washings may be appropriately combined.
  • an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid
  • an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water.
  • concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate depending on impurities to be removed, the configuration of the semiconductor device to be cleaned, and the like.
  • the ammonia concentration of the diluted ammonia water should be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
  • the concentration of hydrogen fluoride in the diluted hydrofluoric acid should be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or higher is preferably used for ultrasonic cleaning, and a frequency of 900 kHz or higher is more preferably used. By using the frequency, damage to the oxide 230b and the like can be reduced.
  • the above cleaning treatment may be performed multiple times, and the cleaning liquid may be changed for each cleaning treatment.
  • a treatment using diluted hydrofluoric acid or diluted ammonia water may be performed as the first cleaning treatment
  • a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
  • wet cleaning is performed using diluted ammonia water.
  • impurities attached to the surfaces of the oxides 230a and 230b or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.
  • a heat treatment may be performed after the above etching or after the above cleaning.
  • the heat treatment may be performed at 100° C. or higher and 450° C. or lower, preferably 350° C. or higher and 400° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxides 230a and 230b, and oxygen vacancies can be reduced. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved.
  • after heat treatment in an oxygen atmosphere heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the air.
  • the insulating film 252A is an insulating film that becomes the insulator 252 and the insulator 152 in a later step.
  • the insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 252A is preferably formed using an ALD method. As described above, the insulating film 252A is preferably formed with a thin film thickness, and it is necessary to reduce variations in film thickness.
  • the ALD method is a method of forming a film by alternately introducing a precursor and a reactant (for example, an oxidizing agent). Film thickness can be adjusted. Also, as shown in FIGS. 12B and 12C, the insulating film 252A needs to be deposited on the bottom and side surfaces of the opening 258 and the opening 158 with good coverage. In particular, in the opening 258, it is preferable to form a film with good coverage on the top surface and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Further, in the opening 158, it is preferable to form a film with good coverage on the side surface and the upper surface of the conductor 242b. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed with good coverage over the opening.
  • ozone (O 3 ), oxygen (O 2 ), water (H 2 O), or the like can be used as an oxidizing agent.
  • oxygen (O 2 ), or the like that does not contain hydrogen as an oxidant hydrogen that diffuses into the oxide 230b can be reduced.
  • the insulating film 252A is formed by thermal ALD using aluminum oxide.
  • the insulating film 250A is an insulating film that becomes the insulator 250 and the insulator 150 in a later step.
  • Heat treatment may be performed before the insulating film 250A is formed, or the heat treatment may be performed under reduced pressure and the insulating film 250A may be formed continuously without exposure to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed to the surface of the insulating film 252A or the like can be removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced.
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.
  • the insulating film 250A can be formed using a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 facing the oxide 230b through the thin insulator 252 in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • silicon oxynitride is deposited by PECVD as the insulating film 250A.
  • microwave treatment refers to treatment using an apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • Dotted lines shown in FIGS. 12B to 12D indicate microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals.
  • a microwave treatment apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • the frequency of the microwave processing device may be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz.
  • High-density oxygen radicals can be generated by using high-density plasma.
  • the power of the power source for applying microwaves in the microwave processing apparatus may be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less.
  • the microwave processing apparatus may have a power supply for applying RF to the substrate side. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
  • the above microwave treatment is preferably performed under reduced pressure, and the pressure should be 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less.
  • the treatment temperature may be 750°C or lower, preferably 500°C or lower, for example, about 250°C.
  • heat treatment may be continuously performed without exposure to the outside air.
  • the temperature may be 100° C. or higher and 750° C. or lower, preferably 300° C. or higher and 500° C. or lower.
  • the microwave treatment may be performed using oxygen gas and argon gas.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) should be greater than 0% and 100% or less.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) should be greater than 0% and 50% or less.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) should be 10% or more and 40% or less.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) should be 10% or more and 30% or less.
  • microwave treatment is performed in an oxygen-containing atmosphere to turn oxygen gas into plasma using microwaves or high frequencies such as RF. It can act on the region between 242a and conductor 242b.
  • the region 230bc can also be irradiated with microwaves or high frequencies such as RF. That is, microwaves, high frequencies such as RF, oxygen plasma, or the like can be applied to the region 230bc shown in FIG. 2A.
  • the V OH in region 230bc can be disrupted and hydrogen can be removed from region 230bc. That is, VOH contained in the region 230bc can be reduced.
  • oxygen vacancies and VOH in the region 230bc can be reduced, and the carrier concentration can be lowered.
  • oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 are supplied to the oxygen vacancies formed in the region 230bc, thereby further reducing the oxygen vacancies in the region 230bc and increasing the carrier concentration. can be lowered.
  • conductors 242a and 242b are provided on the regions 230ba and 230bb shown in FIG. 2A.
  • the conductor 242 preferably functions as a shielding film against the action of microwaves, high frequencies such as RF, oxygen plasma, and the like when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductor 242 preferably has a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
  • the conductors 242a and 242b block the effects of microwaves, high frequencies such as RF, oxygen plasma, and the like, so that these effects do not reach the regions 230ba and 230bb. do not have.
  • reduction of V OH and supply of an excessive amount of oxygen do not occur in the regions 230ba and 230bb due to the microwave treatment, so that a decrease in carrier concentration can be prevented.
  • An insulator 252 having a barrier property against oxygen is provided in contact with side surfaces of the conductors 242a and 242b. Accordingly, formation of an oxide film on the side surfaces of the conductors 242a and 242b due to microwave treatment can be suppressed.
  • the film quality of the insulator 252 and the insulator 250a can be improved, the reliability of the transistor 200 is improved.
  • oxygen vacancies and V OH can be selectively removed from the oxide semiconductor region 230bc to make the region 230bc i-type or substantially i-type. Furthermore, excessive supply of oxygen to the regions 230ba and 230bb functioning as a source region or a drain region can be suppressed, and conductivity can be maintained. As a result, variations in the electrical characteristics of the transistor 200 can be suppressed, and variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.
  • heat energy may be directly transmitted to the oxide 230b due to the electromagnetic interaction between the microwave and the molecules in the oxide 230b. This thermal energy may heat the oxide 230b.
  • Such heat treatment is sometimes called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. Further, when hydrogen is contained in the oxide 230b, it is conceivable that this thermal energy is transmitted to hydrogen in the oxide 230b and thus activated hydrogen is released from the oxide 230b.
  • the above microwave treatment may be performed after the insulating film 252A is formed.
  • the microwave treatment may be performed after the insulating film 252A is formed without performing the microwave treatment after the insulating film 250A is formed.
  • an insulating film to be the insulator 250b may be formed after the insulating film 250A is formed. At this time, an insulating film to be the insulator 250b is formed in the opening 258 and inside the opening 258.
  • the insulating film to be the insulator 250b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film to be the insulator 250b is preferably formed using an insulator having a function of suppressing diffusion of oxygen.
  • An insulating film to be the insulator 250 b can be provided using a material similar to that of the insulator 222 .
  • hafnium oxide may be deposited by thermal ALD as an insulating film to be the insulator 250b.
  • the above microwave treatment is preferably performed after the insulating film 250A is formed.
  • the microwave treatment may be performed after the insulating film to be the insulator 250b is formed without performing the microwave treatment after the insulating film 250A is formed.
  • heat treatment may be performed while maintaining the reduced pressure.
  • hydrogen in the insulating film 252A, the insulating film 250A, the insulating film to be the insulator 250b, the oxide 230b, and the oxide 230a can be efficiently removed.
  • part of the hydrogen may be gettered by the conductors 242 (the conductors 242a and 242b).
  • the step of performing the heat treatment may be repeated a plurality of times while the reduced pressure state is maintained.
  • the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.
  • microwave treatment that is, microwave annealing may serve as the heat treatment. When the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.
  • the insulating films 252A, 250A, and the insulating films to be the insulator 250b diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, in a post-process such as formation of a conductive film to be the conductor 260 or a post-treatment such as heat treatment, hydrogen, water, impurities, or the like diffuse into the oxide 230b, the oxide 230a, or the like through the insulator 252. can be suppressed.
  • the insulating film 254A is an insulating film that becomes the insulator 254 and the insulator 154 in a later step.
  • a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be used for forming the insulating film 254A.
  • the insulating film 254A is preferably formed using the ALD method similarly to the insulating film 252A. By using the ALD method, the insulating film 254A can be formed with a thin film thickness and good coverage. In this embodiment mode, silicon nitride is deposited by the PEALD method as the insulating film 254A.
  • a conductive film to be the conductors 260a and 160a, and a conductive film to be the conductors 260b and 160b are formed in this order.
  • the conductive films to be the conductors 260a and 160a and the conductive films to be the conductors 260b and 160b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. can.
  • a titanium nitride film is formed as a conductive film to be the conductors 260a and 160a by an ALD method
  • tungsten is formed by a CVD method as a conductive film to be the conductors 260b and 160b. form a film.
  • the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive films to be the conductors 260a and 160a, and the conductive films to be the conductors 260b and 160b are exposed, and the insulator 280 is exposed. Grind until smooth. That is, the portions of the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive films to be the conductors 260a and 160a, and the conductive films to be the conductors 260b and 160b exposed from the openings 258 and 158 are removed. Remove.
  • Body 150, insulator 154, and conductor 160 are formed (see FIGS. 14A-14D).
  • the insulator 252 is provided in contact with the inner walls and side surfaces of the opening 258 overlapping the oxide 230b.
  • Conductor 260 is arranged to fill opening 258 with insulator 252 , insulator 250 , and insulator 254 interposed therebetween.
  • transistor 200 is formed.
  • the insulator 152 is provided in contact with the inner walls and side surfaces of the opening 158 overlapping the conductor 242b.
  • Conductor 160 is arranged to fill opening 158 with insulator 152 , insulator 150 , and insulator 154 interposed therebetween.
  • the capacitive element 100 is formed.
  • the transistor 200 and the capacitor 100 can be manufactured in parallel in the same process.
  • insulators 252 and 152, insulators 250 and 150, insulators 254 and 154, conductors 260a and 160a, and conductors 260b and 160b are each the same. It can be formed using a material. Accordingly, the number of steps in manufacturing a semiconductor device including the transistor 200 and the capacitor 100 can be reduced.
  • heat treatment may be performed under the same conditions as the above heat treatment.
  • the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
  • the concentrations of moisture and hydrogen in the insulators 250 and 280 can be reduced.
  • the insulator 282 may be formed continuously without exposure to the air.
  • insulator 282 is formed over insulator 252, insulator 250, conductor 260, insulator 152, insulator 150, conductor 160, and insulator 280 (FIGS. 14A-14D). reference).
  • the insulator 282 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 282 is preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 282 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • aluminum oxide is deposited as the insulator 282 by a pulse DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas.
  • the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • the RF power applied to the substrate is 1.86 W/cm 2 or less. Preferably, it is 0 W/cm 2 or more and 0.62 W/cm 2 or less. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed.
  • the insulator 282 may be formed to have a two-layer structure.
  • the lower layer of the insulator 282 is deposited with an RF power of 0 W/cm 2 applied to the substrate, and the upper layer of the insulator 282 is deposited with an RF power of 0.62 W/cm 2 applied to the substrate. .
  • the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 while the insulator 280 is being formed.
  • the insulator 280 can contain excess oxygen.
  • the insulator 282 is preferably formed while heating the substrate.
  • an etching mask is formed over the insulator 282 by a lithography method, and the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216 are etched. is processed until the top surface of the insulator 214 is exposed (see FIGS. 15A to 15D).
  • wet etching may be used for the processing, use of dry etching is preferable for fine processing.
  • heat treatment may be performed.
  • the heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 350° C. or higher and 600° C. or lower.
  • the temperature of the heat treatment is preferably lower than the temperature of the heat treatment performed after forming the oxide film 230B.
  • the heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing the heat treatment, part of the oxygen added to the insulator 280 diffuses into the oxide 230 through the insulator 250 and the like.
  • the insulator 282 the insulator 280, the insulator 275, the insulator 222, and the insulator 216 are processed, so that the insulator 280 can be included in the insulator 280 from the side surface thereof. Oxygen and hydrogen bound to the oxygen can be released to the outside. Hydrogen combined with oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.
  • an insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230 in a region of the oxide 230 that overlaps with the conductor 260 .
  • Insulator 252 has a barrier property against oxygen and can reduce diffusion of an excessive amount of oxygen into oxide 230 .
  • Oxygen can thereby be supplied to the region 230bc and its vicinity so that an excessive amount of oxygen is not supplied. Accordingly, oxygen vacancies and VOH formed in the region 230bc can be reduced while suppressing oxidation of the side surfaces of the conductor 242 due to excess oxygen. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
  • the volume of the insulator 280 for one transistor 200 may become excessively small.
  • the amount of oxygen that diffuses into the oxide 230 is significantly reduced in the above heat treatment. If the oxide 230 is heated in contact with an oxide insulator (eg, the insulator 250 or the like) that does not contain enough oxygen, oxygen in the oxide 230 might be released.
  • the insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230 in a region of the oxide 230 overlapping with the conductor 260 . Since the insulator 252 has a barrier property against oxygen, release of oxygen from the oxide 230 can be reduced even in the above heat treatment. Thereby, oxygen vacancies and VOH formed in the region 230bc can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be improved.
  • a transistor having favorable electrical characteristics and favorable reliability can be formed regardless of whether the amount of oxygen supplied from the insulator 280 is large or small. can be done. Therefore, it is possible to provide a semiconductor device in which variations in electrical characteristics of the transistor 200 are suppressed within the substrate surface.
  • an insulator 283 is formed over the insulator 282 (see FIGS. 16A to 16D).
  • the insulator 283 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 283 is preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 283 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the insulator 283 may be multi-layered.
  • a silicon nitride film may be formed using a sputtering method, and a silicon nitride film may be formed over the silicon nitride film using an ALD method.
  • an insulating film to be the insulator 274 is formed on the insulator 283 .
  • the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulating film by a CVD method.
  • the insulating film to be the insulator 274 is polished by CMP treatment until the insulator 283 is exposed, thereby planarizing the upper surface of the insulating film and forming the insulator 274 (see FIGS. 16A to 16D). Part of the top surface of the insulator 283 may be removed by the CMP treatment.
  • an insulator 285 is formed over the insulator 274 and the insulator 283 (see FIGS. 17A to 17D).
  • the insulator 285 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 285 is preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 285 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • silicon oxide is deposited as the insulator 285 by a sputtering method.
  • openings are formed in the insulators 271, 275, 280, 282, 283, and 285 to reach the conductors 242a (see FIGS. 17A and 17B).
  • the formation of the opening may be performed using a lithography method.
  • the shape of the opening is circular when viewed from above, but the shape is not limited to this.
  • the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners when viewed from above.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 .
  • the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • the anisotropic etching of the insulating film that becomes the insulator 241 for example, a dry etching method or the like may be used.
  • a dry etching method or the like By providing the insulator 241 on the side wall of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240 to be formed next can be prevented.
  • impurities such as water and hydrogen contained in the insulator 280 and the like can be prevented from diffusing into the conductor 240 .
  • the conductive film preferably has a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
  • a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. can be used.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 240 with a flat top surface can be formed by leaving the conductive film only in the opening (see FIGS. 17A to 17D). Note that part of the top surface of the insulator 285 is removed by the CMP treatment in some cases.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 246 is processed by lithography to form the conductor 246 in contact with the upper surface of the conductor 240 .
  • part of the insulator 285 in a region where the conductor 246 and the insulator 285 do not overlap may be removed.
  • a semiconductor device including the transistor 200 illustrated in FIGS. 1A to 1D can be manufactured.
  • the capacitor 100 and the transistor 200 can be manufactured in the same process. Accordingly, the number of steps for manufacturing a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.
  • ⁇ Microwave processing device> A microwave processing apparatus that can be used in the above method for manufacturing a semiconductor device is described below.
  • FIG. 18 the configuration of a manufacturing apparatus in which impurities are less mixed when manufacturing a semiconductor device or the like will be described with reference to FIGS. 18 to 21.
  • FIG. 18 the configuration of a manufacturing apparatus in which impurities are less mixed when manufacturing a semiconductor device or the like will be described with reference to FIGS. 18 to 21.
  • FIG. 18 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700.
  • the manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning substrates, and an atmosphere-side substrate transfer chamber for transferring substrates from the atmosphere-side substrate supply chamber 2701 .
  • the atmospheric side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chamber 2706a. , chamber 2706b, chamber 2706c and chamber 2706d.
  • a gate valve GV is provided at the connecting portion of each chamber, and each chamber can be independently held in a vacuum state except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702 .
  • the atmosphere-side substrate transfer chamber 2702 is provided with a transfer robot 2763a
  • the transfer chamber 2704 is provided with a transfer robot 2763b. The substrate can be transported within the manufacturing apparatus 2700 by the transport robot 2763a and the transport robot 2763b.
  • the back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1 ⁇ 10 ⁇ 4 Pa or less, preferably 3 ⁇ 10 ⁇ 5 Pa or less, more preferably 1 ⁇ 10 ⁇ 5 Pa or less.
  • the partial pressure of gas molecules (atoms) having a mass-to-charge ratio (m/z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less. and more preferably 3 ⁇ 10 ⁇ 6 Pa or less.
  • the partial pressure of gas molecules (atoms) having an m/z of 28 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less, more preferably 3 ⁇ 10 ⁇ 5 Pa or less. ⁇ 10 ⁇ 6 Pa or less.
  • the partial pressure of gas molecules (atoms) with m/z of 44 in the transfer chamber 2704 and each chamber is, for example, 3 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 5 Pa or less, more preferably 3 ⁇ 10 ⁇ 5 Pa or less. ⁇ 10 ⁇ 6 Pa or less.
  • the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, or the like.
  • the transfer chamber 2704 and each chamber have a structure with little external or internal leakage.
  • the leak rate of the transfer chamber 2704 is 1 ⁇ 10 0 Pa/min or less, preferably 5 ⁇ 10 ⁇ 1 Pa/min or less.
  • the leak rate of each chamber is 1 ⁇ 10 ⁇ 1 Pa/min or less, preferably 5 ⁇ 10 ⁇ 2 Pa/min or less.
  • the leak rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass spectrometer, or the like. For example, it may be derived from the total pressure 10 minutes after the start of vacuuming with a vacuum pump such as a turbo-molecular pump and the total pressure 10 minutes after the valve is closed.
  • the total pressure after 10 minutes from the start of the evacuation may be an average value obtained by measuring the total pressure a plurality of times.
  • the leak rate depends on external and internal leaks.
  • An external leak is an inflow of gas from outside the vacuum system due to a minute hole, poor seal, or the like.
  • Internal leaks result from leaks from partitions such as valves in the vacuum system or from released gas from internal components. In order to keep the leak rate below the above numerical value, it is necessary to take measures against both external and internal leaks.
  • the transfer chamber 2704 and the opening/closing parts of each chamber may be sealed with metal gaskets.
  • Metal gaskets are preferably made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leaks.
  • passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like it is possible to suppress released gas containing impurities released from the metal gasket, thereby reducing internal leaks.
  • aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities is used as a member constituting the manufacturing apparatus 2700 .
  • an alloy containing iron, chromium, nickel, or the like may be coated with the aforementioned metal containing impurities and emitting less gas. Alloys containing iron, chromium, nickel, and the like are rigid, heat resistant, and workable.
  • the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the emitted gas can be reduced.
  • the members of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.
  • the members of the manufacturing apparatus 2700 are preferably made of metal as much as possible. It is advisable to thinly coat with chromium or the like.
  • the adsorbate existing in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 and each chamber because it is adsorbed on the inner wall or the like, but it is a cause of gas release when the transfer chamber 2704 and each chamber is evacuated. becomes. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation capacity to desorb as much as possible the adsorbate existing in the transfer chamber 2704 and each chamber and to evacuate them in advance.
  • the transfer chamber 2704 and each chamber may be baked in order to facilitate the desorption of the adsorbate. By baking, the desorption speed of the adsorbate can be increased by about ten times. Baking may be performed at 100° C.
  • the desorption speed of water and the like which is difficult to desorb only by exhausting, can be further increased.
  • the desorption speed of the adsorbate can be further increased.
  • an inert gas such as a heated noble gas, oxygen, or the like to increase the pressure in the transfer chamber 2704 and each chamber, and then evacuate the transfer chamber 2704 and each chamber again after a certain period of time.
  • an inert gas or oxygen having a temperature of 40° C. or more and 400° C. or less, preferably 50° C. or more and 200° C.
  • the pressure is preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less.
  • the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.
  • the chamber 2706b and the chamber 2706c are, for example, chambers capable of subjecting an object to be processed to microwave processing. Note that the chamber 2706b and the chamber 2706c are different only in the atmosphere when the microwave treatment is performed. Since other configurations are common, they will be collectively described below.
  • the chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812 and an exhaust port 2819. Further, outside the chambers 2706b and 2706c, etc., there are a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, and a waveguide 2807. , a matching box 2815 , a high frequency power supply 2816 , a vacuum pump 2817 and a valve 2818 are provided.
  • a high frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804 .
  • Mode converter 2805 is connected to slot antenna plate 2808 via waveguide 2807 .
  • Slot antenna plate 2808 is placed in contact with dielectric plate 2809 .
  • gas supply source 2801 is connected to mode converter 2805 via valve 2802 .
  • Gas is sent to chambers 2706b and 2706c by gas pipe 2806 passing through mode converter 2805, waveguide 2807 and dielectric plate 2809.
  • the vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c through the valve 2818 and the exhaust port 2819 .
  • the high-frequency power supply 2816 is connected to the substrate holder 2812 through the matching box 2815 .
  • the substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically chucking or mechanically chucking the substrate 2811 . It also functions as an electrode to which power is supplied from the high frequency power supply 2816 . It also has a heating mechanism 2813 inside and has a function of heating the substrate 2811 .
  • the vacuum pump 2817 for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbomolecular pump, or the like can be used. Also, in addition to the vacuum pump 2817, a cryotrap may be used. The use of a cryopump and a cryotrap is particularly preferable because water can be discharged efficiently.
  • the heating mechanism 2813 for example, a heating mechanism that heats using a resistance heating element or the like may be used.
  • a heating mechanism that heats by heat conduction or heat radiation from a medium such as heated gas may be used.
  • RTA Rapid Thermal Annealing
  • GRTA Gas Rapid Thermal Annealing
  • LRTA Low Rapid Thermal Annealing
  • GRTA performs heat treatment using high temperature gas.
  • An inert gas is used as the gas.
  • the gas supply source 2801 may be connected to the refiner via a mass flow controller. It is preferable to use a gas having a dew point of ⁇ 80° C. or lower, preferably ⁇ 100° C. or lower.
  • a gas having a dew point of ⁇ 80° C. or lower preferably ⁇ 100° C. or lower.
  • oxygen gas, nitrogen gas, and noble gas such as argon gas may be used.
  • dielectric plate 2809 for example, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), or the like may be used. Further, another protective layer may be formed on the surface of dielectric plate 2809 . As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like may be used. Since the dielectric plate 2809 will be exposed to a particularly high-density region of the high-density plasma 2810, which will be described later, damage can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.
  • the high-frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz.
  • a microwave generated by the high frequency generator 2803 is transmitted to the mode converter 2805 via the waveguide 2804 .
  • the microwave transmitted as TE mode is converted into TEM mode.
  • the microwave is transmitted to slot antenna plate 2808 via waveguide 2807 .
  • Slot antenna plate 2808 is provided with a plurality of slot holes, and microwaves pass through the slot holes and dielectric plate 2809 .
  • an electric field can be generated below the dielectric plate 2809 to generate high density plasma 2810 .
  • Ions and radicals according to the gas species supplied from the gas supply source 2801 are present in the high-density plasma 2810 . For example, there are oxygen radicals.
  • the ions and radicals generated by the high-density plasma 2810 can modify the film on the substrate 2811 .
  • the high-frequency power supply 2816 for example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz and 27.12 MHz may be used.
  • RF Radio Frequency
  • oxygen radical treatment using high-density plasma 2810 can be performed.
  • the chamber 2706a and the chamber 2706d are, for example, chambers capable of irradiating an object to be processed with electromagnetic waves.
  • the only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic waves. Since there are many common parts in other configurations, they will be collectively described below.
  • the chambers 2706 a and 2706 d have one or more lamps 2820 , substrate holders 2825 , gas inlets 2823 and exhaust ports 2830 . Also, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chambers 2706a and 2706d.
  • a gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822 .
  • Vacuum pump 2828 is connected to exhaust port 2830 through valve 2829 .
  • the lamp 2820 is arranged facing the substrate holder 2825 .
  • the substrate holder 2825 has the function of holding the substrate 2824 . Further, the substrate holder 2825 has a heating mechanism 2826 inside and has a function of heating the substrate 2824 .
  • a light source having a function of emitting electromagnetic waves such as visible light, ultraviolet light, or infrared light may be used.
  • a light source having a function of emitting an electromagnetic wave having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.
  • a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp may be used.
  • the electromagnetic waves radiated from the lamp 2820 can be partially or wholly absorbed by the substrate 2824 to modify the film or the like on the substrate 2824 .
  • defects can be created or reduced, or impurities can be removed. Note that if the substrate 2824 is heated while the substrate 2824 is heated, defects can be efficiently generated or reduced, or impurities can be removed.
  • electromagnetic waves radiated from the lamps 2820 may cause the substrate holder 2825 to generate heat to heat the substrate 2824 .
  • the heating mechanism 2826 may not be provided inside the substrate holder 2825 .
  • the vacuum pump 2828 refers to the description of the vacuum pump 2817.
  • the heating mechanism 2826 the description of the heating mechanism 2813 is referred to.
  • the gas supply source 2821 the description of the gas supply source 2801 is referred to.
  • the microwave processing device that can be used in this embodiment is not limited to the above.
  • a microwave processing apparatus 2900 shown in FIG. 21 can be used.
  • Microwave processing apparatus 2900 has quartz tube 2901 , exhaust port 2819 , gas supply source 2801 , valve 2802 , high frequency generator 2803 , waveguide 2804 , gas pipe 2806 , vacuum pump 2817 and valve 2818 .
  • the microwave processing apparatus 2900 also has a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901 . Further, the microwave processing apparatus 2900 may have heating means 2903 outside the quartz tube 2901 .
  • the microwave generated by the high-frequency generator 2803 is applied to the substrate provided inside the quartz tube 2901 through the waveguide 2804 .
  • a vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818 and can adjust the pressure inside the quartz tube 2901 .
  • a gas supply source 2801 is also connected to a gas pipe 2806 via a valve 2802 so that a desired gas can be introduced into the quartz pipe 2901 .
  • the heating means 2903 can heat the substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801 .
  • the microwave treatment apparatus 2900 heat treatment and microwave treatment can be performed on the substrate 2811 at the same time. Further, microwave treatment can be performed after the substrate 2811 is heated. Further, heat treatment can be performed after microwave treatment is performed on the substrate 2811 .
  • All of the substrates 2811_1 to 2811_n may be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates.
  • the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n ⁇ 1 may be processing substrates.
  • the substrates 2811_1, 2811_2, 2811_n ⁇ 1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n ⁇ 2 may be processing substrates.
  • the use of a dummy substrate is preferable because a plurality of substrates to be processed can be uniformly processed during microwave treatment or heat treatment, and variations among the substrates to be processed can be reduced.
  • placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because direct exposure of the processing substrate to microwaves can be suppressed.
  • FIG. 4A shows a top view of a semiconductor device.
  • FIG. 4B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line of A1-A2 shown in FIG. 4A.
  • FIG. 4C is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in FIG. 4A.
  • FIG. 4D is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in FIG. 4A.
  • the top view of FIG. 4A omits some elements for clarity of illustration.
  • the semiconductor devices shown in FIGS. 4A to 4D are modifications of the semiconductor devices shown in FIGS. 1A to 1D.
  • the semiconductor devices shown in FIGS. 4A to 4D are different from the semiconductor devices shown in FIGS. 1A to 1D in that the insulator 283 is in contact with part of the top surface of the insulator 212 .
  • Transistor 200 is thus disposed within the region encapsulated by insulator 283 and insulator 212 .
  • hydrogen contained outside the sealed region can be prevented from entering the sealed region.
  • 4A to 4D show a structure in which the insulator 212 and the insulator 283 are provided as single layers; however, the present invention is not limited to this.
  • each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.
  • a silicon nitride film is formed as a lower layer of the insulator 283 by a sputtering method, and a silicon nitride film is formed as an upper layer of the insulator 283 by an ALD method.
  • the hydrogen concentration in the lower layer of the insulator 282 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas.
  • a film formed by an ALD method with good coverage is used to block the overlapping portion of the pinhole or discontinuity. be able to.
  • the insulator 283 has a two-layer laminated structure, part of the top surface of the upper layer of the insulator 283 may be removed. Also, it may be difficult to clearly detect the boundary between the upper layer and the lower layer of the insulator 283 .
  • the conductor 205 may have a three-layer laminated structure of a conductor 205a, a conductor 205b, and a conductor 205c.
  • the conductor 205c is provided in contact with the upper surface of the conductor 205b.
  • a structure in which the side surface of the conductor 205c is in contact with the conductor 205a may be employed.
  • the upper surface of the conductor 205c and the uppermost portion of the conductor 205a may be substantially aligned.
  • the conductor 205c preferably uses a conductive material that has a function of reducing the diffusion of hydrogen.
  • the conductor 205b can be wrapped with the conductor 205a and the conductor 205c, so that impurities such as hydrogen contained in the conductor 205b diffuse into the oxide 230 through the insulators 216, 224, and the like. can prevent you from doing it.
  • a conductive material having a function of suppressing diffusion of oxygen for the conductors 205a and 205c, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity.
  • the insulator 271a and the insulator 271b may each have a two-layer laminated structure.
  • a lower layer of the insulator 271a and the insulator 271b preferably functions as a barrier insulating film against at least oxygen. Therefore, the lower layers of the insulators 271a and 271b preferably have a function of suppressing diffusion of oxygen. Accordingly, oxygen contained in the insulator 280 can be prevented from diffusing into the conductors 242a and 242b. Therefore, the oxygen contained in the insulator 280 can prevent the conductors 242a and 242b from being oxidized to increase the resistivity and reduce the on-current.
  • the upper layers of the insulators 271a and 271b function as protective layers for leaving the lower layers of the insulators 271a and 271b.
  • the insulating layer to be the lower layer of the insulators 271a and 271b is removed.
  • an insulating layer which is an upper layer of the insulators 271a and 271b is provided between the hard mask and an insulating layer which is a lower layer of the insulators 271a and 271b, whereby the insulators 271a and 271b are formed.
  • the underlying insulating layer can remain.
  • silicon oxide or the like is preferably used as an upper layer of the insulators 271a and 271b.
  • OS transistor such as the transistor 200 has little change in electrical characteristics due to radiation irradiation, that is, it has high resistance to radiation, so it can be suitably used in an environment where radiation may be incident.
  • OS transistors can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor included in a semiconductor device provided in a space shuttle, an artificial satellite, a space probe, or the like.
  • Radiation includes, for example, X-rays, neutron beams, and the like.
  • outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may include the thermosphere, the mesosphere, and the stratosphere.
  • the OS transistor can be used as a transistor that constitutes a semiconductor device provided in a nuclear power plant, a radioactive waste disposal site, or a working robot in a disposal site.
  • it can be suitably used for a transistor that constitutes a semiconductor device provided in a remote-controlled robot that is remotely controlled for dismantling nuclear reactor facilities, retrieving nuclear fuel or fuel debris, and conducting field surveys in spaces with a large amount of radioactive materials.
  • FIG. 22A shows a top view of the semiconductor device 500.
  • FIG. The x-axis shown in FIG. 22A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis.
  • 22B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 22A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 22C is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in FIG. 22A, and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted in the top view of FIG. 22A for clarity of illustration.
  • a semiconductor device 500 shown in FIGS. 22A to 22C is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • a semiconductor device 500 shown in FIGS. 22A to 22C differs from the semiconductor device shown in FIGS. 1A to 1D in that a sealing portion 265 is formed so as to surround a plurality of transistors 200 and capacitors 100.
  • FIG. 22A to 22C differs from the semiconductor device shown in FIGS. 1A to 1D in that a sealing portion 265 is formed so as to surround a plurality of transistors 200 and capacitors 100.
  • a semiconductor device 500 has a plurality of transistors 200, a plurality of capacitive elements 100, and a plurality of opening regions 400 arranged in a matrix.
  • a plurality of conductors 260 that function as gate electrodes of the transistor 200 are provided extending in the y-axis direction.
  • a plurality of conductors 160 functioning as upper electrodes of the capacitor 100 are provided extending in the y-axis direction.
  • Open region 400 is formed in a region that does not overlap oxide 230 , conductor 260 , and conductor 160 .
  • a sealing portion 265 is formed to surround the plurality of transistors 200 , the plurality of conductors 260 , the plurality of capacitor elements 100 , the plurality of conductors 160 , and the plurality of opening regions 400 .
  • the number, arrangement, and size of the transistor 200, the conductor 260, the capacitive element 100, the conductor 160, and the opening region 400 are not limited to the structure shown in FIG. It can be set as appropriate.
  • the encapsulant 265 surrounds the plurality of transistors 200, the plurality of capacitive elements 100, the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282.
  • insulator 283 is provided to cover insulator 216 , insulator 222 , insulator 275 , insulator 280 , and insulator 282 .
  • the insulator 283 is in contact with the upper surface of the insulator 214 .
  • An insulator 274 is provided between the insulator 283 and the insulator 285 over the sealing portion 265 .
  • the top surface of the insulator 274 is approximately level with the top surface of the insulator 283 .
  • an insulator similar to the insulator 280 can be used.
  • the plurality of transistors 200 and the plurality of capacitive elements 100 can be wrapped with the insulators 283 , 214 and 212 .
  • one or more of the insulator 283, the insulator 214, and the insulator 212 preferably function as barrier insulating films against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from entering the region of the sealing portion 265 .
  • the insulator 282 has openings in the opening regions 400 .
  • the insulator 280 may have a groove overlapping the opening of the insulator 282.
  • the depth of the groove of the insulator 280 should be at least as deep as the upper surface of the insulator 275 is exposed, and for example, it may be about 1/4 or more and 1/2 or less of the maximum film thickness of the insulator 280 .
  • the insulator 283 is in contact with the side surfaces of the insulator 282 , the side surfaces of the insulator 280 , and the top surface of the insulator 280 inside the opening region 400 .
  • the insulator 274 is partially formed so as to fill the recess formed in the insulator 283 within the opening region 400 .
  • the upper surface of the insulator 274 formed in the opening region 400 and the height of the uppermost surface of the insulator 283 may approximately match.
  • Heat treatment is performed in a state where the opening region 400 is formed and the insulator 280 is exposed from the opening of the insulator 282 , whereby oxygen contained in the insulator 280 is removed while oxygen is supplied to the oxide 230 . can be diffused out of the open area 400 .
  • sufficient oxygen is supplied from the insulator 280 containing oxygen which is released by heating to the region functioning as a channel formation region in the oxide semiconductor layer and the vicinity thereof, and an excessive amount of oxygen is removed. can be prevented from being supplied.
  • hydrogen contained in the insulator 280 can be combined with oxygen and released to the outside through the opening region 400 . Hydrogen combined with oxygen is released as water. Therefore, hydrogen contained in the insulator 280 can be reduced, and entry of hydrogen contained in the insulator 280 into the oxide 230 can be reduced.
  • the shape of the opening region 400 in top view is substantially rectangular, but the present invention is not limited to this.
  • the top view shape of the open area 400 may be a rectangle, an ellipse, a circle, a rhombus, or a combination thereof.
  • the area and arrangement intervals of the opening regions 400 can be appropriately set according to the design of the semiconductor device including the transistor 200 and the capacitive element 100 . For example, in a region where the density of the transistors 200 is low, the area of the opening regions 400 may be widened or the arrangement interval of the opening regions 400 may be narrowed. Further, for example, in a region where the density of the transistors 200 is high, the area of the opening regions 400 may be narrowed or the arrangement interval of the opening regions may be widened.
  • FIG. 23A is a top view of the semiconductor device 600.
  • FIG. A semiconductor device 600 includes a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b according to one embodiment of the present invention.
  • FIG. 23B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in FIG. 23A, and is also a cross-sectional view of the transistors 200a and 200b in the channel length direction. Note that some elements are omitted in the top view of FIG. 23A for clarity of illustration.
  • the insulator 224, the oxide 230a, the oxide 230b, the conductor 242c, the insulator 271c, the conductor 240, the insulator 241, and the conductor 246 are connected to the transistor 200a and the transistor 200b.
  • the semiconductor device 600 has a symmetrical configuration with the dashed-dotted line A3-A4 as the axis of symmetry.
  • the conductor 242c serves also as one of the source electrode and the drain electrode of the transistor 200a and one of the source electrode and the drain electrode of the transistor 200b.
  • an insulator 271c is provided over the conductor 242c.
  • a conductor 246 functioning as a wiring and a conductor 240 functioning as a plug are also shared by the transistors 200a and 200b. In this manner, two transistors and two capacitors share wirings, plugs, and the like, whereby the area occupied by one transistor element and one capacitor element can be reduced when viewed from above. . Therefore, a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a novel transistor can be provided according to one embodiment of the present invention.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with favorable frequency characteristics can be provided.
  • a semiconductor device with high operation speed can be provided.
  • a semiconductor device with little variation in transistor characteristics can be provided.
  • a semiconductor device with favorable electrical characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device with high field-effect mobility can be provided.
  • a semiconductor device with low power consumption can be provided.
  • FIG. 24 An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.
  • a semiconductor device illustrated in FIG. 24 is a memory device including a transistor using an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor.
  • the memory device includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor.
  • a semiconductor device of one embodiment of the present invention includes a transistor 200 and a capacitor 100 over a transistor 300 as illustrated in FIG. Note that the transistor 200 described in the above embodiment can be used as the transistor 200 . Further, as the capacitor 100, the capacitor 100 described in the above embodiment can be used.
  • a transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced. In addition, since the frequency characteristics of the transistor 200 are high as described in the above embodiment, reading from and writing to the memory device can be performed at high speed.
  • a wiring 1001 is electrically connected to the source of the transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300.
  • a wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the other of the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100 , and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100 .
  • the memory devices shown in FIG. 24 can form a memory array by arranging them in a matrix.
  • Transistor 300 is provided on substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 consisting of part of substrate 311, and a low region functioning as a source or drain region. It has a resistance region 314a and a low resistance region 314b. Transistor 300 can be either p-channel or n-channel.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN transistor because it utilizes the projections of the semiconductor substrate.
  • an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 illustrated in FIG. 24 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration or driving method.
  • a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures.
  • the wiring layer can be provided in a plurality of layers depending on the design.
  • a plurality of structures may be grouped together and given the same reference numerals.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as a wiring and a part of the conductor functions as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300 as interlayer films.
  • conductors 328, 330, and the like electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326, respectively. Note that the conductors 328 and 330 function as plugs or wirings.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape thereunder.
  • the top surface of the insulator 322 may be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330 .
  • an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.
  • a conductor 356 is formed over the insulators 350 , 352 , and 354 .
  • Conductor 356 functions as a plug or wiring.
  • the insulator 210 , the insulator 212 , the insulator 214 , and the insulator 216 are embedded with conductors 218 , conductors forming the transistor 200 (conductors 205 ), and the like. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the capacitor 100 or the transistor 300 .
  • an insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug.
  • the insulator 217 is provided in contact with inner walls of openings formed in the insulators 210 , 212 , 214 , and 216 . That is, the insulator 217 is provided between the conductor 218 and the insulators 210 , 212 , 214 , and 216 .
  • the conductor 205 can be formed in parallel with the conductor 218;
  • an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since insulator 217 is provided in contact with insulator 210 , insulator 212 , insulator 214 , and insulator 222 , impurities such as water or hydrogen from insulator 210 or insulator 216 are oxidized through conductor 218 . It is possible to suppress mixing into the object 230 .
  • silicon nitride is suitable because it has a high blocking property against hydrogen.
  • oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218 .
  • the insulator 217 can be formed by a method similar to that of the insulator 241 .
  • a PEALD method may be used to form a silicon nitride film, and anisotropic etching may be used to form an opening reaching the conductor 356 .
  • Insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
  • the material should be selected according to the function of the insulator.
  • the insulator 210, the insulator 352, the insulator 354, and the like have an insulator with a low dielectric constant.
  • the insulator preferably contains silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, resin, or the like.
  • the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. and resin.
  • silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained.
  • resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used for the insulators 214, 212, 350, and the like.
  • Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. , ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like are metal materials, alloy materials, metal nitride materials, metal oxide materials, or the like formed of any of the above materials.
  • conductive materials can be used in a single layer or in lamination. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
  • an insulator having an excess oxygen region is provided near the oxide semiconductor in some cases.
  • an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 241 may be provided between the insulators 224 and 280 containing excess oxygen and the conductor 240 . Since the insulator 241 is in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 are sealed with an insulator having a barrier property. can be done.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulator 241 .
  • silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used.
  • silicon nitride is preferable because it has a high blocking property against hydrogen.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can also be used.
  • the transistor 200 may be sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283 as described in the above embodiment. With such a structure, entry of hydrogen contained in the insulator 274 or the like into the insulator 280 or the like can be reduced.
  • the conductor 240 penetrates through the insulators 283 and 282, and the conductor 218 penetrates through the insulators 214 and 212.
  • the insulator 241 is in contact with the conductor 240.
  • An insulator 217 is provided in contact with the conductor 218 . Accordingly, hydrogen entering inside the insulators 212 , 214 , 282 , and 283 through the conductors 240 and 218 can be reduced.
  • the transistor 200 is sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like are removed from the outside. It is possible to reduce contamination from
  • a conductor 112 is provided on the conductor 240 .
  • the conductor 112 corresponds to the conductor 246 shown in FIG. 1B, for example. That is, the conductor 112 functions as wiring.
  • the conductor 112 has a single-layer structure in FIG. 24, it is not limited to this structure and may have a laminated structure of two or more layers. For example, between a conductor with a barrier property and a conductor with high conductivity, a conductor with a barrier property and a conductor with high adhesion to the conductor with high conductivity may be formed.
  • An insulator 130 is provided to cover the conductor 112 , and an insulator 146 is provided on the insulator 130 .
  • An insulator that can be used as the insulator 283 described in the above embodiment is preferably used as the insulator 130 .
  • an insulator that can be used for the insulators 210, 352, 354, and the like is preferably used.
  • dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) provided when taking out a plurality of semiconductor devices in the form of chips by dividing a large-area substrate into individual semiconductor elements will be described.
  • a dividing method for example, grooves (dicing lines) for dividing the semiconductor elements are first formed in the substrate, and then cut along the dicing lines to divide (divide) into a plurality of semiconductor devices.
  • the region where the insulator 283 and the insulator 214 are in contact overlaps the dicing line. That is, openings are formed in the insulators 282 , 280 , 275 , 224 , 222 , and 216 in the vicinity of the dicing line region provided at the outer edge of the memory cell having the plurality of transistors 200 . prepare.
  • the insulators 214 and 283 are in contact with each other in the openings provided in the insulators 282 , 280 , 275 , 224 , 222 , and 216 .
  • the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 may have openings.
  • the insulator 212 and the insulator 212 and the insulator 214 283 are in contact with each other.
  • the insulator 212 and the insulator 283 may be formed using the same material and the same method.
  • adhesion can be improved. For example, it is preferable to use silicon nitride.
  • the insulator 212 , the insulator 214 , the insulator 282 , and the insulator 283 can wrap the transistor 200 .
  • At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water; therefore, the semiconductor element described in this embodiment is formed.
  • this structure can prevent excess oxygen in the insulators 280 and 224 from diffusing to the outside.
  • excess oxygen in insulator 280 and insulator 224 is effectively supplied to the oxide in which the channel in transistor 200 is formed.
  • Oxygen vacancies in the oxide in which a channel is formed in the transistor 200 can be reduced by the oxygen.
  • the oxide in which the channel of the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, it is possible to suppress variations in the electrical characteristics of the transistor 200 and improve its reliability.
  • FIG. 25A shows a block diagram showing a configuration example of the storage device 50 according to one embodiment of the present invention.
  • a memory device 50 shown in FIG. 25A has a drive circuit 21 and a memory array 20 .
  • the memory array 20 has multiple memory cells 10 .
  • FIG. 25A shows an example in which a memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • rows and columns extend in directions orthogonal to each other.
  • the X direction (direction along the X axis) is defined as “row”
  • the Y direction (direction along Y axis) is defined as “column”. It can also be called “line”.
  • the memory cell 10 in row 1, column 1 is indicated as memory cell 10[1,1], and the memory cell 10 in row m, column n is indicated as memory cell 10[m,n].
  • an arbitrary row may be referred to as i row.
  • j column when indicating an arbitrary column, it may be described as j column. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the memory cell 10 in the i-th row and the j-th column is indicated as the memory cell 10[i, j].
  • the memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction.
  • the wiring WL provided in the first line (first row) is indicated as the wiring WL[1]
  • the wiring WL provided in the m-th line (m-th row) is indicated as the wiring WL[m].
  • the wiring PL provided in the first line (first row) is indicated as a wiring PL[1]
  • the wiring PL provided in the m-th line (m-th row) is indicated as a wiring PL[m].
  • the wiring BL provided in the first line (first column) is referred to as the wiring BL[1]
  • the wiring BL provided in the nth line (nth column) is referred to as the wiring BL[n].
  • a plurality of memory cells 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • a plurality of memory cells 10 provided in the j-th column are electrically connected to a wiring BL in the j-th column (wiring BL[j]).
  • DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory) can be applied to the memory array 20 .
  • a DOSRAM is a RAM having 1T (transistor) and 1C (capacitor) type memory cells, and is a memory in which an access transistor is a transistor (hereinafter also referred to as an "OS transistor") having an oxide semiconductor in a channel formation region.
  • OS transistor a transistor having an oxide semiconductor in a channel formation region.
  • a DOSRAM can hold electric charge corresponding to data held in a capacitive element (capacitor) for a long time by turning off (non-conducting) an access transistor. Therefore, a DOSRAM can reduce the frequency of refresh operations compared to a DRAM composed of transistors having silicon in the channel formation region (hereinafter also referred to as "Si transistors"). As a result, low power consumption can be achieved.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling on/off (conducting state or non-conducting state) of an access transistor functioning as a switch.
  • the wiring PL has a function of transmitting a backgate potential to the backgate of the OS transistor, which is an access transistor, in addition to functioning as a constant potential line connected to the capacitor. Note that a wiring BGL (not shown) can be separately provided as a wiring for transmitting the back gate potential.
  • the drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41 , a control circuit 32 and a voltage generation circuit 33 .
  • each circuit, each signal and each voltage can be appropriately discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • the signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • the signal WDA is write data and the signal RDA is read data.
  • a signal PON1 and a signal PON2 are power gating control signals. The signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit having a function of controlling the overall operation of the storage device 50.
  • the control circuit logically operates the signal CE, the signal GW and the signal BW to determine the operation mode (for example, write operation, read operation) of the storage device 50 .
  • control circuit 32 generates a control signal for peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33 . For example, when an H level signal is applied to signal WAKE, signal CLK is input to voltage generation circuit 33, and voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing data to and reading data from the memory cell 10 .
  • the peripheral circuit 41 includes a row decoder 42 (Row Decoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (Column Driver), an input circuit 47 (Input Circuit), an output circuit 48 ( Output Circuit) and a sense amplifier 46 (Sense Amplifier).
  • the row decoder 42 and column decoder 44 have the function of decoding the signal ADDR.
  • Row decoder 42 is a circuit for specifying a row to be accessed
  • column decoder 44 is a circuit for specifying a column to be accessed.
  • Row driver 43 has a function of selecting line WL designated by row decoder 42 .
  • the column driver 45 has a function of writing data to the memory cells 10, a function of reading data from the memory cells 10, a function of holding the read data, and the like.
  • the input circuit 47 has a function of holding the signal WDA. Data held by the input circuit 47 is output to the column driver 45 . Output data of the input circuit 47 is data (Din) to be written to the memory cell 10 . Data (Dout) read from the memory cells 10 by the column driver 45 is output to the output circuit 48 .
  • the output circuit 48 has a function of holding Dout. Also, the output circuit 48 has a function of outputting Dout to the outside of the storage device 50 . Data output from the output circuit 48 is the signal RDA.
  • the PSW 22 has the function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW 23 has the function of controlling the supply of VHM to row driver 43 .
  • the high power supply voltage of the memory device 50 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to drive word lines to a high level and is higher than VDD.
  • the signal PON1 controls ON/OFF of the PSW22
  • the signal PON2 controls ON/OFF of the PSW23.
  • the number of power supply domains to which VDD is supplied is one, but it can be plural. In this case, a power switch may be provided for each power domain.
  • the memory array 20 can be provided over the driving circuit 21 .
  • the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and power consumption and signal delay can be reduced.
  • miniaturization of the storage device 50 can be realized.
  • the memory array 20 can be provided by stacking a plurality of layers of the memory array 20 on the drive circuit 21 . By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased.
  • FIG. 25B shows an example in which k layers (k is an integer of 2 or more) of memory arrays 20 are stacked on the drive circuit 21 .
  • the memory array 20 provided in the first layer is indicated as memory array 20[1]
  • the memory array 20 provided in the second layer is indicated as memory array 20[2]
  • the memory array 20 provided in the k-th layer is indicated as memory array 20[2].
  • the resulting memory array 20 is shown as memory array 20[k].
  • FIG. 25C shows an example of a circuit diagram of memory cells 10 provided in the memory array 20, which is a different layer.
  • FIG. 25C illustrates the memory cell 10[1] provided in the first-layer memory array 20[1] and the memory cell 10[2] provided in the second-layer memory array 20[2].
  • the memory cell 10[1] has a transistor Tr1 and a capacitive element Cp1.
  • the memory cell 10[2] has a transistor Tr2 and a capacitive element Cp2.
  • memory cells in each layer may be referred to as memory cells 10 in the case of items common to memory arrays in each layer.
  • the transistor Tr, the capacitor Cp, and each wiring (BL, WL, and the like) the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL, for example.
  • one of the source and the drain of the transistor Tr1 is connected to the wiring BL[1].
  • the other of the source and the drain of transistor Tr1 is connected to one electrode of capacitive element Cp1.
  • the other electrode of the capacitive element Cp1 is connected to the wiring PL[1].
  • a gate of the transistor Tr1 is connected to the wiring WL[1].
  • a back gate of the transistor Tr1 is connected to the wiring BGL.
  • one of the source and the drain of the transistor Tr2 is connected to the wiring BL[2].
  • the other of the source and drain of transistor Tr2 is connected to one electrode of capacitive element Cp2.
  • the other electrode of the capacitive element Cp2 is connected to the wiring PL[2].
  • a gate of the transistor Tr2 is connected to the wiring WL[2].
  • a back gate of the transistor Tr2 is connected to the wiring PL[1].
  • the same configuration as the second layer is repeated for the third and subsequent layers.
  • the memory cell 10[j] provided in the j-th layer (j is an integer satisfying 2 ⁇ j ⁇ k) memory array 20[j] one of the source and the drain of the transistor Trj is connected to the wiring BL[j]. be.
  • the other of the source and drain of transistor Trj is connected to one electrode of capacitive element Cpj.
  • the other electrode of capacitive element Cpj is connected to line PL[j].
  • a gate of the transistor Trj is connected to the wiring WL[j].
  • a back gate of the transistor Trj is connected to the wiring PL[j ⁇ 1].
  • the wiring PL is a wiring that applies a constant potential to hold the potential of the capacitor Cp.
  • the constant potential applied to the wiring PL is a constant potential (V BG ) for controlling the threshold voltage of the transistor Tr applied to the wiring BGL. By doing so, it is possible to control the threshold voltage of the transistor Tr included in the memory array 20 of each layer and reduce the variation in the voltage applied to the capacitive element Cp.
  • the wiring PL can be configured to have the function of the wiring BGL, so that the wiring BGL can be reduced.
  • 26A and 26B are schematic diagrams illustrating configuration examples of the memory cells 10 connected to the wirings BL in the memory arrays 20[1] to 20[k] provided in multiple layers. Note that a structure in which a plurality of memory cells (memory cells 10) are electrically connected to one wiring BL is also called a “memory string”.
  • FIG. 26A shows, as an example, the wiring BL[OD] connected to the memory cells 10 of the memory arrays 20 of odd-numbered layers, such as the first, third, and fifth layers.
  • the wiring BL[OD] connects a plurality of memory cells 10 in odd-numbered layers and is connected to the sense amplifier 46 included in the driver circuit 21 .
  • Each layer of memory array 20 (memory arrays 20[1], 20[3], and 20[5] are shown as examples) has a plurality of memory cells 10[1], 10[3] arranged in a matrix, respectively. , 10[5], and wiring WL and wiring PL extending in the X direction. Note that the wiring WL and the wiring PL included in each memory array 20 of each layer are omitted for the sake of clarity of the drawing.
  • FIG. 26A also shows a circuit diagram of the memory cells 10[1] and 10[3] connected to the wiring BL[OD]. Since the wiring BL[OD] is not connected to the memory cells 10 in the even-layered memory arrays 20, the corresponding memory arrays 20[2] and 20[4] are shown blank.
  • the memory cell 10[1] and memory cell 10[3] have the circuit diagram shown in FIG. 26A.
  • the back gate of the transistor Tr1 included in the memory cell 10[1] is connected to the wiring BGL, and the back gate of the transistor Tr3 included in the memory cell 10[3] is connected to the wiring PL[2].
  • the constant potential applied to the wiring PL[2] is a constant potential (V BG ) applied to the wiring BGL for controlling the threshold voltage of the transistor Tr1. Therefore, it is possible to control the threshold voltage of the transistor Tr3 included in the memory array 20[3] and reduce the variation of the voltage applied to the capacitive element Cp2 (not shown).
  • the wiring PL[2] can also function as the wiring BGL; therefore, the wiring BGL in the memory array 20[3] can be reduced.
  • FIG. 26B shows, as an example, the wiring BL[EV] connected to the memory cells 10 of the memory arrays 20 of even-numbered layers, such as the second, fourth, and sixth layers.
  • the wiring BL[EV] connects a plurality of memory cells 10 in even-numbered layers and is connected to the sense amplifier 46 included in the driver circuit 21 .
  • the memory arrays 20 of each layer (memory arrays 20[2], 20[4], and 20[6] are shown as examples) each have a plurality of memory cells 10[2], 10[4] arranged in a matrix. , 10[6], and wiring WL and wiring PL extending in the X direction. Note that the wiring WL and the wiring PL included in each memory array 20 of each layer are omitted for the sake of clarity of the drawing.
  • FIG. 26B also shows a circuit diagram of the memory cells 10[2] and 10[4] connected to the wiring BL[EV]. Since the memory cells 10 in the memory arrays 20 on the odd-numbered layers are not connected to the wiring BL[EV], the memory arrays 20[1] and 20[3] are shown blank.
  • the memory cell 10[2] and memory cell 10[4] have the circuit diagram shown in FIG. 26B.
  • the back gate of the transistor Tr2 included in the memory cell 10[2] is connected to the wiring PL[1]
  • the back gate of the transistor Tr4 included in the memory cell 10[4] is connected to the wiring PL[3].
  • the constant potential applied to the wiring PL[1] is a constant potential (V BG ) applied to the wiring BGL for controlling the threshold voltage of the transistor Tr1. Therefore, it is possible to control the threshold voltage of the transistor Tr2 included in the memory array 20[2] and reduce the fluctuation of the voltage applied to the capacitive element Cp1 (not shown).
  • the wiring PL[1] can also function as the wiring BGL; therefore, the wiring BGL in the memory array 20[2] can be reduced. The same can be said for the memory cell 10[4] in the fourth layer.
  • FIG. 27A a memory string having memory cells 10[1], 10[3], and 10[5] connected to the wiring BL[OD] illustrated in FIG. 26A and the wiring BL[EV] illustrated in FIG. are shown in combination with a memory string having memory cells 10[2], 10[4], 10[6] connected to each other.
  • FIG. 27A six layers of memory arrays 20[1] to 20[6] are shown as an example.
  • Each memory string shown in FIG. 27A has a wiring BL[OD] and a wiring BL[EV] extending in the Z direction.
  • One of the memory cells 10[1], 10[3], and 10[5] paired with the wiring BL[OD] interposed therebetween is paired with the wiring BL[EV] interposed therebetween when viewed in the Z direction.
  • the memory cells 10[1] to 10[6] connected to the wiring BL[OD] or the wiring BL[EV] and arranged so as to overlap each other are the memory cells 10[6] in the lower layer as illustrated in FIG. 27B. is connected to the back gate of the transistor Tr of the memory cell 10 in the upper layer.
  • the wiring PL3 connected to the memory cell 10[3] in the third layer is connected to the back gate of the transistor Tr4 in the upper memory cell 10[4].
  • the constant potential applied to the wiring PL is a constant potential (V BG ) for controlling the threshold voltage of the transistor Tr. can be controlled and variations in the voltage applied to the capacitive element Cp can be reduced.
  • V BG constant potential
  • the wiring PL can be configured to have the function of the wiring BGL, so that the wiring BGL can be reduced.
  • FIG. 27A the wiring BL[OD] to which the memory cells 10 provided in the odd-numbered layers are connected and the wiring BL[EV] to which the memory cells 10 provided in the even-numbered layers are connected are shown in FIG. 27A. , and are provided on the drive circuit 21.
  • the wiring BL[OD] to which the memory cells 10 provided in the odd-numbered layers are connected is connected to the memory cells 10 provided in the even-numbered layers.
  • the wiring PL is shared between the memory cells 10 arranged so as to overlap when viewed in the Z direction, and the wiring corresponding to the wiring BGL can be omitted, so that the electrical characteristics of the memory device can be stabilized.
  • miniaturization of the storage device can be achieved.
  • FIG. 29A is a layout diagram for explaining an arrangement example of wirings and semiconductor layers in the memory cell 10 described above.
  • FIG. 29A illustrates the wiring WL and the wiring PL extending in the X direction, the semiconductor layer 11, and the wiring BL extending in the Z direction.
  • the semiconductor layer 11 shown in FIG. 29A is provided so that two wirings WL and two wirings PL intersect each other, and two memory cells 10 are arranged by being connected to one wiring BL. It shows how it is done.
  • the wiring WL, the wiring PL, and the conductive layer 12 are provided on the semiconductor layer 11 so as to overlap with each other.
  • a transistor Tr is provided in a region where the wiring WL and the semiconductor layer 11 overlap.
  • a capacitive element Cp is provided in a region where the wiring PL and the semiconductor layer 11 overlap.
  • the conductive layer 12 is a conductive layer for connecting the transistor Tr to the wiring BL. Note that the detailed description of the cross-sectional view of the memory cell 10 is the same as the description in the first embodiment, so the above description is incorporated.
  • an upper layer wiring PL and a lower layer wiring WL are provided to overlap each other, and an upper layer wiring WL and a lower layer wiring PL are provided to overlap each other. configuration.
  • the layout diagrams of the two layers of memory arrays 20 provided to overlap each other do not overlap.
  • FIG. 29A illustrates a configuration in which the semiconductor layer 11 extending in the Y direction is provided so as to intersect the wiring WL and the wiring PL at right angles
  • the configuration is not limited to this.
  • one end of the semiconductor layer 11 extending in the Y direction may be arranged so as to be inclined in the X direction so as to intersect with the wiring WL and the wiring PL.
  • the memory density of the memory cell 10 can be further increased.
  • FIG. 30A is a schematic plan view when stacking the memory array 20[3] and the memory array 20[4] in which the layout diagram shown in FIG. 29 is arranged in a 2 ⁇ 2 arrangement.
  • FIG. 30B illustrates the arrangement of upper and lower wirings PL[3], PL[4] and wirings WL[3], WL[4] on a cross section including the thick dotted line A-B shown in FIG. 30A. It is a cross-sectional schematic diagram for doing.
  • the wiring WL[3] in the memory array 20[3] can be arranged to overlap with the wiring PL[4] in the memory array 20[4].
  • the wiring WL[4] in the memory array 20[4] overlaps with the wiring PL[5] (not shown) in the upper memory array 20[5] (not shown). can do.
  • the wiring WL and the wiring PL can be arranged to overlap each other; Even so, since the wiring PL of the upper memory array 20 is a wiring to which a constant potential is applied, the influence on the operation of the upper memory cell 10 can be reduced.
  • FIG. 30A is extended to the memory arrays 20[1] to 20[5], and the transistor 200 and the capacitor 100 described in any of the above embodiments are added to each memory array. is shown in FIG. Similarly, the cross-sectional plane including the thick dotted lines A to C-D shown in FIG. 32 shows a cross-sectional view in which the capacitor 100 and the capacitive element 100 are provided.
  • transistor 200a two sets of transistor 200 and capacitor 100 provided over the same oxide 230 are transistor 200a, transistor 200b, capacitor 100a, and It is described as a capacitive element 100b.
  • the combination of the transistor 200a and the capacitor 100a or the combination of the transistor 200b and the capacitor 100b corresponds to the memory cell 10.
  • the conductor 260 corresponds to the wiring WL
  • the conductor 160 corresponds to the wiring PL
  • the oxide 230 corresponds to the semiconductor layer 11 .
  • the conductor 260 of the upper transistor 200b is provided over the conductor 160 of the lower capacitor 100a, and the conductor 260 of the lower transistor 200a is overlaid.
  • a conductor 160 of the capacitive element 100b is provided.
  • the wiring WL and the wiring PL are arranged to overlap each other, so that the operation of the transistor 200 in the lower layer is less likely to affect the operation of the transistor 200 in the upper layer.
  • the semiconductor device shown in FIGS. 31 and 32 has a conductor 206 instead of the conductor 246, unlike the semiconductor device shown in FIG.
  • the conductor 206 is provided in the same layer as the conductor 205 functioning as the back gate of the transistor 200 . That is, the conductor 240 functioning as plugs of the transistors 200a and 200b is electrically connected to the conductor 206 provided in the same layer as the upper back gate.
  • a conductor 247 provided in the same manner as the conductor 240 is arranged so as to overlap with the conductor 160 .
  • Conductor 247 is electrically connected to conductor 205 functioning as a back gate in the upper layer.
  • the conductor 205 in the second and subsequent layers has the same potential as the conductor 160, so that the constant potential applied to the wiring PL controls the threshold voltage of the transistor Tr and is applied to the capacitive element Cp. Voltage fluctuations can be reduced.
  • the conductor 160 functions as a wiring, so the conductor 205 in the second and subsequent layers does not have to extend.
  • the conductor 206 is electrically connected to a conductor 248 provided in the same manner as the conductor 240 . Furthermore, conductor 248 is connected to conductor 207 provided in the same layer as conductor 205 .
  • the conductor 206, the conductor 248, and the conductor 207 are provided in each layer of the memory array, and the conductor 206, the conductor 248, and the conductor 207 in each layer are connected to function as the wiring BL. do.
  • the conductors 240 of the memory arrays 20[2] and 20[4] are connected to the wirings BL, and the wirings BL connected to the even-layered memory arrays 20 are shown. Although not shown, wirings BL connected to the memory arrays 20 on the odd-numbered layers are also provided.
  • the transistor 300 shown in FIG. 24 can be provided in the driver circuit 21 provided under the memory array 20[1].
  • FIGS. 34A and 34B An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIGS. 34A and 34B.
  • a plurality of circuits (systems) are mounted on the chip 1200 .
  • SoC System on Chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) to connect with the first surface of the package substrate 1201 as shown in FIG. 34B.
  • a plurality of bumps 1202 are provided on the rear surface of the first surface of the package substrate 1201 and connected to the motherboard 1203 .
  • the mother board 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222 .
  • storage devices such as a DRAM 1221 and a flash memory 1222 .
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221 .
  • the speed and capacity of the DRAM 1221 can be increased.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200 .
  • the aforementioned DOSRAM can be used for the memory.
  • the GPU 1212 is suitable for parallel computation of a large amount of data, and can be used for image processing or sum-of-products operations. By providing the image processing circuit or the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened. And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog computation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation unit 1213 may be provided with the sum-of-products calculation circuit.
  • the memory controller 1214 has a circuit functioning as a controller for the DRAM 1221 and a circuit functioning as an interface for the flash memory 1222 .
  • the interface 1215 has an interface circuit with externally connected devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, game controllers, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used as such an interface.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212 , a motherboard 1203 provided with a DRAM 1221 and a flash memory 1222 can be called a GPU module 1204 .
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum operation circuit using the GPU 1212 enables a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recurrent neural network
  • DBM deep Boltzmann machine
  • DBN deep belief network
  • This embodiment mode shows an example of an electronic component and an electronic device in which the storage device or the like described in the above embodiment mode is incorporated.
  • FIG. 35A shows a perspective view of an electronic component 700 and a board (mounting board 704) on which the electronic component 700 is mounted.
  • Electronic component 700 shown in FIG. 35A has storage device 720 in mold 711 .
  • FIG. 35A is partially omitted to show the inside of electronic component 700 .
  • Electronic component 700 has lands 712 outside mold 711 . Land 712 is electrically connected to electrode pad 713 , and electrode pad 713 is electrically connected to storage device 720 by wire 714 .
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed board 702 .
  • the memory device 720 has a drive circuit layer 721 and a memory circuit layer 722 .
  • FIG. 35B A perspective view of the electronic component 730 is shown in FIG. 35B.
  • Electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • An electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 provided on the interposer 731 .
  • an integrated circuit such as a CPU, GPU, or FPGA can be used.
  • a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 732 .
  • a silicon interposer, a resin interposer, or the like can be used as the interposer 731 .
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. A plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 731 also has a function of electrically connecting the integrated circuit provided over the interposer 731 to electrodes provided over the package substrate 732 . For these reasons, the interposer is sometimes called a "rewiring board" or an "intermediate board".
  • through electrodes are provided in the interposer 731 and the integrated circuit and the package substrate 732 are electrically connected using the through electrodes.
  • a TSV Through Silicon Via
  • a silicon interposer is preferably used as the interposer 731 . Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
  • the interposer that mounts the storage device 720 is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts the storage device 720 .
  • the reliability is less likely to deteriorate due to the difference in expansion coefficient between the integrated circuit and the interposer.
  • the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur.
  • a 2.5D package 2.5-dimensional packaging in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided overlapping the electronic component 730 .
  • a heat sink it is preferable that the heights of the integrated circuits provided over the interposer 731 be uniform.
  • the memory device 720 and the semiconductor device 735 have the same height.
  • An electrode 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate.
  • FIG. 35B shows an example of forming the electrodes 733 with solder balls.
  • BGA All Grid Array
  • the electrodes 733 may be formed of conductive pins.
  • PGA Peripheral Component Interconnect
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN Quad Flat Non-leaded package
  • the semiconductor devices described in the above embodiments are, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor devices described in the above embodiments are applied to various removable storage devices such as memory cards (eg, SD cards), USB memories, and SSDs (solid state drives).
  • 36A to 36E schematically show some configuration examples of removable storage devices.
  • the semiconductor devices described in the previous embodiments are processed into packaged memory chips and used for various storage devices and removable memories.
  • FIG. 36A is a schematic diagram of a USB memory.
  • USB memory 1100 has housing 1101 , cap 1102 , USB connector 1103 and substrate 1104 .
  • a substrate 1104 is housed in a housing 1101 .
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104 .
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 or the like.
  • FIG. 36B is a schematic diagram of the appearance of the SD card
  • FIG. 36C is a schematic diagram of the internal structure of the SD card.
  • SD card 1110 has housing 1111 , connector 1112 and substrate 1113 .
  • a substrate 1113 is housed in a housing 1111 .
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113 .
  • a wireless chip having a wireless communication function may be provided on the substrate 1113 .
  • data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110 .
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 or the like.
  • FIG. 36D is a schematic diagram of the appearance of the SSD
  • FIG. 36E is a schematic diagram of the internal structure of the SSD.
  • SSD 1150 has housing 1151 , connector 1152 and substrate 1153 .
  • a substrate 1153 is housed in a housing 1151 .
  • substrate 1153 has memory chip 1154 , memory chip 1155 and controller chip 1156 attached thereto.
  • a memory chip 1155 is a work memory for the controller chip 1156, and may be a DOSRAM chip, for example.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 or the like.
  • a semiconductor device can be used for a processor such as a CPU or a GPU, or a chip.
  • 37A to 37H illustrate specific examples of electronic devices including processors such as CPUs and GPUs, or chips according to one embodiment of the present invention.
  • a GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as televisions, monitors for desktop or notebook information terminals, digital signage (digital signage), large game machines such as pachinko machines, etc. , digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like.
  • the electronic device can be equipped with artificial intelligence.
  • the electronic device of one embodiment of the present invention may have an antenna.
  • An image, information, or the like can be displayed on the display portion by receiving a signal with the antenna.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared).
  • An electronic device of one embodiment of the present invention can have various functions. For example, functions to display various information (still images, moving images, text images, etc.) on the display unit, touch panel functions, calendars, functions to display the date or time, functions to execute various software (programs), wireless communication function, a function of reading a program or data recorded on a recording medium, and the like. Examples of electronic devices are shown in FIGS. 37A to 37H.
  • FIG. 37A shows a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5100 includes a housing 5101 and a display unit 5102. As an input interface, the display unit 5102 is provided with a touch panel, and the housing 5101 is provided with buttons.
  • the information terminal 5100 can execute an application using artificial intelligence.
  • Applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5102.
  • An application displayed on the display portion 5102, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
  • a notebook information terminal 5200 is illustrated in FIG. 37B.
  • the notebook information terminal 5200 has an information terminal main body 5201 , a display section 5202 , and a keyboard 5203 .
  • the notebook information terminal 5200 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Also, by using the notebook information terminal 5200, it is possible to develop new artificial intelligence.
  • a smartphone and a notebook information terminal are shown as examples of electronic devices in FIGS. 37A and 37B, respectively, but information terminals other than smartphones and notebook information terminals can be applied.
  • Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.
  • FIG. 37C shows a portable game machine 5300, which is an example of a game machine.
  • a portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like.
  • Housing 5302 and housing 5303 can be removed from housing 5301 .
  • the connection portion 5305 provided in the housing 5301 to another housing (not shown)
  • the video output to the display portion 5304 can be output to another video device (not shown). can.
  • the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time.
  • the chips described in the above embodiments can be incorporated into the chips or the like provided in the substrates of the housings 5301, 5302, and 5303.
  • FIG. 37D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is wirelessly or wiredly connected to the stationary game machine 5400 .
  • a low power consumption game machine By applying the GPU or chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 and the stationary game machine 5400, a low power consumption game machine can be realized.
  • the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • the progress of the game, the speech and behavior of creatures appearing in the game, and the expressions that occur in the game are determined by the program of the game. , which enables expressions not limited to game programs. For example, it is possible to express changes in the content of questions asked by the player, the progress of the game, the time, and the speech and behavior of characters appearing in the game.
  • the game players can be anthropomorphically configured by artificial intelligence. can play games.
  • FIGS. 37C and 37D illustrate a portable game machine and a stationary game machine as examples of game machines
  • game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these.
  • Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in amusement facilities (game arcades, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like. are mentioned.
  • a GPU or chip of one aspect of the present invention can be applied to large-scale computers.
  • FIG. 37E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 37F is a diagram showing a rack-mounted computer 5502 that the supercomputer 5500 has.
  • a supercomputer 5500 has a rack 5501 and a plurality of rack-mount computers 5502 .
  • a plurality of computers 5502 are stored in the rack 5501 .
  • the computer 5502 is provided with a plurality of substrates 5504, and the GPUs or chips described in the above embodiments can be mounted over the substrates.
  • the supercomputer 5500 is a large computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of computation, resulting in high power consumption and high chip heat generation.
  • a low power consumption supercomputer can be realized.
  • the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.
  • FIGS. 37E and 37F illustrate a supercomputer as an example of a large computer
  • the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Large computers to which the GPU or chip of one aspect of the present invention is applied include, for example, computers that provide services (servers), large general-purpose computers (mainframes), and the like.
  • a GPU or chip of one embodiment of the present invention can be applied to automobiles, which are mobile objects, and to the vicinity of the driver's seat of automobiles.
  • FIG. 37G is a diagram showing the vicinity of the windshield in the interior of an automobile, which is an example of a mobile object.
  • FIG. 37G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to the pillar.
  • the display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 can complement the field of view (blind spot) blocked by the pillars by displaying an image from an imaging device (not shown) provided in the automobile. That is, by displaying an image from an imaging device provided outside the automobile, blind spots can be compensated for and safety can be enhanced. In addition, by projecting an image that supplements the invisible part, safety confirmation can be performed more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system for automobiles.
  • the chip can be used in a system for road guidance, danger prediction, and the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like, and the chip of one embodiment of the present invention can be applied to these moving objects. It is possible to give a system using artificial intelligence.
  • FIG. 37H shows an electric refrigerator-freezer 5800, which is an example of an appliance.
  • the electric freezer-refrigerator 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric freezer-refrigerator 5800 has a function of automatically generating a menu based on the ingredients stored in the electric freezer-refrigerator 5800, the expiration date of the ingredients, etc. It can have a function of automatically adjusting the temperature according to the temperature.
  • Electric refrigerators and freezers have been described as an example of electrical appliances, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, the effects thereof, and the like described in the present embodiment can be appropriately combined with the descriptions of other electronic devices.
  • a semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has little change in electrical characteristics due to irradiation with radiation. In other words, since it has high resistance to radiation, it can be suitably used in an environment where radiation may be incident. For example, OS transistors can be suitably used when used in outer space.
  • FIGS. 1-10 A specific example of applying a semiconductor device of one embodiment of the present invention to space equipment will be described with reference to FIGS.
  • FIG. 38 shows a satellite 6800 as an example of space equipment.
  • Artificial satellite 6800 has fuselage 6801 , solar panel 6802 , antenna 6803 , secondary battery 6805 , and controller 6807 .
  • FIG. 38 illustrates a planet 6804 in outer space.
  • Outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include the thermosphere, the mesosphere, and the stratosphere.
  • outer space is an environment with a high radiation dose, more than 100 times higher than on the ground.
  • radiation include electromagnetic radiation (electromagnetic radiation) typified by X-rays and gamma rays, and particle radiation typified by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays. be done.
  • the power required for the satellite 6800 to operate is generated. However, less power is generated, for example, in situations where the solar panel is not illuminated by sunlight, or where the amount of sunlight illuminated by the solar panel is low. Thus, the power required for satellite 6800 to operate may not be generated.
  • a secondary battery 6805 may be provided in the satellite 6800 so that the satellite 6800 can operate even when the generated power is low. Note that the solar panel is sometimes called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via antenna 6803 and can be received by, for example, a receiver located on the ground or other satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be determined.
  • artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor that is one embodiment of the present invention is preferably used for the control device 6807 .
  • An OS transistor has less variation in electrical characteristics due to radiation irradiation than a Si transistor. In other words, it has high reliability and can be suitably used even in an environment where radiation may be incident.
  • the artificial satellite 6800 can be configured to have a sensor.
  • artificial satellite 6800 can have a function of detecting sunlight that hits and is reflected by an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface by adopting a configuration having a thermal infrared sensor.
  • artificial satellite 6800 can function as an earth observation satellite, for example.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • a semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.

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