WO2023124119A1 - 检测电路及包含该检测电路的电源管理系统 - Google Patents

检测电路及包含该检测电路的电源管理系统 Download PDF

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WO2023124119A1
WO2023124119A1 PCT/CN2022/113212 CN2022113212W WO2023124119A1 WO 2023124119 A1 WO2023124119 A1 WO 2023124119A1 CN 2022113212 W CN2022113212 W CN 2022113212W WO 2023124119 A1 WO2023124119 A1 WO 2023124119A1
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detection circuit
current
voltage
signal
threshold voltage
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PCT/CN2022/113212
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English (en)
French (fr)
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谭磊
陈昌彦
张海波
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圣邦微电子（北京）股份有限公司
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Publication of WO2023124119A1 publication Critical patent/WO2023124119A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/257—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output

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  • the present disclosure relates to the technical field of circuits, and more particularly to a detection circuit and a power management system including the detection circuit.
  • the PMBus Power Management Bus
  • IR35201 and PXE1610 integrate a large number of different types of ADC (Analog to Digital Converter, analog-to-digital converter) and DAC (Digital to Analog Converter, digital-to-analog converter) to realize the The function of monitoring multiple parameters needs to integrate a large number of devices in the circuit, which greatly increases the area and cost of the chip.
  • the purpose of the present disclosure is to provide a detection circuit with a simple structure and a power management system including the detection circuit.
  • the detection circuit is based on demand-oriented optimization, and completes the monitoring and setting of all parameters with a single structure. The area and cost of the circuit are greatly reduced.
  • a detection circuit including: a threshold voltage generation circuit, used to generate a threshold voltage; a voltage-current conversion circuit, used to offset the signal to be detected relative to the threshold voltage The shift voltage is converted into a proportional current; and a current-type successive approximation quantizer is used to obtain a detection result based on the quantization of the proportional current.
  • the detection result is a comparison result between the signal to be detected and the threshold voltage or a quantification result of a portion of the signal to be detected entering the threshold voltage defined window.
  • the detection circuit further includes: a differential sampling switch configured to provide an offset voltage or a reference ground voltage to the voltage-current conversion circuit.
  • the voltage-current conversion circuit includes: a storage capacitor, the first terminal of which is used to couple with the output terminal of the threshold generation circuit and the input terminal of the signal to be detected; a first transistor, used for the control terminal Coupled with the second end of the storage capacitor; the first resistor, the first end is used to couple with the second end of the first transistor, and the second end is used to communicate with the offset through the differential sampling switch voltage or a reference ground voltage; and a second transistor, the control terminal of which is used to receive a bias voltage, the second terminal is used to couple with the first terminal of the first transistor, and the first terminal is used to output the proportional current.
  • the current-type successive approximation quantizer includes: an operational amplifier, the first input end of which is coupled to the first end of the second transistor, and the second input end is coupled to a clamping voltage; a current source array, for generating a reference current based on the clamping voltage, and providing it to the first input terminal of the operational amplifier; and a comparator, coupled to the output terminal of the operational amplifier, for connecting the output of the operational amplifier to Quantify the results for the comparison.
  • the reference current provided by the current source array is a fixed current value.
  • the reference current provided by the current source array is a variable current value, by adjusting the The quantization result is obtained with reference to the current value of the current.
  • the current-type successive approximation quantizer further includes: a SAR logic circuit, configured to control the switching of the current source array according to the comparison result, and adjust the current value of the reference current in a successive approximation until the quantization ends.
  • a SAR logic circuit configured to control the switching of the current source array according to the comparison result, and adjust the current value of the reference current in a successive approximation until the quantization ends.
  • the detection circuit further includes: a first switch configured to couple the first end of the storage capacitor to the output end of the threshold voltage generation circuit in the threshold establishment phase; a second switch configured to detect The stage couples the first end of the storage capacitor to the input end of the signal to be detected.
  • the detection circuit further includes: a third switch configured to ground the first terminal of the storage capacitor in the first sub-phase of the threshold establishment phase, so as to realize charge reset.
  • the threshold establishment phase further includes a second sub-phase after the first sub-phase, and the threshold voltage generating circuit is configured to generate the threshold voltage in the second sub-phase.
  • the voltage-current conversion circuit further includes: a fourth switch configured to couple the control terminal and the first terminal of the first transistor during the threshold establishment phase.
  • the detection circuit includes multiple input terminals, and the detection circuit is configured to detect the signals to be detected at the multiple input terminals in a time-division manner.
  • the detection circuit further includes a register array for storing a plurality of control codes corresponding to the signals to be detected at the plurality of input terminals, and the threshold voltage generation circuit generates a corresponding threshold voltage.
  • the threshold voltage generation circuit is a capacitive digital-to-analog converter.
  • a power management system including the detection circuit described above.
  • the detection circuit of the present disclosure uses a capacitive DAC to generate the lower limit voltage of the window, and converts the offset voltage of the signal to be detected relative to the lower limit voltage into a current through a voltage-current conversion circuit, and then uses a current-type sequential comparison quantizer to compare The current is quantified to finally obtain the comparison result of the signal to be detected and the lower limit voltage or the quantization result of the signal to be detected in windowing.
  • the circuit structure is simpler, which can greatly reduce the area of the power management system using the detection circuit and reduce the circuit. cost.
  • FIG. 1 shows a schematic structural diagram of a detection circuit according to a first embodiment of the present disclosure
  • FIG. 2 shows a schematic circuit diagram of the current source array 131 in FIG. 1;
  • FIG. 3 shows a schematic timing diagram of the detection circuit of the first embodiment of the present disclosure
  • FIG. 4 shows a schematic structural diagram of a detection circuit according to a second embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of a detection circuit according to a third embodiment of the present disclosure
  • FIG. 6 shows a timing diagram of a detection circuit according to a third embodiment of the present disclosure.
  • circuitry may include single or multiple combined hardware circuits, programmable circuits, state machine circuits and/or elements capable of storing instructions for execution by programmable circuits.
  • an element or circuit is “connected” or “coupled to” another element, or that an element/circuit is “connected” or “coupled between” two nodes, it can be directly coupled or connected to another element.
  • An intermediate element may also exist between one element or two elements, and the connection or coupling between elements may be physical, logical, or a combination thereof.
  • an element is referred to as being “directly coupled to” or “directly connected to” another element, there are no intervening elements present.
  • FIG. 1 shows a schematic structural diagram of a detection circuit according to a first embodiment of the present disclosure.
  • the detection circuit 100 includes a threshold voltage generation circuit 110, a voltage-current conversion circuit 120, a current-type successive approximation quantizer (Successive Approximation Register ADC, SAR ADC) 130, and switches S1-S5.
  • the threshold voltage generation circuit 120 is used to generate the threshold voltage Vb, and the voltage-current conversion circuit 120 converts the offset voltage of the signal Vx to be detected relative to the threshold voltage Vb into a proportional current Ir by means of time-division subtraction.
  • the successive approximation quantizer 130 is used to receive the proportional current Ir, and obtain a detection result based on the quantization of the proportional current Ir, wherein the detection result is characterized as a comparison result between the signal to be detected Vx and the threshold voltage Vb.
  • the voltage-current conversion circuit 120 includes a storage capacitor CH, transistors Q1 and Q2, and a resistor R1.
  • the first terminal of the storage capacitor CH is coupled to the threshold voltage generating circuit 110 via the switch S1 and is coupled to the input terminal of the signal to be detected Vx via the switch S2 .
  • the second terminal of the storage capacitor CH is coupled to the control terminal of the transistor Q1 .
  • the switch S4 is coupled between the control terminal and the first terminal of the transistor Q1, the second terminal of the transistor Q1 is coupled to the first terminal of the resistor R1, and the second terminal of the resistor R1 is coupled to the offset voltage Vos or ground via the switch S5 .
  • the control terminal of the transistor Q2 is used to receive a bias voltage Vbias, the second terminal of the transistor Q2 is coupled to the first terminal of the transistor Q1, and the first terminal is used to output the proportional current Ir.
  • the switches S1 and S2 are turned on sequentially to provide the threshold voltage Vb and the signal Vx to be detected to the first end of the storage capacitor CH respectively, and the offset voltage between the threshold voltage Vb and the signal Vx to be detected is stored in the capacitor CH .
  • the transistor Q1 and the resistor R1 are used to convert the offset voltage on the storage capacitor CH into a current signal, and output it through the transistor Q2.
  • the cascaded structure of transistors Q2 and Q1 is used to increase the source impedance of the current signal Ir, and the selection of the bias voltage Vbias needs to ensure that the transistor Q2 still works in a linear state when the current signal Ir is at the maximum design value.
  • the transistor Q2 is mainly used to improve the performance of the voltage-current conversion circuit 120 , and in some other embodiments, the transistor Q2 can also be removed, which is not limited in the embodiments of the present disclosure.
  • the first end of the storage capacitor CH is also used to couple to the ground through the switch S3, and the switch S3 is used to connect the storage capacitor CH to the ground, so as to reset the charges on the capacitor.
  • the transistors Q1 and Q2 are, for example, NMOS transistors, and their first terminal, second terminal and control terminal are respectively the drain, source and gate of the NMOS transistors.
  • the current-mode successive approximation quantizer 130 includes a current source array (also known as a weighted current array or a current steering DAC) 131 , an operational amplifier AMP1 and a comparator COMP.
  • the current source array 131 is used to generate a reference current Ic.
  • the operational amplifier AMP1 has two input terminals and one output terminal, the first input terminal of which is coupled to the first terminal of the transistor Q2 and the output terminal of the current source array 131, the second input terminal is coupled to the clamping voltage Vforce, and the output terminal It is coupled to the input terminal of the comparator COMP, and the comparator COMP is used for quantizing the output of the operational amplifier AMP1 into the comparison result.
  • the operational amplifier AMP1 takes the reference current Ic output by the current source array 131 as a load (transistor Q2 serves as a current sink (current sink), and the current source array 131 serves as a current source (current source), both of which are at the first input of the operational amplifier AMP1
  • the terminals are mutual loads), amplifies and outputs the voltage difference between the junction point of the proportional current Ir and the reference current Ic and the clamping voltage Vforce, and the comparator COMP outputs the final comparison result "0" based on the voltage difference amplified by the operational amplifier AMP1 or "1".
  • the current source array 131 of this embodiment includes an operational amplifier AMP2 , a resistor R2 , transistors Q3 and Q4 , and a plurality of switch branches S31 - S3n.
  • the transistor Q3 and the resistor R2 are coupled between the power terminal Vcs and the ground.
  • the operational amplifier AMP2 has two input terminals and one input terminal, the first input terminal of which is coupled to the first terminal of the resistor R2, the second input terminal is coupled to the clamping voltage Vforce, and the output terminal is coupled to the control terminal of the transistor Q3 .
  • the transistor Q4 and the transistor Q3 form a current mirror, which is used to mirror the current Iref to the switch branches S31-S3n.
  • the first terminal of the transistor Q4 is coupled to the power supply terminal Vcs, and the second terminal is connected to one of the switch branches S31-S3n.
  • the common terminal is coupled, and the control terminal is coupled to the control terminal of the transistor Q3.
  • the switching branches S31-S3n are, for example, a binary-weighted current source array composed of MOS transistors with a width-to-length ratio of binary weighting. Through the switching of the switching branches S31-S3n, the required reference current Ic can be obtained at the other common terminal.
  • the reference current Ic is a fixed current value, and the selection of the current value is mainly set according to the detected environment. For example, when in a fast and high-precision comparison environment, the current value of the reference current Ic is relatively large; when In a power-saving comparative environment, the current value of the reference current Ic is relatively small.
  • the transistors Q3 and Q4 are, for example, PMOS transistors, and their first terminal, second terminal and control terminal are respectively the source, drain and gate of the PMOS transistor.
  • the threshold voltage generation circuit 110 can be realized by a capacitive DAC (digital-to-analog converter), and the capacitive DAC can include a plurality of weighted capacitors, such as binary weighted capacitors 2 N C ⁇ ⁇ C and a plurality of switches, by controlling switching of a plurality of switches in the capacitive DAC, a threshold voltage Vb corresponding to the signal Vx to be detected is generated.
  • a capacitive DAC digital-to-analog converter
  • the detection circuit 100 may further include a register array 140, which is used to store a binary control code corresponding to the signal Vx to be detected, and the binary control code is controlled by the capacitive DAC110 The switches in the switch switch, resulting in the corresponding threshold voltage. It can be understood that the circuit structure of the capacitive DAC and the circuit principle of converting the binary control code into a corresponding analog voltage are conventional techniques in the art, and will not be repeated here.
  • FIG. 3 shows a schematic timing diagram of the detection circuit of the first embodiment of the present disclosure.
  • the signal Used to control the on and off of switches S1 and S4 the signal Used to control the on and off of the switch S3, the signal It is used to control the on and off of the switch S2.
  • the detection circuit of this embodiment is implemented to operate on the signal Threshold settling phase and signal at high level These two phases are the detection phase at high level, the threshold detection phase further includes the signal is high for the first sub-stage and signals is the second sub-phase of the high level.
  • the working principle of the detection circuit of this embodiment will be further described below with reference to FIG. 3 .
  • the switch S1 and S4 are turned on, the switch S1 couples the first end of the storage capacitor CH to the output end of the capacitive DAC 110 , and the switch S4 couples the control end of the transistor Q1 to the first end.
  • Simultaneous signal Inverting to a high level the switch S3 is turned on, and the first end of the storage capacitor CH is grounded, so that the charge in the capacitor is reset.
  • the capacitive DAC 110 performs switching according to the control code provided by the register array 140, outputs the threshold voltage Vb, and stores it in the storage capacitor CH.
  • the switch S2 After that, the signal Switching to a high level, the switch S2 is turned on, the switch S2 couples the first terminal of the storage capacitor CH to the input terminal of the signal Vx to be detected, and the signal Vx to be detected is provided to the storage capacitor CH. Since the threshold voltage Vb has been stored on the storage capacitor CH, the offset voltage of the signal Vx to be detected relative to the threshold voltage Vb is converted into a proportional current through the transistor Q1 and the resistor R1, and then passed through the subsequent current-type successive approximation quantizer 130 based on Proportional current quantization outputs comparison results.
  • the signal Vx to be detected needs to be further differentiated outside of windowing, for example, when collecting the operating voltage of the load point, it is necessary to immediately deduct the voltage drop of the return path, which can be used in the detection stage
  • the corresponding offset voltage Vos is connected to the voltage-current conversion circuit 120 through the differential sampling switch S5.
  • Figure 3 also includes the signal located at Delayed signal before delayed signal Used to avoid switch shoot-through in the circuit.
  • FIG. 4 shows a schematic structural diagram of a detection circuit according to a second embodiment of the present disclosure.
  • the difference between the detection circuit 200 of this embodiment and the detection circuit 100 of the first embodiment is that the output detection result is the quantization result of the part where the signal Vx to be detected enters the window defined by the threshold voltage Vb, that is, the signal Vx to be detected is in the The numerical result of the portion within the window.
  • the reference current Ic provided by the current source array 131 is a variable current value, and the current value of the reference current Ic is adjusted in a successive approximation manner to finally obtain the quantized result.
  • the detection circuit 200 of this embodiment is compared with the detection circuit 100 of the first embodiment, the current-type successive approximation quantizer 130 also includes a SAR logic circuit 132, and the SAR logic circuit 132 is used to output the comparison result according to the comparator COMP "0" and "1" control the SAR (successive approximation) conversion in the current source array 131, and continuously generate each bit output of the SAR ADC from high to low in a successive approximation mode, until the whole quantization ends, and finally obtain the to-be-detected Numerical result of signal Vx within the window.
  • the principle of the SAR logic circuit 132 controlling the SAR conversion in the current source array 131 according to the output of the comparator COMP is a conventional technology in the art, and will not be repeated here.
  • the detection circuit 200 of this embodiment can also be controlled by using the timing diagram in FIG. is high during the detection phase, when the signal When it is at a high level, the signal to be detected Vx is also provided to the storage capacitor CH, and then the offset voltage of the signal to be detected Vx relative to the threshold voltage Vb is converted into a proportional current through the transistor Q1 and the resistor R1, and passed through the comparator AMP1 and the amplifier COMP uses the current source array 131 as the load to output the comparison result, and then the detection circuit 200 of this embodiment further includes controlling the current source array 131 to perform SAR transformation through the SAR logic circuit 132 according to the comparison result, and finally obtains the quantization result of the signal Vx to be detected.
  • the detection circuit 200 of this embodiment can simultaneously have two functions of threshold value comparison and signal quantization.
  • threshold value comparison it is only necessary to disconnect the SAR logic circuit 132 so that the current source array 131 outputs a reference current Ic with a fixed current value.
  • signal quantization it is only necessary to connect the SAR logic circuit 132 to the circuit again.
  • the two functions of threshold value comparison and quantization can be realized in one circuit at the same time, which can greatly reduce the scale and cost of the circuit.
  • FIG. 5 and FIG. 6 respectively show a structural diagram and a timing diagram of a detection circuit according to a third embodiment of the present disclosure.
  • the difference between the detection circuit 300 of this embodiment and the detection circuit 200 of the second embodiment is that the detection circuit 300 includes a plurality of input terminals and a plurality of switches S21-S2n, and the detection circuit 300 detects multiple inputs in time division according to a certain beat.
  • the signals Vx1-Vxn to be detected at terminals, and perform threshold comparison or quantization operations on the input signals to be detected according to specific requirements.
  • the timing signal CLK includes the first time slot to the nth time slot, and the detection circuit 300 is configured to detect the signal to be detected at the corresponding input port in each time slot.
  • the operation of the detection circuit 300 in each time slice also includes the signal Set up the stage and signal for a high-level threshold for the high-level detection phase, and the threshold establishment phase also includes signal is high for the first sub-stage and signals is the second sub-phase of the high level.
  • the register array 140 of the detection circuit 300 of this embodiment also stores a plurality of binary control codes, the plurality of binary control codes are in one-to-one correspondence with the signals to be detected at a plurality of input terminals, and the capacitive DAC 110 is configured to establish The stage generates the threshold voltage Vb corresponding to the currently input signal to be detected based on the binary control code provided by the register array 140 .
  • the switch S1 couples the first end of the storage capacitor CH to the output end of the capacitive DAC 110
  • the switch S4 couples the first end of the transistor Q1 to the control end.
  • the storage capacitor CH discharges to ground to reset the charge on the capacitor.
  • the capacitive DAC 110 generates a threshold voltage Vb corresponding to the signal Vx1 to be detected according to the binary control code provided by the register array 140 .
  • the detection circuit 300 enters the detection stage, the switch S21 is turned on, and the signal to be detected Vx1 is coupled to the storage capacitor CH, and at the same time, a comparator or a current type is established in the subsequent circuit according to the specific requirements of the signal to be detected Vx1
  • the SAR transformation outputs the comparison result of the signal to be detected Vx1 and the threshold voltage Vb or the quantization result of the signal to be detected Vx1 within the window defined by the threshold voltage Vb.
  • the signal Vx1 to be detected needs to be differentiated outside of windowing, it can be A certain offset voltage Vos is provided to the voltage-current conversion circuit 120 through the differential sampling switch S5.
  • the present disclosure also provides a power management system, the power management system includes the detection circuit described above, and the detection circuit is connected to the power supply unit through a power management bus (power management bus, PMBus) interface to Read various parameters such as the input voltage, output voltage or output voltage offset of the power supply unit, and compare and quantify the thresholds of these parameters, complete the monitoring and setting needs of all parameters with a single circuit structure, greatly reducing power management circuit cost.
  • a power management bus power management bus
  • the detection circuit of the present disclosure uses a capacitive DAC to generate the lower limit voltage of the window, and converts the offset voltage of the signal to be detected relative to the lower limit voltage into a current through a voltage-current conversion circuit, and then uses a current-type sequential comparison quantizer to compare The current is quantified to finally obtain the comparison result of the signal to be detected and the lower limit voltage or the quantization result of the signal to be detected in windowing.
  • the circuit structure is simpler, which can greatly reduce the area of the power management system using the detection circuit and reduce the circuit. cost.
  • the detection circuit multiplexes the current source array in the current-type successive approximation quantizer as a load for threshold comparison or proportional current quantization, which is beneficial to save circuit components and further reduce the circuit area.
  • the detection circuit uses a combination of a capacitive DAC and a current-type SAR ADC to perform window quantization on the parameters. Since the quantization range of the current-type SAR ADC covers different quantization bits of the capacitive DAC, the same parameter can be Multiple quantizations are completed through different combinations of DAC bits and ADC bits, so that multiple quantization averages are used to reduce quantization errors and improve quantization accuracy.

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Abstract

一种检测电路及包含该检测电路的电源管理系统。检测电路包括：阈值电压生成电路（110），用于生成一阈值电压；电压-电流转换电路（120），用于将待检测信号相对于阈值电压的偏移电压转换成比例电流；以及电流型逐次逼近量化器（130），用于基于比例电流量化得到待检测信号与阈值电压的比较结果或待检测信号在窗口化的量化结果，电路结构更加简单，成本更低。

Description

检测电路及包含该检测电路的电源管理系统
本申请要求了申请日为2021年12月27日、申请号为202111614920.9、名称为“检测电路及包含该检测电路的电源管理系统”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本公开涉及电路技术领域，更具体地涉及一种检测电路及包含该检测电路的电源管理系统。
背景技术
在供电要求较复杂的系统中，通常使用多个DC/DC转换器来产生不同的半导体器件所需要的供电要求。导致一个明显结果就是在产品设计、生产测试及日常使用的过程中，控制和监测这些电源将变得更加复杂。
目前，许多高性能DC/DC转换器仍然通过无源元件产生的模拟信号来进行控制。即使采用最先进的电源电路拓扑，也不得不使用外部的电位器和电容来调节诸如启动时间、输出电压值及开关频率等参数，而且这些参数不能随时更改。
PMBus(电源管理总线)开放标准规范定义了一个用来控制功率转换和管理器件的数字通信协议，其可通过定义传输和物理接口以及命令语言来实现变换器与其他设备的通信。现有的DC/DC变换器，例如IR35201和PXE1610在内部集成了大量的不同类型的ADC(Analog to Digital Converter，模数转换器)和DAC(Digital to Analog Converter，数模转换器)来实现对多个参数进行监控的功能，需要在电路中集成大量的器件，大大提高了芯片的面积和成本。
发明内容
有鉴于此，本公开的目的在于提供一种结构简单的检测电路和包含该检测电路的电源管理系统，该检测电路以面向需求优化为出发点，以单一结构完成所有的参数的监控和设置需要，大大降低了电路的面积和成本。
根据本公开实施例的一方面，提供了一种检测电路，包括：阈值电压生成电路，用于生成一阈值电压；电压-电流转换电路，用于将待检测信号相对于所述阈值电压的偏移电压转换成比例电流；以及电流型逐次逼近量化器，用于基于所述比例电流量化得到检测结果。
可选的，所述检测结果为所述待检测信号与所述阈值电压的比较结果或所述待检测信号进入所述阈值电压限定窗口内的部分的量化结果。
可选的，所述检测电路还包括：配置为向所述电压-电流转换电路提供失调电压或参考地电压的差分采样开关。
可选的，所述电压-电流转换电路包括：存储电容，其第一端用于与所述阈值生成电路的输出端和所述待检测信号的输入端耦接；第一晶体管，控制端用于与所述存储电容的第二端耦接；第一电阻，第一端用于与所述第一晶体管的第二端耦接，第二端用于经所述差分采样开关与所述失调电压或参考地电压耦接；以及第二晶体管，其控制端用于接收一偏置电压，第二端用于与所述第一晶体管的第一端耦接，第一端用于输出所述比例电流。
可选的，所述电流型逐次逼近量化器包括：运算放大器，第一输入端与所述第二晶体管的第一端耦接，第二输入端与一钳位电压耦接；电流源阵列，用于基于所述钳位电压生成一参考电流，并提供至所述运算放大器的第一输入端；以及比较器，与所述运算放大器的输出端耦接，用于将所述运算放大器的输出量化为所述比较结果。
可选的，当所述检测结果为所述待检测信号与所述阈值电压的比较结果时，所述电流源阵列提供的所述参考电流为固定电流值。
可选的，当所述检测结果为所述待检测信号在所述阈值电压限定的窗口内的量化结果时，所述电流源阵列提供的所述参考电流为可变电流 值，通过调节所述参考电流的电流值获得所述量化结果。
可选的，电流型逐次逼近量化器还包括：SAR逻辑电路，用于根据所述比较结果控制所述电流源阵列切换，以逐次逼近的方式调节所述参考电流的电流值，直至量化结束。
可选的，所述检测电路还包括：第一开关，配置为在阈值建立阶段耦接所述存储电容的第一端与所述阈值电压生成电路的输出端；第二开关，配置为在检测阶段将所述存储电容的第一端与所述待检测信号的输入端耦接。
可选的，所述检测电路还包括：第三开关，配置为在所述阈值建立阶段的第一子阶段将所述存储电容的第一端接地，以实现电荷复位。
可选的，所述阈值建立阶段还包括所述第一子阶段之后的第二子阶段，所述阈值电压生成电路配置为在所述第二子阶段生成所述阈值电压。
可选的，所述电压-电流转换电路还包括：第四开关，配置为在所述阈值建立阶段耦接所述第一晶体管的控制端和第一端。
可选的，所述检测电路包括多个输入端，所述检测电路配置为以分时的方式检测所述多个输入端的待检测信号。
可选的，所述检测电路还包括寄存器阵列，用于存储与所述多个输入端的待检测信号对应的多个控制码，所述阈值电压生成电路基于所述寄存器阵列提供的控制码产生对应的阈值电压。
可选的，所述阈值电压生成电路为电容型数模转换器。
根据本公开实施例的另一方面，提供了一种电源管理系统，包括上述的检测电路。
综上所述，本公开的检测电路采用电容型DAC产生窗口下限电压，通过电压-电流转换电路将待检测信号相对于下限电压的偏移电压转换成电流，然后使用电流型逐次比较量化器对该电流进行量化，最终得到待检测信号与下限电压的比较结果或待检测信号在窗口化的量化结果，电路结构更加简单，从而可以大大减小使用该检测电路的电源管理系统的面积，降低电路成本。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚。
图1示出了本公开第一实施例的检测电路的结构示意图；
图2示出了图1中的电流源阵列131的电路示意图；
图3示出了本公开第一实施例的检测电路的时序示意图；
图4示出了本公开第二实施例的检测电路的结构示意图；
图5示出了本公开第三实施例的检测电路的结构示意图；
图6示出了本公开第三实施例的检测电路的时序示意图。
具体实施方式
以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
在下文中描述了本公开的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
应当理解，在以下的描述中，“电路”可包括单个或多个组合的硬件电路、可编程电路、状态机电路和/或能存储由可编程电路执行的指令的元件。当称元件或电路“连接到”或者“耦接到”另一元件，或称元件/电路“连接在”或者“耦接在”两个节点之间时，它可以直接耦接或连接到另一元件或者二者之间也可以存在中间元件，元件之间的连接或耦接可以是物理上的、逻辑上的、或者其结合。相反，当称元件“直接耦接到”或“直接连接到”另一元件时，意味着两者不存在中间元件。
图1示出了本公开第一实施例的检测电路的结构示意图。如图1所示，检测电路100包括阈值电压生成电路110、电压-电流转换电路120和电流型逐次逼近量化器(Successive Approximation Register ADC，SAR ADC)130以及开关S1～S5。其中，阈值电压生成电路120用于生成阈值电压Vb，电压-电流转换电路120采用分时减法的方式将待检测信号 Vx相对于所述阈值电压Vb的偏移电压转换成比例电流Ir，电流型逐次逼近量化器130用于接收所述比例电流Ir，并基于所述比例电流Ir量化得到检测结果，其中该检测结果表征为待检测信号Vx与所述阈值电压Vb之间的比较结果。
电压-电流转换电路120包括存储电容CH、晶体管Q1和Q2、以及电阻R1。存储电容CH的第一端经开关S1与阈值电压生成电路110耦接，并且经开关S2与待检测信号Vx的输入端耦接，存储电容CH的第二端与晶体管Q1的控制端耦接。开关S4耦接于晶体管Q1的控制端和第一端之间，晶体管Q1的第二端与电阻R1的第一端耦接，电阻R1的第二端经开关S5与失调电压Vos或地耦接。晶体管Q2的控制端用于接收一偏置电压Vbias，晶体管Q2的第二端与晶体管Q1的第一端耦接，第一端用于输出所述比例电流Ir。
其中，开关S1和S2依次导通，以将阈值电压Vb和待检测信号Vx分别提供至存储电容CH的第一端，所述阈值电压Vb与待检测信号Vx的偏移电压被存储于电容CH。晶体管Q1和电阻R1用于将存储电容CH上的偏移电压转换成电流信号，并通过晶体管Q2进行输出。其中，晶体管Q2和Q1的级联结构用于提高电流信号Ir的源阻抗，偏置电压Vbias的选择需要保证电流信号Ir在最大设计值时晶体管Q2仍工作在线性状态即可。需要说明的是，晶体管Q2主要用于改善电压-电流转换电路120的性能，在另外一些实施例中，也可以将晶体管Q2移除，本公开实施例不对此进行限制。
此外，存储电容CH的第一端还用于经开关S3与地耦接，开关S3用于将存储电容CH接地，以将电容上的电荷复位。
在本实施例中，晶体管Q1和Q2例如为NMOS晶体管，其第一端、第二端和控制端分别为NMOS晶体管的漏极、源极和栅极。
电流型逐次逼近量化器130包括电流源阵列(又称权电流阵列或电流舵DAC)131、运算放大器AMP1以及比较器COMP。电流源阵列131用于生成一参考电流Ic。运算放大器AMP1具有两个输入端和一个输出端，其第一输入端与晶体管Q2的第一端以及电流源阵列131的输出端 耦接，第二输入端与钳位电压Vforce耦接，输出端与比较器COMP的输入端耦接，比较器COMP用于将运算放大器AMP1的输出量化为所述比较结果。其中，运算放大器AMP1以电流源阵列131输出的参考电流Ic为负载(晶体管Q2作为电流宿(current sink)，电流源阵列131作为电流源(current source)，二者在运算放大器AMP1的第一输入端互为负载)，放大并输出比例电流Ir与参考电流Ic的结合点与钳位电压Vforce之间的电压差，比较器COMP基于运算放大器AMP1放大后的电压差输出最终的比较结果“0”或“1”。
进一步的，如图2所示，本实施例的电流源阵列131包括运算放大器AMP2、电阻R2、晶体管Q3和Q4、以及多个开关支路S31～S3n。其中，晶体管Q3和电阻R2耦接于电源端Vcs和地之间。运算放大器AMP2具有两个输入端和一个输入端，其第一输入端与电阻R2的第一端耦接，第二输入端与钳位电压Vforce耦接，输出端与晶体管Q3的控制端耦接。当运算放大器AMP2工作在负反馈环路中时，在晶体管Q3中得到电流Iref＝Vforce/R2。晶体管Q4与晶体管Q3构成电流镜，用于将该电流Iref镜像到开关支路S31～S3n中，晶体管Q4的第一端与电源端Vcs耦接，第二端与开关支路S31～S3n的一个公共端耦接，控制端与晶体管Q3的控制端耦接。开关支路S31～S3n例如为宽长比为二进制加权的MOS管组成的二进制加权的电流源阵列，可以通过开关支路S31～S3n的切换，在其另一个公共端得到需要的参考电流Ic。在本实施例中，参考电流Ic为固定的电流值，该电流值的选择主要根据检测的环境进行设置，例如，当处于快速高精度的比较环境时，参考电流Ic的电流值较大；当处于省电的比较环境时，参考电流Ic的电流值较小。
在本实施例中，晶体管Q3和Q4例如为PMOS晶体管，其第一端、第二端和控制端分别为PMOS晶体管的源极、漏极和栅极。
继续参考图1，在一些实施例中，该阈值电压生成电路110可以通过电容型DAC(数模转换器)实现，该电容型DAC可以包括多个权电容器，例如二进制权电容器2 NC···C以及多个开关，通过控制该电容型DAC中的多个开关切换，产生与所述待检测信号Vx相应的阈值电压 Vb。在另一些实施例中，所述检测电路100还可以包括寄存器阵列140，所述寄存器阵列140用于存储与所述待检测信号Vx对应的二进制控制码，所述二进制控制码通过控制电容型DAC110中的开关切换，从而产生相应的阈值电压。可以理解，电容型DAC的电路结构以及将二进制控制码转换成对应的模拟电压的电路原理为本领域的常规技术，在此不再赘述。
图3示出了本公开第一实施例的检测电路的时序示意图。在图3中，信号
Figure PCTCN2022113212-appb-000001
用于控制开关S1和S4的导通和截止，信号
Figure PCTCN2022113212-appb-000002
用于控制开关S3的导通和截止，信号
Figure PCTCN2022113212-appb-000003
用于控制开关S2的导通和截止。本实施例的检测电路的被执行操作于信号
Figure PCTCN2022113212-appb-000004
处于高电平时的阈值建立阶段和信号
Figure PCTCN2022113212-appb-000005
处于高电平时的检测阶段这两个阶段，阈值检测阶段进一步包括信号
Figure PCTCN2022113212-appb-000006
为高电平的第一子阶段和信号
Figure PCTCN2022113212-appb-000007
为高电平的第二子阶段。下面参照图3对本实施例的检测电路的工作原理做进一步的说明。
首先，信号
Figure PCTCN2022113212-appb-000008
翻转为高电平，开关S1和S4导通，开关S1将存储电容CH的第一端与电容型DAC110的输出端耦接，开关S4将晶体管Q1的控制端和第一端耦接。同时信号
Figure PCTCN2022113212-appb-000009
翻转为高电平，开关S3导通，将存储电容CH的第一端接地，以使得电容中的电荷复位。当信号
Figure PCTCN2022113212-appb-000010
翻转为低电平时，信号
Figure PCTCN2022113212-appb-000011
翻转为高电平，电容型DAC110根据寄存器阵列140提供的控制码进行开关切换，输出所述阈值电压Vb，并储存到存储电容CH上。
之后，信号
Figure PCTCN2022113212-appb-000012
翻转为高电平，开关S2导通，开关S2将存储电容CH的第一端与待检测信号Vx的输入端耦接，待检测信号Vx被提供至存储电容CH。由于存储电容CH上已经存储了阈值电压Vb，因此通过晶体管Q1和电阻R1将待检测信号Vx相对于阈值电压Vb的偏移电压转换成比例电流，并通过之后的电流型逐次逼近量化器130基于比例电流量化输出比较结果。进一步的，当获取该待检测信号Vx时需要在窗口化之外进一步做差分化时，例如在采集负载点的工作电压时需要即时扣除回流路径的压降，可在检测阶段
Figure PCTCN2022113212-appb-000013
通过差分采样开关S5向电压-电流转换电路120接入相应的失调电压Vos。
进一步的，图3中还包括位于信号
Figure PCTCN2022113212-appb-000014
之前的延时信号
Figure PCTCN2022113212-appb-000015
延时信号
Figure PCTCN2022113212-appb-000016
用于避免电路中的开关贯通。
图4示出了本公开第二实施例的检测电路的结构示意图。本实施例的检测电路200与第一实施例的检测电路100的区别在于：输出的检测结果为待检测信号Vx进入所述阈值电压Vb限定窗口内的部分的量化结果，即待检测信号Vx在所述窗口内的部分的数字结果。在本实施例中，电流源阵列131提供的参考电流Ic为可变的电流值，通过逐次逼近的方式调节参考电流Ic的电流值，最终获得该量化结果。
进一步的，本实施例的检测电路200与第一实施例的检测电路100相比，电流型逐次逼近量化器130还包括SAR逻辑电路132，SAR逻辑电路132用于根据比较器COMP输出的比较结果“0”和“1”控制电流源阵列131中的SAR(逐次逼近)变换，以逐次逼近方式从高到低不断产生SAR ADC的每一位输出，直到整个量化结束，最终得到所述待检测信号Vx在窗口内的数字结果。可以理解，SAR逻辑电路132根据比较器COMP的输出控制电流源阵列131中的SAR变换的原理为本领域的常规技术，在此不再赘述。
需要说明的是，本实施例的检测电路200同样可以采用图3中的时序图进行控制，与第一实施例的检测电路100的区别仅在于信号
Figure PCTCN2022113212-appb-000017
处于高电平时的检测阶段，当信号
Figure PCTCN2022113212-appb-000018
处于高电平时，待检测信号Vx同样被提供至存储电容CH，然后通过晶体管Q1和电阻R1将待检测信号Vx相对于阈值电压Vb的偏移电压转换成比例电流，并通过比较器AMP1和放大器COMP以电流源阵列131为负载输出比较结果，之后本实施例的检测电路200进一步包括通过SAR逻辑电路132根据比较结果控制电流源阵列131进行SAR变换，最终得到待检测信号Vx的量化结果。
需要说明的是，本实施例的检测电路200作为检测电路100进一步改进的方案，可以同时具有阈值比较和信号量化这两种功能。当用作阈值比较时，只需要断开SAR逻辑电路132，使得电流源阵列131输出一个固定电流值的参考电流Ic，当用作信号量化时，只需要将SAR逻辑电路132再次接入电路即可，最终在一个电路中同时实现了阈值比较和量 化这两种功能，可以大大降低电路的规模和成本。
图5和图6分别示出了本公开第三实施例的检测电路的结构示意图和时序示意图。本实施例的检测电路300与第二实施例的检测电路200的区别在于：检测电路300包括多个输入端，以及多个开关S21～S2n，检测电路300按照一定的节拍分时检测多个输入端的待检测信号Vx1～Vxn，并根据具体的要求对输入的待检测信号执行阈值比较或量化的操作。如图6所示，时序信号CLK包括第1时间片至第n时间片，检测电路300配置为在每个时间片对相应输入端口的待检测信号进行检测。进一步的，检测电路300在每个时间片的操作还包括信号
Figure PCTCN2022113212-appb-000019
为高电平的阈值建立阶段和信号
Figure PCTCN2022113212-appb-000020
为高电平的检测阶段，并且阈值建立阶段还包括信号
Figure PCTCN2022113212-appb-000021
为高电平的第一子阶段和信号
Figure PCTCN2022113212-appb-000022
为高电平的第二子阶段。
进一步的，本实施例的检测电路300的寄存器阵列140还存储有多个二进制控制码，所述多个二进制控制码与多个输入端的待检测信号一一对应，电容型DAC110配置为在阈值建立阶段基于寄存器阵列140提供的二进制控制码产生与当前输入的待检测信号相对应的阈值电压Vb。
以待检测信号Vx1为例，当信号
Figure PCTCN2022113212-appb-000023
为高电平时，检测电路300处于阈值建立阶段，开关S1将存储电容CH的第一端与电容型DAC110的输出端耦接，开关S4将晶体管Q1的第一端和控制端耦接。同时信号
Figure PCTCN2022113212-appb-000024
处于高电平，存储电容CH对地放电，以将电容上的电荷复位。当信号
Figure PCTCN2022113212-appb-000025
翻转为低电平时，信号
Figure PCTCN2022113212-appb-000026
翻转为高电平，电容型DAC110根据寄存器阵列140提供的二进制控制码产生与待检测信号Vx1相应的阈值电压Vb。当信号
Figure PCTCN2022113212-appb-000027
翻转为低电平后，经过一死区时间
Figure PCTCN2022113212-appb-000028
信号
Figure PCTCN2022113212-appb-000029
翻转为高电平，检测电路300进入检测阶段，开关S21导通，将待检测信号Vx1与存储电容CH耦接，同时根据待检测信号Vx1的具体要求在后级电路中建立比较器或电流型SAR变换，输出待检测信号Vx1与阈值电压Vb的比较结果或者待检测信号Vx1在阈值电压Vb限定的窗口内的量化结果。同样的，若待检测信号Vx1需要在窗口化之外做一定的差分化，可在检测阶段
Figure PCTCN2022113212-appb-000030
通过差分采样开关S5向电压-电流转换电路120提供一定的失调电压Vos。
在另外一些实施例中，本公开还提供了一种电源管理系统，该电源管理系统包括上述的检测电路，所述检测电路通过电源管理总线(power management bus，PMBus)接口与供电单元连接，以读取供电单元的输入电压、输出电压或输出电压偏移等各种参数，并对这些参数进行阈值比较和量化，以单一的电路结构完成了所有参数的监控和设置需要，大大降低了电源管理的电路成本。
综上所述，本公开的检测电路采用电容型DAC产生窗口下限电压，通过电压-电流转换电路将待检测信号相对于下限电压的偏移电压转换成电流，然后使用电流型逐次比较量化器对该电流进行量化，最终得到待检测信号与下限电压的比较结果或待检测信号在窗口化的量化结果，电路结构更加简单，从而可以大大减小使用该检测电路的电源管理系统的面积，降低电路成本。
在进一步的实施例中，检测电路复用电流型逐次逼近量化器中的电流源阵列做负载进行阈值比较或进行比例电流的量化，有利于节省电路元件，进一步减小电路面积。
在进一步的实施例中，检测电路使用电容型DAC和电流型SAR ADC的组合对参数进行窗口量化，由于电流型SAR ADC的量化范围覆盖了电容型DAC的不同量化位，所以针对相同的参数可以通过不同的DAC位和ADC位组合完成多次量化，以便利用多次量化平均以减小量化误差，改善了量化精度。
本领域普通技术人员可以理解，本文中使用的与电路运行相关的词语“期间”、“当”和“当……时”不是表示在启动动作开始时立即发生的动作的严格术语，而是在其与启动动作所发起的反应动作(reaction)之间可能存在一些小的但是合理的一个或多个延迟，例如各种传输延迟等。本文中使用词语“大约”或者“基本上”意指要素值(element)具有预期接近所声明的值或位置的参数。然而，如本领域所周知的，总是存在微小的偏差使得该值或位置难以严格为所声明的值。本领域已恰当的确定了，至少百分之十(10％)(对于半导体掺杂浓度，至少百分之二十(20％))的偏差是偏离所描述的准确的理想目标的合理偏差。当结合信号状态使 用时，信号的实际电压值或逻辑状态(例如“1”或“0”)取决于使用正逻辑还是负逻辑。
此外，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本公开的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该公开仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本公开的原理和实际应用，从而使所属技术领域技术人员能很好地利用本公开以及在本公开基础上的修改使用。本公开仅受权利要求书及其全部范围和等效物的限制。

Claims (16)

  1. 一种检测电路，包括：
    阈值电压生成电路，用于生成一阈值电压；
    电压-电流转换电路，用于将待检测信号相对于所述阈值电压的偏移电压转换成比例电流；以及
    电流型逐次逼近量化器，用于基于所述比例电流量化得到检测结果。
  2. 根据权利要求1所述的检测电路，其中，所述检测结果为所述待检测信号与所述阈值电压的比较结果或所述待检测信号进入所述阈值电压限定窗口内的部分的量化结果。
  3. 根据权利要求2所述的检测电路，其中，还包括：
    配置为向所述电压-电流转换电路提供失调电压或参考地电压的差分采样开关。
  4. 根据权利要求3所述的检测电路，其中，所述电压-电流转换电路包括：
    存储电容，其第一端用于与所述阈值生成电路的输出端和所述待检测信号的输入端耦接；
    第一晶体管，控制端用于与所述存储电容的第二端耦接；
    第一电阻，第一端用于与所述第一晶体管的第二端耦接，第二端用于经所述差分采样开关与所述失调电压或参考地电压耦接；以及
    第二晶体管，其控制端用于接收一偏置电压，第二端用于与所述第一晶体管的第一端耦接，第一端用于输出所述比例电流。
  5. 根据权利要求4所述的检测电路，其中，所述电流型逐次逼近量化器包括：
    运算放大器，第一输入端与所述第二晶体管的第一端耦接，第二输入端与一钳位电压耦接；
    电流源阵列，用于基于所述钳位电压生成一参考电流，并提供至所述运算放大器的第一输入端；以及
    比较器，与所述运算放大器的输出端耦接，用于将所述运算放大器 的输出量化为所述比较结果。
  6. 根据权利要求5所述的检测电路，其中，当所述检测结果为所述待检测信号与所述阈值电压的比较结果时，所述电流源阵列提供的所述参考电流为固定电流值。
  7. 根据权利要求5所述的检测电路，其中，当所述检测结果为所述待检测信号在所述阈值电压限定的窗口内的量化结果时，所述电流源阵列提供的所述参考电流为可变电流值，通过调节所述参考电流的电流值获得所述量化结果。
  8. 根据权利要求7所述的检测电路，其中，电流型逐次逼近量化器还包括：
    SAR逻辑电路，用于根据所述比较结果控制所述电流源阵列切换，以逐次逼近的方式调节所述参考电流的电流值，直至量化结束。
  9. 根据权利要求4所述的检测电路，其中，还包括：
    第一开关，配置为在阈值建立阶段耦接所述存储电容的第一端与所述阈值电压生成电路的输出端；
    第二开关，配置为在检测阶段耦接将所述存储电容的第一端与所述待检测信号的输入端。
  10. 根据权利要求9所述的检测电路，其中，还包括：
    第三开关，配置为在所述阈值建立阶段的第一子阶段将所述存储电容的第一端接地，以实现电荷复位。
  11. 根据权利要求10所述的检测电路，其中，所述阈值建立阶段还包括所述第一子阶段之后的第二子阶段，所述阈值电压生成电路配置为在所述第二子阶段生成所述阈值电压。
  12. 根据权利要求9所述的检测电路，其中，所述电压-电流转换电路还包括：
    第四开关，配置为在所述阈值建立阶段耦接所述第一晶体管的控制端和第一端。
  13. 根据权利要求1所述的检测电路，其中，所述检测电路包括多个输入端，所述检测电路配置为以分时的方式检测所述多个输入端的待 检测信号。
  14. 根据权利要求13所述的检测电路，其中，还包括寄存器阵列，用于存储与所述多个输入端的待检测信号对应的多个控制码，所述阈值电压生成电路基于所述寄存器阵列提供的控制码产生对应的阈值电压。
  15. 根据权利要求14所述的检测电路，其中，所述阈值电压生成电路为电容型数模转换器。
  16. 一种电源管理系统，包括权利要求1至15任一项所述的检测电路。
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