WO2023122863A1 - 一种集成电路、其制备方法及电子设备 - Google Patents

一种集成电路、其制备方法及电子设备 Download PDF

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Publication number
WO2023122863A1
WO2023122863A1 PCT/CN2021/141529 CN2021141529W WO2023122863A1 WO 2023122863 A1 WO2023122863 A1 WO 2023122863A1 CN 2021141529 W CN2021141529 W CN 2021141529W WO 2023122863 A1 WO2023122863 A1 WO 2023122863A1
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Prior art keywords
integrated circuit
channel
layer
substrate
channel layer
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PCT/CN2021/141529
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English (en)
French (fr)
Inventor
戴淑君
仲正
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华为技术有限公司
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Priority to CN202180097680.1A priority Critical patent/CN117223107A/zh
Priority to PCT/CN2021/141529 priority patent/WO2023122863A1/zh
Publication of WO2023122863A1 publication Critical patent/WO2023122863A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors

Definitions

  • the present application relates to the technical field of semiconductors, in particular to an integrated circuit, its preparation method and electronic equipment.
  • the surface of the channel layer usually formed on the substrate, the active regions in each circuit area are separated from each other, and the charges introduced in the subsequent manufacturing will accumulate in the separated active regions and cannot be quickly conducted away. , leading to charge accumulation, which will cause internal damage in the active region and have a great impact on the reliability of the integrated circuit.
  • the application provides an integrated circuit, its preparation method and electronic equipment, aiming at improving the antistatic ability of the device.
  • the present application provides an integrated circuit, including: a substrate, and a channel layer located on the substrate.
  • the integrated circuit may be a field effect transistor, or may also be a high electron mobility transistor, and may also include a source, a drain, and a gate.
  • the integrated circuit may also be a semiconductor triode, and may also include a collector, a base, an emitter, and the like.
  • the integrated circuit may also include: a nucleation layer located between the substrate and the channel layer, and a barrier layer located above the channel layer, and may further include: The buffer layer between the core layer and the channel layer.
  • a passivation layer may also be covered on the barrier layer.
  • the material of the substrate can be a high-resistance substrate, such as a high-insulation SiC substrate, whose resistivity is about 10 9 ⁇ cm2, and a high-resistance Si substrate, whose resistivity is about 10 3 ⁇ cm2. cm2, or the substrate can also be a conductive substrate, such as a sapphire substrate.
  • the material of the nucleation layer can be selected from materials such as AlN
  • the material of the buffer layer can be selected from insulating materials such as AlGaN
  • the material of the channel layer can be selected from conductive materials such as GaN
  • the material of the barrier layer can be selected from insulating materials such as AlGaN.
  • the surface of the channel layer (when the integrated circuit is a high electron mobility transistor, it can be considered as the interface between the channel layer and the barrier layer) may include an active region, an insulating region and a conductive channel , the insulating region is arranged around the active region, and the conductive channel passes through the insulating region and connects the active region and the edge of the integrated circuit.
  • the active area can be connected to the edge of the integrated circuit, so that the electrostatic charge that may be generated in the active area can be conducted away through the edge of the integrated circuit as soon as possible, avoiding the accumulation of charges. Static damage or even burn the integrated circuit.
  • the conductive channels can connect the original discrete active areas in each circuit area to the scribing lane between the circuits (the wafer is cut along the scribing lane). Cutting the wafer to form multiple independent integrated circuits) to realize the conduction between the active regions in each circuit area in the wafer.
  • the charge can be guided away as soon as possible through the conductive channel, so that the entire wafer
  • the active regions in each circuit area are in an equipotential state, and charges will not accumulate in a single circuit area to cause damage to the integrated circuit.
  • the charges accumulated in the dicing track can be conducted away after the dicing track is grounded during the integrated circuit testing process or by using other metal connection methods.
  • the conductive channel in order to conduct the charges in the active area away as soon as possible and avoid electrostatic damage caused by charge accumulation, can choose the shortest path, that is, the conductive channel generally connects the first edge of the active area and the first edge of the active area.
  • the first edge and the second edge can be at any positions on the top, bottom, left, and right sides of the integrated circuit, the number of conductive channels can be one or multiple, and the width of the conductive channels can also be any value.
  • the width of the scribe lane set in the wafer is generally larger than the cutting width due to the allowable alignment offset error, for example, the scribe lane
  • the width of the wafer is 80um, and the width of the wafer cut by a blade or laser is 60um. If there is no or a slight offset, a scribe line of about 10um may remain on one edge of the integrated circuit after cutting along a scribe line.
  • the scribe lane conducts electricity, so the remaining scribe lane can be used as a conductive channel; if there is a certain offset during the cutting process, that is, the scribe lane at the edge of the integrated circuit may be completely cut off during the cutting process, then there may be no Scribe lanes will remain.
  • the scribe lanes may be present on at least one edge of the integrated circuit, and the scribe lanes may be located on multiple edges of the integrated circuit. When cutting along the edge of the integrated circuit with less offset, scribe lanes can be formed around the insulating regions in the final formed integrated circuit.
  • the epitaxial structure in order to realize the formation of an insulating region isolating the integrated circuits at the interface between the barrier layer and the channel layer, after the epitaxial growth of the barrier layer and the channel layer on the wafer, the epitaxial structure can be Nitrogen ions or argon ions are implanted at the position corresponding to the insulating region on the surface of the surface, and nitrogen ions or argon ions are not implanted at the positions corresponding to the active region and the conductive channel, so that the barrier layer and the channel layer are implanted with nitrogen ions at the positions corresponding to the insulating region or argon ions for insulating materials.
  • At least part of the scribe lane needs to ensure conductivity, for example, all the scribe lanes are conductive, or when the conductive channel is located in the circuit On the left and/or right side of the area, only the scribe lanes in the column direction may be conductive, or when the conductive channel is located on the upper side and/or lower side of the circuit area, only the scribe lanes in the row direction may be conductive, Nitrogen ions or argon ions cannot be implanted at the positions corresponding to the conductive scribe lanes.
  • silicon ions can also be implanted on the surface of the epitaxial structure at positions corresponding to the scribing lanes to improve the conductivity of the scribing lanes.
  • magnesium can be implanted at the position corresponding to the active region and the conductive channel on the surface of the epitaxial structure Ions, so that the part of the barrier layer and the channel layer close to the barrier layer is a P-type semiconductor material implanted with magnesium ions at the corresponding position of the active region and the conductive channel, so that the conductivity of the active region and the conductive channel is better.
  • magnesium ions can also be implanted on the surface of the epitaxial structure corresponding to the scribing lane to improve the conductivity of the scribing lane.
  • the barrier layer is an insulating material; when silicon ions or magnesium ions are implanted on the surface of the integrated circuit, the barrier layer is an N-type semiconductor material or a P-type semiconductor Material.
  • the present application provides a method for preparing an integrated circuit provided in any example of the above-mentioned first aspect, including: forming a channel layer on a substrate, the substrate is divided into a plurality of circuit regions arranged in an array and located in the circuit Scribing lanes between regions; nitrogen ions or argon ions are implanted in part of the circuit region, so that the surface of the channel layer forms an insulating region at the ion-implanted position, and an active region and a conductive channel are formed at the non-ion-implanted position , the insulating region is arranged around the active region, the conductive channel passes through the insulating region and connects the active region and the scribing lane; the substrate is cut along the scribing lane to form a plurality of integrated circuits.
  • the integrated circuit may specifically be a field effect transistor, or may also be a high electron mobility transistor.
  • the nucleation layer can be formed on the substrate first, and then the channel layer and barrier layer can be formed. Further, a buffer layer may also be formed on the nucleation layer, and then a channel layer and a barrier layer may be formed.
  • the integrated circuit is a high electron mobility transistor
  • the two-dimensional electron gas formed at the interface between the channel layer and the barrier layer is fully conductive, and there will be no Static damage.
  • the conductive channel can connect the originally separated active regions in each circuit region to the scribing lanes between the circuits, so as to realize the active region in each circuit region in the wafer.
  • the charges can be conducted away as soon as possible through the conductive channel, so that the active regions in each circuit region on the entire wafer are in an equipotential state, and the charges will not gather in a single In the circuit area, it will cause damage to the integrated circuit. Also, the charges accumulated in the scribe lanes can be conducted away after the scribe lanes are grounded during integrated circuit testing or by using other metal connections.
  • the material of the substrate can be a high-resistance substrate, such as a high-insulation SiC substrate, whose resistivity is about 10 9 ⁇ cm 2 , and a high-resistance Si substrate, whose resistivity is about 10 3 ⁇ cm 2 , or, the substrate may also be a conductive substrate, such as a sapphire substrate, which is not limited here.
  • the material of the nucleation layer can be selected from materials such as AlN
  • the material of the buffer layer can be selected from insulating materials such as AlGaN
  • the material of the channel layer can be selected from conductive materials such as GaN
  • the material of the barrier layer can be selected from insulating materials such as AlGaN.
  • the nucleation layer, buffer layer, channel layer and barrier layer can all be obtained by epitaxial growth on the substrate.
  • the active region, the conductive channel and the scribe lane can be Implanting silicon ions, so that the part of the barrier layer and the channel layer close to the barrier layer is an N-type semiconductor material implanted with silicon ions at the positions corresponding to the active area, the conductive channel and the scribe lane, so that the active area, the conductive channel and the Scribe lanes are more conductive.
  • magnesium ions can be implanted at the positions of the active region, the conductive channel and the scribe lane, so that the barrier layer and The part of the channel layer close to the barrier layer is a P-type semiconductor material implanted with magnesium ions at the corresponding positions of the active area, the conductive channel and the scribe track, so that the conductivity of the active area, the conductive channel and the scribe track is better.
  • a passivation layer may also be formed on the barrier layer to alleviate the current collapse effect. Specifically, the passivation layer is etched away at the position corresponding to the scribe lane.
  • the width of the scribe line set in the wafer is generally larger than the cutting width, for example, the width of the scribe line It is 80um, and the width of the wafer cut by a blade or laser is 60um. If there is no or a slight offset, a scribe line of about 10um may remain on one edge of the integrated circuit after cutting along a scribe line. Conductive, so the residual scribe lane can be used as a conductive channel; if there is a certain offset during the cutting process, that is, the scribe lane on the edge of the integrated circuit may be completely cut off during the cutting process, there may be no residue on a certain edge of the integrated circuit Scribe road.
  • the scribe lane can exist on at least one edge of the integrated circuit, and the scribe lane can also be located on multiple edges of the integrated circuit, and the cutting offset is less when cutting along the edge of the integrated circuit, Scribing lanes disposed around the insulating region can then be formed in the finally formed integrated circuit.
  • the present application provides an electronic device, which includes a circuit board and an integrated circuit as described in various implementation manners of the first aspect disposed on the circuit board.
  • Figure 1a is a schematic structural view of a conventional epitaxial structure
  • FIG. 1b is another structural schematic diagram of a conventional epitaxial structure
  • FIG. 2 is a schematic top view of a conventional wafer
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a conventional wafer
  • FIG. 4 is a schematic cross-sectional structure diagram of an integrated circuit provided by an embodiment of the present application.
  • Fig. 5a is a schematic cross-sectional structure diagram of another integrated circuit provided by the embodiment of the present application.
  • Fig. 5b is a schematic cross-sectional structure diagram of another integrated circuit provided by the embodiment of the present application.
  • FIG. 6 is a schematic top view of the interface between the channel layer and the barrier layer in the integrated circuit provided by the embodiment of the present application;
  • FIG. 7 is a schematic top view of the interface between the channel layer and the barrier layer in the wafer provided by the embodiment of the present application.
  • FIG. 8 is another schematic top view of the interface between the channel layer and the barrier layer in the integrated circuit provided by the embodiment of the present application.
  • FIG. 9 is another schematic top view of the interface between the channel layer and the barrier layer in the integrated circuit provided by the embodiment of the present application.
  • FIG. 10 is a schematic diagram of another top view structure of the interface between the channel layer and the barrier layer in the wafer provided by the embodiment of the present application;
  • Fig. 11 is a schematic diagram of a cross-sectional structure along the OO direction in Fig. 10;
  • Fig. 12 is a schematic diagram of another cross-sectional structure along the OO direction in Fig. 10;
  • FIG. 13 is a schematic flowchart of a method for manufacturing an integrated circuit provided by an embodiment of the present application.
  • Gallium nitride (GaN)-based high electron mobility transistor (High Electron Mobility Transistor, HEMT) has developed rapidly in the past 30 years. Compared with gallium arsenide (GaAs) HEMT, GaN HEMT has a higher breakdown voltage and higher The electron saturation speed, higher frequency, many research institutes and companies join the ranks of its research.
  • GaN materials have performance advantages such as large band gap, high breakdown field strength, high polarization coefficient, high electron mobility and electron saturation drift speed, and have great application prospects in the fields of power electronics and radio frequency.
  • GaN HEMT devices mainly use the two-dimensional electron gas generated by the polarization effect at the AlGaN/GaN heterojunction interface to achieve high electron mobility. This device has the advantages of high withstand voltage, high power density, and fast working speed.
  • Microwave radio frequency devices mainly use GaN devices as power amplifiers.
  • the function of the power amplifier is to amplify the radio frequency signal inside the active antenna unit (AAU) of the base station, and then transmit it through the antenna.
  • Power electronic devices mainly use GaN devices as power switches, as fast charging for mobile phones and other terminal products, and as switches for lidar.
  • GaN-based radio frequency devices are usually epitaxially grown on high-resistance substrates, such as high-insulation silicon carbide (SiC) substrates (with a resistivity of about 10 9 ⁇ cm 2 ), high-resistance silicon (Si) Substrate (whose resistivity is about 10 3 ⁇ cm 2 ), etc.
  • SiC high-insulation silicon carbide
  • Si high-resistance silicon
  • a conventional epitaxial structure may include an AlGaN barrier layer, a GaN channel layer, an AlN nucleation layer, and a SiC substrate from top to bottom; or, referring to Figure 1b, a conventional epitaxial structure may sequentially from top to bottom Including AlGaN barrier layer, GaN channel layer, AlGaN buffer layer, AlN nucleation layer and Si substrate.
  • the surface layer of the epitaxial structure is a non-conductive AlGaN material, and its thickness is about 20nm.
  • N nitrogen
  • the method of implanting nitrogen (N) ions is often used in the preparation process to isolate the circuit area on the wafer (wafer), so a separate active area will appear on the surface of the wafer (the active area can also be called a conductive area. ).
  • the surface of the wafer will also be covered with a passivation layer formed of non-conductive dielectric materials such as SiN/SiO. Therefore, in the subsequent process, such as cleaning, plasma bombardment and other processes The introduced charge will accumulate in the separated active region, causing internal damage of the active region and having a great impact on the reliability of the device.
  • the area filled with dots in Figure 3 is the area where nitrogen ions are implanted, and then carried out on the surface of the epitaxial structure Passivation treatment, that is, using a dielectric material such as SiN or SiO to form a passivation layer covering the entire surface of the epitaxial structure, and etching the part of the passivation layer in the scribing lane D between the circuit regions S, and then following the scribing lane D-dicing the wafer 100 to form multiple individual devices.
  • Passivation treatment that is, using a dielectric material such as SiN or SiO to form a passivation layer covering the entire surface of the epitaxial structure, and etching the part of the passivation layer in the scribing lane D between the circuit regions S, and then following the scribing lane D-dicing the wafer 100 to form multiple individual devices.
  • the etching process such as plasma bombardment or cleaning
  • the charge will accumulate on the surface of the epitaxial structure, resulting in instantaneous High voltage causes damage to the formed device, or burns the device during device testing, or causes potential damage, affecting the life of the device.
  • embodiments of the present application provide an integrated circuit that can solve the above problems, its manufacturing method, and electronic equipment, which will be described in detail below with reference to specific drawings and embodiments.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • Figure 4 exemplarily shows a schematic cross-sectional structure of an integrated circuit provided in an embodiment of the present application
  • Figure 5a schematically shows a schematic cross-sectional structure of another integrated circuit provided in an embodiment of the present application
  • Figure 5b exemplarily shows a schematic cross-sectional structure of an integrated circuit provided in an embodiment of the present application
  • a schematic cross-sectional structure diagram of another integrated circuit provided by the embodiment of the present application is shown.
  • the integrated circuit may include: a substrate 1 , and a channel layer 4 located on the substrate 1 .
  • the integrated circuit may be a field effect transistor, or may also be a high electron mobility transistor, and may further include a source 7 , a drain 8 , and a gate 9 .
  • the integrated circuit may also be a semiconductor triode, and may also include a collector, a base, an emitter, and the like.
  • the integrated circuit may further include: a nucleation layer 2 located between the substrate 1 and the channel layer 4, and a nucleation layer located between the channel layer 4 and The barrier layer 5 above the channel layer 4; referring to FIG. 5b, in another embodiment of the present application, the integrated circuit may further include: a buffer layer 3 located between the nucleation layer 2 and the channel layer 4. Moreover, referring to FIG. 5 a and FIG. 5 b , in order to alleviate the current collapse effect, a passivation layer 6 may also be covered on the barrier layer 5 .
  • the material of the substrate 1 can be a high-resistance substrate, such as a high-insulation SiC substrate, whose resistivity is about 10 9 ⁇ cm 2 , and a high-resistance Si substrate, whose resistivity is about 10 3 ⁇ cm 2 , or, the substrate 1 may also be a conductive substrate, such as a sapphire substrate, which is not limited here.
  • a high-resistance substrate such as a high-insulation SiC substrate, whose resistivity is about 10 9 ⁇ cm 2
  • a high-resistance Si substrate whose resistivity is about 10 3 ⁇ cm 2
  • the substrate 1 may also be a conductive substrate, such as a sapphire substrate, which is not limited here.
  • the material of the nucleation layer 2 can be selected from materials such as AlN
  • the material of the buffer layer 3 can be selected from insulating materials such as AlGaN
  • the material of the channel layer 4 can be selected from conductive materials such as GaN
  • the material of the barrier layer 5 can be selected from insulating materials such as AlGaN.
  • Figure 6 schematically shows a schematic top view of the interface between the channel layer and the barrier layer in the integrated circuit provided by the embodiment of the present application
  • Figure 7 schematically shows the trench in the wafer provided by the embodiment of the present application
  • the surface of the channel layer 4 (when the integrated circuit is a high electron mobility transistor, it can be considered as the interface between the channel layer 4 and the barrier layer 5) can include active Area A, insulating area B and conductive channel C, the insulating area B is arranged around the active area A, the conductive channel C passes through the insulating area B and connects the active area A and the edge of the integrated circuit.
  • the active area A can be connected to the edge of the integrated circuit, so that the electrostatic charge that may be generated in the active area A can be conducted away through the edge of the integrated circuit as soon as possible.
  • the conductive channel C can connect the active area A that is originally separated from each other in each circuit area S to the gap between the circuits.
  • Scribing lane D (the wafer 100 is cut along the dicing lane D to form multiple independent integrated circuits), to realize the conduction between the active regions A in each circuit area S in the wafer 100, when the charge reaches the surface of the wafer 100 Charges can be led away as soon as possible through the conductive channel C, so that the active regions A in the circuit regions S on the entire wafer 100 are in an equipotential state, and the charges will not accumulate in a single circuit region S to cause damage to the integrated circuit. And the charges accumulated in the scribe track D can be conducted away after the scribe track is grounded during the integrated circuit testing process or by using other metal connection methods.
  • the conductive channel C in order to conduct the charges in the active region A away as soon as possible and avoid electrostatic damage caused by charge accumulation, can choose the shortest path, that is, the conductive channel C is generally connected to the first edge of the active region A and the second edge of the integrated circuit closest to the first edge. Specifically, the first edge and the second edge can be at any position on the top, bottom, left, and right of the integrated circuit.
  • Figure 6 shows an example that the conductive channel C is located on the left side of the integrated circuit, and the number of conductive channels C can be one or multiple. It is not limited here.
  • the width of the conductive channel C can also be any value, which is not limited here.
  • Fig. 8 exemplarily shows another top view structural diagram of the interface between the channel layer and the barrier layer in the integrated circuit provided by the embodiment of the present application
  • Fig. 9 exemplarily shows that in the integrated circuit provided by the embodiment of the present application Schematic diagram of another top view structure of the interface between the channel layer and the barrier layer.
  • the width of the scribing lane set in the wafer is generally larger than the cutting width due to a certain alignment offset error.
  • the width of the scribing lane is 80um.
  • the width of the laser cut wafer is 60um. If there is no or a slight offset, a scribe line of about 10um may remain on one edge of the integrated circuit after cutting along a scribe line.
  • the scribe line is conductive, the remaining The scribe lane can be used as a conductive channel; if there is a certain deviation during the cutting process, that is, the scribe lane at the edge of the integrated circuit may be completely cut off during the cutting process, there may be no scribe lane remaining on a certain edge of the integrated circuit. Therefore, referring to FIG. 8 , in the final integrated circuit, the scribe line D may exist on at least one edge of the integrated circuit. In FIG. It can also be located on multiple edges of the integrated circuit. Referring to FIG. 9 , when cutting along the edge of the integrated circuit has less cutting offset, a scribe lane D disposed around the insulating region B can be formed in the finally formed integrated circuit.
  • Fig. 10 schematically shows another top view structural diagram of the interface between the channel layer and the barrier layer in the wafer provided by the embodiment of the present application
  • Fig. 11 schematically shows a kind of interface along the OO direction in Fig. 10 Schematic diagram of the cross-sectional structure.
  • the surface of the epitaxial structure can be implanted with nitrogen ions or argon ions at the position corresponding to the insulating region B (the region filled with dots in FIG. 11 is the region where nitrogen ions or argon ions are implanted, and the horizontal dotted line in FIG.
  • nitrogen ions or argon ions are not implanted at the positions corresponding to the active region A and the conductive channel C, so that the barrier layer 5 and the channel layer 4 correspond to the insulating region B
  • the position is the insulating material implanted with nitrogen ions or argon ions.
  • at least part of the scribe lane D needs to ensure electrical conductivity. For example, all the scribe lanes D shown in FIG.
  • FIG. 12 schematically shows another schematic cross-sectional structure along the OO direction in FIG. 10 .
  • the epitaxial structure is implanted with silicon ions at the position corresponding to the active region A and the conductive channel C, so that the part of the barrier layer 5 and the channel layer 4 close to the barrier layer 5 is implanted at the corresponding position of the active region A and the conductive channel C.
  • the N-type semiconductor material of silicon ions makes the conductivity of the active region A and the conductive channel C better.
  • silicon ions can also be implanted at the position corresponding to the scribing track D on the surface of the epitaxial structure to improve the conductivity of the scribing track D.
  • the surface of the epitaxial structure can correspond to the active region A and the conductive channel C
  • Magnesium ions are implanted into the position, so that the part of the barrier layer 5 and the channel layer 4 close to the barrier layer 5 is a P-type semiconductor material implanted with magnesium ions at the position corresponding to the active region A and the conductive channel C, so that the active region The conductivity of A and conductive channel C is better.
  • magnesium ions can also be implanted at the surface of the epitaxial structure at the position corresponding to the scribing track D to improve the conductivity of the scribing track D.
  • the region filled with dense dots in Figure 12 is the region implanted with nitrogen ions or argon ions
  • the region filled with sparse dots is the region implanted with silicon ions or magnesium ions
  • the horizontal dotted line shows the region between the barrier layer and the channel layer A two-dimensional electron gas formed at the interface between them.
  • the barrier layer 5 is an insulating material, and when silicon ions or magnesium ions are implanted on the surface of the integrated circuit, the barrier layer 5 is an N-type semiconductor material or a P type semiconductor material.
  • FIG. 13 exemplarily shows a schematic flowchart of a method for manufacturing an integrated circuit provided by an embodiment of the present application.
  • the integrated circuit can be prepared by the following preparation method, which includes the following steps:
  • a channel layer is formed on a substrate, and the substrate is divided into a plurality of circuit regions arranged in an array and scribe lanes between the circuit regions.
  • the integrated circuit may specifically be a field effect transistor, or may also be a high electron mobility transistor.
  • a nucleation layer can be formed on the substrate first, then a channel layer can be formed, and a barrier layer can be formed on the channel layer.
  • a buffer layer may also be formed on the nucleation layer, and then a channel layer may be formed.
  • the material of the substrate can be a high-resistance substrate, such as a high-insulation SiC substrate with a resistivity of about 10 9 ⁇ cm 2 , a high-resistance Si substrate with a resistivity of about 10 3 ⁇ cm 2 , or , the substrate may also be a conductive substrate, such as a sapphire substrate, which is not limited here.
  • the material of the nucleation layer can be selected from materials such as AlN
  • the material of the buffer layer can be selected from insulating materials such as AlGaN
  • the material of the channel layer can be selected from conductive materials such as GaN
  • the material of the barrier layer can be selected from insulating materials such as AlGaN.
  • the nucleation layer, buffer layer, channel layer and barrier layer can all be obtained by epitaxial growth on the substrate.
  • Implant nitrogen ions or argon ions in part of the circuit area so that the surface of the channel layer forms an insulating region at the ion-implanted position, and forms an active region and a conductive channel at a position that is not ion-implanted.
  • the insulating region is surrounded by The source area is provided, and the conductive channel passes through the insulating area and communicates with the active area and the scribe lane. That is, ions are not implanted in the positions corresponding to the scribe lane, the active area and the conductive channel.
  • the integrated circuit is a high electron mobility transistor
  • the two-dimensional electron gas formed at the interface between the channel layer and the barrier layer is fully conductive, and there will be no Static damage.
  • the conductive channel can connect the originally separated active regions in each circuit region to the scribing lanes between the circuits, so as to realize the active region in each circuit region in the wafer.
  • the charges can be conducted away as soon as possible through the conductive channel, so that the active regions in each circuit region on the entire wafer are in an equipotential state, and the charges will not gather in a single In the circuit area, it will cause damage to the integrated circuit. Also, the charges accumulated in the scribe lanes can be conducted away after the scribe lanes are grounded during integrated circuit testing or by using other metal connections.
  • silicon ions can be implanted in the positions of the active region, the conductive channel and the scribe lane, so that the potential barrier
  • the part close to the barrier layer in the layer and channel layer is N-type semiconductor material implanted with silicon ions at the corresponding position of the active area, conductive channel and scribe track, so that the conductivity of the active area, conductive channel and scribe track is better.
  • magnesium ions can be implanted at the positions of the active region, the conductive channel and the scribe lane, so that the barrier layer and The part of the channel layer close to the barrier layer is a P-type semiconductor material implanted with magnesium ions at the corresponding positions of the active area, the conductive channel and the scribe track, so that the conductivity of the active area, the conductive channel and the scribe track is better.
  • a passivation layer can also be formed on the barrier layer to mitigate the current collapse effect. Specifically, the passivation layer is etched away at the position corresponding to the scribe lane.
  • the width of the scribe line set in the wafer is generally larger than the cutting width due to the allowable alignment offset error.
  • the width of the scribe line is 80um, using a blade or laser
  • the width of the cut wafer is 60um. If there is no or slight offset, a scribe line of about 10um may remain on one edge of the integrated circuit after cutting along a scribe line. Since the scribe line is conductive, the remaining scribe line It can be used as a conductive channel; if there is a certain offset during the cutting process, that is, the scribe line on the edge of the integrated circuit may be completely cut off during the cutting process, then there may be no scribe line left on a certain edge of the integrated circuit.
  • the scribe lane can exist on at least one edge of the integrated circuit, and the scribe lane can also be located on multiple edges of the integrated circuit, and the cutting offset is less when cutting along the edge of the integrated circuit, Scribing lanes disposed around the insulating region can then be formed in the finally formed integrated circuit.
  • the embodiment of the present application also provides an electronic device, which may include a circuit board and any integrated circuit provided in the foregoing embodiments of the present application, where the integrated circuit is arranged on the circuit board. Since the problem-solving principle of the electronic device is similar to that of the aforementioned integrated circuit, the implementation of the electronic device can refer to the implementation of the aforementioned integrated circuit, and the repetition will not be repeated.

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Abstract

本申请公开了一种集成电路、其制备方法及电子设备，集成电路包括：衬底，位于衬底之上的沟道层；其中，沟道层的表面可以包括有源区、绝缘区和导电通道，绝缘区围绕有源区设置，导电通道穿过绝缘区且连通有源区和集成电路的边缘。通过在沟道层的表面形成导电通道可以将有源区连通至集成电路的边缘，使在有源区可能产生的静电电荷通过集成电路边缘尽快导走，避免电荷积累产生静电损伤甚至烧毁集成电路。

Description

一种集成电路、其制备方法及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及到一种集成电路、其制备方法及电子设备。
背景技术
集成电路在制作时，通常在衬底上形成的沟道层的表面，各电路区域内的有源区相互分离，在后续制作时引入的电荷将积累在分离的有源区，无法快速导走，导致电荷累积，会造成有源区内部损伤，对集成电路的可靠性带来较大影响。
发明内容
本申请提供一种集成电路、其制备方法及电子设备，旨在提高器件的抗静电能力。
第一方面，本申请提供了一种集成电路，包括：衬底，位于衬底之上的沟道层。集成电路具体可以为场效应晶体管，或者，也可以为高电子迁移率晶体管，还可以包括源极、漏极和栅极等。集成电路具体还可以为半导体三极管，还可以包括集电极、基极和发射极等。当集成电路为高电子迁移率晶体管时，集成电路还可以包括：位于衬底和沟道层之间的成核层，以及位于沟道层之上的势垒层，进一步还可以包括：位于成核层和沟道层之间的缓冲层。并且，为了缓解电流崩塌效应，在势垒层之上还可以覆盖钝化层。具体地，为了避免微波损伤，衬底的材料可以选用高阻衬底，例如高绝缘SiC衬底，其电阻率约10 9Ω·cm2，高阻Si衬底，其电阻率约10 3Ω·cm2，或者，衬底也可以导电衬底，例如蓝宝石衬底等。成核层的材料可以选用AlN等材料，缓冲层的材料可以选用AlGaN等绝缘材料，沟道层的材料可以选用GaN等导电材料，势垒层可以选用AlGaN等绝缘材料。
在本申请实施例中，沟道层的表面(当集成电路为高电子迁移率晶体管时，可以认为在沟道层和势垒层之间的界面)可以包括有源区、绝缘区和导电通道，绝缘区围绕有源区设置，导电通道穿过绝缘区且连通有源区和集成电路的边缘。通过在沟道层和势垒层之间的界面形成导电通道可以将有源区连通至集成电路的边缘，使在有源区可能产生的静电电荷通过集成电路边缘尽快导走，避免电荷积累产生静电损伤甚至烧毁集成电路。在集成电路制备过程中，晶圆未被切割成独立的多个集成电路之前，导电通道可以将各电路区域中原本相互分立的有源区连通至电路之间的划片道(晶圆沿着划片道切割形成独立的多个集成电路)，实现晶圆中各电路区域内有源区之间的导通，当电荷到达晶圆表面时电荷能够通过导电通道尽快被导走，使整个晶圆上的各电路区域中的有源区处于等电位状态，电荷不会聚集在单个电路区域内而导致集成电路产生损伤。并且集聚在划片道中的电荷可以在集成电路测试过程中或采用其他金属连接方式将划片道接地后导走。
在本申请一个可能的实现方式中，为了实现将有源区内的电荷尽快导走，避免电荷聚集产生静电损伤，导电通道可以选取最短路径，即导电通道一般连通有源区的第一边缘和与第一边缘距离最近的集成电路的第二边缘。具体地，第一边缘和第二边缘可以在集成电路上下左右的任意位置，导电通道的数量可以为一个也可以为多个，导电通道的宽度也可以为任意数值。
在本申请一个可能的实现方式中，在晶圆切割成多个集成电路时，由于允许存在一定 的对位偏移误差，在晶圆中设置的划片道宽度一般会大于切割宽度，例如划片道的宽度为80um，采用刀片或激光切割晶圆的宽度为60um，若不存在或存在微量的偏移时，沿着一条划片道切割后在集成电路的一个边缘可能残留约10um的划片道，由于划片道导电，因此残留的划片道可以作为导电通道；若在切割过程中出现一定的偏移，即切割过程中可能完全切割掉集成电路边缘的划片道，则在集成电路的某个边缘可能不会残留划片道。因此，在最终形成的集成电路中，划片道可以存在于集成电路的至少一个边缘，划片道还可以位于集成电路的多个边缘。当沿着集成电路的边缘切割时切割偏移量较少，则在最终形成的集成电路中可以形成围绕绝缘区设置的划片道。
在本申请一个可能的实现方式中，为了实现在势垒层和沟道层之间界面形成隔离各集成电路的绝缘区，在晶圆上外延生长势垒层和沟道层后，可以外延结构的表面对应绝缘区的位置注入氮离子或氩离子，在对应有源区和导电通道的位置不注入氮离子或氩离子，使势垒层和沟道层在绝缘区对应的位置为注入氮离子或氩离子的绝缘材料。并且，为了保证有源区内产生的静电电荷可以通过导电通道连通至划片道而被导走，至少部分的划片道需要保证导电性，例如全部划片道具有导电性，或者当导电通道位于电路区域的左侧和/或右侧时可以仅列方向的划片道具有导电性，或者当导电通道位于电路区域的上侧和/或下侧时可以仅行方向的划片道具有导电性，在具有导电性的划片道对应的位置不能注入氮离子或氩离子。
在本申请一个可能的实现方式中，在晶圆上的外延结构表面对应绝缘区的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以在外延结构的表面对应有源区和导电通道的位置注入硅离子，使势垒层和沟道层中靠近势垒层的部分在有源区和导电通道对应的位置为注入硅离子的N型半导体材料，使有源区和导电通道的导电性更好。同样，也可以外延结构的表面对应划片道的位置注入硅离子，提高划片道的导电性。或者，在晶圆上的外延结构表面对应绝缘区的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以外延结构的表面对应有源区和导电通道的位置注入镁离子，使势垒层和沟道层中靠近势垒层的部分在有源区和导电通道对应的位置为注入镁离子的P型半导体材料，使有源区和导电通道的导电性更好。同样，也可以外延结构的表面对应划片道的位置注入镁离子，提高划片道的导电性。值得注意的是，在集成电路表面未注入硅离子或镁离子时，势垒层为绝缘材料，当在集成电路表面注入硅离子或镁离子后，势垒层为N型半导体材料或P型半导体材料。
第二方面，本申请提供了上述第一方面任意实例的提供的集成电路的制备方法，包括：在衬底上形成沟道层，衬底划分为呈阵列排布的多个电路区域和位于电路区域之间的划片道；在电路区域内的部分区域注入氮离子或氩离子，使沟道层的表面在离子注入的位置形成绝缘区，在未被离子注入的位置形成有源区和导电通道，绝缘区围绕有源区设置，导电通道穿过绝缘区且连通有源区和划片道；沿划片道切割衬底，形成多个集成电路。
在本申请一个可能的实现方式中，集成电路具体可以为场效应晶体管，或者，也可以为高电子迁移率晶体管。当集成电路为高电子迁移率晶体管时，可以先在衬底上形成成核层，之后形成沟道层和势垒层。进一步地，还可以在成核层上形成缓冲层，之后形成沟道层和势垒层。
具体地，当集成电路为高电子迁移率晶体管时，在进行氮离子或氩离子注入之前，在沟道层和势垒层之间的界面形成的二维电子气为整面导电，不会存在静电损伤。在沟道层 和势垒层之间的界面形成绝缘区后，导电通道可以将各电路区域中原本相互分立的有源区连通至电路之间的划片道，实现晶圆中各电路区域内有源区之间的导通，当电荷到达晶圆表面时电荷能够通过导电通道尽快被导走，使整个晶圆上的各电路区域中的有源区处于等电位状态，电荷不会聚集在单个电路区域内而导致集成电路产生损伤。并且，集聚在划片道中的电荷可以在集成电路测试过程中或采用其他金属连接方式将划片道接地后导走。
在本申请一个可能的实现方式中，衬底的材料可以选用高阻衬底，例如高绝缘SiC衬底，其电阻率约10 9Ω·cm 2，高阻Si衬底，其电阻率约10 3Ω·cm 2，或者，衬底也可以导电衬底，例如蓝宝石衬底，在此不做限定。成核层的材料可以选用AlN等材料，缓冲层的材料可以选用AlGaN等绝缘材料，沟道层的材料可以选用GaN等导电材料，势垒层可以选用AlGaN等绝缘材料。成核层、缓冲层、沟道层和势垒层都可以采用在衬底上外延生长的方式获得。
在本申请一个可能的实现方式中，在晶圆对应绝缘区的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以在有源区、导电通道和划片道的位置注入硅离子，使势垒层和沟道层中靠近势垒层的部分在有源区、导电通道和划片道对应的位置为注入硅离子的N型半导体材料，使有源区、导电通道和划片道的导电性更好。或者，在晶圆对应绝缘区的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以有源区、导电通道和划片道的位置注入镁离子，使势垒层和沟道层中靠近势垒层的部分在有源区、导电通道和划片道对应的位置为注入镁离子的P型半导体材料，使有源区、导电通道和划片道的导电性更好。
在本申请一个可能的实现方式中，还可以在势垒层上形成钝化层，以缓解电流崩塌效应。具体地，钝化层在划片道对应的位置处被刻蚀掉。
在本申请一个可能的实现方式中，在切割成多个集成电路时，由于允许存在一定的对位偏移误差，在晶圆中设置的划片道宽度一般会大于切割宽度，例如划片道的宽度为80um，采用刀片或激光切割晶圆的宽度为60um，若不存在或存在微量的偏移时，沿着一条划片道切割后在集成电路的一个边缘可能残留约10um的划片道，由于划片道导电，因此残留的划片道可以作为导电通道；若在切割过程中出现一定的偏移，即切割过程中可能完全切割掉集成电路边缘的划片道，则在集成电路的某个边缘可能不会残留划片道。因此，在最终形成的集成电路中，划片道可以存在于集成电路的至少一个边缘，划片道还可以位于集成电路的多个边缘，当沿着集成电路的边缘切割时切割偏移量较少，则在最终形成的集成电路中可以形成围绕绝缘区设置的划片道。
第三方面，本申请提供了一种电子设备，该电子设备包括电路板以及设置在电路板上的如第一方面的各种实施方式所述的集成电路。
上述第三方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1a为常规的外延结构的一种结构示意图；
图1b为常规的外延结构的另一种结构示意图；
图2为常规的晶圆的俯视示意图；
图3为常规的晶圆的剖面结构示意图；
图4为本申请实施例提供的一种集成电路的剖面结构示意图；
图5a为本申请实施例提供的另一种集成电路的剖面结构示意图；
图5b为本申请实施例提供的另一种集成电路的剖面结构示意图；
图6为本申请实施例提供的集成电路中沟道层和势垒层之间界面的一种俯视结构示意图；
图7为本申请实施例提供的晶圆中沟道层和势垒层之间界面的一种俯视结构示意图；
图8为本申请实施例提供的集成电路中沟道层和势垒层之间界面的另一种俯视结构示意图；
图9为本申请实施例提供的集成电路中沟道层和势垒层之间界面的另一种俯视结构示意图；
图10为本申请实施例提供的晶圆中沟道层和势垒层之间界面的另一种俯视结构示意图；
图11为图10中沿OO方向的一种剖面结构示意图；
图12为图10中沿OO方向的另一种剖面结构示意图；
图13为本申请实施例提供的一种集成电路的制备方法的流程示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
氮化镓(GaN)基高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)在近30年发展迅猛，相比于砷化镓(GaAs)HEMT，GaN HEMT具有更高的击穿电压，更高的电子饱和速度，更高的频率，很多研究所与公司加入其研究行列。
半导体GaN材料具有禁带宽度大、击穿场强高、极化系数高、电子迁移率和电子饱和漂移速度高等性能优势，在电力电子和射频领域应用前景巨大。GaN HEMT器件主要是利用AlGaN/GaN异质结界面处极化效应产生的二维电子气实现高电子迁移率，这种器件具有耐压高、功率密度高、工作速度快等优点。
本申请可以应用于微电子领域：包括微波射频器件和电力电子器件等，也可能扩展到光电器件或者其它微电子领域。微波射频器件主要采用GaN器件做功率放大器，功率放大器的作用是将基站的有源天线单元(active antenna unit，AAU)内部的射频信号放大，然后通过天线发射出去。电力电子器件主要采用GaN器件做功率开关，作为手机等终端产品的快充，激光雷达的开关等。
GaN-based射频器件为避免微波损耗，通常在高阻衬底上进行外延生长，例如高绝缘碳化硅(SiC)衬底(其电阻率约10 9Ω·cm 2)，高阻硅(Si)衬底(其电阻率约10 3Ω·cm 2)等。参照图1a，常规的外延结构从上至下可以依次包括AlGaN势垒层、GaN沟道层、AlN成核层和SiC衬底；或者，参照图1b，常规的外延结构从上至下可以依次包括AlGaN势垒层、GaN沟道层、AlGaN缓冲层、AlN成核层和Si衬底。外延结构的表层是不导电的AlGaN材料，其厚度约为20nm左右，在AlGaN势垒层和GaN沟道层之间的界面有一层导电性较好的二维电子气(2-dimension electron gas，2DEG)。虽然2DEG导电，但制备工艺中常采用注入氮(N)离子的方式将晶圆(wafer)上的电路区域进行隔离，因此wafer表面将出现分离的有源区(有源区也可以称为导电区)。同时为将wafer表面钝化，缓解电 流崩塌效应，在wafer表面还会覆盖采用SiN/SiO等不导电介质材料形成的钝化层，因此在后续的工艺过程中，例如清洗、等离子体轰击等工艺引入的电荷将积累在分离的有源区，造成有源区内部损伤，对器件的可靠性带来较大影响。
具体地，在现有技术中制备的GaN-based射频器件时，参照图2和图3，在晶圆100上外延生长各膜层形成外延结构后，会在势垒层和沟道层之间的界面形成二维电子气，图3中横向虚线所示，在除了电路区域S的有源区A之外的其他区域注入氮(N)离子形成绝缘区B(也称为隔离区)，实现器件与电路之间有源区A的隔离，同时在电路区域S之间的划片道D也会注入氮离子，图3中填充点的区域为氮离子注入的区域，之后在外延结构的表面进行钝化处理，即采用SiN或SiO等介质材料形成覆盖外延结构整个表面的钝化层，并对钝化层在电路区域S之间的划片道D内的部分进行刻蚀，后续沿着划片道D切割晶圆100形成多个独立的器件。在刻蚀工艺过程中，例如等离子体轰击或清洗等工艺，若有电荷轰击到外延结构的表面，由于衬底为高阻衬底不导电，则电荷会积累在外延结构的表面，导致产生瞬间高压，对形成的器件造成损伤，或者在器件测试过程中烧毁器件，或者造成潜在的损伤，影响器件寿命。
为此，本申请实施例提供了一种可以解决上述问题的集成电路、其制备方法及电子设备，下面结合具体的附图以及实施例对其进行详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
图4示例性示出了本申请实施例提供的一种集成电路的剖面结构示意图，图5a示例性示出了本申请实施例提供的另一种集成电路的剖面结构示意图，图5b示例性示出了本申请实施例提供的另一种集成电路的剖面结构示意图。
参照图4，在本申请实施例中，集成电路可以包括：衬底1，位于衬底1之上的沟道层4。集成电路具体可以为场效应晶体管，或者，也可以为高电子迁移率晶体管，还可以包括源极7、漏极8和栅极9等。集成电路具体还可以为半导体三极管，还可以包括集电极、基极和发射极等。当集成电路为高电子迁移率晶体管时，参照图5a，在本申请另一实施例中，集成电路还可以包括：位于衬底1和沟道层4之间的成核层2，以及位于沟道层4之上的势垒层5；参照图5b，在本申请另一实施例中，集成电路还可以包括：位于成核层2和沟道层4之间的缓冲层3。并且，参照图5a和图5b，为了缓解电流崩塌效应，在势垒层5之上还可以覆盖钝化层6。具体地，为了避免微波损伤，衬底1的材料可以选用高阻衬底，例如高绝缘SiC衬底，其电阻率约10 9Ω·cm 2，高阻Si衬底，其电阻率约10 3Ω·cm 2，或者，衬底1也可以导电衬底，例如蓝宝石衬底，在此不做限定。成核层2的材料可以选用AlN等材料，缓冲层3的材料可以选用AlGaN等绝缘材料，沟道层4的材料可 以选用GaN等导电材料，势垒层5可以选用AlGaN等绝缘材料。
图6示例性示出了本申请实施例提供的集成电路中沟道层和势垒层之间界面的一种俯视结构示意图，图7示意性示出了本申请实施例提供的晶圆中沟道层和势垒层之间界面的一种俯视结构示意图。
参照图6，在本申请实施例中，沟道层4的表面(当集成电路为高电子迁移率晶体管时，可以认为在沟道层4和势垒层5之间的界面)可以包括有源区A、绝缘区B和导电通道C，绝缘区B围绕有源区A设置，导电通道C穿过绝缘区B且连通有源区A和集成电路的边缘。通过在沟道层4和势垒层5之间的界面形成导电通道C可以将有源区A连通至集成电路的边缘，使在有源区A可能产生的静电电荷通过集成电路边缘尽快导走，避免电荷积累产生静电损伤甚至烧毁集成电路。参照图7，在集成电路制备过程中，晶圆100未被切割成独立的多个集成电路之前，导电通道C可以将各电路区域S中原本相互分立的有源区A连通至电路之间的划片道D(晶圆100沿着划片道D切割形成独立的多个集成电路)，实现晶圆100中各电路区域S内有源区A之间的导通，当电荷到达晶圆100表面时电荷能够通过导电通道C尽快被导走，使整个晶圆100上的各电路区域S中的有源区A处于等电位状态，电荷不会聚集在单个电路区域S内而导致集成电路产生损伤。并且集聚在划片道D中的电荷可以在集成电路测试过程中或采用其他金属连接方式将划片道接地后导走。
在本申请实施例中，为了实现将有源区A内的电荷尽快导走，避免电荷聚集产生静电损伤，导电通道C可以选取最短路径，即导电通道C一般连通有源区A的第一边缘和与第一边缘距离最近的集成电路的第二边缘。具体地，第一边缘和第二边缘可以在集成电路上下左右的任意位置，图6举例示意出导电通道C位于集成电路的左侧位置，导电通道C的数量可以为一个也可以为多个，在此不做限定。导电通道C的宽度也可以为任意数值，在此不做限定。
图8示例性示出了本申请实施例提供的集成电路中沟道层和势垒层之间界面的另一种俯视结构示意图，图9示例性示出了本申请实施例提供的集成电路中沟道层和势垒层之间界面的另一种俯视结构示意图。
具体地，在晶圆切割成多个集成电路时，由于允许存在一定的对位偏移误差，在晶圆中设置的划片道宽度一般会大于切割宽度，例如划片道的宽度为80um，采用刀片或激光切割晶圆的宽度为60um，若不存在或存在微量的偏移时，沿着一条划片道切割后在集成电路的一个边缘可能残留约10um的划片道，由于划片道导电，因此残留的划片道可以作为导电通道；若在切割过程中出现一定的偏移，即切割过程中可能完全切割掉集成电路边缘的划片道，则在集成电路的某个边缘可能不会残留划片道。因此，参照图8，在最终形成的集成电路中，划片道D可以存在于集成电路的至少一个边缘，图8中是以划片道D位于集成电路的一个边缘为例进行示意说明，划片道D还可以位于集成电路的多个边缘。参照图9，当沿着集成电路的边缘切割时切割偏移量较少，则在最终形成的集成电路中可以形成围绕绝缘区B设置的划片道D。
图10示意性示出了本申请实施例提供的晶圆中沟道层和势垒层之间界面的另一种俯视结构示意图，图11示意性示出了图10中沿OO方向的一种剖面结构示意图。
参照图10和图11，为了实现在势垒层5和沟道层4之间界面形成隔离各集成电路的绝缘区B，在晶圆100上外延生长势垒层5和沟道层4后，可以外延结构的表面对应绝缘区B的位置注入氮离子或氩离子(图11中填充点的区域为氮离子或氩离子注入的区域， 图11中横向虚线示出了在势垒层5和沟道层4之间的界面形成的二维电子气)，在对应有源区A和导电通道C的位置不注入氮离子或氩离子，使势垒层5和沟道层4在绝缘区B对应的位置为注入氮离子或氩离子的绝缘材料。并且，为了保证有源区A内产生的静电电荷可以通过导电通道C连通至划片道D而被导走，至少部分的划片道D需要保证导电性，例如图10所示的全部划片道D具有导电性，或者当导电通道C位于电路区域S的左侧和/或右侧时可以仅列方向的划片道D具有导电性，或者当导电通道C位于电路区域S的上侧和/或下侧时可以仅行方向的划片道具有导电性，在具有导电性的划片道对应的位置不能注入氮离子或氩离子。
图12示意性示出了图10中沿OO方向的另一种剖面结构示意图。
参照图12，在本申请另一实施例中，在晶圆100上的外延结构表面对应绝缘区B的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以在外延结构的表面对应有源区A和导电通道C的位置注入硅离子，使势垒层5和沟道层4中靠近势垒层5的部分在有源区A和导电通道C对应的位置为注入硅离子的N型半导体材料，使有源区A和导电通道C的导电性更好。同样，也可以外延结构的表面对应划片道D的位置注入硅离子，提高划片道D的导电性。或者，在晶圆100上的外延结构表面对应绝缘区B的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以外延结构的表面对应有源区A和导电通道C的位置注入镁离子，使势垒层5和沟道层4中靠近势垒层5的部分在有源区A和导电通道C对应的位置为注入镁离子的P型半导体材料，使有源区A和导电通道C的导电性更好。同样，也可以外延结构的表面对应划片道D的位置注入镁离子，提高划片道D的导电性。图12中填充密点的区域为氮离子或氩离子注入的区域，填充疏点的区域为硅离子注入的区域或镁离子注入的区域，横向虚线示出了在势垒层和沟道层之间的界面形成的二维电子气。值得注意的是，在集成电路表面未注入硅离子或镁离子时，势垒层5为绝缘材料，当在集成电路表面注入硅离子或镁离子后，势垒层5为N型半导体材料或P型半导体材料。
为了方便理解本申请实施例提供的集成电路，下面结合附图详细说明其制备方法。图13示例性示出了本申请实施例提供的一种集成电路的制备方法的流程示意图。
参照图13，集成电路可以采用如下制备方法制备而成，该方法包括以下步骤：
S1、在衬底上形成沟道层，衬底划分为呈阵列排布的多个电路区域和位于电路区域之间的划片道。
可选地，集成电路具体可以为场效应晶体管，或者，也可以为高电子迁移率晶体管。当集成电路为高电子迁移率晶体管时，可以先在衬底上形成成核层，之后形成沟道层，并在沟道层上形成势垒层。进一步地，还可以在成核层上形成缓冲层，之后形成沟道层。
具体地，衬底的材料可以选用高阻衬底，例如高绝缘SiC衬底，其电阻率约10 9Ω·cm 2，高阻Si衬底，其电阻率约10 3Ω·cm 2，或者，衬底也可以导电衬底，例如蓝宝石衬底，在此不做限定。成核层的材料可以选用AlN等材料，缓冲层的材料可以选用AlGaN等绝缘材料，沟道层的材料可以选用GaN等导电材料，势垒层可以选用AlGaN等绝缘材料。成核层、缓冲层、沟道层和势垒层都可以采用在衬底上外延生长的方式获得。
S2、在电路区域内的部分区域注入氮离子或氩离子，使沟道层的表面在离子注入的位置形成绝缘区，在未被离子注入的位置形成有源区和导电通道，绝缘区围绕有源区设置，导电通道穿过绝缘区且连通有源区和划片道。即划片道、有源区和导电通道对应的位置不 注入离子。
具体地，当集成电路为高电子迁移率晶体管时，在进行氮离子或氩离子注入之前，在沟道层和势垒层之间的界面形成的二维电子气为整面导电，不会存在静电损伤。在沟道层和势垒层之间的界面形成绝缘区后，导电通道可以将各电路区域中原本相互分立的有源区连通至电路之间的划片道，实现晶圆中各电路区域内有源区之间的导通，当电荷到达晶圆表面时电荷能够通过导电通道尽快被导走，使整个晶圆上的各电路区域中的有源区处于等电位状态，电荷不会聚集在单个电路区域内而导致集成电路产生损伤。并且，集聚在划片道中的电荷可以在集成电路测试过程中或采用其他金属连接方式将划片道接地后导走。
进一步地，在晶圆对应绝缘区的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以在有源区、导电通道和划片道的位置注入硅离子，使势垒层和沟道层中靠近势垒层的部分在有源区、导电通道和划片道对应的位置为注入硅离子的N型半导体材料，使有源区、导电通道和划片道的导电性更好。或者，在晶圆对应绝缘区的位置注入氮离子或氩离子之后，为了使集成电路的表面导电性更好，可以有源区、导电通道和划片道的位置注入镁离子，使势垒层和沟道层中靠近势垒层的部分在有源区、导电通道和划片道对应的位置为注入镁离子的P型半导体材料，使有源区、导电通道和划片道的导电性更好。
还可以在势垒层上形成钝化层，以缓解电流崩塌效应。具体地，钝化层在划片道对应的位置处被刻蚀掉。
S3、沿划片道切割衬底，形成多个集成电路。
具体地，在切割成多个集成电路时，由于允许存在一定的对位偏移误差，在晶圆中设置的划片道宽度一般会大于切割宽度，例如划片道的宽度为80um，采用刀片或激光切割晶圆的宽度为60um，若不存在或存在微量的偏移时，沿着一条划片道切割后在集成电路的一个边缘可能残留约10um的划片道，由于划片道导电，因此残留的划片道可以作为导电通道；若在切割过程中出现一定的偏移，即切割过程中可能完全切割掉集成电路边缘的划片道，则在集成电路的某个边缘可能不会残留划片道。因此，在最终形成的集成电路中，划片道可以存在于集成电路的至少一个边缘，划片道还可以位于集成电路的多个边缘，当沿着集成电路的边缘切割时切割偏移量较少，则在最终形成的集成电路中可以形成围绕绝缘区设置的划片道。
本申请实施例还提供了一种电子设备，该电子设备可包括电路板和本申请上述实施例提供的任一种集成电路，该集成电路设置在电路板上。由于该电子设备解决问题的原理与前述一种集成电路相似，因此该电子设备的实施可以参见前述集成电路的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种集成电路，其特征在于，包括：
    衬底；
    沟道层，位于所述衬底之上；
    其中，所述沟道层的表面包括有源区、绝缘区和导电通道，所述绝缘区围绕所述有源区设置，所述导电通道穿过所述绝缘区且连通所述有源区和所述集成电路的边缘。
  2. 如权利要求1所述的集成电路，其特征在于，所述沟道层的表面还包括：位于所述集成电路的至少一个边缘的划片道。
  3. 如权利要求2所述的集成电路，其特征在于，所述划片道围绕所述绝缘区设置。
  4. 如权利要求1-3任一项所述的集成电路，其特征在于，所述导电通道连通所述有源区的第一边缘和与所述第一边缘距离最近的所述集成电路的第二边缘。
  5. 如权利要求1-4任一项所述的集成电路，其特征在于，还包括位于所述沟道层之上的势垒层，所述势垒层和所述沟道层在所述绝缘区对应的位置为注入氮离子或氩离子的绝缘材料。
  6. 如权利要求1-5任一项所述的集成电路，其特征在于，还包括位于所述沟道层之上的势垒层，所述势垒层为绝缘材料。
  7. 如权利要求1-5任一项所述的集成电路，其特征在于，还包括位于所述沟道层之上的势垒层，所述势垒层和所述沟道层中靠近所述势垒层的部分在所述有源区和所述导电通道对应的位置为注入硅离子的N型半导体材料。
  8. 如权利要求1-5任一项所述的集成电路，其特征在于，还包括位于所述沟道层之上的势垒层，所述势垒层和所述沟道层中靠近所述势垒层的部分在所述有源区和所述导电通道对应的位置为注入镁离子的P型半导体材料。
  9. 如权利要求1-8任一项所述的集成电路，其特征在于，还包括：位于所述衬底与所述沟道层之间的成核层。
  10. 如权利要求1-9任一项所述的集成电路，其特征在于，所述衬底为高阻衬底。
  11. 一种集成电路的制备方法，其特征在于，包括：
    在衬底上形成沟道层，所述衬底划分为呈阵列排布的多个电路区域和位于所述电路区域之间的划片道；
    在所述电路区域内的部分区域注入氮离子或氩离子，使所述沟道层的表面在离子注入 的位置形成绝缘区，在未被离子注入的位置形成有源区和导电通道，所述绝缘区围绕所述有源区设置，所述导电通道穿过所述绝缘区且连通所述有源区和所述划片道；
    沿所述划片道切割所述衬底，形成多个所述集成电路。
  12. 如权利要求11所述的制备方法，其特征在于，在所述沟道层上形成所述源极、漏极和栅极之前，还包括：
    在所述有源区、所述导电通道和所述划片道的位置注入硅离子形成N型半导体材料。
  13. 如权利要求11所述的制备方法，其特征在于，在所述沟道层上形成所述源极、漏极和栅极之前，还包括：
    在所述有源区、所述导电通道和所述划片道的位置注入镁离子形成P型半导体材料。
  14. 如权利要求11-13任一项所述的制备方法，其特征在于，在衬底上形成沟道层之前，还包括：在所述衬底上形成成核层；
    在所述电路区域内的部分区域注入氮离子或氩离子之前，还包括：在所述沟道层上形成势垒层。
  15. 一种电子设备，其特征在于，包括电路板以及设置在所述电路板上的如权利要求1-10任一项所述的集成电路。
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