WO2023116783A1 - 半导体氧化物晶体管及其制备方法 - Google Patents

半导体氧化物晶体管及其制备方法 Download PDF

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WO2023116783A1
WO2023116783A1 PCT/CN2022/140784 CN2022140784W WO2023116783A1 WO 2023116783 A1 WO2023116783 A1 WO 2023116783A1 CN 2022140784 W CN2022140784 W CN 2022140784W WO 2023116783 A1 WO2023116783 A1 WO 2023116783A1
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sub
active layer
layer
substrate
insulating layer
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French (fr)
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孟敬恒
曾明
韩宝东
罗杰
平延磊
李永杰
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北京超弦存储器研究院
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present disclosure relates to the field of semiconductor components and preparation technologies, in particular to a semiconductor oxide transistor and a preparation method thereof.
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • IGZO TFT oxide thin film transistors represented by IGZO TFT are more and more used in various electronic devices due to their good performance.
  • IGZO materials have good adhesion and bonding properties with other materials, and can be grown on the surface of various materials to make 2D or 3D electronic devices.
  • the present disclosure provides a semiconductor oxide transistor and a preparation method thereof.
  • the present disclosure provides a semiconductor oxide transistor on a substrate, comprising:
  • the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked in sequence along a direction away from the substrate, the first sub-insulating layer includes a first container, and the second sub-insulating layer includes a second tank, the first tank covers the second tank and part of the second sub-insulation layer, and the second tank is arranged around the part of the second sub-insulation layer;
  • the active layer includes a first part of the active layer and a second part of the active layer, the first part of the active layer is arranged in the first container, and the second part of the active layer is arranged in the second container in the slot;
  • the orthographic projection of the gate on the substrate is the same as the orthographic projection of the second part of the active layer on the substrate the projections have no overlap and are at least partially buried in the second partially active layer;
  • the source electrode and the drain electrode are oppositely disposed on a side of the second part of the active layer away from the substrate.
  • a gate insulating layer disposed between the gate and the first part of the active layer and the second part of the active layer.
  • a second insulating layer located on a side of the gate away from the substrate, and disposed around the source and the drain; the gate is on the substrate
  • the orthographic projection of is located within the orthographic projection of the second insulating layer on the substrate.
  • the plane of the second part of the active layer is zigzag.
  • different insulating materials are used for the first insulating layer and the second insulating layer; or, the same insulating material is used for the first insulating layer and the second insulating layer.
  • the first insulating layer and the second insulating layer use different insulating materials
  • the first insulating layer uses a nitride insulating material
  • the second insulating layer uses an oxide insulating material
  • the second insulating layer includes a third sub-insulating layer and a fourth sub-insulating layer;
  • the third sub-insulation layer is located on a side of the active layer away from the substrate;
  • the fourth sub-insulation layer is located on the side of the gate away from the substrate; the orthographic projection of the gate on the substrate is located at the front of the fourth sub-insulation layer on the substrate inside the projection.
  • a third insulating layer is disposed between the first insulating layer and the substrate, and the third insulating layer is made of an oxide insulating material.
  • the active layer is made of indium gallium zinc oxide material.
  • the substrate is made of a silicon substrate material.
  • the present disclosure also provides a method for preparing a semiconductor oxide transistor, comprising the following steps:
  • a first insulating layer and an active layer are formed on the substrate, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked in sequence along a direction away from the substrate, the active layer includes a first part of the active layer and a second part of the active layer; the first sub-insulation layer includes a first tank, the second sub-insulation layer includes a second tank, and the first tank covers the The second cavity and part of the second sub-insulation layer, and the second cavity is arranged around the part of the second sub-insulation layer; the first part of the active layer is arranged in the first cavity, and A second part of the active layer is disposed in the second container;
  • the orthographic projection of the gate on the substrate is the same as the orthographic projection of the second part of the active layer on the substrate the projections have no overlap and are at least partially buried in the second partially active layer;
  • the method further includes: forming a second insulating layer around the source and the drain.
  • a first insulating layer and an active layer are formed on the substrate, the first insulating layer includes a first sub-insulation layer and a second sub-insulation layer stacked in sequence along a direction away from the substrate,
  • the active layer includes a first part of the active layer and a second part of the active layer;
  • the first sub-insulation layer includes a first container,
  • the second sub-insulation layer includes a second container, and the first container
  • the slot covers the second slot and part of the second sub-insulation layer, and the second slot surrounds the part of the second sub-insulation layer; the first part is provided in the first slot.
  • the source layer is provided with a second part of the active layer in the second cavity, including: forming the first sub-insulation layer on the substrate through a deposition process;
  • the second part of the active layer is filled into the second cavity, and the plane of the second part of the active layer is in a circular shape.
  • the method for forming the first cavity in the first sub-insulation layer by using a patterning process includes:
  • the first dry etching is performed to transfer the pattern of the first cavity to the first sub-insulation layer to form the first cavity.
  • the method for forming the second cavity in the second sub-insulation layer by using a patterning process includes:
  • a second mask is set on the second sub-insulation layer deposited and formed above the first part of the active layer
  • the second dry etching is performed to transfer the pattern of the second cavity to the second sub-insulation layer to form the second cavity, and the plane of the second cavity is curved.
  • wet cleaning is performed on the surface of the substrate; and a third insulating layer is formed on the substrate by using a deposition process.
  • forming the gate on the side of the first part of the active layer away from the substrate includes:
  • a fourth sub-insulation layer is deposited on the upper end of the fourth container.
  • forming a relatively established source and drain on the side of the second part of the active layer away from the substrate includes:
  • a drain material is deposited inside the drain tank to form a drain.
  • a chemical mechanical polishing process is used to perform grinding treatment, so that the top surfaces of the source electrode and the drain electrode are flush with the top surfaces of the fourth insulating layer around them.
  • the present disclosure also provides a memory including any semiconductor oxide transistor described above.
  • the present disclosure also provides an electronic device, including the memory.
  • the method of "depositing insulating material—making a container—filling the active layer (IGZO material)” is used instead of directly indium gallium zinc oxide (IGZO) material Etching is carried out to realize the integral formation of the active layer; with this active layer forming method, fine patterning process, such as dry etching, can be used to make the cell, so that the pattern will not be like wet etching
  • fine patterning process such as dry etching
  • the minimum line width of the IGZO material is limited, and it can also avoid the formation of difficult-to-volatile by-product residues caused by the direct dry etching of the IGZO material, resulting in unclear pattern boundaries; therefore, the transistor can be made into fine patterns, and the transistor preparation accuracy and integration can be improved.
  • the prepared transistor structure can include an active layer, and the transistor manufactured by this method is provided with an active layer at the lower end and the periphery of the gate (word line), and the gate (word line) and the active layer The two are isolated by the gate insulating layer, that is, only the upper end of the gate (word line) is not wrapped by the active layer; the gate (word line) of the field effect transistor is on the substrate and wrapped, that is, the buried In-type gate (word line) structure, the transistor structure uses IGZO material as the channel (Channel) of carriers (electrons), and can take advantage of the advantages of IGZO material in terms of electron mobility, bandgap width, and current switching ratio. Reduce leakage and improve transistor performance.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor oxide transistor in an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for preparing a semiconductor oxide transistor in an embodiment of the present disclosure
  • FIG. 3 is a flow chart of the active layer forming process in which the active layer is decomposed into two layers in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • Fig. 4 is the gate embedding process flowchart of the embodiment of the preparation method of the semiconductor oxide transistor of the present disclosure
  • FIG. 5 is a flow chart of the source and drain forming process of an embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • FIG. 6 is a schematic diagram after depositing a third insulating layer on the substrate in an embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • Figure a is a schematic cross-sectional view
  • Figure b is a schematic perspective view
  • FIG. 7 is a schematic diagram after depositing the first sub-insulation layer on the third insulation layer in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure;
  • Figure a is a schematic cross-sectional view, and
  • Figure b is a schematic perspective view;
  • Fig. 8 is a schematic diagram of the first container formed by patterning process in the embodiment of the method for preparing a semiconductor oxide transistor of the present disclosure
  • Fig. a is a schematic cross-sectional view
  • Fig. b is a schematic perspective view
  • Fig. 9 is a schematic diagram after filling the first part of the active layer in the first cavity in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • Fig. a is a cross-sectional schematic diagram
  • Fig. b is a perspective schematic diagram
  • FIG. 10 is a schematic diagram after forming a second sub-insulation layer by deposition on the first part of the active layer in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • FIG. a is a schematic cross-sectional diagram
  • FIG. b is a schematic three-dimensional diagram
  • FIG. 11 is a schematic diagram of a second cell formed by a patterning process in an embodiment of the method for preparing a semiconductor oxide transistor of the present disclosure
  • FIG. a is a schematic cross-sectional view
  • FIG. b is a perspective schematic view
  • FIG. 12 is a schematic diagram of the overall active layer formed after the second active layer is filled in the second cavity in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure;
  • Figure a is a schematic cross-sectional view, and
  • Figure b is a perspective schematic view;
  • Fig. 13 is a schematic diagram after depositing and forming a third sub-insulating layer on the overall active layer in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • Fig. a is a schematic cross-sectional view
  • Fig. b is a schematic perspective view
  • Fig. 14 is a schematic diagram of a third container after the third dry etching in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • Fig. a is a cross-sectional schematic diagram
  • Fig. b is a perspective schematic diagram
  • FIG. 15 is a schematic diagram of the formation of the fourth tank after cleaning the second sub-insulation layer at the bottom of the third tank with hot phosphoric acid in the embodiment of the method for preparing a semiconductor oxide transistor of the present disclosure;
  • Figure a is a schematic cross-sectional view, and
  • Figure b is Stereoscopic diagram;
  • FIG. 16 is a schematic diagram of an oxide layer formed by high-temperature deposition in an embodiment of the method for preparing a semiconductor oxide transistor of the present disclosure
  • Figure a is a schematic cross-sectional view
  • Figure b is a schematic perspective view
  • FIG. 17 is a schematic diagram of a gate material formed after depositing a gate material inside the fourth tank in an embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure
  • Figure a is a schematic cross-sectional view
  • Figure b is a schematic perspective view
  • Fig. 18 is a schematic diagram of the fourth sub-insulation layer buried in the gate and the fourth cavities after forming the gate after forming the gate in the embodiment of the method for manufacturing the semiconductor oxide transistor of the present disclosure; is a cross-sectional schematic diagram, and Figure b is a three-dimensional schematic diagram;
  • Fig. 19 is a schematic diagram after performing the fourth dry etching to form source and drain tanks in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure;
  • Figure a is a schematic cross-sectional view, and
  • Figure b is a perspective schematic view ;
  • 20 is a perspective view after filling the source and drain tanks to form the source and the drain in the embodiment of the method for manufacturing a semiconductor oxide transistor of the present disclosure.
  • IGZO material When IGZO material is processed by dry etching, it will produce difficult-to-volatile by-products, which are easy to form residues that are difficult to remove on the workpiece, resulting in unclear pattern boundaries; while the wet-etching pattern fidelity of IGZO material is not strong, and the pattern The minimum line width of the IGZO material is limited; therefore, the IGZO material cannot be finely patterned, which hinders the use of the IGZO material for high-precision transistors.
  • embodiments of the present disclosure provide a semiconductor oxide transistor and a manufacturing method thereof to solve the above technical problems.
  • an embodiment of the present disclosure provides a semiconductor oxide transistor located on a substrate 1, including:
  • the first insulating layer 5 includes a first sub-insulating layer 51 and a second sub-insulating layer 52 stacked in sequence along the direction away from the substrate 1, the first sub-insulating layer 51 includes the first cavity 9, and the second sub-insulating layer 52 Including the second container 10 , the first container 9 covers the second container 10 and part of the second sub-insulation layer 52 , and the second container 10 is arranged around the part of the second sub-insulation layer 52 .
  • the active layer 7 includes a first part of the active layer 71 and a second part of the active layer 72; the first part of the active layer 71 is arranged in the first container 9, and the second part of the active layer 72 is arranged in the second container 10 middle.
  • the gate 3 is located on the side of the first part of the active layer 71 away from the substrate 1, and the orthographic projection of the gate 3 on the substrate 1 does not overlap with the orthographic projection of the second part of the active layer 72 on the substrate 2, And at least partially buried in the second part of the active layer 72 .
  • the source 2 and the drain 4 are oppositely disposed on a side of the second portion of the active layer 72 away from the substrate 1 . , that is, the source electrode 2 and the drain electrode 4 are relatively disposed on the upper surface of the second part of the active layer 72;
  • the field effect transistor of this solution is a fin field effect transistor, and the active layer is formed by filling the groove, which avoids direct etching of the active layer, and the active layer can be Using indium gallium zinc oxide (IGZO) material, fine patterns can be formed; an active layer is provided at the lower end and the periphery of the gate, and the gate and the active layer are separated by a gate insulating layer, that is, the gate The upper end of the transistor is not wrapped by the active layer; the gate word line of the field effect transistor is wrapped on the substrate, that is, the buried word line structure is adopted, and the transistor structure uses IGZO material as the carrier (electron) channel (Channel), the advantages of IGZO materials in terms of electron mobility, bandgap width and current switching ratio can be used to reduce leakage and improve the performance of transistors.
  • IGZO indium gallium zinc oxide
  • the material of the active layer can also be ZnOx, InOx, In2O3, SnO2, TiOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnz Oa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa , InGaSiO and other materials.
  • a gate insulating layer 8 disposed between the gate 3 and the first part of the active layer 71 and the second part of the active layer 72 .
  • FIG. 1 , FIG. 17 , FIG. 18 and FIG. 19 it also includes: a second insulating layer 6 located on the side of the gate 3 away from the substrate 1 and arranged on the source 2 and the drain.
  • the periphery of pole 2; the orthographic projection of gate 3 on substrate 1 is located within the orthographic projection of second insulating layer 6 on substrate 1.
  • the second insulating layer 6 includes a third sub-insulating layer 61 and a fourth sub-insulating layer 62;
  • the third sub-insulation layer 61 is located on the side of the active layer away from the substrate 1;
  • the fourth sub-insulation layer 62 is located on the side of the gate 3 away from the substrate 1 ; the orthographic projection of the gate 3 on the substrate 1 is located within the orthographic projection of the fourth sub-insulation layer 62 on the substrate 1 .
  • a third insulating layer 16 is provided between the lower end of the first insulating layer 5 and the substrate 1 for isolation.
  • the first insulating layer, the second insulating layer and the third insulating layer are selected to embed the transistor, and the first insulating layer, the second insulating layer and the third insulating layer can use the same Different insulating materials can also be used; on the one hand, it can ensure the performance of the transistor, and on the other hand, it can also protect the transistor and improve its life.
  • the first insulating layer 5 and the second insulating layer 6 are made of different insulating materials;
  • the first insulating layer 5 is a nitride, for example, silicon nitride (SiN) can be used.
  • the second insulating layer 6 is an oxide, for example, silicon dioxide (SiO 2 ).
  • the first insulating layer and the second insulating layer in this scheme are selected as different insulating materials, and the selection can consider that the etching selectivity ratio of the two is not lower than 5 (that is, the etching selectivity range is 5 ⁇ : 1), for example, silicon nitride (SiN) and silicon dioxide (SiO 2 ) are selected respectively.
  • the etching selectivity ratio of the two is not lower than 5 (that is, the etching selectivity range is 5 ⁇ : 1), for example, silicon nitride (SiN) and silicon dioxide (SiO 2 ) are selected respectively.
  • SiN silicon nitride
  • SiO 2 silicon dioxide
  • an embodiment of the present disclosure provides a method for preparing a semiconductor oxide transistor, which is used to prepare the above-mentioned semiconductor oxide transistor, including the following steps:
  • the active layer 7 is filled in the cavity, and the active layer 7 includes a first part of the active layer 71 and a second part of the active layer 72;
  • a gate insulating layer 8 is deposited between the gate 3 and the first part of the active layer 71 and the second part of the active layer 72;
  • the periphery of the source 2 and the drain 4 is filled with a second insulating layer 6 .
  • this solution adopts the method of "depositing insulating material - making a container - filling IGZO material” instead of directly etching the IGZO material, so as to realize the overall molding of the active layer;
  • fine patterning process such as dry etching, can be used to make the cell, so that the pattern will not be limited by the minimum line width like wet etching IGZO material, and it can also avoid direct processing of IGZO material.
  • Dry etching produces non-volatile by-products to form residues that cause pattern boundaries to be unclear; therefore, transistors can be made into fine patterns, and the accuracy and integration of transistors can be improved; the prepared transistor structure can contain active layers, using IGZO materials to make
  • the channel (Channel) of carriers (electrons) can reduce leakage and improve the performance of transistors by taking advantage of the advantages of IGZO materials in terms of electron mobility, bandgap width, and current switching ratio.
  • step S200 the active layer forming process is as follows:
  • the plane of the second cavity 10 is in the shape of a loop
  • the active layer is decomposed into two layers, and the two steps of "depositing insulating material - making a container - filling the active layer (IGZO material)" cycle processing to obtain the first part of the active layer and the second part of the active layer respectively, and the first part of the active layer and the second part of the active layer are integrated to obtain the active layer; wherein, the first container and the second part
  • the tank is formed by dry etching, but the IGZO material is not directly dry-etched, and no volatile by-products form residues that cause pattern boundaries to be unclear, so that transistors can be made into fine patterns, and transistor fabrication accuracy and integration are improved.
  • step S100 in step S100,
  • the surface of the substrate is cleaned by a wet method; and a third insulating layer 16 is formed on the substrate by a deposition process.
  • the surface of the substrate is first cleaned to remove impurities, so that the insulating material film is better combined with the substrate during deposition; the deposition process can be used on the substrate
  • a third insulating layer is formed on the bottom to isolate the first insulating layer from the substrate. Due to the different etching rates of different insulating materials, it is convenient to etch the first insulating layer, avoiding the impact of etching on the substrate, and improving the etching accuracy. .
  • step S220 the method of forming the first container by patterning process is as follows:
  • the first part of the active layer is filled and formed by a patterning process, that is, firstly according to the first cavity
  • the pattern design of the first mask is set to block the part that does not need to be etched, and the part that is not blocked by the first mask is etched by dry method. After etching to a predetermined depth, the pattern of the first cavity is transferred to the etched first sub-section. The first cavity is formed on the insulating layer. In this way, direct dry etching of the IGZO material is avoided, and the generation of hard-to-volatile by-product residues is prevented from affecting fine patterns.
  • step S250 the method of forming the second cavity above the first part of the active layer by patterning process is as follows:
  • a second mask is set on the second sub-insulation layer 52 deposited and formed on the first part of the active layer 71;
  • the second active layer is filled with a patterned process to make the second cavity, that is, firstly, the second cavity
  • the pattern design of the second mask is set to block the part that does not need to be etched, and the part that is not blocked by the second mask is etched by dry method. After etching to a predetermined depth, the pattern of the second container tank is transferred to the etched second sub-mask.
  • the second cavities are formed on the insulating layer. In this way, direct dry etching of the IGZO material is avoided, and the residue of hard-to-volatile by-products is prevented from affecting fine patterns.
  • step S230 after the first part of the active layer is filled, a chemical mechanical polishing process is used for grinding; in step S260, after the second part of the active layer is filled, a chemical mechanical polishing process is used for grinding flat handle.
  • step S300 the gate burying process includes:
  • a third sub-insulation layer 61 is formed on the upper end of the active layer 7 through a deposition process, and oxide is deposited in FIG. 13 ;
  • S330 perform dry etching for the third time, transfer the gate pattern to the third sub-insulation layer 61 on the upper end of the active layer 7 to form a third cavity 11, and the bottom of the third cavity 11 It is flush with the upper surface of the second part of the active layer 72, and the bottom surface of the third cavity 11 exposes the second sub-insulation layer 52 surrounded by the inner side of the second part of the active layer 72;
  • S350 forms an oxide layer 13 by high-temperature deposition, and retains the oxide layer 13 on the side of the fourth container 12, the bottom and the side of the fourth container 12 through a patterning process, that is, the gate electrode. pole insulating layer 8;
  • S370 deposit a fourth sub-insulation layer 62 on the upper end of the fourth container 12 to bury the gate 3 and the fourth container 12;
  • the sub-insulation layer 62 is oxide.
  • the gate embedding process mainly adopts dry etching method, which will not be limited by the minimum line width, and can produce Fine-patterned transistors; field effect transistors on the active layer, using IGZO material as the carrier (electron) channel (Channel), can take advantage of the advantages of IGZO material in terms of electron mobility, bandgap width and current switching ratio , reduce the leakage, and improve the performance of the transistor; in addition, use hot phosphoric acid (H 3 PO 4 ) cleaning method to remove the gate imitation (Dummy gate) to form the fourth tank, the gate imitation in the embodiment shown in Figure 14 (Dummy gate) It can be seen that it is the second sub-insulation layer located in the active layer package (that is, the designed gate buried position), which can avoid the use of dry etching to touch the previously formed active layer due to control errors, and avoid The generation of non-volatile by-product residues affects
  • step S400 the source and drain forming process includes:
  • S420 perform dry etching for the fourth time, and transfer the source and drain patterns to the third sub-insulation layer 61 and the fourth sub-insulation layer 62 (the third sub-insulation layer 61 and the fourth sub-insulation layer 62 are all components of the second insulating layer 6) to form the source capacitor tank 14 and the drain capacitor tank 15, the bottom surface of the source capacitor tank 14 and the drain capacitor tank 15 are connected to the grid 3 are flush with each other, so that the bottom surfaces of the source tank 14 and the drain tank 15 expose the second part of the active layer 72;
  • the source and drain forming process of this solution mainly adopts dry etching method, which will not be limited by the minimum line width , can produce transistors with fine patterns; it can avoid the use of dry etching to touch the previously formed active layer due to control errors, and avoid the generation of difficult-to-volatile by-product residues that affect fine patterns.
  • step S360 after the gate material is deposited inside the fourth cavity 12, a chemical mechanical polishing process is used to perform a flattening treatment, so that the top surface of the gate material is in contact with the second part of the active layer 72 flush with the upper surface;
  • step S370 after burying the gate electrode and the fourth container groove, a chemical mechanical polishing process is used to perform grinding treatment, so that the top surface of the fourth sub-insulation layer 62 is consistent with the top surface of the designed source and/or drain. The surface position is flush;
  • a chemical mechanical polishing process is used to perform grinding treatment, so that the top surface of the source electrode 2, the top surface of the drain electrode 4 and the top surface of the fourth sub-insulating layer 62 around them are Face flush.
  • the gate electrode, the fourth sub-insulation layer, the source electrode and the drain electrode formed by the deposition process are all polished by a chemical mechanical polishing process (CMP), so that the filled IGZO
  • CMP chemical mechanical polishing process
  • the gate and the third sub-insulation layer are conducive to the combination with the upper material layer in the subsequent process, and the process accuracy is guaranteed
  • the source and drain are ground to make the surface of the transistor It is smoother and more beautiful, which can improve the reliability of the electrical connection when the transistor is in use, and ensure the performance of the device.
  • the first mask, the second mask, the third mask and the fourth mask all use photoresist material; in step S216, the gate material uses polysilicon or metal material.
  • this scheme selects photoresist (PR) material to set each mask layer, its optical performance is better, and it is beneficial to carry out dry etching;
  • the gate material adopts polysilicon ( polycrystalline silicon) or metal (Metal) material, the material is easy to obtain, the cost is relatively low, and the technology is relatively mature, which is conducive to the control of production cost and the performance of the device is guaranteed.
  • an embodiment of the present disclosure provides a memory, including the semiconductor oxide transistor provided in any one of the above embodiments.
  • the memory provided by the embodiment of the present application has the same inventive concept and the same beneficial effect as the previous embodiments, and the content not shown in detail in the memory can refer to the previous embodiments, and will not be repeated here.
  • an embodiment of the present disclosure provides an electronic device, including the memory provided by any one of the foregoing embodiments.
  • the electronic device provided by the embodiment of the present application has the same inventive concept and the same beneficial effect as the previous embodiments, and the content not shown in detail in the electronic device can refer to the previous embodiments, and will not be repeated here.

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Abstract

本公开提供了一种半导体氧化物晶体管及其制备方法，晶体管包括第一绝缘层、有源层、栅极、源极、漏极、栅极绝缘层和第二绝缘层，第一绝缘层设置于衬底上，第一绝缘层包括容槽；有源层设置于所述容槽中，有源层包括第一部分有源层和第二部分有源层；栅极绝缘层设置于栅极与第一部分有源层和第二部分有源层之间；源极和漏极相对设置于第二部分有源层上表面；第二绝缘层填充于源极和漏极周边。制备方法包括在衬底上通过沉积工艺和图形化工艺形成容槽；以向容槽内填充的方式形成有源层；在有源层上制备场效应晶体管。

Description

半导体氧化物晶体管及其制备方法
相关交叉引用
本申请要求于2021年12月24日在国家知识产权局提交的申请号为202111597808.9的中国专利申请的优先权，其全部内容通过引用并入本文。
技术领域
本公开涉及半导体元器件及制备技术领域，特别涉及一种半导体氧化物晶体管及其制备方法。
背景技术
IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)材料具有高的电子迁移率(10～30cm 2/Vs)，高的带隙宽度(3.1eV)，优良的低漏电性能，并且具有较高的电流开关比(Ion/Ioff>～10 8)。目前，以IGZO TFT为代表的氧化物薄膜晶体管由于具有良好的性能，越来越多的应用于各种电子器件。另外，IGZO材料与其它材料的附着结合性能较好，可以生长在各种材料表面用来制作2D或3D电子器件。
发明内容
本公开提供了一种半导体氧化物晶体管及其制备方法。
本公开提供了一种半导体氧化物晶体管，半导体氧化物晶体管位于衬底上，包括：
第一绝缘层，包括沿远离所述衬底的方向依次层叠的第一子绝缘层和第二子绝缘层，所述第一子绝缘层包括第一容槽，所述第二子绝缘层包括第二容槽，所述第一容槽覆盖所述第二容槽和部分所述第二子绝缘层，且所述第二容槽环绕该部分所述第二子绝缘层设置；
有源层，包括第一部分有源层和第二部分有源层，所述第一部分有源层设置于所述第一容槽中，所述第二部分有源层设置于所述第二容槽中；
栅极，位于所述第一部分有源层远离所述衬底的一侧，所述栅极在所述衬底上的正投影与所述第二部分有源层在所述衬底上的正投影无交叠，且至少部分埋入所述第二部分有源层中；
源极和漏极，相对设置于所述第二部分有源层远离所述衬底的一侧。
可选地，还包括：栅极绝缘层，设置于所述栅极与所述第一部分有源层和所述第二部分有源层之间。
可选地，还包括：第二绝缘层，位于所述栅极远离所述衬底的一侧，并设置于所述源极和所述漏极周边；所述栅极在所述衬底上的正投影位于所述第二绝缘层在所述衬底上的正投影内。
可选的，所述第二部分有源层的平面呈回字形。
可选的，所述第一绝缘层和第二绝缘层采用不同绝缘材料；或者，所述第一绝缘层和第二绝缘层采用相同绝缘材料。
可选的，当所述第一绝缘层和第二绝缘层采用不同绝缘材料时，所述第一绝缘层采用氮化物绝缘材料，所述第二绝缘层采用氧化物绝缘材料。
可选的，所述第二绝缘层包括第三子绝缘层和第四子绝缘层；
所述第三子绝缘层位于所述有源层远离所述衬底的一侧；
所述第四子绝缘层位于所述栅极远离所述衬底的一侧；所述栅极在所述衬底上的正投影位于所述第四子绝缘层在所述衬底上的正投影内。可选的，所述第一绝缘层与所述衬底之间设置有第三绝缘层，所述第三绝缘层采用氧化物绝缘材料。
可选的，所述有源层采用铟镓锌氧化物材料。
可选的，所述衬底采用硅衬底材料。
本公开还提供了一种半导体氧化物晶体管的制备方法，包括以下步骤：
准备衬底；
在所述衬底上形成第一绝缘层和有源层，所述第一绝缘层包括沿远离所述衬底的方向依次层叠的第一子绝缘层和第二子绝缘层，所述有源层包括第一部分有源层和第二部分有源层；所述第一子绝缘层包括第一容槽，所述第二子绝缘层包括第二容槽，所述第一容槽覆盖所述第二容槽和部分所述第二子绝缘层，且所述第二容槽环绕该部分所述第二子绝缘层设置；在所述第一容槽中设置有第一部分有源层，在所述第二容槽中设置有第二部分有源层；
在所述第一部分有源层远离所述衬底的一侧制作栅极；所述栅极在所述衬底上的正投影与所述第二部分有源层在所述衬底上的正投影无交叠，且至少部分埋入所述第二部分有源层中；
在所述第二部分有源层远离所述衬底的一侧制作相对设立的源极和漏极；
可选地，还包括：在所述栅极与所述第一部分有源层和所述第二部分有源层之间制作栅极绝缘层。
可选地，还包括：在所述源极和所述漏极周边制作第二绝缘层。
可选的，在所述衬底上形成第一绝缘层和有源层，所述第一绝缘层包括沿远离所述衬底的方向依次层叠的第一子绝缘层和第二子绝缘层，所述有源层包括第一部分有源层和第二部分有源层；所述第一子绝缘层包括第一容槽，所述第二子绝缘层包括第二容槽，所述第一容槽覆盖所述第二容槽和部分所述第二子绝缘层，且所述第二容槽环绕该部分所述第二子绝缘层设置；在所述第一容槽中设置有第一部分有源层，在所述第二容槽中设置有第二部分有源层，包括：在衬底上通过沉积工艺形成所述第一子绝缘层；
采用图形化工艺在所述第一子绝缘层中形成所述第一容槽；
向所述第一容槽内填充所述第一部分有源层；
在所述第一部分有源层上方通过沉积工艺形成所述第二子绝缘层；
采用图形化工艺在所述第二子绝缘层中形成所述第二容槽；
向所述第二容槽内填充所述第二部分有源层，所述第二部分有源层的平面呈回形。
可选的，采用图形化工艺在所述第一子绝缘层中形成所述第一容槽的方法包括：
根据第一容槽图案设计，在所述衬底上通过沉积工艺形成的所述第一子绝缘层上设置第一掩膜；
进行第一次干法刻蚀，将所述第一容槽图案转移至所述第一子绝缘层形成所述第一容槽。
可选的，采用图形化工艺在所述第二子绝缘层中形成所述第二容槽的方法包括：
根据第二容槽图案设计，在所述第一部分有源层上方沉积形成的所述第 二子绝缘层上设置第二掩膜；
进行第二次干法刻蚀，将所述第二容槽图案转移至所述第二子绝缘层形成所述第二容槽，所述第二容槽的平面呈回形。
可选的，填充所述第一部分有源层后，和/或
填充所述第二部分有源层后，
采用化学机械抛光工艺进行磨平处理。
可选的，在所述衬底上形成第一绝缘层和有源层前，对衬底表面进行湿法清洗；并采用沉积工艺在衬底上形成第三绝缘层。
可选的，所述在所述第一部分有源层远离所述衬底的一侧制作栅极包括：
在所述第二部分有源层上通过沉积工艺形成第三子绝缘层；
根据栅极图案设计，在所述第三子绝缘层上设置第三掩膜；
进行第三次干法刻蚀，将栅极图案转移至所述第二部分有源层上端的所述第三子绝缘层形成第三容槽，所述第三容槽的底部与所述第二部分有源层的上表面齐平；
采用热磷酸清洗第三容槽的底面暴露的第二子绝缘层，形成第四容槽，所述第四容槽的底部与所述第一部分有源层的上表面齐平；
采用高温沉积工艺形成氧化层，并通过图案化工艺保留所述第三容槽的侧面、所述第四容槽的底部和侧面的氧化层，即为栅极绝缘层；
在所述第四容槽内部沉积栅极材料形成栅极；
在第四容槽的上端沉积第四子绝缘层。
可选的，所述在所述第二部分有源层远离所述衬底的一侧制作相对设立的源极和漏极包括：
根据源极和漏极图案设计，在所述第四子绝缘层上设置第四掩膜；
进行第四次干法刻蚀，将所述源极和漏极图案转移至所述第三子绝缘层和所述第四子绝缘层形成源极容槽和漏极容槽，所述源极容槽和所述漏极容槽的底面与所述栅极的顶面齐平；
在所述源极容槽的内部沉积源极材料形成源极；
在所述漏极容槽的内部沉积漏极材料形成漏极。
可选的，在形成源极和漏极后，采用化学机械抛光工艺进行磨平处理，使得源极的顶面、漏极的顶面与其周边第四绝缘层的顶面齐平。
本公开还提供了一种存储器，包括任一所述的半导体氧化物晶体管。
本公开还提供了一种电子设备，包括所述的存储器。
本公开的半导体氧化物晶体管及其制备方法，制备时，采用“沉积绝缘材料——制作容槽——填充有源层(IGZO材料)”的方式代替直接对铟镓锌氧化物(IGZO)材料进行刻蚀，有源层以此实现有源层整体成型；采用这种有源层成型方式，制作容槽可以选择使用精细图形工艺，如干法刻蚀，使得图形不会像湿法刻蚀IGZO材料那样最小线宽受到限制，也可避免对IGZO材料直接进行干法刻蚀产生难挥发的副产物形成残留造成图案界线不清；因此，使得晶体管可以制作精细图案，提高晶体管制备精度和集成度；另外，制备的晶体管结构中可以包含有源层，采用此方法制作的晶体管，在栅极(字线)的下端与周边都设有有源层，栅极(字线)与有源层两者以栅极绝缘层进行了隔离，即栅极(字线)只有上端面没有被有源层包裹；场效应晶体管的栅极(字线)在衬底上且被包裹，即采用了埋入式栅极(字线)结构，该晶体管结构利用IGZO材料做载流子(电子)的通道(Channel)，可借助IGZO材料在电子迁移率、带隙宽度和电流开关比等方面的优势，降低漏电，提高了晶体管的性能。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
下面通过附图和实施例，对本公开的技术方案做进一步的详细描述。
附图说明
附图用来提供对本公开的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开，并不构成对本公开的限制。在附图中：
图1为本公开实施例中一种半导体氧化物晶体管截面示意图；
图2为本公开实施例中一种半导体氧化物晶体管的制备方法流程图；
图3为本公开的半导体氧化物晶体管的制备方法实施例中将有源层分解为两层的有源层成型工艺流程图；
图4为本公开的半导体氧化物晶体管的制备方法实施例的栅极埋设工艺 流程图；
图5为本公开的半导体氧化物晶体管的制备方法实施例的源极和漏极成型工艺流程图；
图6为本公开的半导体氧化物晶体管的制备方法实施例中在衬底上沉积第三绝缘层后示意图；其中的图a为截面示意图，图b为立体示意图；
图7为本公开的半导体氧化物晶体管的制备方法实施例中在第三绝缘层上沉积第一子绝缘层后示意图；其中的图a为截面示意图，图b为立体示意图；
图8为本公开的半导体氧化物晶体管的制备方法实施例中采用图形化工艺形成第一容槽后示意图；其中的图a为截面示意图，图b为立体示意图；
图9为本公开的半导体氧化物晶体管的制备方法实施例中在第一容槽内填充第一部分有源层后示意图；其中的图a为截面示意图，图b为立体示意图；
图10为本公开的半导体氧化物晶体管的制备方法实施例中在第一部分有源层上方通过沉积形成第二子绝缘层后示意图；其中的图a为截面示意图，图b为立体示意图；
图11为本公开的半导体氧化物晶体管的制备方法实施例中采用图形化工艺形成第二容槽后示意图；其中的图a为截面示意图，图b为立体示意图；
图12为本公开的半导体氧化物晶体管的制备方法实施例中在第二容槽内填充第二有源层后形成整体有源层示意图；其中的图a为截面示意图，图b为立体示意图；
图13为本公开的半导体氧化物晶体管的制备方法实施例中在整体有源层上沉积形成第三子绝缘层后示意图；其中的图a为截面示意图，图b为立体示意图；
图14为本公开的半导体氧化物晶体管的制备方法实施例中通过第三次干法刻蚀形成第三容槽后示意图；其中的图a为截面示意图，图b为立体示意图；
图15为本公开的半导体氧化物晶体管的制备方法实施例中采用热磷酸清洗第三容槽底部的第二子绝缘层后形成第四容槽示意图；其中的图a为截面示意图，图b为立体示意图；
图16为本公开的半导体氧化物晶体管的制备方法实施例中采用高温沉积形成氧化层后示意图；其中的图a为截面示意图，图b为立体示意图；
图17为本公开的半导体氧化物晶体管的制备方法实施例中在第四容槽内部沉积栅极材料形成栅极后示意图；其中的图a为截面示意图，图b为立体示意图；
图18为本公开的半导体氧化物晶体管的制备方法实施例中形成栅极后在第四容槽的上端沉积形成第四子绝缘层埋住栅极以及第四容槽后示意图；其中的图a为截面示意图，图b为立体示意图；
图19为本公开的半导体氧化物晶体管的制备方法实施例中进行第四次干法刻蚀形成源极容槽和漏极容槽后示意图；其中的图a为截面示意图，图b为立体示意图；
图20为本公开的半导体氧化物晶体管的制备方法实施例中填充源极容槽和漏极容槽形成源极和漏极后的立体图。
具体实施方式
以下结合附图对本公开的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。
IGZO材料采用干法刻蚀加工时会产生难挥发的副产物，易在工件上形成难以清除的残留物，造成图案界线不清；而IGZO材料的湿法刻蚀图形保真度不强，图形的最小线宽受到限制；因而使得IGZO材料无法进行精细图案制作，这给IGZO材料用于高精密度的晶体管带来障碍。
为此，本公开实施例提供了一种半导体氧化物晶体管及其制备方法，用以解决以上技术问题。
如图1所示，以及参见图8-图12所示，本公开实施例提供了一种半导体氧化物晶体管，半导体氧化物晶体管位于衬底1上，包括：
第一绝缘层5，包括沿远离衬底1的方向依次层叠的第一子绝缘层51和第二子绝缘层52，第一子绝缘层51包括第一容槽9，第二子绝缘层52包括第二容槽10，第一容槽9覆盖第二容槽10和部分第二子绝缘层52，且第二容槽10环绕该部分第二子绝缘层52设置。
有源层7，包括第一部分有源层71和第二部分有源层72；第一部分有源 层71设置于第一容槽9中，第二部分有源层72设置于第二容槽10中。
栅极3，位于第一部分有源层71远离衬底1的一侧，栅极3在衬底1上的正投影与第二部分有源层72在衬底2上的正投影无交叠，且至少部分埋入第二部分有源层72中。
源极2和漏极4，相对设置于第二部分有源层72远离衬底1的一侧。，即源极2和漏极4相对设置于第二部分有源层72的上表面；
上述技术方案的工作原理和有益效果为：本方案的场效应管为鳍式场效应晶体管，采用容槽填充方式实现有源层成型，避免了直接对有源层进行刻蚀，有源层可以采用铟镓锌氧化物(IGZO)材料，可以形成精细图案；在栅极的下端与周边都设有有源层，栅极与有源层两者以栅极绝缘层进行了隔离，即栅极的上端没有被有源层包裹；场效应管的栅极字线在衬底上且被包裹，即采用了埋入式字线结构，该晶体管结构利用IGZO材料做载流子(电子)的通道(Channel)，可借助IGZO材料在电子迁移率、带隙宽度和电流开关比等方面的优势，降低漏电，提高了晶体管的性能。在其他的实施例中，有源层的材料也可以为ZnOx、InOx、In2O3、SnO2、TiOx、ZnxOyNz、MgxZnyOz、InxZnyOz、InxGayZnzOa、ZrxInyZnzOa、HfxInyZnzOa、SnxInyZnzOa、AlxSnyInzZnaOd、SixInyZnzOa、ZnxSnyOz、AlxZnySnzOa、GaxZnySnzOa、ZrxZnySnzOa、InGaSiO等其他材料。
在一个实施例中，如图1所示，还包括：栅极绝缘层8，设置于栅极3与第一部分有源层71和第二部分有源层72之间。
在一个实施例中，如图1、图17、图18和图19所示，还包括：第二绝缘层6，位于栅极3远离衬底1的一侧，并设置于源极2和漏极2周边；栅极3在衬底1上的正投影位于第二绝缘层6在衬底1上的正投影内。
在一个实施例中，如图1、图17、图18和图19所示，第二绝缘层6包括第三子绝缘层61和第四子绝缘层62；
第三子绝缘层61位于有源层远离衬底1的一侧；
第四子绝缘层62位于栅极3远离衬底1的一侧；栅极3在衬底1上的正投影位于第四子绝缘层62在衬底1上的正投影内。
在一个实施例中，如图1所示，所述第一绝缘层5的下端与衬底1之间设置第三绝缘层16进行隔离。
上述技术方案的工作原理和有益效果为：本方案选择第一绝缘层、第二绝缘层和第三绝缘层对晶体管进行埋设，第一绝缘层、第二绝缘层和第三绝缘层可以采用相同的绝缘材料，也可以采用不同的绝缘材料；一方面可以保障晶体管的性能，另一方面还对晶体管形成保护，提高寿命。
在一个实施例中，如图1所示，所述第一绝缘层5和第二绝缘层6采用不同绝缘材料；所述第一绝缘层5为氮化物，例如可以采用氮化硅(SiN)；第二绝缘层6为氧化物，例如可以采用二氧化硅(SiO 2)。
上述技术方案的工作原理和有益效果为：本方案中的第一绝缘层和第二绝缘层选择为不同绝缘材料，选择可以考虑两者的蚀刻选择比不低于5(即蚀刻选择比范围为5～∞：1)，例如分别选择采用氮化硅(SiN)和二氧化硅(SiO 2)，通过这种选择，可以方便在晶体管制备中更好地使用刻蚀工艺，提高刻蚀工艺的加工质量。
如图1-2和图6-20所示，本公开实施例提供了一种半导体氧化物晶体管的制备方法，用于制备上述半导体氧化物晶体管，包括以下步骤：
S100准备衬底1；
S200在所述衬底1上形成第一绝缘层5；
通过构图工艺，在所述第一绝缘层5中形成容槽；
在所述容槽中填充有源层7，所述有源层7包括第一部分有源层71和第二部分有源层72；
S300通过栅极埋设工艺形成栅极3；
在所述栅极3与所述第一部分有源层71、所述第二部分有源层72之间沉积有栅极绝缘层8；
S400通过源极和漏极成型工艺，在所述第二部分有源层72的上表面形成相对设立的源极2和漏极4；
所述源极2和所述漏极4周边填充有第二绝缘层6。
上述技术方案的工作原理和有益效果为：本方案采用“沉积绝缘材料——制作容槽——填充IGZO材料”的方式代替直接对IGZO材料进行刻蚀，以此实现有源层整体成型；采用这种有源层成型方式，制作容槽可以选择使用精细图形工艺，如干法刻蚀，使得图形不会像湿法刻蚀IGZO材料那样最小线宽受到限制，也可避免对IGZO材料直接进行干法刻蚀产生难挥发的副产物形 成残留造成图案界线不清；因此，使得晶体管可以制作精细图案，提高晶体管制备精度和集成度；制备的晶体管结构中可以包含有源层，利用IGZO材料做载流子(电子)的通道(Channel)，可借助IGZO材料在电子迁移率、带隙宽度和电流开关比等方面的优势，降低漏电，提高了晶体管的性能。
在一个实施例中，如图3和图7-12所示，在S200步骤中，有源层成型过程如下：
S210如图7所示，在衬底1上通过沉积工艺形成第一子绝缘层51；
S220如图8所示，采用图形化工艺在所述第一子绝缘层51中形成第一容槽9；
S230如图9所示，向第一容槽9内填充第一部分有源层71；
S240如图10所示，在第一部分有源层71上方通过沉积工艺形成第二子绝缘层52；
S250如图11所示，采用图形化工艺在第二子绝缘层52中形成第二容槽10，第二容槽10的平面呈回形；
S260如图12所示，向第二容槽10内填充第二部分有源层72，第二部分有源层72的平面呈回形；第二部分有源层72与第一部分有源层71形成一体的有源层7。
上述技术方案的工作原理和有益效果为：本方案中对于前述的晶体管，将其中的有源层分解为两层，通过两次“沉积绝缘材料——制作容槽——填充有源层(IGZO材料)”循环加工分别得到第一部分有源层和第二部分有源层，第一部分有源层和第二部分有源层形成一体，即得到有源层；其中，第一容槽和第二容槽通过干法刻蚀成型，但不对IGZO材料直接进行干法刻蚀，不会产生难挥发的副产物形成残留造成图案界线不清，使得晶体管可以制作精细图案，提高晶体管制备精度和集成度。
在一个实施例中，如图6所示，在S100步骤中，
采用湿法清洗衬底表面；并采用沉积工艺在衬底上形成第三绝缘层16。
上述技术方案的工作原理和有益效果为：本方案在制备晶体管的初始时，先对衬底表面进行清洗，去除杂质，使得沉积时绝缘材料薄膜与衬底结合更好；可以采用沉积工艺在衬底上形成第三绝缘层，将第一绝缘层与衬底隔离，由于不同绝缘材料的刻蚀速率不同，方便对第一绝缘层进行刻蚀，避免刻蚀 影响衬底，提高刻蚀精确度。
在一个实施例中，如图8所示，在S220步骤中，采用图形化工艺形成第一容槽的方法为：
根据第一容槽图案设计，设置第一掩膜；
进行第一次干法刻蚀，如图8所示，将第一容槽图案转移至第一子绝缘层51形成第一容槽9。
上述技术方案的工作原理和有益效果为：本方案在制备带有有源层的晶体管时，对第一部分有源层填充形成的第一容槽以图形化工艺制作，即先根据第一容槽的图案设计设置第一掩膜阻挡不需要刻蚀的部分，采用干法刻蚀未被第一掩膜阻挡部分，刻蚀至预定深度即将第一容槽图案转移到被刻蚀的第一子绝缘层上形成第一容槽，通过此方式避免了直接对IGZO材料进行干法刻蚀，防止产生难挥发的副产物残留影响精细图案。
在一个实施例中，如图11所示，在S250步骤中，采用图形化工艺在第一部分有源层上方形成第二容槽的方法为：
根据第二容槽图案设计，在第一部分有源层71上方沉积形成的第二子绝缘层52上设置第二掩膜；
进行第二次干法刻蚀，如图11所示，将第二容槽图案转移至第一部分有源层71上方的第二子绝缘层52形成第二容槽10，所述第二容槽的平面呈回形。
上述技术方案的工作原理和有益效果为：本方案在制备带有有源层的晶体管时，对第二有源层填充形成的第二容槽以图形化工艺制作，即先根据第二容槽的图案设计设置第二掩膜阻挡不需要刻蚀的部分，采用干法刻蚀未被第二掩膜阻挡部分，刻蚀至预定深度即将第二容槽图案转移到被刻蚀的第二子绝缘层上形成第二容槽，通过此方式避免了直接对IGZO材料进行干法刻蚀，防止产生难挥发的副产物残留影响精细图案。
在一个实施例中，在S230步骤中，填充第一部分有源层后，采用化学机械抛光工艺进行磨平处理；在S260步骤中，填充第二部分有源层后，采用化学机械抛光工艺进行磨平处理。
上述技术方案的工作原理和有益效果为：本方案在每次填充IGZO材料后，都采用化学机械抛光工艺(CMP)进行磨平处理，使得填充的IGZO材料更 平整，有利于后续工艺中与其上端材料层的结合，保障工艺精度。
在一个实施例中，如图4和图13-18所示，在S300步骤中，所述栅极埋设工艺包括：
S310如图13所示，在形成一体的有源层7后，在有源层7的上端通过沉积工艺形成第三子绝缘层61，图13中沉积的是氧化物；
S320根据栅极图案设计，在所述第三子绝缘层61上设置第三掩膜；
S330如图14所示，进行第三次干法刻蚀，将栅极图案转移至有源层7上端的所述第三子绝缘层61形成第三容槽11，第三容槽11的底部与第二部分有源层72的上表面齐平，第三容槽11的底面暴露出回形第二部分有源层72内侧包围的第二子绝缘层52；
S340如图15所示，采用热磷酸清洗第三容槽11的底面暴露的第二子绝缘层52，让第三容槽11加深形成第四容槽12，第四容槽12的底部与第一部分有源层71的上表面齐平；
S350如图16所示，采用高温沉积形成氧化层13，并通过图案化工艺保留所述第四容槽12的侧面、所述第四容槽12的底部和侧面的氧化层13，即为栅极绝缘层8；
S360如图17所示，在第四容槽12内部沉积栅极材料形成栅极3；
S370如图18所示，在第四容槽12的上端沉积第四子绝缘层62，埋住栅极3以及第四容槽12；图18中在第四容槽12的上端沉积的第四子绝缘层62是氧化物。
上述技术方案的工作原理和有益效果为：本方案在有源层上制作场效应管的工艺中，对栅极埋设工艺主要采用干法刻蚀方式，不会受到最小线宽限制，可以制作出精细图案的晶体管；场效应管在有源层上，利用IGZO材料做载流子(电子)的通道(Channel)，可借助IGZO材料在电子迁移率、带隙宽度和电流开关比等方面的优势，降低漏电，提高了晶体管的性能；另外，采用热磷酸(H 3PO 4)清洗方式去除栅极仿造物(Dummy gate)形成第四容槽，图14所示实施例中其栅极仿造物(Dummy gate)可以看出是位于有源层包裹中(即设计的栅极埋入位置)的第二子绝缘层，可以避免采用干法刻蚀由于控制误差触及之前成型的有源层，避免产生难挥发的副产物残留影响精细图案，其中第三子绝缘层和第四子绝缘层为第二绝缘层的组成部分。
在一个实施例中，如图5和图19-20所示，在S400步骤中，所述源极和漏极成型工艺包括：
S410根据源极和漏极图案设计，在第四子绝缘层62上设置第四掩膜；
S420如图19所示，进行第四次干法刻蚀，将源极和漏极图案转移至所述第三子绝缘层61和所述第四子绝缘层62(所述第三子绝缘层61和所述第四子绝缘层62都是第二绝缘层6的组成部分)形成源极容槽14和漏极容槽15，源极容槽14和漏极容槽15的底面与栅极3的顶面齐平，使得源极容槽14和漏极容槽15的底面暴露出第二部分有源层72；
S430如图20所示，在源极容槽14的内部沉积源极材料形成源极2；
S440如图20所示，在漏极容槽15的内部沉积漏极材料形成漏极4。
上述技术方案的工作原理和有益效果为：本方案在有源层上制作场效应管的工艺中，对源极和漏极成型工艺，主要采用干法刻蚀方式，不会受到最小线宽限制，可以制作出精细图案的晶体管；可以避免采用干法刻蚀由于控制误差触及之前成型的有源层，避免产生难挥发的副产物残留影响精细图案。
在一个实施例中，在S360步骤中，在第四容槽12内部沉积栅极材料后，采用化学机械抛光工艺进行磨平处理，使得栅极材料的顶面与第二部分有源层72的上表面齐平；
在S370步骤中，埋住栅极以及第四容槽后，采用化学机械抛光工艺进行磨平处理，使得所述第四子绝缘层62的顶面与设计的源极和/或漏极的顶面位置齐平；
在S430和S440步骤分别形成源极2和漏极4后，采用化学机械抛光工艺进行磨平处理，使得源极2的顶面、漏极4的顶面与其周边第四子绝缘层62的顶面平齐。
上述技术方案的工作原理和有益效果为：本方案对沉积工艺形成的栅极、第四子绝缘层、源极和漏极都采用化学机械抛光工艺(CMP)进行磨平处理，使得填充的IGZO材料更平整，一方面使得栅极和第三子绝缘层有利于后续工艺中与其上端材料层的结合，保障工艺精度；另一方面，对源极和漏极进行磨平处理，可以使得晶体管表面更平整美观，可以提高晶体管使用时的电连接可靠性，保障器件性能。
在一个实施例中，所述第一掩膜、第二掩膜、第三掩膜和第四掩膜都采 用光刻胶材料；在S216步骤中，所述栅极材料采用多晶硅或者金属材料。
上述技术方案的工作原理和有益效果为：本方案选择光刻胶(PR)材料用来设置各个掩膜层，其光学性能较好，有利于干法刻蚀的进行；栅极材料采用多晶硅(polycrystalline silicon)或者金属(Metal)材料，材料容易得到，成本较低，技术较为成熟，有利于制作成本控制，且器件性能有保障。
基于同一发明构思，本公开实施例提供了一种存储器，包括如上述任一实施例提供的半导体氧化物晶体管。
本申请实施例提供的存储器，与前面的各实施例具有相同的发明构思及相同的有益效果，该存储器中未详细示出的内容可参照前面的各实施例，在此不再赘述。
基于同一发明构思，本公开实施例提供了一种电子设备，包括如上述任一实施例提供的的存储器。
本申请实施例提供的电子设备，与前面的各实施例具有相同的发明构思及相同的有益效果，该电子设备中未详细示出的内容可参照前面的各实施例，在此不再赘述。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围，例如在结构上和工艺上将第一部分有源层和/或所述第二部分有源层再进行分层及制备等。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种半导体氧化物晶体管，所述半导体氧化物晶体管位于衬底上，其特征在于，包括：
    第一绝缘层，包括沿远离所述衬底的方向依次层叠的第一子绝缘层和第二子绝缘层，所述第一子绝缘层包括第一容槽，所述第二子绝缘层包括第二容槽，所述第一容槽覆盖所述第二容槽和部分所述第二子绝缘层，且所述第二容槽环绕该部分所述第二子绝缘层设置；
    有源层，包括第一部分有源层和第二部分有源层，所述第一部分有源层设置于所述第一容槽中，所述第二部分有源层设置于所述第二容槽中；
    栅极，位于所述第一部分有源层远离所述衬底的一侧，所述栅极在所述衬底上的正投影与所述第二部分有源层在所述衬底上的正投影无交叠，且至少部分埋入所述第二部分有源层中；
    源极和漏极，相对设置于所述第二部分有源层远离所述衬底的一侧。
  2. 根据权利要求1所述的半导体氧化物晶体管，其特征在于，还包括：
    栅极绝缘层，设置于所述栅极与所述第一部分有源层和所述第二部分有源层之间。
  3. 根据权利要求2所述的半导体氧化物晶体管，其特征在于，还包括：
    第二绝缘层，位于所述栅极远离所述衬底的一侧，并设置于所述源极和所述漏极周边；所述栅极在所述衬底上的正投影位于所述第二绝缘层在所述衬底上的正投影内。
  4. 根据权利要求2所述的半导体氧化物晶体管，其特征在于，所述第二部分有源层的平面呈回字形。
  5. 根据权利要求3所述的半导体氧化物晶体管，其特征在于，所述第一绝缘层和第二绝缘层采用不同绝缘材料；或者，所述第一绝缘层和第二绝缘层采用相同绝缘材料。
  6. 根据权利要求5所述的半导体氧化物晶体管，其特征在于，当所述第一绝缘层和第二绝缘层采用不同绝缘材料时，所述第一绝缘层采用氮化物绝缘材料，所述第二绝缘层采用氧化物绝缘材料。
  7. 根据权利要求3所述的半导体氧化物晶体管，其特征在于，所述第二绝缘层包括第三子绝缘层和第四子绝缘层；
    所述第三子绝缘层位于所述有源层远离所述衬底的一侧；
    所述第四子绝缘层位于所述栅极远离所述衬底的一侧；所述栅极在所述衬底上的正投影位于所述第四子绝缘层在所述衬底上的正投影内。
  8. 根据权利要求1所述的半导体氧化物晶体管，其特征在于，所述第一绝缘层与所述衬底之间设置有第三绝缘层，所述第三绝缘层采用氧化物绝缘材料。
  9. 根据权利要求1-8中任一项所述的半导体氧化物晶体管，其特征在于，所述有源层采用铟镓锌氧化物材料。
  10. 根据权利要求1-8中任一项所述的半导体氧化物晶体管，其特征在于，所述衬底采用硅衬底材料。
  11. 一种半导体氧化物晶体管的制备方法，其特征在于，包括以下步骤：
    准备衬底；
    在所述衬底上形成第一绝缘层和有源层，所述第一绝缘层包括沿远离所述衬底的方向依次层叠的第一子绝缘层和第二子绝缘层，所述有源层包括第一部分有源层和第二部分有源层；所述第一子绝缘层包括第一容槽，所述第二子绝缘层包括第二容槽，所述第一容槽覆盖所述第二容槽和部分所述第二子绝缘层，且所述第二容槽环绕该部分所述第二子绝缘层设置；在所述第一容槽中设置有第一部分有源层，在所述第二容槽中设置有第二部分有源层；
    在所述第一部分有源层远离所述衬底的一侧制作栅极；所述栅极在所述衬底上的正投影与所述第二部分有源层在所述衬底上的正投影无交叠，且至少部分埋入所述第二部分有源层中；
    在所述第二部分有源层远离所述衬底的一侧制作相对设立的源极和漏极。
  12. 根据权利要求11所述的半导体氧化物晶体管的制备方法，还包括：
    在所述栅极与所述第一部分有源层和所述第二部分有源层之间制作栅极绝缘层。
  13. 根据权利要求11所述的半导体氧化物晶体管的制备方法，还包括：
    在所述源极和所述漏极周边制作第二绝缘层。
  14. 根据权利要求11所述的半导体氧化物晶体管的制备方法，其特征在于，在所述衬底上形成第一绝缘层和有源层，所述第一绝缘层包括沿远离所述衬底的方向依次层叠的第一子绝缘层和第二子绝缘层，所述有源层包括第 一部分有源层和第二部分有源层；所述第一子绝缘层包括第一容槽，所述第二子绝缘层包括第二容槽，所述第一容槽覆盖所述第二容槽和部分所述第二子绝缘层，且所述第二容槽环绕该部分所述第二子绝缘层设置；在所述第一容槽中设置有第一部分有源层，在所述第二容槽中设置有第二部分有源层，包括：
    在衬底上通过沉积工艺形成所述第一子绝缘层；
    采用图形化工艺在所述第一子绝缘层中形成所述第一容槽；
    向所述第一容槽内填充所述第一部分有源层；
    在所述第一部分有源层上方通过沉积工艺形成所述第二子绝缘层；
    采用图形化工艺在所述第二子绝缘层中形成所述第二容槽；
    向所述第二容槽内填充所述第二部分有源层，所述第二部分有源层的平面呈回形。
  15. 根据权利要求14所述的半导体氧化物晶体管的制备方法，其特征在于，采用图形化工艺在所述第一子绝缘层中形成所述第一容槽的方法包括：
    根据第一容槽图案设计，在所述衬底上通过沉积工艺形成的所述第一子绝缘层上设置第一掩膜；
    进行第一次干法刻蚀，将所述第一容槽图案转移至所述第一子绝缘层形成所述第一容槽。
  16. 根据权利要求14所述的半导体氧化物晶体管的制备方法，其特征在于，采用图形化工艺在所述第二子绝缘层中形成所述第二容槽的方法包括：
    根据第二容槽图案设计，在所述第一部分有源层上方沉积形成的所述第二子绝缘层上设置第二掩膜；
    进行第二次干法刻蚀，将所述第二容槽图案转移至所述第二子绝缘层形成所述第二容槽，所述第二容槽的平面呈回形。
  17. 根据权利要求14所述的半导体氧化物晶体管的制备方法，其特征在于，填充所述第一部分有源层后，和/或
    填充所述第二部分有源层后，
    采用化学机械抛光工艺进行磨平处理。
  18. 根据权利要求11所述的半导体氧化物晶体管的制备方法，其特征在于，在所述衬底上形成第一绝缘层和有源层前，对衬底表面进行湿法清洗； 并采用沉积工艺在衬底上形成第三绝缘层。
  19. 根据权利要求11所述的半导体氧化物晶体管的制备方法，其特征在于，所述在所述第一部分有源层远离所述衬底的一侧制作栅极包括：
    在所述第二部分有源层上通过沉积工艺形成第三子绝缘层；
    根据栅极图案设计，在所述第三子绝缘层上设置第三掩膜；
    进行第三次干法刻蚀，将栅极图案转移至所述第二部分有源层上端的所述第三子绝缘层形成第三容槽，所述第三容槽的底部与所述第二部分有源层的上表面齐平；
    采用热磷酸清洗第三容槽的底面暴露的第二子绝缘层，形成第四容槽，所述第四容槽的底部与所述第一部分有源层的上表面齐平；
    采用高温沉积工艺形成氧化层，并通过图案化工艺保留所述第三容槽的侧面、所述第四容槽的底部和侧面的氧化层，即为栅极绝缘层；
    在所述第四容槽内部沉积栅极材料形成栅极；
    在第四容槽的上端沉积第四子绝缘层。
  20. 根据权利要求19所述的半导体氧化物晶体管的制备方法，其特征在于，所述在所述第二部分有源层远离所述衬底的一侧制作相对设立的源极和漏极包括：
    根据源极和漏极图案设计，在所述第四子绝缘层上设置第四掩膜；
    进行第四次干法刻蚀，将所述源极和漏极图案转移至所述第三子绝缘层和所述第四子绝缘层形成源极容槽和漏极容槽，所述源极容槽和所述漏极容槽的底面与所述栅极的顶面齐平；
    在所述源极容槽的内部沉积源极材料形成源极；
    在所述漏极容槽的内部沉积漏极材料形成漏极。
  21. 根据权利要求20所述的半导体氧化物晶体管的制备方法，其特征在于，在形成源极和漏极后，采用化学机械抛光工艺进行磨平处理，使得源极的顶面、漏极的顶面与其周边第四绝缘层的顶面齐平。
  22. 一种存储器，其特征在于，包括如权利要求1至10任一所述的半导体氧化物晶体管。
  23. 一种电子设备，其特征在于，包括如权利要求22所述的存储器。
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