WO2023116218A1

WO2023116218A1 - Residual voltage elimination circuit and electronic apparatus

Info

Publication number: WO2023116218A1
Application number: PCT/CN2022/129261
Authority: WO
Inventors: 朱红磊; 廖亮; 于宏全
Original assignee: 中兴通讯股份有限公司
Priority date: 2021-12-21
Filing date: 2022-11-02
Publication date: 2023-06-29
Also published as: CN116316497A

Abstract

Provided are a residual voltage elimination circuit and an electronic apparatus. The residual voltage elimination circuit is applied to the electronic apparatus. The electronic apparatus comprises a power supply (VS1) and a load (Load). The power supply (VS1) is connected to the load (Load) by means of a power supply switch (S1). The residual voltage elimination circuit comprises a discharge device (T) connected to the load (Load) in parallel. When the power supply switch (S1) is in a turn-on state, the discharge device (T) is in a cut-off state and does not affect a normal working circuit; when the power supply switch (S1) is switched from the turn-on state to a turn-off state, the discharge device (T) is switched from the cut-off state to a conduction state, and the load (Load) releases voltage by means of the discharge device (T).

Description

Residual voltage elimination circuit and electronic equipment

Cross References to Related Applications

This application is based on a Chinese patent application with application number 202111570988.1 and a filing date of December 21, 2021, and claims the priority of this Chinese patent application. The entire content of this Chinese patent application is hereby incorporated by reference into this application.

technical field

The present application relates to the technical field of residual voltage discharge, in particular to a residual voltage elimination circuit and electronic equipment.

Background technique

For communication products, when the external power supply is removed, it is often necessary for the device to quickly enter the power-free state (that is, the device itself does not have any remaining charge), so as to ensure that the device is in the initialization state when it is powered on again.

In some cases, by connecting a discharge resistor in parallel on the power supply bus of the device, when the external power supply is removed, the device releases the residual voltage through the discharge resistor to ensure that the device is in an initialization state when it is powered on again. However, if the resistance value of the discharge resistor is large, the discharge time will be prolonged; if the resistance value is small, although the discharge time is shortened, serious leakage will occur when the circuit works normally.

Therefore, how to provide a residual voltage elimination circuit that does not affect the normal working circuit and can quickly eliminate the residual charge in the circuit after the external power supply is removed has become an urgent technical problem to be solved.

Contents of the invention

Embodiments of the present application provide a residual voltage eliminating circuit and electronic equipment.

In the first aspect, the embodiment of the present application provides a residual voltage elimination circuit, which is applied to electronic equipment. The electronic equipment includes a power supply and a load. The power supply is connected to the load through a power supply switch. The residual voltage elimination circuit Including: a discharge device, the discharge device is connected in parallel with the load; when the power supply switch is in the closed state, the discharge device is in the cut-off state; when the power supply switch is switched from the closed state to the open state, the discharge The device switches from an off state to an on state, and the load discharges voltage through the discharge device.

In a second aspect, an embodiment of the present application provides an electronic device, and the electronic device includes the residual voltage elimination circuit provided in the first aspect above.

Additional features and advantages of the application will be set forth in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solution of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

Fig. 1 is a schematic diagram of a residual voltage elimination circuit in some cases;

Fig. 2 is a schematic diagram of a residual voltage elimination circuit provided by an embodiment of the present application;

Fig. 3 is a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application;

Fig. 4 is a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application;

Fig. 5 is a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application;

FIG. 6 is a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the embodiments described here are only used to explain the present application, not to limit the present application.

It should be understood that in the description of the embodiments of the present application, multiple (or multiple) means more than two, greater than, less than, exceeding, etc. are understood as not including the original number, and above, below, within, etc. are understood as including the original number. If there is a description of "first", "second", etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the indicated The sequence relationship of the technical characteristics.

For communication products, when the external power supply is removed, it is often necessary for the device to quickly enter the no-power state (that is, the device itself does not have any remaining charge), so as to ensure that the device is in the initialization state when it is powered on next time.

In some cases, as shown in Figure 1, by connecting the discharge resistor _RL in parallel on the power supply bus of the device, when the external power supply VS is removed, that is, the power switch S is switched from the closed state to the open state, and the device passes through The discharge resistor _RL releases the residual voltage, that is, quickly eliminates the residual charge in the load circuit through the discharge resistor _RL , so as to ensure that the device is in an initialization state when it is powered on again. However, if the resistance of the discharge resistor _RL is large, the discharge time will be prolonged; if the resistance of the discharge resistor _RL is small, the discharge time will be shortened, but serious leakage will occur when the circuit works normally.

Therefore, how to provide a residual voltage elimination circuit that does not affect the normal working circuit and can quickly eliminate the residual charge in the device after the external power supply is removed has become an urgent technical problem to be solved.

Based on this, according to the first aspect of the embodiments of the present application, a residual voltage elimination circuit is provided, which does not affect the normal working circuit, and can quickly eliminate the residual charge in the circuit after the external power supply is removed.

FIG. 2 shows a schematic diagram of a residual voltage elimination circuit provided by an embodiment of the present application. As shown in FIG. 2 , the residual voltage elimination circuit 100 is applied to electronic equipment. The electronic equipment includes a power supply VS1 and a load Load. The power supply VS1 is connected to the load Load through a power supply switch S1 .

The residual voltage elimination circuit 100 includes: a discharge device T connected in parallel to the load Load;

When the power supply switch S1 is in the closed state, the discharge device T is in the off state; when the power supply switch S1 is switched from the closed state to the off state, the discharge device T is switched from the off state to the on state, and the load Load releases the voltage through the discharge device T.

It can be understood that when the power supply switch S1 is in the closed state and the discharge device T is in the cut-off state, the circuit where the discharge device T is located is disconnected, and the residual voltage elimination circuit 100 does not affect the normal working circuit; when the power supply switch S1 is switched from the closed state to the off state Open state, that is, when the power supply VS1 is removed, the discharge device T switches from the off state to the on state, then the circuit path where the discharge device T is located, the load Load releases the voltage through the discharge device T, that is, the discharge device T quickly Eliminate residual charge in the circuit.

In some embodiments, refer to FIG. 3 , which shows a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application. As shown in FIG. 3 , the residual voltage elimination circuit 100 also includes a control unit 110 ;

The control unit 110 is connected in parallel with the load Load and connected with the discharge device T;

When the power supply switch S1 switches from the closed state to the open state, the control unit 110 controls the discharge device T to switch from the off state to the on state.

It can be understood that, when the power supply switch S1 is in the closed state, the circuit where the control unit 110 is located is disconnected, and the residual voltage elimination circuit 100 does not affect the normal working circuit, for example, the circuit where the load Load is located; when the power supply switch S1 is switched from the closed state To the off state, the control unit 110 controls the discharge device T to switch from the off state to the on state, then the circuit path where the discharge device T is located, the load Load releases the voltage through the discharge device T, that is, the discharge device T quickly eliminates the residual charge in the circuit .

In some embodiments, the control unit includes a first switch tube and a capacitor;

The capacitor is connected in parallel with the load, and the first end of the capacitor is grounded; the first switch tube is connected in parallel with the load through its control terminal and outflow end, and the outflow end of the first switch tube is connected to the discharge device, and the inflow end of the first switch tube Connect to the second terminal of the capacitor.

It can be understood that the above-mentioned inflow end and outflow end indicate the direction of current flow. The capacitor is connected in parallel with the load, that is, the capacitor is connected in parallel with the power supply, wherein the first end of the capacitor is connected to the positive pole of the power supply, and the second end of the capacitor is connected to the negative pole of the power supply and grounded.

By setting the capacitor in the control unit, when the power supply switch is switched from the closed state to the disconnected state, the capacitor discharges the charge and drives the first switch to conduct, so that the first switch controls the discharge device to switch from the off state to the on state.

It should be understood that the first switch transistor may be a controllable element such as a PMOS transistor (Positive channel Metal Oxide Semiconductor, PMOS).

In one embodiment, the first switch transistor is a PMOS transistor. It should be understood that the gate G of the PMOS transistor is the control terminal, the source S of the PMOS transistor is the inflow terminal, and the drain D of the PMOS transistor is the outflow terminal. When the voltage of the gate G of the PMOS transistor is lower than the voltage of the source S, the PMOS transistor is turned on, and the current flows from the source S to the drain D.

Referring to FIG. 4 , FIG. 4 shows a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application. As shown in Figure 4, the capacitor C1 is connected in parallel with the load Load, and the first end of the capacitor C1 is grounded; the PMOS transistor T1 is connected in parallel with the load Load through its gate G and drain D, wherein the gate G is connected to the positive pole, and the drain D is connected to the negative electrode, and the drain D of the PMOS transistor T1 is connected to the discharge device T, and the source S of the PMOS transistor T1 is connected to the second end of the capacitor C1.

It can be understood that when the power supply switch S1 is in the closed state, the power supply VS1 charges the capacitor C1, and the voltage on the capacitor C1 is close to but less than the voltage on the power supply bus, that is, the voltage at the source S of the PMOS transistor T1 is close to but less than the PMOS The voltage at the gate G of the transistor T1, at this time, the PMOS transistor T1 is blocked. When the power supply switch S1 switches from the closed state to the open state, because the load Load continues to work, the voltage on the power supply bus drops rapidly, that is, the voltage at the gate G of the PMOS transistor T1 drops rapidly, and finally the gate G of the PMOS transistor T1 The voltage at the source S is lower than the voltage at the source S, the PMOS transistor T1 is turned on, and the current flows from the source S to the drain D, so that the PMOS transistor T1 controls the discharge device T to switch from the off state to the on state through its drain D , then the circuit path where the discharge device T is located, the load Load releases the voltage through the discharge device T, that is, the residual charge in the circuit is quickly eliminated through the discharge device T.

In some embodiments, the control unit further includes a first resistor. The first resistor is connected in series with the capacitor, wherein one end of the first resistor is connected with the second end of the capacitor.

It can be understood that the first resistor is connected in series with the capacitor to limit the current. When the power supply switch is in the closed state, the power supply charges the capacitor through the first resistor so that the voltage on the capacitor is lower than the voltage on the power supply bus, that is, the The voltage at the inflow terminal of the first switch tube is lower than the voltage at the control terminal, and the first switch tube is blocked, so that the discharge device is in a cut-off state.

In some embodiments, refer to FIG. 5, which shows a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application. As shown in FIG. 5, the first switch tube is a PMOS tube T1, and the first resistor R1 is connected in series with capacitor C1. When the power supply switch S1 is in the closed state, the power supply VS1 charges the capacitor C1 through the first resistor R1, so that the voltage on the capacitor C1 is lower than the voltage on the power supply bus, that is, the source of the PMOS transistor T1 The voltage of pole S is lower than the voltage of gate G, and PMOS transistor T1 is blocked.

In some embodiments, the control unit further includes a diode, which is connected in series between the first resistor and the capacitor, wherein the anode of the diode is connected to the first resistor, and the cathode of the diode is connected to the capacitor.

Referring to FIG. 5, a diode D1 is connected in series between the first resistor R1 and the capacitor C1, which can prevent the capacitor from releasing the charge when the power supply switch S1 is switched from the closed state to the open state, causing the current to flow in reverse and affecting other circuits. .

In some embodiments, the control unit further includes a second resistor connected in series with the first switch tube, wherein one end of the second resistor is connected to the outflow end of the first switch tube.

Referring to Fig. 5, the first switch tube is a PMOS tube T1, the second resistor R2 is connected in series with the PMOS tube T1, wherein one end of the second resistor is connected to the drain D of the PMOS tube T1, the capacitor C1, the source S of the PMOS tube T1 A closed loop is formed between the drain D and the second resistor R2. When the power supply switch S1 is switched from the closed state to the open state, the capacitor C1 releases the charge and is charged in the capacitor C1, the source S and the drain D of the PMOS transistor T1, and the second The two resistors R2 form a current loop.

By setting the second resistor, when the power supply switch S1 is switched from the closed state to the open state, the charge on the capacitor C1 is consumed in time to prevent the voltage from rising too slowly when the power supply switch S1 is quickly closed again, and the occurrence of PMOS transistor T1 The voltage of the gate G is lower than the voltage of its source S, resulting in false conduction of the PMOS transistor T1.

In some embodiments, the second resistor is an adjustable resistor.

It can be understood that, in different practical applications, the discharge speed of the capacitor can be controlled by adjusting the resistance value of the second resistor, so as to improve the applicability of the residual voltage eliminating circuit.

In some embodiments, the discharge device is a second switch tube; the second switch tube is connected to the load in parallel through its inflow end and outflow end, and the control end of the second switch tube is connected to the outflow end of the first switch tube.

It can be understood that the above-mentioned inflow end and outflow end indicate the direction of current flow. The second switch tube is connected in parallel with the load through its inflow end and outflow end, that is, it is connected in parallel with the power supply, wherein the inflow end of the second switch tube is connected to the positive pole of the power supply, and the outflow end of the second switch tube is connected to the negative pole of the power supply.

It should be understood that the second switch transistor may be a controllable device such as an NMOS transistor (N Metal Oxide Semiconductor, NMOS) or an Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor, IGBT).

In some embodiments, the first switch transistor is an NMOS transistor. It should be understood that the gate G of the NMOS transistor is the control terminal, the drain D of the NMOS transistor is the inflow terminal, and the source S of the NMOS transistor is the outflow terminal. Referring to Figure 5, the NMOS transistor T2 is connected in parallel with the load through its drain D and source S, that is, it is connected in parallel with the power supply, wherein the drain D of the NMOS transistor T2 is connected to the positive pole of the power supply, and the source S of the NMOS transistor T2 is connected to the power supply Negative pole, the gate G of the NMOS transistor T2 is connected with the first switch transistor. When a positive voltage is applied to the gate G of the NMOS transistor T2, the NMOS transistor T2 is turned on, the current flows from the drain D to the source S, and the load Load releases the voltage through the NMOS transistor T2, that is, quickly eliminates the remaining voltage in the circuit through the NMOS transistor T2. charge.

In some embodiments, the second switch tube is an IGBT tube. It should be understood that the gate G of the IGBT tube is the control terminal, the emitter E of the IGBT tube is the inflow terminal, and the collector C is the outflow terminal. Referring to FIG. 6 , FIG. 6 shows a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application. As shown in Figure 6, the IGBT tube T3 is connected in parallel with the load through its emitter E and collector C, that is, it is connected in parallel with the power supply, where the emitter E of the IGBT tube T3 is connected to the positive pole of the power supply, and the collector C of the IGBT tube T3 It is connected to the negative pole of the power supply, and the grid G of the IGBT transistor T3 is connected to the first switch transistor. When a positive voltage is applied to the gate G of the IGBT tube T3, the IGBT tube T3 is turned on, and the current flows from the emitter E to the collector C. charge.

In some embodiments, the residual voltage elimination circuit further includes a third resistor. The third resistor is connected in series with the second switch tube, wherein one end of the third resistor is connected with the inflow end of the second switch tube.

Referring to FIG. 6, FIG. 6 shows a schematic diagram of a residual voltage elimination circuit provided by another embodiment of the present application. As shown in FIG. 6, the second switch tube is an IGBT tube T3, and the third resistor R3 is connected in series with the IGBT tube T3 , wherein one end of the third resistor R3 is connected to the emitter E of the IGBT tube T3.

It can be understood that by setting the third resistor, the current passing through the second switching tube can be limited, preventing the second switching tube from being burned out, and preventing the power supply from being pulled down due to excessive instantaneous current.

It can be understood that the third resistor may be an adjustable resistor, so as to improve the applicability of the residual voltage elimination circuit in different practical application scenarios.

The following describes the residual voltage elimination circuit provided by this application in the form of an embodiment:

Embodiment one

Referring to FIG. 5 , the residual voltage elimination circuit is applied to electronic equipment. The electronic equipment includes a power supply VS1 and a load Load. The power supply VS1 is connected to the load Load through a power supply switch S1 .

The residual voltage elimination circuit includes: a control unit 110 and an NMOS transistor T2. The control unit 110 includes: a PMOS transistor T1, a capacitor C1, a first resistor R1, a second resistor R2 and a diode D1.

As shown in Figure 5, the first resistor R1, the diode D1 and the capacitor C1 are connected in series and connected in parallel with the load Load, wherein the cathode of the diode D1 is connected to the first resistor R1, the anode of the diode D1 is connected to the capacitor C1, and the capacitor C1 The first end of the ground.

The PMOS transistor T1 is connected in parallel with the load Load through the gate G and the drain D, wherein the gate G of the PMOS transistor T1 is connected to the positive pole of the power supply, the drain D of the PMOS transistor T1 is connected to the negative pole of the power supply through the second resistor R2, and the PMOS transistor T1 is connected to the negative pole of the power supply. The source S is connected to the second end of the capacitor C1.

The NMOS transistor T2 is connected in parallel with the load Load through the drain D and the source S, wherein the drain D of the NMOS transistor T2 is connected to the positive pole of the power supply, the source S of the NMOS transistor T2 is connected to the negative pole of the power supply, and the gate G of the NMOS transistor T2 is connected to the PMOS The drain D connection of the tube.

When the power supply switch S1 is in the closed state, the power supply VS1 powers up the capacitor C1 through the first resistor R1 and the diode D1, and the voltage on the capacitor C1 is lower than the voltage on the power supply bus, that is, the voltage at the source S of the PMOS transistor T1 is lower than its The voltage at the gate G, at this time, the PMOS transistor T1 is blocked, and the NMOS transistor T2 is in a cut-off state.

When the power supply switch S1 switches from the closed state to the open state, because the load Load continues to work, the voltage on the power supply bus of the device drops rapidly, that is, the voltage at the gate G of the PMOS transistor T1 drops rapidly, and the capacitor C1 discharges, eventually causing The voltage at the gate G of the PMOS transistor T1 is lower than the voltage at the source S, the PMOS transistor T1 is turned on, and the current flows from the source S to the drain D, thereby applying a positive voltage to the gate G of the NMOS transistor T2, The NMOS transistor T2 switches from the off state to the on state, and the load Load releases the voltage through the NMOS transistor T2, that is, quickly eliminates the residual charge in the circuit through the NMOS transistor T2.

Embodiment two

Referring to FIG. 6 , the residual voltage elimination circuit is applied to electronic equipment. The electronic equipment includes a power supply VS1 and a load Load. The power supply VS1 is connected to the load Load through a power supply switch S1 .

The residual voltage elimination circuit includes: a control unit 110, an IGBT tube T3, and a third resistor R3. The control unit 110 includes: a PMOS transistor T1, a capacitor C1, a first resistor R1 and a diode D1.

As shown in Figure 6, the first resistor R1, the diode D1 and the capacitor C1 are connected in series and connected in parallel with the load Load, wherein the cathode of the diode D1 is connected to the first resistor R1, the anode of the diode D1 is connected to the capacitor C1, and the capacitor C1 The first end of the ground.

The PMOS transistor T1 is connected in parallel with the load Load through the gate G and the drain D, wherein the gate G of the PMOS transistor T1 is connected to the positive pole of the power supply, the drain D of the PMOS transistor T1 is connected to the negative pole of the power supply, and the source S of the PMOS transistor T1 is connected to the capacitor The second terminal of C1 is connected.

The IGBT tube T3 is connected in parallel with the load Load through the emitter E and the collector C, wherein the emitter E of the IGBT tube T3 is connected to the positive pole of the power supply, the collector C of the IGBT tube T3 is connected to the negative pole of the power supply, and the gate G of the IGBT tube T3 is connected to the PMOS The drain D connection of the tube.

When the power supply switch S1 is in the closed state, the power supply VS1 powers up the capacitor C1 through the first resistor R1 and the diode D1, and the voltage on the capacitor C1 is lower than the voltage on the power supply bus, that is, the voltage at the collector C of the PMOS transistor T1 is lower than its The voltage at the gate G, at this time, the PMOS transistor T1 is blocked, and the IGBT transistor T3 is in the cut-off state.

When the power supply switch S1 switches from the closed state to the open state, because the load Load continues to work, the voltage on the power supply bus of the device drops rapidly, that is, the voltage at the gate G of the PMOS transistor T1 drops rapidly, and the capacitor C1 discharges, eventually causing The voltage at the gate G of the PMOS transistor T1 is lower than the voltage at the source S, the PMOS transistor T1 is turned on, and the current flows from the source S to the drain D of the PMOS transistor T1, so that at the gate G of the IGBT transistor T3 When a positive voltage is applied, the IGBT tube T3 switches from the off state to the on state, and the load Load releases the voltage through the third resistor R3 and the IGBT tube T3, that is, the residual charge in the circuit is quickly eliminated through the third resistor R3 and the IGBT tube T3.

The residual voltage elimination circuit provided in the embodiment of the present application is applied to electronic equipment. The electronic equipment includes a power supply and a load. The power supply is connected to the load through a power switch. The residual voltage elimination circuit includes a discharge device connected in parallel with the load. When the power supply switch is in In the closed state, the discharge device is in the cut-off state, which does not affect the normal working circuit; when the power switch switches from the closed state to the disconnected state, the discharge device switches from the cut-off state to the conduction state, and the load releases the voltage through the discharge device, quickly eliminating the circuit The remaining charge in the battery ensures that the device is in the initialization state when it is powered on next time, so as to avoid affecting the operation of the device when it is powered on next time.

The embodiment of the present application also provides an electronic device, which includes the residual voltage elimination circuit provided by the above-mentioned embodiment of the invention. For the circuit structure and beneficial effects of the residual voltage elimination circuit, refer to the above-mentioned embodiment, and will not be repeated here.

Embodiments of the application are described herein, including certain embodiments known to the inventors for carrying out the application. Variations of those described embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the embodiments of the application to be practiced otherwise than as described herein. Accordingly, the scope of this application includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, the scope of the application encompasses any combination of the above-described elements in all possible variations thereof unless otherwise indicated herein or otherwise clearly contradicted by context.

Claims

A residual voltage elimination circuit is applied to electronic equipment, the electronic equipment includes a power supply and a load, the power supply is connected to the load through a power switch, and the residual voltage elimination circuit includes:

a discharge device connected in parallel with the load;

When the power supply switch is in the closed state, the discharge device is in the off state; when the power supply switch is switched from the closed state to the off state, the discharge device is switched from the off state to the on state, and the load is passed through the The discharge device releases the voltage.
The residual voltage elimination circuit according to claim 1, wherein the residual voltage elimination circuit further comprises a control unit;

The control unit is connected in parallel with the load and connected with the discharge device;

When the power supply switch switches from a closed state to an open state, the control unit controls the discharge device to switch from an off state to an on state.
The residual voltage elimination circuit according to claim 2, wherein the control unit comprises a first switch tube and a capacitor;

The capacitor is connected in parallel with the load, and the first end of the capacitor is grounded;

The first switch tube is connected in parallel with the load through its control end and outflow end, and the outflow end of the first switch tube is connected to the discharge device; the inflow end of the first switch tube is connected to the capacitor the second end connection.
The residual voltage elimination circuit according to claim 3, wherein the control unit further comprises a first resistor;

The first resistor is connected in series with the capacitor, wherein one end of the first resistor is connected to the second end of the capacitor.
The residual voltage elimination circuit according to claim 4, wherein the control unit further comprises a diode;

The diode is connected in series between the first resistor and the capacitor, wherein the anode of the diode is connected to the first resistor, and the cathode of the diode is connected to the capacitor.
The residual voltage elimination circuit according to claim 3, wherein the control unit further comprises a second resistor;

The second resistor is connected in series with the first switch tube, wherein one end of the second resistor is connected to the outflow end of the first switch tube.
The residual voltage elimination circuit according to claim 6, wherein the second resistor is an adjustable resistor.
The residual voltage elimination circuit according to claim 3, wherein the discharge device is a second switch tube;

The second switch tube is connected in parallel with the load through its inflow end and outflow end, and the control end of the second switch tube is connected with the outflow end of the first switch tube.
The residual voltage elimination circuit according to claim 8, wherein the residual voltage elimination circuit further comprises a third resistor;

The third resistor is connected in series with the second switch tube, wherein one end of the third resistor is connected to the inflow end of the second switch tube.
An electronic device, comprising the residual voltage eliminating circuit according to any one of claims 1 to 9.