CN210578471U

CN210578471U - Overvoltage protection circuit

Info

Publication number: CN210578471U
Application number: CN201922249383.7U
Authority: CN
Inventors: 王信翔
Original assignee: Jiangsu Yueteng Semiconductor Technology Co Ltd
Current assignee: Jiangsu Yueteng Semiconductor Technology Co Ltd
Priority date: 2019-12-13
Filing date: 2019-12-13
Publication date: 2020-05-19
Anticipated expiration: 2029-12-13

Abstract

The utility model relates to an overvoltage protection field discloses an overvoltage protection circuit, including input terminal, trigger circuit, control circuit, switch circuit and output terminal, input terminal electric connection contact circuit, control circuit and switch circuit respectively, and the trigger circuit electricity is connected control circuit, and the control circuit electricity is connected switch circuit, and the output terminal is connected to the switch circuit electricity, and when the input voltage of input terminal was excessive pressure, trigger circuit triggered, and the control circuit control switch circuit breaks off; when the input voltage of the input terminal is in a normal range, the trigger circuit is not triggered, and the control circuit controls the switch circuit to be conducted. The utility model discloses a zener diode D1 among the trigger circuit sets up the overvoltage protection threshold value, is punctured the back when zener diode D1, and control circuit control switch circuit breaks off, and input terminal is the state of opening circuit with output terminal, and then realizes overvoltage protection, simple structure moreover.

Description

Overvoltage protection circuit

Technical Field

The utility model relates to an overvoltage protection field, concretely relates to overvoltage crowbar.

Background

Most of the portable electronic products in life are supplied with low voltage. However, in an actual application circuit, external interference, accidental short circuit or hot plugging can cause the input voltage of an electronic product to suddenly rise, and the excessively high input voltage can affect the performance of the circuit and even burn out the circuit.

The basic architecture and the mode of the existing overvoltage protection circuit mainly include the following steps that firstly, the withstand voltage of an MOS tube adopted by a chip process is improved, but the mode is influenced by a semiconductor process; secondly, a composite double-MOS tube technology is adopted, when one MOS tube is damaged, the circuit is switched to another MOS tube for working; thirdly, a chip with higher voltage resistance is used as a switch circuit, and once the overvoltage input voltage is detected, the chip with the higher voltage resistance is immediately turned off, so that the load circuit is protected from being damaged. The second scheme and the third scheme have higher complexity, more required devices and connection points, high cost and more possibility of causing the risk of defective pixels.

SUMMERY OF THE UTILITY MODEL

In view of the deficiency of the background art, the utility model provides an overvoltage protection circuit, the technical problem that solve provide an overvoltage protection circuit that simple structure, low cost and reliability are high.

For solving the technical problem, the utility model provides a following technical scheme: the overvoltage protection circuit comprises an input terminal, a trigger circuit, a control circuit, a switch circuit and an output terminal.

The input terminal is respectively and electrically connected with the contact circuit, the control circuit and the switch circuit, the trigger circuit is electrically connected with the control circuit, the control circuit is electrically connected with the switch circuit, and the switch circuit is electrically connected with the output terminal.

When the input voltage of the input terminal is over-voltage, the trigger circuit is triggered, and the control circuit drives the switch circuit to be disconnected; when the input voltage of the input terminal is in a normal range, the trigger circuit is not triggered, and the control circuit drives the switch circuit to be conducted.

Further, the trigger circuit comprises resistors R1 and R2, a voltage stabilizing diode D1 and a fourth PMOS tube P4; one end of the resistor R1 is electrically connected with the input terminal, the other end of the resistor R1 is electrically connected with the source electrode of the fourth PMOS tube P4 and one end of the resistor R2 respectively, the other end of the resistor R2 is electrically connected with the drain electrode of the fourth PMOS tube and the cathode of the voltage stabilizing diode D1 respectively, and the anode of the voltage stabilizing diode D1 is grounded.

Further, the control circuit comprises resistors R3, R4, R5, R6, a first PMOS tube P1, a second PMOS tube P2, and voltage-stabilizing diodes D2 and D3; the input terminals are respectively and electrically connected with one end of a resistor R4, a source electrode of a first PMOS tube P1 and a source electrode of a second PMOS tube P2, the other end of the resistor R4 is electrically connected with a negative electrode of a voltage-stabilizing diode D2, an anode of a voltage-stabilizing diode D2 is respectively and electrically connected with a gate electrode of the first PMOS tube P1 and one end of a resistor R3, the other end of a resistor R3 is electrically connected with a source electrode of a fourth PMOS tube, a drain electrode of the first PMOS tube P1 is respectively and electrically connected with one end of a resistor R5 and a gate electrode of the second PMOS tube P2, a drain electrode of the second PMOS tube P2 is respectively and electrically connected with one end of a resistor R6, a negative electrode of a voltage-stabilizing diode D3 and a gate electrode of the fourth PMOS tube P4, and the other ends of.

Further, the switch circuit includes a third PMOS transistor P3, a source of the third PMOS transistor P3 is electrically connected to the input terminal, a drain of the third PMOS transistor P3 is electrically connected to the output terminal, and a gate of the third PMOS transistor P3 is electrically connected to a gate of the second PMOS transistor P2.

Furthermore, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the fourth PMOS transistor P4 are enhancement-type PMOS transistors.

The over-voltage protection threshold is the breakdown voltage of zener diode D1 plus the voltage drop of the breakdown current over the R1 and R2 resistors at that time. When the input voltage of the input terminal is lower than the overvoltage protection threshold, the zener diode D1 is not broken down, and at this time, the branch where the zener diode D1 is located has no conduction current, the gate potential of the first PMOS transistor P1 is high and is not yet turned on, the resistor R5 pulls the gate potentials of the second PMOS transistor P2 and the third PMOS transistor P3 to a low level, so the second PMOS transistor P2 and the third PMOS transistor P3 are in a fully-on state, the resistor R6 limits the current of the branch where the second PMOS transistor P2 is located, the P4 is in an off state, and the output voltage of the output terminal is the same as the input voltage of the input terminal.

When the input voltage of the input terminal is higher than the overvoltage protection threshold, the zener diode D1 is broken down, and at this time, the branch where the zener diode D1 is located generates a conducting current, the gate potential of the first PMOS transistor P1 is pulled to a low potential and controlled by the clamping voltage of the zener diode D2, and the gate potential of the first PMOS transistor P1 is clamped to a threshold voltage different from the input voltage amplitude, so that the difference between the gate voltage and the source voltage of the first PMOS transistor P1 is within a normal range without breaking down, and the first PMOS transistor P1 is protected to a certain extent. When the first PMOS transistor P1 is turned on, the resistor R5 is used to limit the current from being too large, and at the same time, the second PMOS transistor P2 and the third PMOS transistor P3 are turned off, the fourth PMOS transistor P4 is turned on, and no output voltage is provided at the output terminal, thereby achieving overvoltage protection.

When the trigger circuit is not triggered, the fourth PMOS tube P4 is cut off, and the resistor R2 is connected into the circuit; when the trigger circuit is triggered, the fourth PMOS transistor P4 is turned on, and the resistor R2 is short-circuited. Therefore, the hysteresis voltage can be set by adjusting the proportional relation between R2 and R1, and specifically, the hysteresis voltage is the breakdown voltage of the zener diode D1 plus the voltage drop of the breakdown current at the time across the resistance of R1. After the overvoltage protection circuit is triggered, as long as the input voltage of the input terminal is between the overvoltage protection threshold and the hysteresis voltage, the third PMOS transistor P3 is still in the off state, so that the third PMOS transistor P3 can be ensured not to be intermittently turned on and off due to the fluctuation of the input voltage of the input terminal.

Compared with the prior art, the utility model beneficial effect who has is: the overvoltage protection threshold value is set through the breakdown voltage of the voltage stabilizing diode D1, when the input voltage is too high, the voltage stabilizing diode D1 is broken down, the control circuit controls the third PMOS tube P3 to be disconnected, the output terminal does not have output voltage, overvoltage protection is carried out on a load connected with the output terminal, and the structure of the whole overvoltage protection circuit is simplified.

Drawings

The utility model discloses there is following figure:

FIG. 1 is a block diagram of the present invention;

fig. 2 is a schematic circuit diagram of the present invention.

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.

As shown in fig. 1-2, the overvoltage protection circuit includes an input terminal VIN, a trigger circuit 1, a control circuit 2, a switch circuit 3, and an output terminal VOUT.

The input terminal VIN is respectively electrically connected with the contact circuit 1, the control circuit 2 and the switch circuit 3, the trigger circuit 1 is electrically connected with the control circuit 2, the control circuit 2 is electrically connected with the switch circuit 3, and the switch circuit 3 is electrically connected with the output terminal VOUT.

When the input voltage of the input terminal VIN is overvoltage, the trigger circuit 1 triggers, and the control circuit 2 controls the switch circuit 3 to be switched off; when the input voltage of the input terminal VIN is in the normal range, the trigger circuit 1 is not triggered, and the control circuit 2 controls the switch circuit 3 to be turned on.

Further, the trigger circuit 1 comprises resistors R1 and R2, a zener diode D1 and a fourth PMOS transistor P4; one end of the resistor R1 is electrically connected to the input terminal VIN, the other end of the resistor R1 is electrically connected to the source of the fourth PMOS transistor P4 and one end of the resistor R2, the other end of the resistor R2 is electrically connected to the drain of the fourth PMOS transistor and the cathode of the zener diode D1, and the anode of the zener diode D1 is grounded.

Further, the control circuit 2 comprises resistors R3, R4, R5, R6, a first PMOS transistor P1, a second PMOS transistor P2, and zener diodes D2 and D3; the input terminal VIN is electrically connected to one end of a resistor R4, a source of the first PMOS transistor P1 and a source of the second PMOS transistor P2 respectively, the other end of the resistor R4 is electrically connected to a cathode of a zener diode D2, an anode of the zener diode D2 is electrically connected to a gate of the first PMOS transistor P1 and one end of a resistor R3 respectively, the other end of the resistor R3 is electrically connected to a source of the fourth PMOS transistor, a drain of the first PMOS transistor P1 is electrically connected to one end of a resistor R5 and a gate of the second PMOS transistor P2 respectively, a drain of the second PMOS transistor P2 is electrically connected to one end of a resistor R6, a cathode of the zener diode D3 and a gate of the fourth PMOS transistor P4 respectively, and the other end of the resistor R6, an anode of the zener diode D3 and the other end of.

Further, the switch circuit 3 includes a third PMOS transistor P3, a source of the third PMOS transistor P3 is electrically connected to the input terminal VIN, a drain of the third PMOS transistor P3 is electrically connected to the output terminal VOUT, and a gate of the third PMOS transistor P3 is electrically connected to a gate of the second PMOS transistor P2.

Furthermore, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the fourth PMOS transistor P4 are enhancement type PMOS transistors.

The over-voltage protection threshold is the breakdown voltage of zener diode D1 plus the voltage drop of the breakdown current over the R1 and R2 resistors at that time. When the input voltage of the input terminal VIN is lower than the overvoltage protection threshold, the zener diode D1 is not broken down, and at this time, there is no conducting current in the branch where the zener diode D1 is located, the gate potential of the first PMOS transistor P1 is high and is not yet turned on, the resistor R5 pulls the gate potentials of the second PMOS transistor P2 and the third PMOS transistor P3 to a low level, so the second PMOS transistor P2 and the third PMOS transistor P3 are in a fully conducting state, the resistor R6 limits the current in the branch where the second PMOS transistor P2 is located, the P4 is in a cut-off state, and the output voltage of the output terminal VOUT is the same as the input voltage of the input terminal VIN.

When the input voltage of the input terminal VIN is higher than the overvoltage protection threshold, the zener diode D1 is broken down, and at this time, the branch where the zener diode D1 is located generates a conducting current, the gate potential of the first PMOS transistor P1 is pulled to a low potential and controlled by the clamping voltage of the zener diode D2, and the gate potential of the first PMOS transistor P1 is clamped to a threshold voltage different from the input voltage amplitude, so that the difference between the gate voltage and the source voltage of the first PMOS transistor P1 is within a normal range without breaking down, and the first PMOS transistor P1 is protected to a certain extent. When the first PMOS transistor P1 is turned on, the resistor R5 is used to limit the current from being too large, and meanwhile, the second PMOS transistor P2 and the third PMOS transistor P3 are turned off, the fourth PMOS transistor P4 is turned on, and no output voltage is provided at the output terminal VOUT, thereby achieving overvoltage protection.

When the trigger circuit 1 is not triggered, the fourth PMOS tube P4 is cut off, and the resistor R2 is connected into the circuit; when the trigger circuit 1 triggers, the fourth PMOS transistor P4 is turned on, and the resistor R2 is short-circuited. Therefore, the proportional relation between R2 and R1 can be adjusted to set the hysteresis voltage, which is the breakdown voltage of the Zener diode D1 plus the voltage drop of the breakdown current on the R1 resistor. After the overvoltage protection circuit is triggered, as long as the input voltage of the input terminal VIN is between the overvoltage protection threshold and the hysteresis voltage, the third PMOS transistor P3 is still in the off state, so that the third PMOS transistor P3 is ensured not to be intermittently turned on and off due to the fluctuation of the input voltage of the input terminal VIN.

In this embodiment, if there is no resistor R2, that is, the hysteresis voltage cannot be set, the overvoltage protection threshold is the sum of the breakdown voltage of the zener diode D1 and the voltage drop of the breakdown current at this time across the resistor R1, as long as the input voltage is higher than the voltage protection threshold, the third PMOS transistor P3 is turned off, and the input voltage is lower than the overvoltage protection threshold, the third PMOS transistor is turned on, so that as long as the input voltage fluctuates back and forth at the overvoltage protection threshold, the third PMOS transistor P3 may be intermittently turned on or off, which affects the operating stability of the circuit.

In light of the above, the present invention is not limited to the above embodiments, and various changes and modifications can be made by the worker without departing from the scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims

1. Overvoltage protection circuit, its characterized in that: the circuit comprises an input terminal, a trigger circuit, a control circuit, a switch circuit and an output terminal;

the input terminal is respectively and electrically connected with the contact circuit, the control circuit and the switch circuit, the trigger circuit is electrically connected with the control circuit, the control circuit is electrically connected with the switch circuit, and the switch circuit is electrically connected with the output terminal;

when the input voltage of the input terminal is over-voltage, the trigger circuit triggers, and the control circuit drives the switch circuit to be disconnected; when the input voltage of the output terminal is in a normal range, the trigger circuit is not triggered, and the control circuit drives the switch circuit to be conducted.

2. The overvoltage protection circuit of claim 1, wherein: the trigger circuit comprises resistors R1 and R2, a voltage-stabilizing diode D1 and a fourth PMOS tube P4; one end of the resistor R1 is electrically connected with the input terminal, the other end of the resistor R1 is electrically connected with the source electrode of the fourth PMOS tube P4 and one end of the resistor R2 respectively, the other end of the resistor R2 is electrically connected with the drain electrode of the fourth PMOS tube and the cathode of the voltage stabilizing diode D1 respectively, and the anode of the voltage stabilizing diode D1 is grounded.

3. The overvoltage protection circuit of claim 2, wherein: the control circuit comprises resistors R3, R4, R5, R6, a first PMOS tube P1, a second PMOS tube P2, and voltage-stabilizing diodes D2 and D3; the input terminals are respectively and electrically connected with one end of a resistor R4, a source electrode of a first PMOS tube P1 and a source electrode of a second PMOS tube P2, the other end of the resistor R4 is electrically connected with a negative electrode of a voltage stabilizing diode D2, an anode of a voltage stabilizing diode D2 is respectively and electrically connected with a grid electrode of the first PMOS tube P1 and one end of a resistor R3, the other end of the resistor R3 is electrically connected with a source electrode of the fourth PMOS tube, a drain electrode of the first PMOS tube P1 is respectively and electrically connected with one end of a resistor R5 and a grid electrode of a second PMOS tube P2, a drain electrode of the second PMOS tube P2 is respectively and electrically connected with one end of the resistor R6, a negative electrode of the voltage stabilizing diode D3 and a grid electrode of the fourth PMOS tube P4, and the other ends of the resistor R6, a positive electrode of the voltage stabilizing.

4. The overvoltage protection circuit of claim 3, wherein: the switch circuit comprises a third PMOS tube P3, wherein the source electrode of the third PMOS tube P3 is electrically connected with the input terminal, the drain electrode of the third PMOS tube P3 is electrically connected with the output terminal, and the grid electrode of the third PMOS tube P3 is electrically connected with the grid electrode of the second PMOS tube P2.

5. The overvoltage protection circuit of claim 4, wherein: the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are enhancement type PMOS tubes.