WO2023108958A1 - 基于包络追踪技术和 Doherty 构架的功率放大电路及其设计方法 - Google Patents

基于包络追踪技术和 Doherty 构架的功率放大电路及其设计方法 Download PDF

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WO2023108958A1
WO2023108958A1 PCT/CN2022/085470 CN2022085470W WO2023108958A1 WO 2023108958 A1 WO2023108958 A1 WO 2023108958A1 CN 2022085470 W CN2022085470 W CN 2022085470W WO 2023108958 A1 WO2023108958 A1 WO 2023108958A1
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power supply
transistor
power
apt
doherty
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PCT/CN2022/085470
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English (en)
French (fr)
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阮金龙
夏勤
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陕西亚成微电子股份有限公司
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Priority to EP22905728.6A priority Critical patent/EP4451558A1/en
Publication of WO2023108958A1 publication Critical patent/WO2023108958A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit

Definitions

  • the invention belongs to the technical field of communication base stations, in particular to a power amplification circuit based on envelope tracking technology and Doherty framework and a design method thereof.
  • base station power amplifiers are designed with Doherty-based power amplifier circuits, which can take into account the efficiency of the average output power and the linearity of the output peak power.
  • the Doherty framework includes a first input matching network conversion module, a second input matching network conversion module, a first transistor, a second transistor, a first output matching network conversion module, a second output matching network conversion module, a first load conversion module, a second a second load conversion module and a third load conversion module;
  • the output terminal of the first input matching network conversion module is connected to the gate of the first transistor; the output terminal of the second input matching network conversion module is connected to the gate of the second transistor;
  • the input end of the first output matching network conversion module is connected to the drain of the first transistor; the input end of the second output matching network conversion module is connected to the drain of the second transistor;
  • the input end of the first load conversion module is connected with the output of the first output matching network conversion module, and the input end of the second load conversion module is connected with the output end of the second output matching network conversion module;
  • the input end of the third load changing module is respectively connected to the output end of the first load changing module and the output end of the second load changing module,
  • the external power supply adopts a fixed voltage module, and the output terminal of the fixed voltage module is connected to the drain of the first transistor, or connected to the drain of the first transistor and the drain of the second transistor respectively.
  • the fixed voltage module can only provide a fixed leakage voltage
  • the power amplifier circuit is in the linear region when the expected average output power of the base station falls back, so the efficiency is difficult to guarantee.
  • the present invention proposes a power amplifier circuit based on envelope tracking technology and Doherty architecture.
  • the output terminals of the ET power supply or the APT power supply are simultaneously connected to the drains of the first transistor and the second transistor in the Doherty architecture.
  • the above-mentioned Doherty architecture is a Doherty architecture suitable for narrowband signals, or a double-matched Doherty architecture suitable for wideband signals.
  • the present invention also provides the above-mentioned design method based on the envelope tracking technology and the power amplifier circuit of the Doherty framework, and the specific implementation steps are as follows:
  • Step 1 Determine the saturation power P1 of the power amplifier circuit according to the given input signal peak-to-average ratio PAR and the average effective output power Pave;
  • P1 Pave+PAR
  • Step 2 Determine the saturation power value P1/2 of a single transistor in the Doherty architecture
  • Step 3 Using simulation software and calling a single transistor model, perform loadpull simulation, adjust the leakage voltage of a single transistor model, record the corresponding leakage voltage value of the transistor model when the saturation power of the transistor model is P1/2, and use this leakage voltage value as ET The maximum voltage value of the power supply or APT power supply , and the corresponding drain voltage value of the transistor model when the saturation power of the transistor model is Pave, and take this drain voltage value as the average effective voltage value of the ET power supply or APT power supply ;
  • Step 4 Pass the maximum voltage value and mean rms voltage Calculate the minimum voltage value of ET power supply or APT power supply , get the voltage range of ET power supply or APT power supply, so as to select the appropriate ET power supply or APT power supply;
  • Step 5 Match the ET power supply or APT power supply with the transistor
  • Step 5.1 According to the optimal load value R1 of the selected ET power supply or APT power supply and the drain efficiency DE when the transistor outputs the rated power, obtain the impedance R2 at the pLanA end face of the transistor current source output terminal when the transistor outputs the average power;
  • V1 is the characteristic voltage of the transistor, and the drain efficiency DE when the transistor outputs the rated power is obtained when performing step 3;
  • Step 5.2 Based on the Smith circle impedance transformation method, the impedance of the load is converted to the impedance R2 at the end face of the output terminal pLanA of the transistor current source, so as to realize the matching between the ET power supply or the APT power supply and the transistor;
  • Step 6 The power amplifier circuit based on envelope tracking technology is built.
  • simulation software adopts the Advanced Design System design software system.
  • the power amplifier circuit proposed by the present invention can realize effective matching between Doherty architecture and ET/APT; when ET (Envelope Tracking) power or APT (Average When the optimal load value of the Power Tracking) power supply and the equivalent resistance value at the transistor current source meet the matching conditions, the best matching effect between ET/APT and the transistor is achieved, and the overall efficiency of the entire ET/APT+ transistor is optimized; when the output When the power is backed off by 3dB or 6dB from the rated power, since a voltage value lower than the fixed leakage voltage is used, the power amplifier also works in a saturated state under the backed-off power, which can effectively improve the efficiency at this output power.
  • ET envelope Tracking
  • APT Average When the optimal load value of the Power Tracking
  • Fig. 1 is a traditional structural schematic diagram of a Doherty-based power amplifier circuit suitable for narrowband
  • Fig. 2 is a schematic structural diagram of a conventional Doherty-based power amplifier circuit suitable for broadband
  • Fig. 3 is the structural representation of the power amplifying circuit of embodiment 1;
  • Fig. 4 is the structural representation of the power amplifying circuit of embodiment 2;
  • Envelope Tracking ET envelope Tracking
  • APT Average Power Tracking
  • the present invention provides a power amplifier circuit based on envelope tracking technology and Doherty architecture, including Doherty architecture and external power supply; the main idea of improvement of the circuit is: external power supply adopts ET power supply or APT power supply; ET power supply or APT power supply The output end of the first transistor in the Doherty architecture is connected to the drain of the first transistor, or the output end of the ET power supply or the APT power supply is connected to the drains of the first transistor and the second transistor in the Doherty architecture at the same time;
  • the ET power supply or APT power supply When the ET power supply or APT power supply is connected to the first transistor, it is only necessary to complete the matching of the ET power supply or APT power supply and the first transistor; when the ET power supply or APT power supply is connected to the first transistor and the second transistor at the same time, it is necessary to complete network tracing The power supply is matched with the first transistor and the second transistor.
  • the present invention does not simply combine the ET power supply or APT power supply with the Doherty architecture, how to realize the optimal matching between the ET power supply or the APT power supply and the Doherty architecture, thereby ensuring the output efficiency of the transistor and making the entire ET/APT+ transistor
  • the overall efficiency reaches optimum, the present invention also provides the design method of circuit, and concrete process is as follows:
  • Step 1 Determine the saturation power P1 of the power amplifier circuit according to the given input signal peak-to-average ratio PAR and the average effective output power Pave;
  • P1 Pave+PAR
  • Step 2 Determine the saturation power value P1/2 of a single transistor in the Doherty architecture
  • Step 3 Use simulation software (Advanced Design System) to call a single transistor model, perform loadpull simulation, adjust the leakage voltage of a single transistor model, record the corresponding transistor model leakage voltage value when the saturation power of the transistor model is P1/2, and store the Leakage voltage value as the maximum voltage value of ET power supply or APT power supply , and the corresponding drain voltage value of the transistor model when the saturation power of the transistor model is Pave, and take this drain voltage value as the average effective voltage value of the ET power supply or APT power supply ;
  • Step 4 Pass the maximum voltage value and mean rms voltage Calculate the minimum voltage value of ET power supply or APT power supply , get the voltage range of ET power supply or APT power supply, so as to select the appropriate ET power supply or APT power supply;
  • Step 5 Match the ET power supply or APT power supply with the transistor
  • Step 5.1 According to the optimal load value R1 of the selected ET power supply or APT power supply and the drain efficiency DE when the transistor outputs the rated power, obtain the impedance R2 at the pLanA end face of the transistor current source output terminal when the transistor outputs the average power;
  • V1 is the characteristic voltage of the transistor, and the drain efficiency DE when the transistor outputs the rated power is obtained when performing step 3;
  • Step 5.2 Based on the Smith circle impedance transformation method, the impedance of the load is converted to the impedance R2 at the end face of the output terminal pLanA of the transistor current source, so as to realize the matching between the ET power supply or the APT power supply and the transistor;
  • Step 6 The power amplifier circuit based on envelope tracking technology is built.
  • This embodiment has provided the power amplification circuit structure based on envelope tracking technology and Doherty framework suitable for narrowband, as shown in Figure 3, comprises the first input matching network conversion module, the second input matching network conversion module, the first transistor , a second transistor, an ET power supply or an APT power supply, a first output matching network transformation module, a second output matching network transformation module, a first load transformation module, a second load transformation module, and a third load transformation module;
  • the output terminal of the first input matching network conversion module is connected to the gate of the first transistor; the output terminal of the second input matching network conversion module is connected to the gate of the second transistor;
  • the source and ground of the first transistor and the second transistor; both the first transistor and the second transistor include respective internal current source output terminals pLanA and external output terminals pLanB;
  • the output end of the ET power supply or the APT power supply is connected to the drain of the first transistor, or the output end of the ET power supply or the APT power supply is connected to the drains of the first transistor and the second transistor at the same time; in this embodiment, the ET power supply or the APT power supply only connected to the drain of the first transistor;
  • the input end of the first output matching network conversion module is connected to the drain of the first transistor; the input end of the second output matching network conversion module is connected to the drain of the second transistor;
  • the input end of the first load conversion module is connected to the output end of the first output matching network conversion module, and the input end of the second load conversion module is connected to the output end of the second output matching network conversion module;
  • the input end of the third load changing module is respectively connected to the output end of the first load changing module and the output end of the second load changing module,
  • the output end of the third load changing module is connected to an external load
  • the first input matching network conversion module and the second input matching network conversion module are used to match the maximum gain impedance of the first transistor and the second transistor to a preset impedance;
  • the first transistor and the second transistor are used for signal amplification to facilitate signal transmission;
  • the ET power supply or the APT power supply is used to provide a variable voltage to the first transistor and/or the second transistor to improve the efficiency of the power amplifier;
  • the first output matching network conversion module and the second output matching network conversion module are respectively used to match the maximum power point impedance of the first transistor and the second transistor to a preset impedance;
  • the first load conversion module is used to realize the high efficiency of the power amplifier when the first transistor outputs the rated power output;
  • the second load conversion module is used to realize that when the second transistor circuit is connected, it has no influence on the circuit where the first transistor is located (that is, the first input matching network conversion module to the load). If it is affected, it will cause the first transistor to output rated power. Efficiency becomes lower.
  • the third load changing module is used to convert the load impedance into the input point impedance of the third load changing module.
  • the first output matching network conversion module and the second output matching network conversion module, the first input matching network conversion module and the second input matching network conversion module are all composed of microstrip lines and capacitors;
  • the first transistor Both the transistor and the second transistor include an equivalent resistance, a voltage-controlled current source, a parasitic inductance and a parasitic capacitance.
  • the first input matching network conversion module matches the 50 ohm load impedance to the maximum gain impedance of the first transistor; the first output matching network conversion module matches the 50 ohm load to the maximum power point of the first transistor ( Plan B end face) impedance; the first load transformation module and the third load change module work together to match the 50 ohm load to 100 ohm, and use the first output matching network conversion module to match the converted 100 ohm resistance to the PLanA end face.
  • the first output matching network conversion module is used to match the converted 100-ohm resistance to the end face of PLanA, which is the same as matching the converted 100-ohm resistance to the maximum efficiency point (PLanA) of the power amplifier in the traditional implementation mode.
  • B end face) impedance is different.
  • This embodiment provides the power amplification circuit based on envelope tracking technology and Doherty architecture suitable for broadband, as shown in Figure 4, including a first input matching module, a second input matching module, a first transistor, a second transistor, ET power supply or APT power supply, a first output matching module, a second output matching module and a load conversion module;
  • the output terminal of the first input matching module is connected to the gate of the first transistor; the output terminal of the second input matching module is connected to the gate of the second transistor;
  • the source and ground of the first transistor and the second transistor; both the first transistor and the second transistor include respective internal current source output terminals pLanA and external output terminals pLanB;
  • the output end of the ET power supply or the APT power supply is connected to the drain of the first transistor, or the output end of the ET power supply or the APT power supply is connected to the drains of the first transistor and the second transistor at the same time; in this embodiment, the ET power supply or the APT power supply only connected to the drain of the first transistor;
  • the input end of the first output matching module is connected to the drain of the first transistor; the input end of the second output matching module is connected to the drain of the second transistor;
  • the input end of the load conversion module is connected to the output end of the first output matching module and the output end of the second output matching module;
  • the first input matching module and the second input matching module, the first output matching module and the second output matching module are composed of microstrip lines and capacitors; the first transistor and the second transistor both include equivalent resistors, voltage-controlled current sources, parasitic inductance, and parasitic capacitance.
  • the first input matching module matches the 50 ohm load to the maximum gain impedance of the first transistor; the first output matching module matches the 25 ohm load to the best efficiency point impedance of the first transistor when the signal is small ;
  • the 25 ohm load is matched to the maximum power point of the first transistor (PLan B terminal) impedance (25 ohms is the input point impedance of the load transformation module, which is obtained by cascading the load transformation module with a 50-ohm load); the load transformation module matches the 50-ohm load to 25 ohms;
  • Input the input signal to the first input matching module.
  • the 50 ohm load is converted to 25 ohm through the load conversion module in turn, and the 25 ohm is added to the 50 ohm load through the load conversion module. It is obtained by cascading; the output matching module is used to match the converted 25 ohm resistor to the end face of PLanA.
  • the end face of pLan A represents the output end of the internal current source of the first transistor, that is, the junction of the dotted line and the solid line of pLan A in Fig. 3 and Fig. 4;
  • the end face of pLan B represents the external output end of the first transistor, namely Fig. 3 and the junction of pLan B dotted line and solid line in Figure 4.

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  • Physics & Mathematics (AREA)
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Abstract

本发明公开了一种基于包络追踪技术和Doherty构架的功率放大电路及其设计方法，该电路包括Doherty架构以及外置电源；所述外置电源为ET电源或APT电源；ET电源或APT电源的输出端接入Doherty架构中第一晶体管的漏极；或者ET电源或APT电源的输出端同时与Doherty架构中第一晶体管和第二晶体管的漏极连接。该电路使得功放在回退功率下也工作在饱和状态，进而可以有效提高此输出功率下的效率。

Description

基于包络追踪技术和Doherty构架的功率放大电路及其设计方法 技术领域
本发明属于通信基站技术领域，特别是一种基于包络追踪技术和Doherty构架的功率放大电路及其设计方法。
 背景技术
目前基站类功放在设计的时候都是采用多尔蒂（Doherty）构架的功率放大电路，该功率放大电路可以很好的兼顾输出平均功率时的效率和输出峰值功率时的线性度。
传统的适用于窄带信号的Doherty架构功放电路结构原理如图1所示，包括Doherty构架以及外置电源；
Doherty构架包括第一输入匹配网络转化模块、第二输入匹配网络转化模块、第一晶体管、第二晶体管、第一输出匹配网络转化模块、第二输出匹配网络转化模块、第一负载变换模块、第二负载变换模块以及第三负载变换模块；
第一输入匹配网络转化模块其输出端连接所述第一晶体管的栅极；第二输入匹配网络转化模块的输出端连接所述第二晶体管的栅极；
第一晶体管与第二晶体管的源极与接地；
第一输出匹配网络转化模块的输入端与第一晶体管的漏极连接；第二输出匹配网络转化模块的输入端与第二晶体管的漏极连接；
第一负载变换模块的输入端与第一输出匹配网络转化模块的输出短连接，第二负载变换模块的输入端与第二输出匹配网络转化模块的输出端连接；
第三负载变化模块的输入端分别与第一负载变换模块的输出端以及第二负载变化模块的输出端连接，
第三负载变化模块的输出端及外部负载；
外置电源采用固定电压模块，固定电压模块的输出端与第一晶体管的漏极连接，或者分别和第一晶体管的漏极以及第二晶体管的漏极连接。
由于传统Doherty架构的功放电路窄带特性逐步显现，为了解决带宽偏窄的问题，国内国外相关专家提出了双匹配的Doherty架构的功放电路，其结构如图2所示。该功放电路可以很好的解决带宽问题。
但不论是适用于窄带Doherty架构的功放电路或是适用于宽带Doherty架构的功放电路都存在以下问题：
由于使用了固定电压模块仅能提供固定漏压，在基站期望的平均输出功率有回退的时候，功放电路处于线性区，所以效率都很难保证。
发明内容
针对传统Doherty架构的功放电路存在效率难以保证的问题，本发明提出一种基于包络追踪技术和Doherty构架的功率放大电路。
同时提供了该电路的设计方法。
本发明的目的是通过以下技术方案予以实现，
一种基于包络追踪技术和Doherty构架的功率放大电路，包括Doherty架构以及外置电源；所述外置电源为ET电源或APT电源；ET电源或APT电源的输出端接入Doherty架构中第一晶体管的漏极；
或者ET电源或APT电源的输出端同时与Doherty架构中第一晶体管和第二晶体管的漏极连接。
进一步地，上述Doherty架构为适用于窄带信号的Doherty架构，或者为适用于宽带信号的双匹配Doherty架构。
本发明还提供了上述基于包络追踪技术和Doherty构架的功率放大电路的设计方法，具体实现步骤如下：
步骤1：根据给定的输入信号峰均比PAR和平均有效输出功率Pave确定功率放大电路的饱和功率P1；
P1=Pave+PAR；
步骤2：确定Doherty架构中单个晶体管的饱和功率值P1/2；
步骤3：采用仿真软件并调用单个晶体管模型，进行loadpull仿真，调整单个晶体管模型漏压，记录晶体管模型的饱和功率为P1/2时对应的晶体管模型漏压值，并将该漏压值作为ET电源或APT电源的最大电压值
Figure dest_path_image001
，以及晶体管模型的饱和功率为Pave时对应的晶体管模型漏压值,并将该漏压值作为ET电源或APT电源的平均有效电压值
Figure 168804dest_path_image002
；
步骤4：通过最大电压值
Figure dest_path_image003
和平均有效电压值
Figure 482017dest_path_image004
求取ET电源或APT电源的最小电压值
Figure dest_path_image005
，得到ET电源或APT电源的电压范围，从而选取合适的ET电源或APT电源；
具体计算公式如下：
Figure 855230dest_path_image006
；
其中，
Figure dest_path_image007
、
Figure 843914dest_path_image008
为正数因子，取值范围均大于0且小于1；
步骤5：ET电源或APT电源与晶体管的匹配；
步骤5.1：根据选取的ET电源或APT电源最佳负载值R1以及晶体管输出额定功率时的漏级效率DE，得出晶体管输出平均功率时晶体管电流源输出端pLanA端面处的阻抗R2；
具体计算公式如下：
Figure dest_path_image009
，
其中， V1为晶体管自有特征电压，晶体管输出额定功率时的漏级效率DE再执行步骤3时获取；
步骤5.2：基于史密斯圆阻抗变换方法将负载的阻抗转化到晶体管电流源输出端pLanA端面处的阻抗R2处，从而实现ET电源或APT电源与晶体管的匹配；
步骤6：基于包络追踪技术的功率放大电路搭建完成。
进一步地，上述仿真软件采用Advanced Design System设计软件系统。
与现有技术相比，本发明的有益技术效果如下：
相比于传统的Doherty架构功率放大电路及双匹配Doherty架构功率放大电路，本发明提出的功率放大电路，可实现Doherty架构与ET/APT之间有效匹配；当ET（Envelope Tracking）电源或APT（Average Power Tracking）电源的最佳负载值与晶体管电流源处的等效电阻值满足匹配条件时，实现ET/APT和晶体管最佳匹配效果，使整个ET/APT+晶体管的整体效率达到最优；当输出功率是额定功率回退3dB或者6dB时，由于使用了比固定漏压更低的电压值，使得功放在回退功率下也工作在饱和状态，进而可以有效提高此输出功率下的效率。
 附图说明
通过阅读下文优选的具体实施方式中的详细描述，本发明各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。说明书附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。显而易见地，下面描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。而且在整个附图中，用相同的附图标记表示相同的部件。
图1为传统适用于窄带的基于Doherty构架的功率放大电路结构示意图；
图2为传统适用于宽带的基于Doherty构架的功率放大电路结构示意图；
图3为实施例1的功率放大电路结构示意图；
图4为实施例2的功率放大电路结构示意图；
具体实施方式
下面将参照附图更详细地描述本发明的具体实施例。虽然附图中显示了本发明的具体实施例，然而应当理解，可以以各种形式实现本发明而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本发明，并且能够将本发明的范围完整的传达给本领域的技术人员。
需要说明的是，在说明书及权利要求当中使用了某些词汇来指称特定组件。本领域技术人员应可以理解，技术人员可能会用不同名词来称呼同一个组件。本说明书及权利要求并不以名词的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。如在通篇说明书及权利要求当中所提及的“包含”或“包括”为一开放式用语，故应解释成“包含但不限定于”。说明书后续描述为实施本发明的较佳实施方式，然所述描述乃以说明书的一般原则为目的，并非用以限定本发明的范围。本发明的保护范围当视所附权利要求所界定者为准。
为便于对本发明实施例的理解，下面将结合附图以具体实施例为例做进一步的解释说明，且各个附图并不构成对本发明实施例的限定。
包络追踪ET（Envelope Tracking）技术或平均功率追踪APT（Average Power Tracking）技术可以根据功放输入射频信号的大小来调整功放漏级电压，既可以保证峰值信号的高线性度，也能保证均值信号和小信号时的高效率。所以ET_PA技术一直是功放高效率方案研究的热点。
本发明提供了一种基于包络追踪技术和Doherty构架的功率放大电路，包括Doherty架构以及外置电源；该电路的主要改进思路是：外置电源采用ET电源或APT电源；ET电源或APT电源的输出端接入Doherty架构中第一晶体管的漏极，或者ET电源或APT电源的输出端同时与Doherty架构中第一晶体管和第二晶体管的漏极连接；
当ET电源或APT电源与第一晶体管连接时，只需完成ET电源或APT电源与第一晶体管的匹配；当ET电源或APT电源同时连接第一晶体管和第二晶体管时，需分别完成络追踪电源与第一晶体管、第二晶体管的匹配。
但是，本发明并不是简单的将ET电源或APT电源和Doherty架构进行结合，如何实现ET电源或APT电源和Doherty架构之间的最优匹配，从而确保晶体管的输出效率，使整个ET/APT+晶体管的整体效率达到最优，本发明还提供了电路的设计方法，具体过程如下：
步骤1：根据给定的输入信号峰均比PAR和平均有效输出功率Pave确定功率放大电路的饱和功率P1；
P1=Pave+PAR；
步骤2：确定Doherty架构中单个晶体管的饱和功率值P1/2；
步骤3：采用仿真软件（Advanced Design System）并调用单个晶体管模型，进行loadpull仿真，调整单个晶体管模型漏压，记录晶体管模型的饱和功率为P1/2时对应的晶体管模型漏压值，并将该漏压值作为ET电源或APT电源的最大电压值
Figure 517341dest_path_image010
，以及晶体管模型的饱和功率为Pave时对应的晶体管模型漏压值,并将该漏压值作为ET电源或APT电源的平均有效电压值
Figure dest_path_image011
；
步骤4：通过最大电压值
Figure 933279dest_path_image012
和平均有效电压值
Figure dest_path_image013
求取ET电源或APT电源的最小电压值
Figure 793788dest_path_image014
，得到ET电源或APT电源的电压范围，从而选取合适的ET电源或APT电源；
具体计算公式如下：
Figure dest_path_image015
；
其中，
Figure 586163dest_path_image016
、
Figure dest_path_image017
为正数因子，取值范围均大于0且小于1；
步骤5：ET电源或APT电源与晶体管的匹配；
步骤5.1：根据选取的ET电源或APT电源最佳负载值R1以及晶体管输出额定功率时的漏级效率DE，得出晶体管输出平均功率时晶体管电流源输出端pLanA端面处的阻抗R2；
具体计算公式如下：
Figure 848517dest_path_image018
，
其中， V1为晶体管自有特征电压，晶体管输出额定功率时的漏级效率DE再执行步骤3时获取；
步骤5.2：基于史密斯圆阻抗变换方法将负载的阻抗转化到晶体管电流源输出端pLanA端面处的阻抗R2处，从而实现ET电源或APT电源与晶体管的匹配；
步骤6：基于包络追踪技术的功率放大电路搭建完成。
基于上述对本发明电路改进思路及设计方法的说明，现根据以下两个实施例对本发明进行详细的介绍：
实施例1
该实施例给出了适用于窄带的基于包络追踪技术和Doherty构架的功率放大电路结构，如图3所示，包括第一输入匹配网络转化模块、第二输入匹配网络转化模块、第一晶体管、第二晶体管、ET电源或APT电源、第一输出匹配网络转化模块、第二输出匹配网络转化模块、第一负载变换模块、第二负载变换模块以及第三负载变换模块；
第一输入匹配网络转化模块其输出端连接所述第一晶体管的栅极；第二输入匹配网络转化模块的输出端连接所述第二晶体管的栅极；
第一晶体管与第二晶体管的源极与接地；第一晶体管与第二晶体管都包括各自的内部电流源输出端pLanA和外部输出端pLanB；
ET电源或APT电源的输出端接入第一晶体管的漏极，或者ET电源或APT电源的输出端同时与第一晶体管和第二晶体管的漏极连接；本实施例中ET电源或APT电源仅连接所述第一晶体管的漏极；
第一输出匹配网络转化模块的输入端与第一晶体管的漏极连接；第二输出匹配网络转化模块的输入端与第二晶体管的漏极连接；
第一负载变换模块的输入端与第一输出匹配网络转化模块的输出端连接，第二负载变换模块的输入端与第二输出匹配网络转化模块的输出端连接；
第三负载变化模块的输入端分别与第一负载变换模块的输出端以及第二负载变化模块的输出端连接，
第三负载变化模块的输出端及外部负载连接；
本实施例中，各组成部分的功能如下：
第一输入匹配网络转化模块和第二输入匹配网络转化模块，用于将第一晶体管和第二晶体管的最大增益阻抗匹配到预设阻抗；
第一晶体管和第二晶体管用于信号放大，便于信号传输；
ET电源或APT电源用于给第一晶体管和/或第二晶体管提供可变电压，提高功率放大器的效率；
第一输出匹配网络转化模块和第二输出匹配网络转化模块分别用于将第一晶体管和第二晶体管的最大功率点阻抗匹配到预设阻抗；
第一负载变换模块，用于第一晶体管输出额定功率输出时实现功放的高效率；
第二负载变换模块，用于实现第二晶体管电路接入时对第一晶体管所在电路（即第一输入匹配网络转化模块至负载）无影响，如果造成影响，会导致第一晶体管输出额定功率时效率变低。
第三负载变化模块，用于将负载阻抗转换为第三负载变换模块的输入点阻抗。
本实施例中：第一输出匹配网络转化模块和第二输出匹配网络转化模块、第一输入匹配网络转化模块和第二输入匹配网络转化模块均由微带线和电容组成；所述第一晶体管和第二晶体管均包括等效电阻、压控电流源、寄生电感和寄生电容。
本实施例在工作时：第一输入匹配网络转化模块将50欧姆负载阻抗匹配到第一晶体管的最大增益阻抗；第一输出匹配网络转化模块将50欧姆负载匹配到第一晶体管的最大功率点（PLan B端面）阻抗；第一负载变换模块和第三负载变化模块共同作用将50欧姆负载匹配到100欧姆，采用第一输出匹配网络转化模块将转换的100欧姆电阻匹配到PLanA端面。
其中，采用第一输出匹配网络转化模块将转换的100欧姆电阻匹配到PLanA端面，与传统实施方式中将转换的100欧姆电阻匹配到功率放大器的最大效率点（PLan B端面）阻抗不同。
实施例2
该实施例给出了适用于宽带的基于包络追踪技术和Doherty构架的功率放大电路，如图4所示，包括第一输入匹配模块、第二输入匹配模块、第一晶体管、第二晶体管、ET电源或APT电源、第一输出匹配模块、第二输出匹配模块以及负载变换模块；
第一输入匹配模块的输出端连接所述第一晶体管的栅极；第二输入匹配模块的输出端连接所述第二晶体管的栅极；
第一晶体管与第二晶体管的源极与接地；第一晶体管与第二晶体管都包括各自的内部电流源输出端pLanA和外部输出端pLanB；
ET电源或APT电源的输出端接入第一晶体管的漏极，或者ET电源或APT电源的输出端同时与第一晶体管和第二晶体管的漏极连接；本实施例中ET电源或APT电源仅连接所述第一晶体管的漏极；
第一输出匹配模块的输入端与第一晶体管的漏极连接；第二输出匹配模块的输入端与第二晶体管的漏极连接；
负载变换模块的输入端与第一输出匹配模块的输出端以及第二输出匹配模块的输出端连接；
负载变化模块的输出端及外部负载连接；
本实施例中：第一输入匹配模块和第二输入匹配模块、第一输出匹配模块和第二输出匹配模块均由微带线和电容组成；所述第一晶体管和第二晶体管均包括等效电阻、压控电流源、寄生电感和寄生电容。
本实施例在工作时：第一输入匹配模块将50欧姆负载匹配到第一晶体管的最大增益阻抗；第一输出匹配模块在小信号时将25欧姆负载匹配到第一晶体管的最佳效率点阻抗；在大信号时25欧姆负载匹配到第一晶体管的最大功率点（PLan B端面）阻抗（其中25欧姆为负载变换模块的输入点阻抗，是通过负载变换模块加50欧姆的负载级联得到）；负载变换模块将50欧姆负载匹配到25欧姆；
将输入信号输入到第一输入匹配模块，与流过包络追踪电源的信号重合后，依次通过负载变换模块，将50欧姆负载转换为25欧姆，其中25欧姆是通过负载变换模块加50欧姆负载级联得到；采用输出匹配模块将转换的25欧姆电阻匹配到PLanA端面。
图3与图4中，pLan A端面表示第一晶体管内部电流源输出端，即图3与图4中pLan A虚线与实线的结点；pLan B端面表示第一晶体管外部输出端，即图3与图4中pLan B虚线与实线的结点。
尽管以上结合附图对本发明的实施方案进行了描述，但本发明并不局限于上述的具体实施方案和应用领域，上述的具体实施方案仅仅是示意性的、指导性的，而不是限制性的。本领域的普通技术人员在本说明书的启示下和在不脱离本发明权利要求所保护的范围的情况下，还可以做出很多种的形式，这些均属于本发明保护之列。

Claims (4)

  1. 一种基于包络追踪技术和Doherty构架的功率放大电路，包括Doherty架构以及外置电源；其特征在于：
    所述外置电源为ET电源或APT电源；ET电源或APT电源的输出端接入Doherty架构中第一晶体管的漏极；
    或者ET电源或APT电源的输出端同时与Doherty架构中第一晶体管和第二晶体管的漏极连接。
  2. 根据权利要求1所述的基于包络追踪技术和Doherty构架的功率放大电路，其特征在于：Doherty架构为适用于窄带信号的Doherty架构，或者为适用于宽带信号的双匹配Doherty架构。
  3. 一种如权利要求1所述的基于包络追踪技术和Doherty构架的功率放大电路的设计方法，其特征在于，包括以下步骤：
    步骤1：根据给定的输入信号峰均比PAR和平均有效输出功率Pave确定功率放大电路的饱和功率P1；
    P1=Pave+PAR；
    步骤2：确定Doherty架构中单个晶体管的饱和功率值P1/2；
    步骤3：采用仿真软件并调用单个晶体管模型，进行loadpull仿真，调整单个晶体管模型漏压，记录晶体管模型的饱和功率为P1/2时对应的晶体管模型漏压值，并将该漏压值作为ET电源或APT电源的最大电压值
    Figure dest_path_image001
    ，以及晶体管模型的饱和功率为Pave时对应的晶体管模型漏压值,并将该漏压值作为ET电源或APT电源的平均有效电压值
    Figure 980187dest_path_image002
    ；
    步骤4：通过最大电压值
    Figure dest_path_image003
    和平均有效电压值
    Figure 327991dest_path_image004
    求取ET电源或APT电源的最小电压值
    Figure dest_path_image005
    ，得到ET电源或APT电源的电压范围，从而选取合适的ET电源或APT电源；
    具体计算公式如下：
    Figure 738374dest_path_image006
    ；
    其中，
    Figure dest_path_image007
    、
    Figure 651972dest_path_image008
    为正数因子，取值范围均大于0且小于1；
    步骤5：ET电源或APT电源与晶体管的匹配；
    步骤5.1：根据选取的ET电源或APT电源最佳负载值R1以及晶体管输出额定功率时的漏级效率DE，得出晶体管输出平均功率时晶体管电流源输出端pLanA端面处的阻抗R2；
    具体计算公式如下：
    Figure dest_path_image009
    ，
    其中， V1为晶体管自有特征电压，晶体管输出额定功率时的漏级效率DE再执行步骤3时获取；
    步骤5.2：基于史密斯圆阻抗变换方法将负载的阻抗转化到晶体管电流源输出端pLanA端面处的阻抗R2处，从而实现ET电源或APT电源与晶体管的匹配；
    步骤6：基于包络追踪技术的功率放大电路搭建完成。
  4. 根据权利要求3所述基于包络追踪技术和Doherty构架的功率放大电路的设计方法，其特征在于：所述仿真软件采用Advanced Design System设计软件系统。
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