WO2023108649A1 - 用于版图映射的方法、装置、设备、介质以及程序产品 - Google Patents

用于版图映射的方法、装置、设备、介质以及程序产品 Download PDF

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Publication number
WO2023108649A1
WO2023108649A1 PCT/CN2021/139313 CN2021139313W WO2023108649A1 WO 2023108649 A1 WO2023108649 A1 WO 2023108649A1 CN 2021139313 W CN2021139313 W CN 2021139313W WO 2023108649 A1 WO2023108649 A1 WO 2023108649A1
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Prior art keywords
layout
constraint information
circuit
devices
rules
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PCT/CN2021/139313
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English (en)
French (fr)
Inventor
蒋君文
陆肖
张富华
龚辰
张嘉瑾
叶天
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华为技术有限公司
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Priority to PCT/CN2021/139313 priority Critical patent/WO2023108649A1/zh
Priority to CN202180037029.5A priority patent/CN116710921A/zh
Publication of WO2023108649A1 publication Critical patent/WO2023108649A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Definitions

  • Embodiments of the present disclosure generally relate to the field of chip design, and more specifically relate to a method, device, device, medium and program product for layout mapping.
  • the process parameters and design rules of two different processes are often different.
  • the process parameters of a specific process may include the unit resistance and unit capacitance of the metal in this process
  • the design rules of a specific process may include The distance between the source regions and the distance between the metal lines should be greater than a predetermined value. Therefore, it is necessary to map the chip layout (also called layout migration) to ensure that the chip layout for another process can meet the design requirements.
  • a conventional mapping scheme for mapping a chip layout from one process to another process may include: using Electronic Design Automation (Electronic Design Automation, EDA) software to export from the original layout a layout design exchange format ( Graphic Design System, GDS) file; written by the designer or obtained through the tape-out manufacturer's layer migration script; and use the layer migration script to operate on the GDS file to replace the layer in the original layout and obtain a new version for the new process picture. Since the design rules of the new process are different from those of the original process, the new layout obtained in this way will often have a large number of design rule check (Design Rule Check, DRC) errors, so designers need to invest a lot of time to correct DRC problem to get a new layout ready for tapeout. Therefore, conventional layout mapping solutions are highly dependent on the manual participation of designers, which makes layout mapping less efficient and leads to a longer chip development cycle.
  • EDA Electronic Design Automation
  • GDS Graphic Design System
  • embodiments of the present disclosure aim to provide a solution for layout mapping.
  • a method for layout mapping comprising: based on a first netlist file characterizing a first circuit and a first layout for realizing the first circuit, determining a The first constraint information associated with the circuit, the first netlist file and the first layout are associated with the first process, and the first constraint information at least indicates the layout rules and wiring rules of the devices in the first circuit in the first layout; based on The first netlist file and the process design kit associated with the second process determine the second netlist file associated with the second process, the second netlist file characterizes the second circuit, the second process is different from the first process, The second circuit has the same circuit topology as the first circuit; and based on the first constraint information and the second netlist file, determining a second layout associated with the second process for implementing the second circuit.
  • This method uses the constraint information based on the original layout to carry out automatic layout and routing to replace the scheme of directly replacing hierarchical or parameterized cells in conventional schemes.
  • the method according to the present disclosure can avoid the misalignment, overlap and DRC problems in the conventional solution to the greatest extent, thus greatly reducing the workload of designers.
  • the method according to the present disclosure does not need to be customized for different processes, so that the decoupling of layout mapping and processes can be realized.
  • the layout rule includes relative position information of the multiple devices in the first circuit in the first layout
  • the wiring rule includes wiring information of the multiple devices in the first circuit in the first layout.
  • layout design the relative positional relationship between devices such as alignment and symmetry and wiring information have an important impact on the quality of the final layout.
  • the relative position information and connection information of multiple devices in the layout mapping the mature design in this aspect in the first layout can be inherited to improve the quality of the obtained second layout, thereby improving the efficiency of layout migration.
  • determining the first constraint information based on the first netlist file and the first layout includes: comparing the first layout and the first netlist file to extract the components and connections in the first circuit and Correspondence of patterns in the first layout; and extracting first constraint information from the first layout based on the correspondence. In this way, the relationship between the first circuit and the first layout can be constructed, so as to facilitate subsequent analysis of the first layout and extraction of layout rules and wiring rules from the first layout.
  • the first constraint information also indicates placement rules and routing rules of the auxiliary device in the first layout.
  • the auxiliary device is not included in the first circuit, and a pattern corresponding to the auxiliary device is included in the first layout.
  • Determining the first constraint information further includes: obtaining layer information of the first layout, the layer information indicating the position of the pattern element in the corresponding layer of the first layout; and analyzing the layer information to extract the auxiliary device in the first layout layout rules and routing rules. Since the arrangement of auxiliary devices in the first layout contains rich design experience of engineers and will affect the characteristics of other devices around, the arrangement of auxiliary devices in the first layout can also be Mapped to the second layout, so as to further improve the placement and routing quality of the second layout.
  • determining the second netlist file includes: replacing devices in the first netlist file with corresponding devices in a process design kit associated with the second process, so as to obtain the second netlist file. In this way, the second netlist file for the second process can be obtained more conveniently and quickly based on the first netlist file for the first process.
  • determining the second layout includes: determining second constraint information associated with the second circuit based on the first constraint information and the second netlist file, the second constraint information at least indicating layout rules and routing rules; and based on the second constraint information, determining a second layout.
  • the placement and routing rules of the second layout used to realize the new circuit can be determined based on the layout rules and routing rules in the first layout, so as to inherit the mature design of the first layout as much as possible to reduce overlap and misalignment and DRC problems, thereby improving the efficiency of layout mapping.
  • determining the second constraint information includes: extracting from the first constraint information a first layout feature associated with the first process, the first layout feature at least indicating the composition of the first device group, and the first device group
  • the first device group includes a plurality of devices in the first layout that satisfy at least one combination condition in the combination condition set, and the combination condition set includes: a plurality of devices belonging to the same type of devices , or a plurality of devices form a functional block
  • the devices in the second circuit are grouped with reference to the first layout feature to obtain a second layout feature associated with the second process, and the second layout feature at least indicates that it is related to the first device group
  • the second device group includes a plurality of devices of the second process; and determining second constraint information based on the second layout feature. Since an integrated circuit usually includes a large number of devices in practice, by grouping the devices in the circuit,
  • the first constraint information further indicates layout rules and routing rules of the auxiliary device in the first layout, the auxiliary device is not included in the first circuit, and the pattern corresponding to the auxiliary device is included in the first layout.
  • the combined condition set further includes: the pattern corresponding to the device in the first circuit is surrounded by the pattern corresponding to the auxiliary device in the first layout. Since the arrangement of auxiliary devices contains rich design experience of engineers, by considering auxiliary devices when grouping devices, the grouping of devices can be more reasonable, and the mature design of the first layout can be inherited, thereby further improving the second layout. Placement and routing quality of the layout.
  • determining the second constraint information based on the second layout feature includes: receiving a user's operation on a graphic element associated with the second layout feature via a user interface; based on the operation, adjusting the second layout feature to obtain the target a layout feature; and based on the target layout feature, determining second constraint information.
  • the second layout feature can be presented to the user in an intuitive manner, and the user can edit the second constraint information in real time, and present the modified layout to the user intuitively in a visual manner.
  • determining the second layout based on the second constraint information includes: splicing a plurality of device template units to form a second device group based on the second constraint information, and the plurality of device template units respectively correspond to multiple components in the second process.
  • devices based on the second constraint information, connect the device template units in the second device group; based on the second constraint information, arrange the second device group and the device template units corresponding to other devices; and based on the second constraint information, connect A second device group and device template units corresponding to other devices.
  • the devices in the second circuit can be placed and routed hierarchically by means of the device template unit. Since the device template unit is adaptively designed so that splicing device template units will not overlap. Therefore, it is possible to prevent dislocation, overlap and DRC problems from occurring when the second layout is placed and routed, thereby avoiding the repair of the layout by later designers to the greatest extent.
  • a device template cell can be designed by extending the corresponding layout level in the parameterized cell to the boundary of the device cell. In this way, it is possible to avoid overlapping when splicing a plurality of device template units, thereby ensuring that dislocation, overlap and DRC problems will not occur when splicing device template units to form the second device group.
  • the first constraint information also indicates the parasitic capacitance and parasitic resistance RC parameters of the wires in the first layout
  • the second constraint information also indicates the width, length or spacing of multiple wires used in the second process
  • the second constraint information is determined.
  • the second constraint information includes calculating widths, lengths or spacings of the plurality of wires for the second process based on the RC parameters and metal properties associated with the second process. In this way, the RC parameters of the second layout can be kept consistent with the first layout as much as possible.
  • determining the second layout includes: determining a candidate layout associated with the second process for implementing the second circuit based on the second constraint information; if the RC parameters of the wires in the candidate layout are consistent with the first layout If the deviation of the RC parameters of the wires in the first layout is greater than a predetermined threshold, the second constraint information is updated based on the RC parameters of the wires in the first layout; and the second layout is determined based on the updated second constraint information. In this way, the constraint information used for placement and routing can be adaptively adjusted according to the RC parameters of the candidate layout, so that the RC parameters of the second layout can be kept consistent with the first layout.
  • an apparatus for layout mapping includes a first constraint information determination module, a second netlist file determination module and a second layout determination module.
  • the first constraint information determination module is configured to determine first constraint information associated with the first circuit based on the first netlist file characterizing the first circuit and the first layout for implementing the first circuit, the first netlist file Associated with the first layout and the first process, the first constraint information at least indicates layout rules and wiring rules of devices in the first circuit in the first layout.
  • the second netlist file determination module is configured to determine a second netlist file associated with the second process based on the first netlist file and a process design suite associated with the second process, the second netlist file characterizing the second For the circuit, the second process is different from the first process, and the second circuit has the same circuit topology as the first circuit.
  • the second layout determining module is configured to determine a second layout associated with the second process for implementing the second circuit based on the first constraint information and the second netlist file. The device uses the constraint information based on the original layout to carry out automatic layout and routing to replace the scheme of directly replacing the hierarchical or parameterized units in the conventional scheme.
  • the device according to the present disclosure can avoid the problems of misalignment, overlap and DRC in conventional solutions to the greatest extent, thus greatly reducing the workload of designers.
  • the device according to the present disclosure does not need to be customized for different processes, so that the decoupling of layout mapping and process can be realized.
  • the layout rule includes relative position information of the multiple devices in the first circuit in the first layout
  • the wiring rule includes wiring information of the multiple devices in the first circuit in the first layout.
  • layout design the relative positional relationship between devices such as alignment and symmetry and wiring information have an important impact on the quality of the final layout.
  • the relative position information and connection information of multiple devices in the layout mapping the mature design in this aspect in the first layout can be inherited to improve the quality of the obtained second layout, thereby improving the efficiency of layout migration.
  • the first constraint information determination module is further configured to: compare the first layout with the first netlist file, so as to extract the relationship between the devices and connections in the first circuit and the patterns in the first layout a corresponding relationship; and based on the corresponding relationship, extracting first constraint information from the first layout. In this way, the relationship between the first circuit and the first layout can be constructed, so as to facilitate subsequent analysis of the first layout and extraction of layout rules and wiring rules from the first layout.
  • the first constraint information further indicates layout rules and routing rules of the auxiliary device in the first layout, the auxiliary device is not included in the first circuit, and the pattern corresponding to the auxiliary device is included in the first layout.
  • the first constraint information determining module is further configured to: obtain layer information of the first layout, the layer information indicates the position of the pattern element in the corresponding layer of the first layout; and analyze the layer information to extract auxiliary Placement rules and routing rules of the device in the first layout.
  • the arrangement of auxiliary devices in the first layout contains rich design experience of engineers and will have an impact on the characteristics of other surrounding devices
  • the arrangement of auxiliary devices in the first layout can also be changed through the device according to this implementation Mapped to the second layout, so as to further improve the placement and routing quality of the second layout.
  • the second netlist file determination module is further configured to: replace the devices in the first netlist file with corresponding devices in the process design kit associated with the second process, so as to obtain the second netlist document. In this way, the second netlist file for the second process can be obtained more conveniently and quickly based on the first netlist file for the first process.
  • the second layout determination module is further configured to: determine second constraint information associated with the second circuit based on the first constraint information and the second netlist file, the second constraint information at least indicates that the second circuit the layout rule and the routing rule of the device; and based on the second constraint information, determine the second layout.
  • the placement and routing rules of the second layout used to realize the new circuit can be determined based on the layout rules and routing rules in the first layout, so as to inherit the mature design of the first layout as much as possible to reduce overlap and misalignment and DRC problems, thereby improving the efficiency of layout mapping.
  • determining the second constraint information associated with the second circuit based on the first constraint information and the second netlist file includes: extracting a first layout feature associated with the first process from the first constraint information, The first layout feature at least indicates the composition of the first device group, and the layout rules and wiring rules of the first device group in the first layout, and the first device group includes at least one combination condition in the first layout that satisfies the combination condition set multiple devices, the combined condition set includes: multiple devices belong to the same type of device, or multiple devices form a functional block; refer to the first layout feature to group the devices in the second circuit to obtain the The second layout feature of the connection, the second layout feature at least indicates the composition of the second device group, and the layout rules and wiring rules of the second device group, the second device group corresponds to the first device group, and the second device group includes A plurality of devices of the second process; and determining second constraint information based on the second layout characteristics. Since integrated circuits often include a large number of devices in practice, by grouping devices in the circuit
  • the first constraint information further indicates layout rules and routing rules of the auxiliary device in the first layout, the auxiliary device is not included in the first circuit, and the pattern corresponding to the auxiliary device is included in the first layout.
  • the combined condition set further includes: the pattern corresponding to the device in the first circuit is surrounded by the pattern corresponding to the auxiliary device in the first layout. Since the arrangement of auxiliary devices contains rich design experience of engineers, by considering auxiliary devices when grouping devices, the grouping of devices can be more reasonable, and the mature design of the first layout can be inherited, thereby further improving the second layout. Placement and routing quality of the layout.
  • determining the second constraint information based on the second layout feature includes: receiving a user's operation on a graphic element associated with the second layout feature via a user interface; based on the operation, adjusting the second layout feature to obtain the target a layout feature; and based on the target layout feature, determining second constraint information.
  • the second layout feature can be presented to the user in an intuitive manner, and the user can edit the second constraint information in real time, and present the modified layout to the user intuitively in a visual manner.
  • determining the second layout based on the second constraint information includes: splicing a plurality of device template units to form a second device group based on the second constraint information, and the plurality of device template units respectively correspond to multiple components in the second process.
  • devices based on the second constraint information, connect the device template units in the second device group; based on the second constraint information, arrange the second device group and the device template units corresponding to other devices; and based on the second constraint information, connect A second device group and device template units corresponding to other devices.
  • the devices in the second circuit can be placed and routed hierarchically by means of the device template unit. Since the device template unit is adaptively designed so that splicing device template units will not overlap. Therefore, it is possible to prevent dislocation, overlap and DRC problems from occurring when the second layout is placed and routed, thereby avoiding the repair of the layout by later designers to the greatest extent.
  • a device template cell can be designed by extending the corresponding layout level in the parameterized cell to the boundary of the device cell. In this way, it is possible to avoid overlapping when splicing a plurality of device template units, thereby ensuring that dislocation, overlap and DRC problems will not occur when splicing device template units to form the second device group.
  • the first constraint information also indicates the parasitic capacitance and parasitic resistance RC parameters of the wires in the first layout
  • the second constraint information also indicates the width, length or spacing of the plurality of wires used in the second process, based on the first layout
  • a constraint information and a second netlist file determining second constraint information associated with the second circuit includes: calculating widths of a plurality of wires for the second process based on RC parameters and metal characteristics associated with the second process, length or spacing. In this way, the RC parameters of the second layout can be kept consistent with the first layout as much as possible.
  • determining the second layout based on the second constraint information includes: determining a candidate layout associated with the second process for implementing the second circuit based on the second constraint information; if the RC of the wire in the candidate layout If the deviation of the parameter from the RC parameter of the wire in the first layout is greater than a predetermined threshold, update the second constraint information based on the RC parameter of the wire in the first layout; and determine the second layout based on the updated second constraint information.
  • the constraint information used for placement and routing can be adaptively adjusted according to the RC parameters of the candidate layout, so that the RC parameters of the second layout can be kept consistent with the first layout.
  • an electronic device includes: at least one processor; and at least one memory, the at least one memory being coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, such that An electronic device performs the method according to the first aspect of the present disclosure.
  • the electronic device uses the constraint information based on the first layout to perform automatic layout and routing instead of directly replacing the hierarchical or parameterized unit in the conventional solution. In this way, the problems of misalignment, overlap and DRC in conventional solutions can be avoided to the greatest extent, so the workload of designers can be greatly reduced.
  • a computer readable storage medium stores a computer program which, when executed by a processor, implements the method according to the first aspect of the present disclosure.
  • the computer-readable storage medium uses the constraint information of the first layout to perform automatic layout and routing instead of directly replacing hierarchical or parameterized units in conventional solutions. In this way, the problems of misalignment, overlap and DRC in conventional solutions can be avoided to the greatest extent, so the workload of designers can be greatly reduced.
  • a computer program product comprising computer-executable instructions which, when executed by a processor, cause a computer to implement the method according to the first aspect of the present disclosure .
  • the computer program product uses the constraint information of the first layout to perform automatic layout and routing to replace the solution of directly replacing hierarchical or parameterized units in the conventional solution. In this way, the problems of misalignment, overlap and DRC in conventional solutions can be avoided to the greatest extent, so the workload of designers can be greatly reduced.
  • Figure 1 shows a block diagram of an example environment according to some embodiments of the present disclosure
  • Fig. 2 shows a schematic block diagram of an exemplary first circuit to be transplanted
  • FIG. 3 shows a schematic diagram of a first layout for implementing the first circuit shown in FIG. 2;
  • FIG. 4 shows a flowchart of a method for layout mapping according to some embodiments of the present disclosure
  • Fig. 5 shows a flowchart of a method for determining first constraint information according to some embodiments of the present disclosure
  • FIG. 6 shows a flowchart of a method for determining a second layout according to some embodiments of the present disclosure
  • Fig. 7 shows a schematic diagram of a graph for presenting a second layout feature according to some embodiments of the present disclosure
  • FIG. 8 shows a block diagram of an example apparatus for layout mapping according to some embodiments of the present disclosure.
  • Figure 9 shows a schematic block diagram of an example device that may be used to implement some embodiments of the present disclosure.
  • the term “comprise” and its variants mean open inclusion, ie “including but not limited to”.
  • the term “or” means “and/or” unless otherwise stated.
  • the term “based on” means “based at least in part on”.
  • the terms “one example embodiment” and “one embodiment” mean “at least one example embodiment.”
  • the term “another embodiment” means “at least one further embodiment”.
  • layer or “layer” as used herein refers to layers of a layout.
  • design rule checking refers to the process of checking whether the physical layout of an integrated circuit satisfies design rules, which are a set of geometric and connectivity constraints imposed to allow margins for the production of acceptable chips.
  • parameterized element denotes a part or assembly of an electrical circuit, the structure of which depends on one or more parameters. In other words, parameterized cells are cells that are automatically generated by EDA software based on the values of these parameters.
  • layout mapping is used to transfer the original layout designed for the original process to the new process to obtain a new layout for the new process.
  • Conventional layout mapping schemes usually include the following two types: First, with the help of customized scripts, the layout design data of the original layout is directly replaced with layers, and all layers under the original process are replaced with the layers of the new process, and then the designers manually Correct the DRC to obtain a new layout; second, replace the parameterized cells (Parameter Cell, PCell) of the original layout with the help of a customized script, replace all PCells of the original process with PCells of the new process, and then the designer Correct the DRC manually to get the new layout.
  • PCell Parameter Cell
  • the first solution is often only applicable to layout mapping scenarios between two very close processes, otherwise it will be difficult or even impossible for designers to obtain a usable new layout by correcting DRC due to the large gap between device architecture and size .
  • the customized script used is strongly related to the process, which means that the layout mapping between any two processes needs to involve the corresponding customized script separately, so that the layout mapping efficiency is limited.
  • Embodiments of the present disclosure propose a scheme for layout mapping to address one or more of the above-mentioned problems and other potential problems.
  • the constraint information for placement and routing is extracted from the original layout and the original circuit to be mapped, and based on the extracted constraint information, the new circuit under the new process is automatically placed and routed, so as to Obtain a new layout for implementing the new circuit.
  • the solution according to the present disclosure replaces the process of directly replacing hierarchical or parameterized cells in the conventional solution by using the automatic placement and routing based on the constraint information of the original layout.
  • the solution according to the present disclosure avoids the problems of misalignment, overlap and DRC caused by direct replacement of layers or parameterized units in conventional solutions to the greatest extent, and thus can greatly reduce the workload of designers.
  • the solutions according to the present disclosure do not need to be customized for different processes, thereby realizing the decoupling of layout mapping and processes.
  • FIG. 1 shows a block diagram of an example environment 100 according to some embodiments of the present disclosure.
  • example environment 100 may generally include electronic device 140 .
  • the electronic device 140 may be a device having computing functions such as a personal computer, a workstation, a server, and the like. The scope of the present disclosure is not limited in this regard.
  • the electronic device 140 can acquire the first netlist file 110 representing the first circuit, the first layout 120 for realizing the first circuit, and a process design kit (Process Design Kit, PDK) 130 associated with the second process as input , wherein the first netlist file 110 and the first layout 120 are associated with the first process.
  • a process design kit Process Design Kit, PDK
  • the first process may be an original process provided by an original chip fabrication plant
  • the second process may be a new process provided by a new chip fabrication plant. The scope of the present disclosure is not limited in this respect.
  • the first netlist file 110 may indicate device information and connection relationships of devices in the first circuit.
  • the device information may be, for example, parameter information of the device such as width and length, the name of the library where the device resides, and so on.
  • the first netlist file 110 may also indicate information such as process parameters for implementing the first circuit.
  • the process parameters may be, for example, the unit resistance and potential capacitance of the metal in the first process.
  • the first layout 120 may indicate placement and routing information of the first circuit in the layout.
  • the first layout 120 may be provided to the electronic device 140, eg, in the form of a GDS file. The scope of the present disclosure is not limited in this regard.
  • the PDK 130 may be a file provided by a chip manufacturer for describing semiconductor process details such as device information and process parameters. It should be understood that, in the context of the present disclosure, the PDK 130 may also represent any other suitable data information that can indicate the name of the circuit device in a specific process and its parameter name. The scope of the present disclosure is not limited in this regard.
  • the first netlist file 110, the first layout 120, and the PDK 130 may be input into the electronic device 140 by a user. In some embodiments, at least part of the first netlist file 110, the first layout 120 and the PDK 130 may have been pre-stored in the electronic device 140. In some embodiments, the electronic device 140 can also be communicatively coupled to other devices, so as to obtain at least part of the first netlist file 110, the first layout 120 and the PDK 130 from other devices. The scope of the present disclosure is not limited in this regard.
  • the electronic device 140 Based on the first netlist file 110 and the first layout 120, the electronic device 140 extracts the layout rules and wiring rules of the circuit under the first process as the first constraint information, and based on the first constraint information, determines the The second constraint information for layout and wiring of the corresponding circuit is performed, and the layout and wiring are performed automatically by considering the second constraint information, so as to obtain a second layout 150 under the second process as an output. This will be described in detail below with reference to FIGS. 2 to 7 .
  • FIG. 2 shows a schematic block diagram of an exemplary first circuit 200 to be transplanted
  • FIG. 3 shows a schematic diagram of a first layout 120 for implementing the first circuit 200 shown in FIG. 2 .
  • FIGS. 2 and 3 For the purpose of illustration and simplification, only some modules of the first circuit 200 and corresponding partial regions in the first layout 120 are shown in FIGS. 2 and 3 , and the first circuit 200 is omitted in FIG. Wiring information in the layout 120 and specific layout patterns.
  • the first circuit 200 exemplarily includes 4 circuit modules, namely, module A 210-1, module B 210-2, module C 210-3, and module D 210-4 (referred to individually or collectively as is the circuit module 210).
  • module A 210-1 can be, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)
  • module B 210-2 can be, for example, a current mirror
  • module C 210 -3 can be, for example, a current amplifier
  • module D 210-4 can, for example, be a filter.
  • the number of circuit modules included in the first circuit 200 may also be any other suitable value, and the circuit modules included in the first circuit 200 may also correspond to any other suitable circuit units or devices. The scope of is not limited in this respect.
  • the first layout 120 exemplarily includes: a first module area 310, guard ring areas (Tap) 320-1 and 320-2 (separately or collectively referred to as Tap 320), a second module area 330 , first device regions 340-1 and 340-2 (individually or collectively referred to as the first device region 340), filling device regions (Dummy) 350-1 to 350-4 (individually or collectively referred to as Dummy 350 ), the second device region 360 and the third device region 370.
  • a first module area 310 guard ring areas (Tap) 320-1 and 320-2 (separately or collectively referred to as Tap 320), a second module area 330 , first device regions 340-1 and 340-2 (individually or collectively referred to as the first device region 340), filling device regions (Dummy) 350-1 to 350-4 (individually or collectively referred to as Dummy 350 ), the second device region 360 and the third device region 370.
  • the first module region 310 may correspond to a current mirror
  • the second module region 330 may correspond to a current amplifier
  • the first device region may correspond to a MOSFET
  • the second device region 360 and the third device region 370 may correspond to correspond to the resistors and capacitors in the filter, respectively.
  • FIG. 3 is not drawn to scale, in practice the first module region 310 and the second module region 330 can be formed by the first device region 340 , the filling device region 350 , the second device region 360 and the third Device region 370 is formed the same as or similar to the device region.
  • the layout area and its layout in FIG. 3 are only schematic and not necessarily drawn to scale. The scope of the present disclosure is not limited in this regard.
  • FIG. 4 shows a flowchart of a method 400 for layout mapping according to some embodiments of the present disclosure.
  • the method 400 may be executed by the electronic device 140 as shown in FIG. 1 . It should be appreciated that method 400 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this respect.
  • the electronic device 140 determines first constraint information associated with the first circuit 200 based on the first netlist file 110 representing the first circuit 200 and the first layout 120 for implementing the first circuit 200, the first The netlist file 110 and the first layout 120 are associated with the first process, and the first constraint information at least indicates layout rules and wiring rules of the devices in the first circuit 200 in the first layout 120 .
  • placement rules mean rules associated with the assigned locations of devices in the layout
  • routing rules mean rules associated with the wiring of devices in the layout.
  • the layout rule may include relative position information of a plurality of devices in the first layout 120, for example, a plurality of devices are aligned with respect to their upper or lower boundaries, a plurality of devices are aligned with respect to their central axis, a plurality of devices are aligned with respect to The central axis of the layout is mirror-symmetrical, multiple devices are adjacent up and down or left and right, the distance between the boundaries of multiple devices, the distance between active regions of multiple devices, and so on.
  • the wiring rules may include the connection information of multiple devices in the layout, for example, the name of the net (Net) used to realize the connection, the connection end between the Net and the device, and the nets included in the Net.
  • the first constraint information may also include device information of the device in the first circuit 200 , for example, parameter information of the device such as width, length, etc., the name of the library where the device resides, and so on. It should be understood that the first constraint information may also include unlisted information and/or may omit listed information, and the scope of the present disclosure is not limited in this respect.
  • the electronic device 140 can use the corresponding relationship between the first circuit 200 and the first layout 120 to extract the first constraint information from the first layout 120 . This will be described in further detail below with reference to FIG. 5 .
  • the electronic device 140 determines a second netlist file associated with the second process based on the first netlist file 110 and the process design suite 130 associated with the second process, the second netlist file characterizing the second circuit , the second process is different from the first process, and the second circuit has the same circuit topology as the first circuit 200 .
  • two circuits having the same circuit topology means that there is a one-to-one correspondence between transistor-level devices in the two circuits. Due to different processes, the device name and parameter name of the same device are often not the same. Therefore, device mapping and parameter mapping need to be performed on the first circuit 200 based on the PDK 130 for the second process to obtain a second circuit for the second process corresponding to the first circuit 200.
  • the electronic device 140 may replace devices in the first netlist file 110 representing the first circuit 200 with corresponding devices in the PDK 130 for the second process, so as to obtain the second netlist.
  • the electronic device 140 can obtain the device name and parameter name of the device in the PDK 130 used for the second process, and use the obtained device name and parameter name to replace the corresponding device name in the first netlist file 110. device name and parameter name, thereby obtaining the second netlist for the second process.
  • the electronic device 140 may determine the second layout 150 associated with the second process for implementing the second circuit based on the first constraint information and the second netlist file.
  • the electronic device 140 may determine second constraint information associated with the second circuit based on the first constraint information and the second netlist file, the second constraint information at least indicating the layout of devices in the second circuit rules and wiring rules.
  • the electronic device 140 may determine the second layout 150 based on the determined second constraint information. This will be described in further detail below with reference to FIGS. 6 and 7 .
  • Fig. 5 shows a flowchart of a method 500 for determining first constraint information according to some embodiments of the present disclosure.
  • method 500 may be implemented as an example of block 402 as shown in FIG. 4 .
  • the method 500 may be executed by the electronic device 140 as shown in FIG. 1 . It should be appreciated that method 500 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this regard.
  • the electronic device 140 may compare the first layout 120 with the first netlist file 110 to extract the corresponding relationship between devices and connections in the first circuit 200 and patterns in the first layout 120 .
  • the electronic device 140 can perform a layout circuit consistency check (Layout Versus Schematic, LVS) on the first layout 120 and the first netlist file 110 by means of software to generate a standard verification database (Standard Verification Database, SVDB) file, the The SVDB file contains the corresponding relationship between the devices and connections in the first circuit 200 and the patterns in the first layout 120 .
  • SVDB standard verification database
  • An exemplary correspondence is that one MOSFET in the first circuit 200 corresponds to the first device region 340 - 1 in the first layout 120 .
  • the electronic device 140 can construct the relationship between the first circuit 200 and the first layout 120 used to realize the first circuit 200, thereby facilitating subsequent analysis of the first layout 120 and extracting layout rules from the first layout 120 and wiring rules.
  • the electronic device 140 may extract first constraint information from the first layout 120 based on the corresponding relationship between devices and connections in the first circuit 200 and patterns in the first layout 120 . For example, referring to FIG. 3 , the electronic device 140 may extract coordinate information of the first device regions 340 - 1 and 340 - 2 from the first layout 120 . The electronic device 140 may determine that the first device regions 340-1 and 340-2 are aligned with respect to their left and right boundaries by analyzing the coordinate information, and that the first device regions 340-1 and 340-2 are adjacent up and down.
  • the electronic device 140 may determine that the layout rule of the two MOSFETs corresponding to the first device regions 340 - 1 and 340 - 2 in the first circuit 200 is that the left border and the right border are aligned and adjacent up and down. In addition, the electronic device 140 may also extract device information such as the width and length of the MOSFET corresponding to the first device region 340 - 1 from the first layout 120 .
  • the electronic device 140 can associate the connection line connecting the two devices in the first circuit 200 with the Net connecting the pattern corresponding to the device in the first layout 120 according to the above correspondence, and from the first In the layout 120, the wire segments of the Net in each layout level and their coordinate information and size information are extracted. Similar to determining the relative position information of the device, by analyzing the coordinate information of the multiple wire segments, the electronic device 140 can determine the relative positional relationship among the multiple wire segments such as alignment and symmetry. In this way, the electronic device 140 can obtain the wiring rules between the devices in the first circuit 200 from the first layout 120 .
  • the first constraint information may also indicate layout rules and routing rules of the auxiliary devices in the first layout 120 .
  • an “auxiliary device” means a device which is not included in the first circuit 200 and whose pattern is included in the first layout 120 .
  • auxiliary devices may be arranged in the layout for the following considerations: to ensure the manufacturability of the chip, to avoid affecting the pattern accuracy and size of the device due to the reflection and diffraction of light in the photolithography process, or to avoid noise in the chip The influence of signals on key signals, etc.
  • Examples of auxiliary devices include, but are not limited to, Tap 320 and Dummy 350 in the layout.
  • the electronic device 140 can analyze the GDS file of the first layout 120 by means of software to obtain layer information of the first layout 120 , the layer information indicates the position of the pattern element in the corresponding layer in the first layout 120 .
  • the electronic device 140 may further analyze and process the obtained layer information, for example, by comparing the layer information with the characteristic pattern pattern representing the auxiliary device to determine whether there is an auxiliary device in the first layout 120, and when there is When assisting the device, determine the size information, coordinate information and connection information of the auxiliary device in the first layout 120 and the surrounding devices.
  • a "characteristic pattern pattern" characterizing a device means a pattern specific to the device in a layout design used to implement the device.
  • the electronic device 140 may determine the layout rules associated with the auxiliary device through coordinate information of the auxiliary device and other devices in the first layout 120 .
  • the electronic device 140 can determine the following exemplary relative position information by analyzing the coordinate information of Dummy 350-1 to 350-4 and the first device regions 340-1 and 340-2: Dummy 350-1 and 350-3 respectively are arranged on the left side of the first device regions 340-1 and 340-2, and Dummy 350-2 and 350-4 are arranged on the right side of the first device regions 340-1 and 340-2, respectively, and Dummy 350- 1 and 350-2 and the first device region 340-1 are aligned with respect to their upper and lower boundaries, thereby obtaining layout rules between Dummy 350-1 to 350-4 and corresponding MOSFETs.
  • the electronic device 140 may determine the wiring rule between the auxiliary device and other devices in a manner similar to that described above with reference to determining the wiring rule of the device in the first circuit 200 , which will not be repeated in this disclosure. Since the arrangement of auxiliary devices contains rich design experience of engineers and will affect the characteristics of other surrounding devices, through the method according to this embodiment, the arrangement of auxiliary devices in the first layout 120 can also be mapped to the second Layout 150, thereby further improving the layout and wiring quality of the second layout 150
  • FIG. 6 shows a flowchart of a method 600 for determining the second layout 150 according to some embodiments of the present disclosure.
  • method 600 may be implemented as an example of block 406 as shown in FIG. 4 .
  • the method 600 may be executed by the electronic device 140 as shown in FIG. 1 . It should be appreciated that method 600 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this respect.
  • the electronic device 140 extracts a first layout feature associated with the first process from the first constraint information, the first layout feature at least indicates the composition of the first device group, and the first device group is in the first layout 120 layout rules and wiring rules, the first device group includes a plurality of devices in the first layout 120 that satisfy at least one combination condition in the combination condition set, and the combination condition set includes: a plurality of devices belonging to the same type of device, or a plurality of devices Devices are organized into functional blocks. Since the first circuit 200 often includes a large number of devices in practice, the first constraint information is simplified by grouping the devices in the present disclosure, thereby improving the efficiency of layout mapping.
  • the electronic device 140 may group devices of the same type in the first circuit 200 into a first device group. For example, electronic device 140 may group multiple MOSFETs together. Electronic device 140 may also group multiple resistors together. In some embodiments, the electronic device 140 may group all devices in a functional block composed of multiple devices into one group. For example, the electronic device 140 may group resistors and capacitors constituting an RC filter into one group.
  • auxiliary devices such as Dummy 350 and Tap 320 exist in the first layout 120
  • the positional relationship between the auxiliary devices and these devices can also be considered when grouping devices. For example, if it is determined that patterns corresponding to devices in the first circuit 200 are surrounded by patterns corresponding to auxiliary devices in the first layout 120, the electronic device 140 may group these devices into one group. For example, in the first layout 120 shown in FIG. 3, since the first module area 310 is surrounded by Tap 320-1, the electronic device 140 can group the devices in the first module area 310 into one group. Similarly, the electronic device 140 may group the devices in the second module area 330 into one group.
  • the electronic device 140 can group the MOSFETs corresponding to the first device regions 340-1 and 340-2 into one group. Since the layout of auxiliary devices contains rich design experience of engineers, by considering auxiliary devices when grouping devices, devices can be grouped more reasonably, and the mature design of the first layout 120 can be inherited, thereby further improving the The layout and routing quality of the second layout 150.
  • the electronic device 140 may also classify the auxiliary devices into the corresponding first device group. In some embodiments, the electronic device 140 may record, for each auxiliary device, the name or number of the device it surrounds. The scope of the present disclosure is not limited in this respect.
  • the electronic device 140 may extract layout rules and wiring rules among the multiple first device groups from the first constraint information.
  • the electronic device 140 can determine the coordinate information of the first device group based on the coordinate information of each device in the first device group, and obtain the coordinate information between multiple first device groups according to the coordinate information of the first device group. For example, the electronic device 140 can determine that the first device group corresponding to the first module area 310 and the plurality of device groups corresponding to the second module area 330 are aligned with respect to their upper boundaries and are aligned with the central axis of the layout Mirror symmetry.
  • the electronic device 140 can also group the wires in the layout based on the grouping of devices. For example, the electronic device 140 may divide the wires in the layout into two parts, namely, wires within a group and wires between groups. The intra-group wires are wires between devices in each first device group, and the inter-group wires are wires between multiple first device groups. The electronic device 140 may extract the wiring rules associated with the wires within the group and the wiring rules associated with the wires between the groups from the wiring rules in the first constraint information.
  • the electronic device 140 groups devices in the second circuit with reference to the first layout feature to obtain a second layout feature associated with the second process, the second layout feature at least indicating that the device group corresponds to the first device group
  • the composition of the second device group, and the layout rules and wiring rules of the second device group, the second device group includes a plurality of devices of the second process.
  • the electronic device 140 can group the devices in the second circuit according to the corresponding relationship between the devices in the first circuit 200 and the devices in the second circuit according to the grouping method of the devices in the first circuit 200 . In other words, a plurality of devices that are grouped under the first process are also grouped under the second process.
  • the placement and routing rules between the second device group are also consistent with the placement and routing rules between the first group of devices.
  • the second layout 150 can be designed as much as possible according to the layout and wiring of the first layout 120 during layout mapping, so as to inherit the excellent circuit characteristics of the first layout 120 .
  • the electronic device 140 determines second constraint information based on the second layout feature.
  • the electronic device 140 may directly determine the layout and routing rules of the devices in the second circuit in the second layout 150 based on the second layout feature. For example, the electronic device 140 may first determine the relative positional relationship and wiring of the devices in the second device group within the group according to the relative positional relationship and wiring mode of the devices in each second device group in the first layout 120 Way. Then, the electronic device 140 may further determine the relative positional relationship and connection manner between the second device groups.
  • FIG. 7 shows a schematic diagram of a graph 700 for presenting a second layout feature according to some embodiments of the present disclosure. For purposes of illustration and simplification, only some of the graphical elements are shown in FIG. 7 .
  • ellipses 710 - 1 to 710 - 8 (individually or collectively referred to as ellipses 710 ) represent the locations and areas of respective second device groups in the second device groups.
  • the dotted line 720 in the center of the graph 700 shows the central axis of the layout.
  • the dotted line 730 shows the neighbor relationship between the respective second device groups.
  • ellipses 710 may have different colors to represent different symmetric relationships. For example, two ellipses 710 corresponding to two first device groups that are mirror-symmetrical about the central axis may be shown in green, and ellipses 710 corresponding to the first device group that are self-symmetrical about the central axis may be shown in red . In this way, the second layout feature can be presented to the user in an intuitive manner. It should be understood that the graphic elements ellipse 710, dotted line 720 and dashed line 730 in FIG. Restricted.
  • electronic device 140 may receive user operations on graphical elements in graph 700 via a user interface. For example, the user can change the position of the graphic element by dragging the corresponding graphic element through an input device such as a mouse.
  • the electronic device 140 may receive the user's drag operation, and determine the changed position of the graphic element as a new position of the corresponding second device group in the second layout 150, and use the new position to determine the second device group The relative positional relationship between the group and other second device groups in the second layout 150 , so as to adjust the second layout feature to obtain the target layout feature corresponding to the changed figure.
  • the electronic device 140 may determine the second constraint information based on the target layout feature in a manner similar to the above description with reference to the second layout feature. In this manner, the user can be enabled to edit the second constraint information in real time, and the modified layout can be intuitively presented to the user in a visual manner.
  • the electronic device 140 may also convert the non-layout constraints in the first constraint information into layout constraints in the second constraint information.
  • the electronic device 140 may also convert the RC constraints into multiple parameters for the second process in the second constraint information. Width, length, or spacing of individual wires.
  • the electronic device 140 can use known metal properties under the second process, such as information such as the unit resistance and unit capacitance of the metal, to calculate according to the RC parameters the parameters used to realize the connection in the second process. The width and length of the wires or the spacing between the wires, so as to make the RC parameter of the second layout 150 consistent with that of the first layout 120 as much as possible.
  • the electronic device 140 determines the second layout 150 based on the second constraint information.
  • the electronic device 140 may hierarchically place and route devices in the second circuit based on the second constraint information. For example, the electronic device 140 may first arrange the devices in the respective second device groups. The electronic device 140 may combine multiple device template units based on the constraint information in the second constraint information related to the components in the corresponding second device group to form the second device group.
  • a "device template cell” means a device cell developed for the second process, which is similar to a PCell in PDK 130. Each device under the second process has a corresponding device template unit.
  • a device template unit may be designed based on a PCell in PDK 130. For example, by extending the corresponding layout level in the PCell to the boundary of the device unit, so that no overlapping occurs when splicing multiple device template units.
  • DRC problems can also be eliminated by pre-running DRC verification and modifying the layout design in the device cell according to the verification results. In this way, problems of misalignment, overlap and DRC will not occur when the device template units are spliced to form the second device group, thereby avoiding the repair of the layout by later designers to the greatest extent. Therefore, the efficiency and automation of layout mapping can be improved.
  • the electronic device 140 may connect the device template units in the second device group according to the second constraint information.
  • the electronic device 140 can stretch and stretch the wire segment based on the wire segment used to realize the connection in the first layout 120 so that the stretched wire segment can be adapted to the layout of the second layout 150 , and the stretched wire segment is used to connect the corresponding device, while keeping the circuit topology formed after the wire segment is connected to the device consistent with that in the first layout 120 .
  • the electronic device 140 may perform layout and wiring of an upper layer.
  • the electronic device 140 may arrange the second device groups and device template units corresponding to the other devices based on the relative positional relationship between the respective second device groups and other devices indicated in the second constraint information. Similar to component wiring, the electronic device 140 can stretch and stretch the wire segment on the basis of the wire segment used to realize the connection in the first layout 120 so that the stretched wire segment can be adapted to the layout of the second layout 150 , and use stretched wire segments to connect devices in the corresponding device groups, while keeping the obtained circuit topology of the second layout 150 consistent with that of the first layout 120 . In this way, based on the determined second constraint information, the placement and wiring of the second circuit can be automatically completed to obtain a candidate layout.
  • the electronic device 140 may calculate the RC parameters of the wires in the candidate layout, and compare the RC parameters of the candidate layout with the RC parameters of the first layout 120, and if the deviation between the two is greater than a predetermined threshold, the electronic device 140 may adjust the width, length or distance of the wire concerned, and update the second constraint information based thereon. The electronic device 140 can then place and route the second circuit based on the updated second constraint information to obtain an updated candidate layout. This process may be performed iteratively until the deviation between the obtained RC parameters of the candidate layout and the RC parameters of the first layout 120 is less than a predetermined threshold. In this way, the RC parameter of the second layout 150 can be kept consistent with that of the first layout 120 .
  • the method for layout mapping according to the present disclosure can extract constraint information for layout and wiring from the original layout and original circuit to be mapped, and based on the extracted Constraint information is used to automatically place and route new circuits in new processes to obtain new layouts for implementing new circuits.
  • the method according to the present disclosure avoids the misalignment, overlap and DRC problems caused by direct replacement of layers or parameterized units in conventional solutions to the greatest extent, and thus can greatly reduce the workload of designers.
  • the method according to the present disclosure does not need to be customized for different processes, thereby realizing the decoupling of layout mapping and processes.
  • Example implementations of the method according to the present disclosure have been described in detail above with reference to FIGS. 1 to 7 , and implementations of corresponding devices will be described below.
  • FIG. 8 shows a block diagram of an example apparatus 800 for layout mapping according to some embodiments of the present disclosure.
  • the apparatus 800 can be used, for example, to implement the electronic device 140 as shown in FIG. 1 .
  • the apparatus 800 may include a first constraint information determining module 802 configured to, based on the first netlist file representing the first circuit and the first Layout, determining first constraint information associated with the first circuit, the first netlist file and the first layout are associated with the first process, and the first constraint information at least indicates the layout of devices in the first circuit in the first layout rules and wiring rules.
  • the apparatus 800 may further include a second netlist file determination module 804, the second netlist file determination module 804 is configured to, based on the first netlist file and the process design kit associated with the second process, determine A second netlist file associated with the second circuit, the second netlist file represents a second circuit, the second process is different from the first process, and the second circuit has the same circuit topology as the first circuit.
  • the apparatus 800 may further include a second layout determination module 806, which is configured to determine, based on the first constraint information and the second netlist file, associated with the second process and used to implement the second Second layout of the circuit.
  • the first constraint information determination module 802 is further configured to: compare the first layout with the first netlist file to extract the devices and connections in the first circuit and the patterns in the first layout and extracting first constraint information from the first layout based on the corresponding relationship.
  • the layout rule includes relative position information of the plurality of devices in the first circuit in the first layout
  • the routing rule includes wiring information of the plurality of devices in the first circuit in the first layout
  • the first constraint information further indicates layout rules and routing rules of the auxiliary device in the first layout, the auxiliary device is not included in the first circuit, and the pattern corresponding to the auxiliary device is included in the first layout.
  • the first constraint information determination module 802 is further configured to: acquire layer information of the first layout, where the layer information indicates the position of the pattern element in the corresponding layer of the first layout; and analyze the layer information to extract Placement rules and routing rules of auxiliary devices in the first layout.
  • the second layout determining module 806 is further configured to: determine second constraint information associated with the second circuit based on the first constraint information and the second netlist file, the second constraint information at least indicates the second Layout rules and routing rules of devices in the circuit; and determining a second layout based on the second constraint information.
  • determining the second constraint information associated with the second circuit based on the first constraint information and the second netlist file includes: extracting a first layout feature associated with the first process from the first constraint information,
  • the first layout feature at least indicates the composition of the first device group, and the layout rules and wiring rules of the first device group in the first layout
  • the first device group includes at least one combination condition in the first layout that satisfies the combination condition set multiple devices, the combined condition set includes: multiple devices belong to the same type of device, or multiple devices form a functional block; refer to the first layout feature to group the devices in the second circuit to obtain the The second layout feature of the connection, the second layout feature at least indicates the composition of the second device group, and the layout rules and wiring rules of the second device group, the second device group corresponds to the first device group, and the second device group includes A plurality of devices of the second process; and determining second constraint information based on the second layout characteristics.
  • the first constraint information further indicates layout rules and routing rules of the auxiliary device in the first layout, the auxiliary device is not included in the first circuit, and the pattern corresponding to the auxiliary device is included in the first layout.
  • the combined condition set further includes: the pattern corresponding to the device in the first circuit is surrounded by the pattern corresponding to the auxiliary device in the first layout.
  • determining the second constraint information based on the second layout feature includes: receiving a user's operation on a graphic element associated with the second layout feature via a user interface; based on the operation, adjusting the second layout feature to obtain the target a layout feature; and based on the target layout feature, determining second constraint information.
  • determining the second layout based on the second constraint information includes: splicing a plurality of device template units to form a second device group based on the second constraint information, and the plurality of device template units respectively correspond to multiple components in the second process. devices; based on the second constraint information, connect the device template units in the second device group; based on the second constraint information, arrange the second device group and the device template units corresponding to other devices; and based on the second constraint information, connect A second device group and device template units corresponding to other devices.
  • the first constraint information also indicates the parasitic capacitance and parasitic resistance RC parameters of the wires in the first layout
  • the second constraint information also indicates the width, length or spacing of the plurality of wires used in the second process, based on the first layout
  • a constraint information and a second netlist file determining second constraint information associated with the second circuit includes: calculating widths of a plurality of wires for the second process based on RC parameters and metal characteristics associated with the second process, length or spacing.
  • determining the second layout based on the second constraint information includes: determining a candidate layout associated with the second process for implementing the second circuit based on the second constraint information; if the RC of the wire in the candidate layout If the deviation of the parameter from the RC parameter of the wire in the first layout is greater than a predetermined threshold, update the second constraint information based on the RC parameter of the wire in the first layout; and determine the second layout based on the updated second constraint information.
  • the second netlist file determination module 804 is further configured to: replace the devices in the first netlist file with corresponding devices in the process design kit associated with the second process, so as to obtain the second netlist table file.
  • the modules and/or units included in the apparatus 800 may be implemented in various ways, including software, hardware, firmware or any combination thereof.
  • one or more units may be implemented using software and/or firmware, such as machine-executable instructions stored on a storage medium.
  • some or all of the units in apparatus 800 may be at least partially implemented by one or more hardware logic components.
  • Exemplary types of hardware logic components include, by way of example and not limitation, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), System on Chips (SOCs), Complex Programmable Logic Devices (CPLD), and so on.
  • modules and/or units shown in FIG. 8 may be implemented in part or in whole as hardware modules, software modules, firmware modules or any combination thereof.
  • the processes, methods or processes described above may be implemented by hardware in the storage system or a host corresponding to the storage system or other computing devices independent of the storage system.
  • Fig. 9 shows a schematic block diagram of an example device 900 that may be used to implement some embodiments of the present disclosure.
  • the device 900 may be used to implement an electronic device.
  • the device 900 includes a central processing unit (CPU) 901 that can be programmed according to computer program instructions stored in a read-only memory (ROM) 902 or loaded from a storage unit 908 into a random-access memory (RAM) 903. computer program instructions to perform various appropriate actions and processes.
  • ROM read-only memory
  • RAM random-access memory
  • computer program instructions to perform various appropriate actions and processes.
  • various programs and data necessary for the operation of the device 900 can also be stored.
  • the CPU 901, ROM 902, and RAM 903 are connected to each other via a bus 904.
  • An input/output (I/O) interface 905 is also connected to the bus 904 .
  • I/O input/output
  • the I/O interface 905 includes: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a magnetic disk, an optical disk, etc. ; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, and the like.
  • the communication unit 909 allows the device 900 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.
  • the processing unit 901 executes various methods and processes described above, such as the method 400 .
  • method 400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 908 .
  • part or all of the computer program may be loaded and/or installed on the device 900 via the ROM 902 and/or the communication unit 909.
  • the CPU 901 may be configured to execute the method 400 in any other suitable manner (for example, by means of firmware).
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • ASSP application specific standard product
  • SOC system on a chip
  • CPLD load programmable logic device
  • Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented.
  • the program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing.
  • machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • magnetic storage or any suitable combination of the foregoing.

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Abstract

本公开的各实施例涉及用于版图映射的方法、设备、介质以及程序产品。本公开的一些实施例提供了一种用于版图映射的方法。在根据本公开的方法中，从待映射的原版图和原电路中提取用于布局和布线的约束信息，并且基于所提取的约束信息来对新工艺下的新电路进行自动布局和布线，以获得用于实现新电路的新版图。通过这种方式，根据本公开的方案在最大程度上避免了常规方案中由直接替换层次或参数化单元而带来的错位、重叠和设计规则检查问题，因此可以大幅降低设计人员的工作量。

Description

用于版图映射的方法、装置、设备、介质以及程序产品 技术领域
本公开的实施例总体上涉及芯片设计领域，更具体地涉及用于版图映射的方法、装置、设备、介质以及程序产品。
背景技术
在集成电路(Integrated Circuit,IC)设计中，通常会需要将针对一种工艺设计的芯片版图转移到另一种工艺。通常，两种不同工艺下的工艺参数和设计规则往往并不相同，例如，特定工艺的工艺参数可以包括该工艺下金属的单位电阻和单位电容，特定工艺的设计规则可以包括该工艺下器件有源区间距、金属线间距应当大于预定值。因此需要进行芯片版图的映射(也称为版图移植)，以保证针对另一种工艺的芯片版图能够满足设计要求。
目前，用于将芯片版图从一种工艺映射到另一种工艺的常规映射方案可以包括：利用电子设计自动化(Electronic Design Automation，EDA)软件从原版图中导出描述原版图的版图设计交换格式(Graphic Design System，GDS)文件；由设计人员编写或通过流片厂商获得层次迁移脚本；以及使用该层次迁移脚本来对GDS文件进行操作，以替换原版图中的层次，获得用于新工艺的新版图。由于新工艺与原工艺下的设计规则不同，因此，通过这种方式获得的新版图往往会有大量的设计规则检查(Design Rule Check，DRC)报错，因此还需要设计人员投入大量时间来修正DRC问题，以获得可用于流片的新版图。因此，常规的版图映射方案高度依赖于设计人员的人工参与，使得版图映射的效率较低，从而导致芯片开发周期较长。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种用于版图映射的方案。
根据本公开的第一方面，提供了一种用于版图映射的方法，该方法包括：基于表征第一电路的第一网表文件和用于实现第一电路的第一版图，确定与第一电路相关联的第一约束信息，第一网表文件和第一版图与第一工艺相关联，第一约束信息至少指示第一电路中的器件在第一版图中的布局规则和布线规则；基于第一网表文件和与第二工艺相关联的工艺设计套件，确定与第二工艺相关联的第二网表文件，第二网表文件表征第二电路，第二工艺不同于第一工艺，第二电路具有与第一电路相同的电路拓扑结构；以及基于第一约束信息和第二网表文件，确定与第二工艺相关联的、用于实现第二电路的第二版图。该方法利用基于原版图的约束信息进行自动布局布线来替代常规方案中直接替换层次或参数化单元的方案。通过这种方式，根据本公开的方法可以在最大程度上避免常规方案中的错位、重叠和DRC问题，因此可以大幅降低设计人员的工作量。此外，根据本公开的方法并不需要针对不同工艺而被定制，从而可以实现版图映射与工艺的解耦。
在一些实现方式中，布局规则包括第一电路中的多个器件在第一版图中的相对位置信息，并且布线规则包括第一电路中的多个器件在第一版图中的连线信息。由于在版图设计中，器件之间的诸如对齐和对称的相对位置关系以及连线信息对于最终得到的版图质量具有重要影响。通过在版图映射中考虑多个器件的相对位置信息和连线信息，可以 继承第一版图中在此方面的成熟设计，以提高所获得的第二版图的质量，从而提高版图移植的效率。
在一些实现方式中，基于第一网表文件和第一版图来确定第一约束信息包括：将第一版图和第一网表文件进行比对，以提取第一电路中的器件和连线与第一版图中的图案的对应关系；以及基于对应关系，从第一版图中提取第一约束信息。通过这种方式，可以构建第一电路与第一版图之间的关系，从而便于后续分析第一版图并从第一版图中提取布局规则和布线规则。
在一些实现方式中，第一约束信息还指示辅助器件在第一版图中的布局规则和布线规则。该辅助器件未被包括在第一电路中、并且与该辅助器件相对应的图案被包括在第一版图中。确定第一约束信息还包括：获取第一版图的图层信息，图层信息指示第一版图的相应图层中的图案元素的位置；以及分析图层信息，以提取辅助器件在第一版图中的布局规则和布线规则。由于第一版图中的辅助器件的布置方式蕴含了丰富的工程师设计经验并且会对周围其它器件的特性产生影响，因此通过根据该实现方式的方法，可以将第一版图中辅助器件的布置方式也映射到第二版图中，从而进一步提高第二版图的布局布线质量。
在一些实现方式中，确定第二网表文件包括：将第一网表文件中的器件替换为与第二工艺相关联的工艺设计套件中的对应器件，以获得第二网表文件。通过这种方式，可以基于第一工艺下的第一网表文件较方便快速地获得用于第二工艺的第二网表文件。
在一些实现方式中，确定第二版图包括：基于第一约束信息和第二网表文件，确定与第二电路相关联的第二约束信息，第二约束信息至少指示第二电路中的器件的布局规则和布线规则；以及基于第二约束信息，确定第二版图。通过这种方式，可以基于第一版图中的布局规则和布线规则来确定用于实现新电路的第二版图的布局布线规则，从而尽可能地继承第一版图的成熟设计，以减少重叠、错位和DRC问题，从而提高版图映射的效率。
在一些实现方式中，确定第二约束信息包括：从第一约束信息中提取与第一工艺相关联的第一布局特征，第一布局特征至少指示第一器件组的组成、以及第一器件组在第一版图中的布局规则和布线规则，第一器件组包括第一版图中的、满足组合条件集中的至少一个组合条件的多个器件，组合条件集包括：多个器件属于同一类型的器件、或者多个器件组成功能块；参照第一布局特征来对第二电路中的器件进行分组，以获得与第二工艺相关联的第二布局特征，第二布局特征至少指示与第一器件组相对应的第二器件组的组成、以及第二器件组的布局规则和布线规则，第二器件组包括第二工艺的多个器件；以及基于第二布局特征，确定第二约束信息。由于在实践中，集成电路往往包括大量的器件，因此通过对电路中的器件进行分组，可以简化用于布局布线的约束信息，以便提高版图映射的效率。
在一些实现方式中，第一约束信息还指示辅助器件在第一版图中的布局规则和布线规则，辅助器件未被包括在第一电路中、并且与辅助器件相对应的图案被包括在第一版图中，组合条件集还包括：与第一电路中的器件相对应的图案在第一版图中被与辅助器件相对应的图案围绕。由于辅助器件的布置方式蕴含了丰富的工程师设计经验，因此通过在对器件进行分组时考虑辅助器件，可以更加合理地对器件进行分组，并且可以继承第一版图的成熟设计，从而进一步提高第二版图的布局布线质量。
在一些实现方式中，基于第二布局特征确定第二约束信息包括：经由用户界面，接收用户对与第二布局特征相关联的图形元素的操作；基于操作，调整第二布局特征，以获得目标布局特征；以及基于目标布局特征，确定第二约束信息。通过这种方式，可以可以以直观的方式向用户呈现第二布局特征，并且使得用户能够实时编辑第二约束信息，并以可视化地方式向用户直观得呈现经修改后的布局。
在一些实现方式中，基于第二约束信息确定第二版图包括：基于第二约束信息，拼接多个器件模板单元以形成第二器件组，多个器件模板单元分别对应于第二工艺中的多个器件；基于第二约束信息，连接第二器件组中的器件模板单元；基于第二约束信息，布置第二器件组和与其它器件相对应的器件模板单元；以及基于第二约束信息，连接第二器件组和与其它器件相对应的器件模板单元。通过这种方式，可以借助于器件模板单元分层次地对第二电路中的器件进行布局和布线。由于器件模板单元被适应性地设计以使得拼接器件模板单元不会产生重叠。因此，可以使得在对第二版图进行布局和布线时不会产生错位、重叠和DRC问题，从而在最大程度上避免了后期设计人员对于版图的修复。
在一些实现方式中，器件模板单元可以通过将参数化单元中相应的版图层次延伸至器件单元的边界而被设计。通过这种方式，可以使得在拼接多个器件模板单元时不会产生重叠，从而确保在拼接器件模板单元以形成第二器件组时不会产生错位、重叠和DRC问题。
在一些实现方式中，第一约束信息还指示第一版图中的导线的寄生电容寄生电阻RC参数，第二约束信息还指示用于第二工艺的多个导线的宽度、长度或者间距，确定第二约束信息包括：基于RC参数和与第二工艺相关联的金属特性，计算用于第二工艺的多个导线的宽度、长度或者间距。通过这种方式可以尽可能地使得第二版图的RC参数与第一版图保持一致。
在一些实现方式中，确定第二版图包括：基于第二约束信息，确定与第二工艺相关联的、用于实现第二电路的候选版图；如果候选版图中的导线的RC参数与第一版图中的导线的RC参数的偏差大于预定阈值，则基于第一版图中的导线的RC参数，更新第二约束信息；以及基于经更新的第二约束信息，确定第二版图。通过这种方式，可以根据候选版图的RC参数来适应性地调整用于布局布线的约束信息，从而可以使得第二版图的RC参数与第一版图保持一致。
根据本公开的第二方面，提供了一种用于版图映射的装置。该装置包括第一约束信息确定模块、第二网表文件确定模块和第二版图确定模块。第一约束信息确定模块被配置为基于表征第一电路的第一网表文件和用于实现第一电路的第一版图，确定与第一电路相关联的第一约束信息，第一网表文件和第一版图与第一工艺相关联，第一约束信息至少指示第一电路中的器件在第一版图中的布局规则和布线规则。第二网表文件确定模块被配置为基于第一网表文件和与第二工艺相关联的工艺设计套件，确定与第二工艺相关联的第二网表文件，第二网表文件表征第二电路，第二工艺不同于第一工艺，第二电路具有与第一电路相同的电路拓扑结构。第二版图确定模块被配置为基于第一约束信息和第二网表文件，确定与第二工艺相关联的、用于实现第二电路的第二版图。该装置利用基于原版图的约束信息进行自动布局布线来替代常规方案中直接替换层次或参数化单元的方案。通过这种方式，根据本公开的装置可以在最大程度上避免常规方案中的错位、 重叠和DRC问题，因此可以大幅降低设计人员的工作量。此外，根据本公开的装置并不需要针对不同工艺而被定制，从而可以实现版图映射与工艺的解耦。
在一些实现方式中，布局规则包括第一电路中的多个器件在第一版图中的相对位置信息，并且布线规则包括第一电路中的多个器件在第一版图中的连线信息。由于在版图设计中，器件之间的诸如对齐和对称的相对位置关系以及连线信息对于最终得到的版图质量具有重要影响。通过在版图映射中考虑多个器件的相对位置信息和连线信息，可以继承第一版图中在此方面的成熟设计，以提高所获得的第二版图的质量，从而提高版图移植的效率。
在一些实现方式中，第一约束信息确定模块还被配置为：将第一版图和第一网表文件进行比对，以提取第一电路中的器件和连线与第一版图中的图案的对应关系；以及基于对应关系，从第一版图中提取第一约束信息。通过这种方式，可以构建第一电路与第一版图之间的关系，从而便于后续分析第一版图并从第一版图中提取布局规则和布线规则。
在一些实现方式中，第一约束信息还指示辅助器件在第一版图中的布局规则和布线规则，辅助器件未被包括在第一电路中、并且与辅助器件相对应的图案被包括在第一版图中，第一约束信息确定模块还被配置为：获取第一版图的图层信息，图层信息指示第一版图的相应图层中的图案元素的位置；以及分析图层信息，以提取辅助器件在第一版图中的布局规则和布线规则。由于第一版图中的辅助器件的布置方式蕴含了丰富的工程师设计经验并且会对周围其它器件的特性产生影响，因此通过根据该实现方式的装置，可以将第一版图中辅助器件的布置方式也映射到第二版图中，从而进一步提高第二版图的布局布线质量。
在一些实现方式中，第二网表文件确定模块还被配置为：将第一网表文件中的器件替换为与第二工艺相关联的工艺设计套件中的对应器件，以获得第二网表文件。通过这种方式，可以基于第一工艺下的第一网表文件较方便快速地获得用于第二工艺的第二网表文件。
在一些实现方式中，第二版图确定模块还被配置为：基于第一约束信息和第二网表文件，确定与第二电路相关联的第二约束信息，第二约束信息至少指示第二电路中的器件的布局规则和布线规则；以及基于第二约束信息，确定第二版图。通过这种方式，可以基于第一版图中的布局规则和布线规则来确定用于实现新电路的第二版图的布局布线规则，从而尽可能地继承第一版图的成熟设计，以减少重叠、错位和DRC问题，从而提高版图映射的效率。
在一些实现方式中，基于第一约束信息和第二网表文件确定与第二电路相关联的第二约束信息包括：从第一约束信息中提取与第一工艺相关联的第一布局特征，第一布局特征至少指示第一器件组的组成、以及第一器件组在第一版图中的布局规则和布线规则，第一器件组包括第一版图中的、满足组合条件集中的至少一个组合条件的多个器件，组合条件集包括：多个器件属于同一类型的器件、或者多个器件组成功能块；参照第一布局特征来对第二电路中的器件进行分组，以获得与第二工艺相关联的第二布局特征，第二布局特征至少指示第二器件组的组成、以及第二器件组的布局规则和布线规则，第二器件组与第一器件组相对应，并且第二器件组包括第二工艺的多个器件；以及基于第二布局特征，确定第二约束信息。由于在实践中，集成电路往往包括大量的器件，因此通 过对电路中的器件进行分组，可以简化用于布局布线的约束信息，以便提高版图映射的效率。
在一些实现方式中，第一约束信息还指示辅助器件在第一版图中的布局规则和布线规则，辅助器件未被包括在第一电路中、并且与辅助器件相对应的图案被包括在第一版图中，组合条件集还包括：与第一电路中的器件相对应的图案在第一版图中被与辅助器件相对应的图案围绕。由于辅助器件的布置方式蕴含了丰富的工程师设计经验，因此通过在对器件进行分组时考虑辅助器件，可以更加合理地对器件进行分组，并且可以继承第一版图的成熟设计，从而进一步提高第二版图的布局布线质量。
在一些实现方式中，基于第二布局特征确定第二约束信息包括：经由用户界面，接收用户对与第二布局特征相关联的图形元素的操作；基于操作，调整第二布局特征，以获得目标布局特征；以及基于目标布局特征，确定第二约束信息。通过这种方式，可以可以以直观的方式向用户呈现第二布局特征，并且使得用户能够实时编辑第二约束信息，并以可视化地方式向用户直观得呈现经修改后的布局。
在一些实现方式中，基于第二约束信息确定第二版图包括：基于第二约束信息，拼接多个器件模板单元以形成第二器件组，多个器件模板单元分别对应于第二工艺中的多个器件；基于第二约束信息，连接第二器件组中的器件模板单元；基于第二约束信息，布置第二器件组和与其它器件相对应的器件模板单元；以及基于第二约束信息，连接第二器件组和与其它器件相对应的器件模板单元。通过这种方式，可以借助于器件模板单元分层次地对第二电路中的器件进行布局和布线。由于器件模板单元被适应性地设计以使得拼接器件模板单元不会产生重叠。因此，可以使得在对第二版图进行布局和布线时不会产生错位、重叠和DRC问题，从而在最大程度上避免了后期设计人员对于版图的修复。
在一些实现方式中，器件模板单元可以通过将参数化单元中相应的版图层次延伸至器件单元的边界而被设计。通过这种方式，可以使得在拼接多个器件模板单元时不会产生重叠，从而确保在拼接器件模板单元以形成第二器件组时不会产生错位、重叠和DRC问题。
在一些实现方式中，第一约束信息还指示第一版图中的导线的寄生电容寄生电阻RC参数，第二约束信息还指示用于第二工艺的多个导线的宽度、长度或者间距，基于第一约束信息和第二网表文件确定与第二电路相关联的第二约束信息包括：基于RC参数和与第二工艺相关联的金属特性，计算用于第二工艺的多个导线的宽度、长度或者间距。通过这种方式可以尽可能地使得第二版图的RC参数与第一版图保持一致。
在一些实现方式中，基于第二约束信息确定第二版图包括：基于第二约束信息，确定与第二工艺相关联的、用于实现第二电路的候选版图；如果候选版图中的导线的RC参数与第一版图中的导线的RC参数的偏差大于预定阈值，则基于第一版图中的导线的RC参数，更新第二约束信息；以及基于经更新的第二约束信息，确定第二版图。通过这种方式，可以根据候选版图的RC参数来适应性地调整用于布局布线的约束信息，从而可以使得第二版图的RC参数与第一版图保持一致。
根据本公开的第三方面，提供了一种电子设备。该电子设备包括：至少一个处理器；以及至少一个存储器，至少一个存储器被耦合到至少一个处理器，并且存储用于由至少一个处理器执行的指令，指令当由至少一个处理器执行时，使得电子设备执行根据本公 开的第一方面的方法。该电子设备利用基于第一版图的约束信息进行自动布局布线来替代常规方案中直接替换层次或参数化单元的方案。通过这种方式，可以在最大程度上避免常规方案中的错位、重叠和DRC问题，因此可以大幅降低设计人员的工作量。
根据本公开的第四方面，提供了一种计算机可读存储介质。该计算机可读存储介质存储有计算机程序，计算机程序在被处理器执行时实现根据本公开的第一方面的方法。该计算机可读存储介质利用基于第一版图的约束信息进行自动布局布线来替代常规方案中直接替换层次或参数化单元的方案。通过这种方式，可以在最大程度上避免常规方案中的错位、重叠和DRC问题，因此可以大幅降低设计人员的工作量。
根据本公开的第五方面，提供了一种计算机程序产品，该计算机程序产品包括计算机可执行指令，计算机可执行指令在被处理器执行时，使计算机实现根据根据本公开的第一方面的方法。该计算机程序产品利用基于第一版图的约束信息进行自动布局布线来替代常规方案中直接替换层次或参数化单元的方案。通过这种方式，可以在最大程度上避免常规方案中的错位、重叠和DRC问题，因此可以大幅降低设计人员的工作量。
提供发明内容部分是为了简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开内容的关键特征或主要特征，也无意限制本公开内容的范围。
附图说明
通过参考附图阅读下文的详细描述，本公开的实施例的上述以及其它目的、特征和优点将变得易于理解。在附图中，以示例而非限制性的方式示出了本公开的若干实施例。
图1示出了根据本公开的一些实施例的示例环境的框图；
图2示出了示例性的待移植的第一电路的示意性框图；
图3示出了用于实现图2所示的第一电路的第一版图的示意图；
图4示出了根据本公开的一些实施例的用于版图映射的方法的流程图；
图5示出了根据本公开的一些实施例的用于确定第一约束信息的方法的流程图；
图6示出了根据本公开的一些实施例的用于确定第二版图的方法的流程图；
图7示出了根据本公开的一些实施例的用于呈现第二布局特征的图形的示意图；
图8示出了根据本公开的一些实施例的用于版图映射的示例装置的框图；以及
图9示出了可以用于实施本公开的一些实施例的示例设备的示意性框图。
具体实施方式
下面将参照附图更详细地描述本公开的优选实施例。虽然附图中显示了本公开的优选实施例，然而应该理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了使本公开更加透彻和完整，并且能够将本公开的范围完整地传达给本领域的技术人员。
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“上”、“下”、“前”、“后”等指示放置或者相对位置关系关系的词汇均基于附图所示的方位或者相对位置关系关系，仅为了 便于描述本公开的原理，而不是指示或者暗示所指的元件必须具有特定的方位、以特定的方位构造或操作，因此不能理解为对本公开的限制。
在本文中使用的术语“层次”或“图层”表示版图的图层。术语“设计规则检查”表示检查集成电路物理版图是否满足设计规则的过程，其中设计规则是为了给合格芯片的生产留出裕量而规定的一系列有关几何图形和连接性的限制。术语“参数化单元”表示电路的部件或组件，其结构取决于一个或多个参数。换言之，参数化单元是EDA软件根据这些参数的值自动生成的单元。
如上所述，版图映射被用于将针对原工艺设计的原版图转移到新工艺，以获得针对新工艺的新版图。常规的版图映射方案通常包括以下两种：第一，借助于定制化脚本，对原版图的版图设计数据直接做层次替换，将原工艺下所有层次换成新工艺的层次，再由设计人员手动修正DRC，以获得新版图；第二，借助于定制化脚本，对原版图的参数化单元(Parameter Cell，PCell)进行替换，将所有原工艺的PCell替换为新工艺的PCell，再由设计人员手动修正DRC，以获得新版图。
然而，这两种常规方案各自存在相应的问题。例如，第一种方案往往只适用于非常接近的两种工艺之间的版图映射场景，否则会由于器件架构和尺寸差距太大的缘故使得设计人员难以甚至无法通过修正DRC来获得可用的新版图。对于第二种方案而言，所使用的定制化脚本与工艺强相关，这意味着对于任意两种工艺之间的版图映射都需要单独涉及相应的定制化脚本，使得版图映射效率受到限制。
本公开的实施例提出了一种用于版图映射的方案，以解决上述问题和其它潜在问题中的一个或多个问题。在根据本公开的方案中，从待映射的原版图和原电路中提取用于布局和布线的约束信息，并且基于所提取的约束信息来对新工艺下的新电路进行自动布局和布线，以获得用于实现新电路的新版图。根据本公开的方案利用基于原版图的约束信息而进行的自动布局和布线替代了常规方案中直接替换层次或参数化单元的流程。通过这种方式，根据本公开的方案在最大程度上避免了常规方案中由直接替换层次或参数化单元而带来的错位、重叠和DRC问题，因此可以大幅降低设计人员的工作量。此外，根据本公开的方案并不需要针对不同工艺而被定制，从而实现了版图映射与工艺的解耦。
图1示出了根据本公开的一些实施例的示例环境100的框图。如图1所示，示例环境100总体上可以包括电子设备140。在一些实施例中，电子设备140可以是诸如个人计算机、工作站、服务器等具有计算功能的设备。本公开的范围在此方面不受限制。
电子设备140可以获取表征第一电路的第一网表文件110、用于实现第一电路的第一版图120、以及与第二工艺相关联的工艺设计套件(Process Design Kit，PDK)130作为输入，其中第一网表文件110和第一版图120与第一工艺相关联。在实践中，可能会需要更换芯片制造厂来对第一电路进行流片。在一些实施例中，第一工艺可以是由原芯片制造厂提供的原工艺，而第二工艺可以是由新的芯片制造厂提供的新工艺。本公开的范围在此方面不受限制。
在一些实施例中，第一网表文件110可以指示第一电路中的器件的器件信息与连接关系。器件信息例如可以是器件的诸如宽度、长度等的参数信息、器件所在库的名称，等等。在一些实施例中，第一网表文件110还可以指示用于实现第一电路的工艺参数等信息。工艺参数例如可以是第一工艺下金属的单位电阻和电位电容。本公开的范围在此方面不受限制。在一些实施例中，第一版图120可以指示第一电路在版图中的布局和布 线信息。在一些实施例中，第一版图120可以例如以GDS文件的形式被提供给电子设备140。本公开的范围在此方面不受限制。
在一些实施例中，PDK 130可以是由芯片制造厂提供的用于描述诸如器件信息和工艺参数等的半导体工艺细节的文件。应当理解的是，在本公开的上下文中，PDK 130还可以表示能够指示电路器件在特定工艺下的名称及其参数名的任何其它合适的数据信息。本公开的范围在此方面不受限制。
在一些实施例中，第一网表文件110、第一版图120和PDK 130可以由用户输入电子设备140。在一些实施例中，第一网表文件110、第一版图120和PDK 130中的至少部分可以已经预先被存储在电子设备140中。在一些实施例中，电子设备140还可以通信地耦连到其它设备，以从其它设备获取第一网表文件110、第一版图120和PDK 130中的至少部分。本公开的范围在此方面不受限制。
电子设备140基于第一网表文件110和第一版图120提取第一工艺下的电路的布局规则和布线规则作为第一约束信息，基于该第一约束信息来确定用于对第二工艺下的对应电路进行布局和布线的第二约束信息，并且通过考虑该第二约束信息来自动布局和布线，从而获得第二工艺下的第二版图150作为输出。这将在下文中结合图2至图7来详细描述。
图2示出了示例性的待移植的第一电路200的示意性框图，并且图3示出了用于实现图2所示的第一电路200的第一版图120的示意图。出于说明和简化的目的，在图2和图3中仅示出了第一电路200的部分模块、以及第一版图120中与此相对应的部分区域，并且在图3中省略了第一版图120中的布线信息以及具体的版图图案。
在图2中，第一电路200示例性地包括4个电路模块，即，模块A 210-1、模块B 210-2、模块C 210-3以及模块D 210-4(单独或统一地被称为电路模块210)。在一个实施例中，模块A 210-1例如可以是金属氧化物半导体场效电晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)，模块B 210-2例如可以是电流镜，模块C 210-3例如可以是电流放大器，并且模块D 210-4例如可以是滤波器。应当理解的是，第一电路200所包括的电路模块的数目还可以是任何其它合适的值，并且第一电路200所包括的电路模块还可以对应于任何其它合适的电路单元或器件，本公开的范围在此方面不受限制。
在图3中，第一版图120示例性地包括：第一模块区域310、保护环区域(Tap)320-1和320-2(单独或统一地被称为Tap 320)、第二模块区域330、第一器件区域340-1和340-2(单独或统一地被称为第一器件区域340)、填充器件区域(Dummy)350-1至350-4(单独或统一地被称为Dummy 350)、第二器件区域360以及第三器件区域370。在一个实施例中，第一模块区域310可以对应于电流镜，第二模块区域330可以对应于电流放大器，第一器件区域可以对应于MOSFET，并且第二器件区域360和第三器件区域370可以分别对应于滤波器中的电阻器和电容器。需要指出的是，由于图3未按比例绘制，因此在实践中第一模块区域310和第二模块区域330可以由与第一器件区域340、填充器件区域350、第二器件区域360和第三器件区域370相同或类似的器件区域构成。应当理解的是，图3中的版图区域及其布局方式仅是示意性的，并且不一定按比例绘制。本公开的范围在此方面不受限制。
在下文中，将参考图2所示的第一电路200和图3所示的第一版图120来描述根据本公开的方案。应当理解的是，根据本公开的方案还可以应用于其它任何合适的电路及 其对应的版图，本公开的范围在此方面不受限制。
图4示出了根据本公开的一些实施例的用于版图映射的方法400的流程图。在一些实施例中，方法400可以由如图1所示的电子设备140执行。应当理解的是，方法400还可以包括未示出的附加框和/或可以省略所示出的框，本公开的范围在此方面不受限制。
在框402，电子设备140基于表征第一电路200的第一网表文件110和用于实现第一电路200的第一版图120，确定与第一电路200相关联的第一约束信息，第一网表文件110和第一版图120与第一工艺相关联，第一约束信息至少指示第一电路200中的器件在第一版图120中的布局规则和布线规则。在本公开的上下文中，“布局规则”表示与器件在版图中所分配的位置相关联的规则，并且“布线规则”表示与器件在版图中的连线相关联的规则。
在一些实施例中，布局规则可以包括多个器件在第一版图120中的相对位置信息，例如，多个器件关于其上边界或下边界对齐、多个器件关于其中轴线对齐、多个器件关于版图的中轴线镜像对称、多个器件上下相邻或者左右相邻、多个器件的边界之间的间距、多个器件的有源区之间的间距，等等。在一些实施例中，布线规则可以包括多个器件在版图中的连线信息，例如，用于实现连线的线网(Net)的名称、Net与器件之间的连接端、Net所包括的导线段(Shape)、导线段所在的版图层次、多个Net之间的对称关系，等等。在一些实施例中，第一约束信息还可以包括第一电路200中的器件的器件信息，例如，器件的诸如宽度、长度等的参数信息、器件所在库的名称，等等。应当理解的是，第一约束信息还可以包括未列出的信息和/或可以省略所列出的信息，本公开的范围在此方面不受限制。
在一些实施例中，电子设备140可以利用第一电路200与第一版图120之间的对应关系来从第一版图120中提取第一约束信息。这将在下文中结合图5进一步详细描述。
在框404，电子设备140基于第一网表文件110和与第二工艺相关联的工艺设计套件130，确定与第二工艺相关联的第二网表文件，第二网表文件表征第二电路，第二工艺不同于第一工艺，第二电路具有与第一电路200相同的电路拓扑结构。在本公开的上下文中，两个电路具有相同的电路拓扑结构表示这两个电路中的晶体管级器件存在一一对应关系。由于在不同工艺下，相同器件的器件名称以及参数名称等信息往往并不相同。因此，需要基于用于第二工艺的PDK 130来对第一电路200执行器件映射与参数映射，以获得与第一电路200相对应的、用于第二工艺的第二电路。
在一些实施例中，电子设备140可以将表征第一电路200的第一网表文件110中的器件替换为用于第二工艺的PDK 130中的对应器件，以获得第二网表。示例性地，电子设备140可以获取器件在用于第二工艺的PDK 130中的器件名称以及参数名称，并且利用所获取的器件名称和参数名称来替换第一网表文件110中的相应器件的器件名称和参数名称，从而得到用于第二工艺的第二网表。
在框406，电子设备140可以基于第一约束信息和第二网表文件，确定与第二工艺相关联的、用于实现第二电路的第二版图150。在一些实施例中，电子设备140可以基于第一约束信息和第二网表文件，确定与第二电路相关联的第二约束信息，该第二约束信息至少指示第二电路中的器件的布局规则和布线规则。电子设备140可以基于所确定的第二约束信息来确定第二版图150。这将在下文中结合图6和图7进一步详细描述。
图5示出了根据本公开的一些实施例的用于确定第一约束信息的方法500的流程图。例如，方法500可以作为如图4所示的框402的一种示例实现。在一些实施例中，方法500可以由如图1所示的电子设备140执行。应当理解的是，方法500还可以包括未示出的附加框和/或可以省略所示出的框，本公开的范围在此方面不受限制。
在框502，电子设备140可以将第一版图120和第一网表文件110进行比对，以提取第一电路200中的器件和连线与第一版图120中的图案的对应关系。例如，电子设备140可以借助于软件对第一版图120和第一网表文件110执行版图电路一致性检查(Layout Versus Schematic，LVS)，以生成标准验证数据库(Standard Verification Database，SVDB)文件，该SVDB文件包含了第一电路200中的器件和连线与第一版图120中的图案的对应关系。示例性的对应关系为第一电路200中的一个MOSFET对应于第一版图120中的第一器件区域340-1。通过这种方式，电子设备140可以构建第一电路200与用于实现第一电路200的第一版图120之间的关系，从而便于后续分析第一版图120并从第一版图120中提取布局规则和布线规则。
在框504，电子设备140可以基于第一电路200中的器件和连线与第一版图120中的图案的对应关系，从第一版图120中提取第一约束信息。例如，参考图3，电子设备140可以从第一版图120中抽取第一器件区域340-1和340-2的坐标信息。电子设备140可以通过分析坐标信息，确定第一器件区域340-1和340-2关于其左边界和右边界对齐，并且第一器件区域340-1和340-2上下相邻。于是，电子设备140可以确定第一电路200中的、与第一器件区域340-1和340-2相对应的两个MOSFET的布局规则为左边界和右边界对齐并且上下相邻。此外，电子设备140还可以从第一版图120中提取与第一器件区域340-1相对应的MOSFET的宽度、长度等器件信息。
在一些实施例中，电子设备140可以根据上述对应关系，将第一电路200中连接两个器件的连线与第一版图120中连接与器件相对应的图案的Net相关联，并且从第一版图120中抽取Net在各个版图层次中的导线段及其坐标信息和尺寸信息。与确定器件的相对位置信息类似地，通过对多个导线段的坐标信息进行分析，电子设备140可以确定多个导线段之间的诸如对齐、对称等的相对位置关系。通过这种方式，电子设备140可以从第一版图120中获取第一电路200中的各个器件之间的布线规则。
在一些实施例中，第一约束信息还可以指示辅助器件在第一版图120中的布局规则和布线规则。在本公开的上文中，“辅助器件”表示如下的器件，该器件未被包括在第一电路200中、并且与该器件相对应的图案被包括在第一版图120中。示例性地，辅助器件可以出于以下考虑而被布置在版图中：保证芯片的可制造性、避免由于光刻过程中光的反射与衍射而影响器件的图案精度和大小、或者避免芯片中噪声信号对关键信号的影响，等等。辅助器件的示例包括但不限于版图中的Tap 320和Dummy 350。电子设备140可以借助于软件解析第一版图120的GDS文件，以获取第一版图120的图层信息，该图层信息指示第一版图120中的相应图层中的图案元素的位置。电子设备140可以进一步对所获取的图层信息进行分析处理，例如通过将图层信息与表征辅助器件的特征图案模式进行比对，来确定在第一版图120中是否存在辅助器件，并且当存在辅助器件时，确定辅助器件在第一版图120中的尺寸信息、坐标信息及与周围器件的连线信息。在本公开的上下文中，表征一种器件的“特征图案模式”表示版图设计中用于实现该器件的特定于该器件的图案。
在一些实施例中，电子设备140可以通过辅助器件以及第一版图120中的其余器件的坐标信息来确定与辅助器件相关联的布局规则。例如，电子设备140可以通过分析Dummy 350-1至350-4以及第一器件区域340-1和340-2的坐标信息，确定如下的示例性相对位置信息：Dummy 350-1和350-3分别被布置在第一器件区域340-1和340-2的左侧，并且Dummy 350-2和350-4分别被布置在第一器件区域340-1和340-2的右侧，并且Dummy 350-1和350-2和第一器件区域340-1关于其上边界和下边界对齐，从而获得Dummy 350-1至350-4与相应的MOSFET之间的布局规则。在一些实施例中，电子设备140可以以与上文参照确定第一电路200中器件的布线规则类似的方式来确定辅助器件与其它器件之间的布线规则，本公开在此不再赘述。由于辅助器件的布置方式蕴含了丰富的工程师设计经验并且会对周围其它器件的特性产生影响，因此通过根据该实施方式的方法，可以将第一版图120中辅助器件的布置方式也映射到第二版图150中，从而进一步提高第二版图150的布局布线质量
图6示出了根据本公开的一些实施例的用于确定第二版图150的方法600的流程图。例如，方法600可以作为如图4所示的框406的一种示例实现。在一些实施例中，方法600可以由如图1所示的电子设备140执行。应当理解的是，方法600还可以包括未示出的附加框和/或可以省略所示出的框，本公开的范围在此方面不受限制。
在框602，电子设备140从第一约束信息中提取与第一工艺相关联的第一布局特征，第一布局特征至少指示第一器件组的组成、以及第一器件组在第一版图120中的布局规则和布线规则，第一器件组包括第一版图120中的、满足组合条件集中的至少一个组合条件的多个器件，组合条件集包括：多个器件属于同一类型的器件、或者多个器件组成功能块。由于在实践中第一电路200往往包括大量的器件，因此在本公开中通过对器件进行分组来简化第一约束信息，从而提高版图映射的效率。
在一些实施例中，电子设备140可以将第一电路200中的属于同一类型的器件归为一个第一器件组。例如，电子设备140可以将多个MOSFET归为一组。电子设备140还可以将多个电阻器归为一组。在一些实施例中，电子设备140可以将由多个器件组成的功能块中的所有器件归为一组。例如，电子设备140可以将构成RC滤波器的电阻器和电容器归为一组。
在一些实施例中，当在第一版图120中存在Dummy 350、Tap 320之类的辅助器件时，还可以在对器件进行分组时考虑辅助器件与这些器件的位置关系。例如，如果确定与第一电路200中的器件相对应的图案在第一版图120中被与辅助器件相对应的图案围绕，则电子设备140可以将这些器件归为一组。例如，在图3所示的第一版图120中，由于第一模块区域310被Tap 320-1围绕，因此电子设备140可以将第一模块区域310中的器件归为一组。类似地，电子设备140可以将第二模块区域330中的器件归为一组。例如，由于第一器件区域340-1和340-2被Dummy 350围绕，因此电子设备140可以将第一器件区域340-1和340-2所对应的MOSFET归为一组。由于辅助器件的布置方式蕴含了丰富的工程师设计经验，因此通过在对器件进行分组时考虑辅助器件，可以更加合理地对器件进行分组，并且可以继承第一版图120的成熟设计，从而进一步提高第二版图150的布局布线质量。
应当理解的是，还可以根据其它任何合适的标准来对器件进行分组，本公开的范围在此方面不受限制。在一些实施例中，电子设备140可以将辅助器件也归入对应的第一 器件组中。在一些实施例中，电子设备140可以为每个辅助器件记录其所围绕的器件的名称或编号。本公开的范围在此方面不受限制。
在确定器件分组之后，电子设备140可以从第一约束信息中提取多个第一器件组之间的布局规则和布线规则。在一些实施例中，电子设备140可以基于第一器件组中的各个器件的坐标信息确定第一器件组的坐标信息，并且根据第一器件组的坐标信息来获取多个第一器件组之间的相对位置关系，例如，电子设备140可以确定与第一模块区域310对应的第一器件组和与第二模块区域330对应的多个器件组关于其上边界对齐、并且关于版图的中轴线呈镜像对称。
在一些实施例中，电子设备140还可以基于器件的分组来对版图中的导线进行分组。例如，电子设备140可以将版图中的导线分为两个部分，即，组内导线和组间导线。组内导线是每个第一器件组中的器件之间的导线，而组间导线是多个第一器件组之间的导线。电子设备140可以从第一约束信息中的布线规则中，提取与组内导线相关联的布线规则、以及与组间导线相关联的布线规则。
在框604，电子设备140参照第一布局特征来对第二电路中的器件进行分组，以获得与第二工艺相关联的第二布局特征，第二布局特征至少指示与第一器件组相对应的第二器件组的组成、以及第二器件组的布局规则和布线规则，第二器件组包括第二工艺的多个器件。在一些实施例中，电子设备140可以根据第一电路200中的器件与第二电路中的器件的对应关系，按照第一电路200中的器件的分组方式来对第二电路中的器件进行分组。换言之，在第一工艺下被归为一组的多个器件在第二工艺下同样被归为一组。此外，第二器件组之间的布局和布线规则同样与第一组器件之间的布局和布线规则保持一致。通过这种方式，可以在进行版图映射时，尽可能地根据第一版图120的布局和布线方式来设计第二版图150，以继承第一版图120的优良电路特性。
在框606，电子设备140基于第二布局特征来确定第二约束信息。在一些实施例中，电子设备140可以直接基于第二布局特征，确定第二电路中的器件在第二版图150中的布局和布线规则。例如，电子设备140可以首先根据每个第二器件组中的器件在第一版图120中的相对位置关系和连线方式，确定第二器件组中的器件在组内的相对位置关系和连线方式。然后，电子设备140可以进一步确定第二器件组之间的相对位置关系和连线方式。
在一些实施例中，电子设备140可以在用户界面上呈现表征第二布局特征的图形。图7示出了根据本公开的一些实施例的用于呈现第二布局特征的图形700的示意图。出于说明和简化的目的，在图7中仅示出了部分图形元素。在图形700中，椭圆710-1至710-8(单独或统一地称为椭圆710)表示第二器件组中的相应第二器件组的位置和面积。位于图形700中央的点划线720示出了版图的中轴线。此外，虚线730示出了各个第二器件组之间的相邻关系。在一些实施例中，椭圆710可以具有不同的颜色，以表示不同的对称关系。例如，关于中轴线镜像对称的两个第一器件组所对应的两个椭圆710可以被示出为绿色，并且关于中轴线自对称的第一器件组所对应的椭圆710可以被示出为红色。通过这种方式，可以以直观的方式向用户呈现第二布局特征。应当理解的是，图7中的图形元素椭圆710、点划线720和虚线730仅是示例性的，还可以以任何合适的图形元素来呈现第二布局特征，本公开的范围在此方面不受限制。
在一些实施例中，电子设备140可以经由用户界面接收用户对图形700中的图形元 素的操作。例如，用户可以通过诸如鼠标之类的输入装置通过拖拽相应的图形元素来改变图形元素的位置。电子设备140可以接收用户的该拖拽操作，并且将图形元素的经改变的位置确定为相应的第二器件组在第二版图150中的新的位置，并且利用新的位置来确定第二器件组在第二版图150中与其它第二器件组的相对位置关系，从而调整第二布局特征，以获得与改变后的图形相对应的目标布局特征。电子设备140可以以与上文参照第二布局特征的描述类似的方式，基于目标布局特征来确定第二约束信息。通过这种方式，可以使得用户能够实时编辑第二约束信息，并且以可视化地方式向用户直观得呈现经修改后的布局。
在一些实施例中，电子设备140还可以将第一约束信息中的非版图约束转换为第二约束信息中的版图约束。例如，在第一约束信息还指示第一版图120中的导线的寄生电容寄生电阻RC参数的情况下，电子设备140还可以将RC约束转化为第二约束信息中的用于第二工艺的多个导线的宽度、长度或者间距。在一些实施例中，电子设备140可以借助于已知的第二工艺下的金属特性，例如金属的单位电阻、单位电容等信息，来根据RC参数计算第二工艺下的用于实现连线的导线的宽度、长度或者导线之间的间距，以尽可能地使得第二版图150的RC参数与第一版图120保持一致。
在框608，电子设备140基于第二约束信息来确定第二版图150。在一些实施例中，电子设备140可以基于第二约束信息分层次地对第二电路中的器件进行布局和布线。例如，电子设备140可以首先布置各个第二器件组中的器件。电子设备140可以基于第二约束信息中与相应的第二器件组中的器件有关的约束信息来拼接多个器件模板单元，以形成第二器件组。在本公开的上下文中，“器件模板单元”表示针对第二工艺开发的器件单元，其与PDK 130中的PCell类似。第二工艺下的每个器件都有相对应的器件模板单元。在一些实施例中，器件模板单元可以基于PDK 130中的PCell而被设计。例如，通过将PCell中相应的版图层次延伸至器件单元的边界，从而使得在拼接多个器件模板单元时不会产生重叠。此外，还可以通过预先运行DRC验证并根据验证结果修改器件单元中的版图设计来消除DRC问题。通过这种方式，可以使得在拼接器件模板单元以形成第二器件组时不会产生错位、重叠和DRC问题，从而在最大程度上避免了后期设计人员对于版图的修复。因此，可以提高版图映射的效率和自动化程度。
电子设备140可以根据第二约束信息来连接第二器件组中的器件模板单元。在一些实施例中，电子设备140可以在第一版图120中用于实现连线的导线段的基础上，通过对导线段进行伸缩来使得经伸缩的导线段可以适于第二版图150的布局，并且利用经伸缩的导线段来连接对应的器件，同时保持导线段与器件连接后构成的电路拓扑结构与第一版图120中一致。
在完成对各个第二器件组的布局和布线之后，电子设备140可以进行上层的布局布线。电子设备140可以基于第二约束信息中指示的各个第二器件组以及其它器件之间的相对位置关系来布置第二器件组和与其它器件相对应的器件模板单元。与组件布线类似地，电子设备140可以在第一版图120中用于实现连线的导线段的基础上，通过对导线段进行伸缩来使得经伸缩的导线段可以适于第二版图150的布局，并且利用经伸缩的导线段来连接对应的器件组中的器件，同时保持所获得的第二版图150的电路拓扑结构与第一版图120中一致。通过这种方式，可以基于所确定的第二约束信息，自动完成对第二电路的布局和布线，以得到候选版图。
在一些实施例中，电子设备140可以计算候选版图中的导线的RC参数，并且将候选版图的RC参数与第一版图120的RC参数进行比较，如果二者的偏差大于预定阈值，则电子设备140可以调整有关的导线的宽度、长度或者距离，并且基于此更新第二约束信息。电子设备140于是可以基于经更新的第二约束信息，来对第二电路进行布局布线，以得到更新的候选版图。该过程可以迭代地执行，直至所获得的候选版图的RC参数与第一版图120的RC参数之间的偏差小于预定阈值。通过这种方式可以使得第二版图150的RC参数与第一版图120保持一致。
通过以上结合图1至图7的描述可以看到，根据本公开的用于版图映射的方法可以从待映射的原版图和原电路中提取用于布局和布线的约束信息，并且基于所提取的约束信息来对新工艺下的新电路进行自动布局和布线，以获得用于实现新电路的新版图。通过这种方式，根据本公开的方法在最大程度上避免了常规方案中由直接替换层次或参数化单元而带来的错位、重叠和DRC问题，因此可以大幅降低设计人员的工作量。此外，根据本公开的方法并不需要针对不同工艺而被定制，从而实现了版图映射与工艺的解耦。
在上文中已经参考图1至图7详细描述了根据本公开的方法的示例实现，在下文中将描述相应的装置的实现。
图8示出了根据本公开的一些实施例的用于版图映射的示例装置800的框图。该装置800例如可以用于实现如图1中所示的电子设备140。如图8所示，装置800可以包括第一约束信息确定模块802，该第一约束信息确定模块802被配置为基于表征第一电路的第一网表文件和用于实现第一电路的第一版图，确定与第一电路相关联的第一约束信息，第一网表文件和第一版图与第一工艺相关联，第一约束信息至少指示第一电路中的器件在第一版图中的布局规则和布线规则。装置800还可以包括第二网表文件确定模块804，该第二网表文件确定模块804被配置为基于第一网表文件和与第二工艺相关联的工艺设计套件，确定与第二工艺相关联的第二网表文件，第二网表文件表征第二电路，第二工艺不同于第一工艺，第二电路具有与第一电路相同的电路拓扑结构。此外，装置800还可以包括第二版图确定模块806，该第二版图确定模块806被配置为基于第一约束信息和第二网表文件，确定与第二工艺相关联的、用于实现第二电路的第二版图。
在一些实施例中，第一约束信息确定模块802还被配置为：将第一版图和第一网表文件进行比对，以提取第一电路中的器件和连线与第一版图中的图案的对应关系；以及基于对应关系，从第一版图中提取第一约束信息。
在一些实施例中，布局规则包括第一电路中的多个器件在第一版图中的相对位置信息，并且布线规则包括第一电路中的多个器件在第一版图中的连线信息。
在一些实施例中，第一约束信息还指示辅助器件在第一版图中的布局规则和布线规则，辅助器件未被包括在第一电路中、并且与辅助器件相对应的图案被包括在第一版图中，第一约束信息确定模块802还被配置为：获取第一版图的图层信息，图层信息指示第一版图的相应图层中的图案元素的位置；以及分析图层信息，以提取辅助器件在第一版图中的布局规则和布线规则。
在一些实施例中，第二版图确定模块806还被配置为：基于第一约束信息和第二网表文件，确定与第二电路相关联的第二约束信息，第二约束信息至少指示第二电路中的器件的布局规则和布线规则；以及基于第二约束信息，确定第二版图。
在一些实施例中，基于第一约束信息和第二网表文件确定与第二电路相关联的第二 约束信息包括：从第一约束信息中提取与第一工艺相关联的第一布局特征，第一布局特征至少指示第一器件组的组成、以及第一器件组在第一版图中的布局规则和布线规则，第一器件组包括第一版图中的、满足组合条件集中的至少一个组合条件的多个器件，组合条件集包括：多个器件属于同一类型的器件、或者多个器件组成功能块；参照第一布局特征来对第二电路中的器件进行分组，以获得与第二工艺相关联的第二布局特征，第二布局特征至少指示第二器件组的组成、以及第二器件组的布局规则和布线规则，第二器件组与第一器件组相对应，并且第二器件组包括第二工艺的多个器件；以及基于第二布局特征，确定第二约束信息。
在一些实施例中，第一约束信息还指示辅助器件在第一版图中的布局规则和布线规则，辅助器件未被包括在第一电路中、并且与辅助器件相对应的图案被包括在第一版图中，组合条件集还包括：与第一电路中的器件相对应的图案在第一版图中被与辅助器件相对应的图案围绕。
在一些实施例中，基于第二布局特征确定第二约束信息包括：经由用户界面，接收用户对与第二布局特征相关联的图形元素的操作；基于操作，调整第二布局特征，以获得目标布局特征；以及基于目标布局特征，确定第二约束信息。
在一些实施例中，基于第二约束信息确定第二版图包括：基于第二约束信息，拼接多个器件模板单元以形成第二器件组，多个器件模板单元分别对应于第二工艺中的多个器件；基于第二约束信息，连接第二器件组中的器件模板单元；基于第二约束信息，布置第二器件组和与其它器件相对应的器件模板单元；以及基于第二约束信息，连接第二器件组和与其它器件相对应的器件模板单元。
在一些实施例中，第一约束信息还指示第一版图中的导线的寄生电容寄生电阻RC参数，第二约束信息还指示用于第二工艺的多个导线的宽度、长度或者间距，基于第一约束信息和第二网表文件确定与第二电路相关联的第二约束信息包括：基于RC参数和与第二工艺相关联的金属特性，计算用于第二工艺的多个导线的宽度、长度或者间距。
在一些实施例中，基于第二约束信息确定第二版图包括：基于第二约束信息，确定与第二工艺相关联的、用于实现第二电路的候选版图；如果候选版图中的导线的RC参数与第一版图中的导线的RC参数的偏差大于预定阈值，则基于第一版图中的导线的RC参数，更新第二约束信息；以及基于经更新的第二约束信息，确定第二版图。
在一些实施例中，第二网表文件确定模块804还被配置为：将第一网表文件中的器件替换为与第二工艺相关联的工艺设计套件中的对应器件，以获得第二网表文件。
装置800中所包括的模块和/或单元可以利用各种方式来实现，包括软件、硬件、固件或其任意组合。在一些实施例中，一个或多个单元可以使用软件和/或固件来实现，例如存储在存储介质上的机器可执行指令。除了机器可执行指令之外或者作为替代，装置800中的部分或者全部单元可以至少部分地由一个或多个硬件逻辑组件来实现。作为示例而非限制，可以使用的示范类型的硬件逻辑组件包括现场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准品(ASSP)、片上系统(SOC)、复杂可编程逻辑器件(CPLD)，等等。
图8中所示的这些模块和/或单元可以部分或者全部地实现为硬件模块、软件模块、固件模块或者其任意组合。特别地，在某些实施例中，上文描述的流程、方法或过程可以由存储系统或与存储系统对应的主机或独立于存储系统的其它计算设备中的硬件来实 现。
图9示出了可以用于实施本公开的一些实施例的示例设备900的示意性框图。设备900可以用于实现电子设备。如图9所示，设备900包括中央处理单元(CPU)901，其可以根据存储在只读存储器(ROM)902中的计算机程序指令或者从存储单元908加载到随机访问存储器(RAM)903中的计算机程序指令，来执行各种适当的动作和处理。在RAM 903中，还可存储设备900操作所需的各种程序和数据。CPU 901、ROM 902以及RAM 903通过总线904彼此相连。输入/输出(I/O)接口905也连接至总线904。
设备900中的多个部件连接至I/O接口905，包括：输入单元906，例如键盘、鼠标等；输出单元907，例如各种类型的显示器、扬声器等；存储单元908，例如磁盘、光盘等；以及通信单元909，例如网卡、调制解调器、无线通信收发机等。通信单元909允许设备900通过诸如因特网的计算机网络和/或各种电信网络与其它设备交换信息/数据。
处理单元901执行上文所描述的各个方法和处理，例如方法400。例如，在一些实施例中，方法400可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元908。在一些实施例中，计算机程序的部分或者全部可以经由ROM 902和/或通信单元909而被载入和/或安装到设备900上。当计算机程序加载到RAM 903并由CPU 901执行时，可以执行上文描述的方法400的一个或多个步骤。备选地，在其它实施例中，CPU 901可以通过其它任何适当的方式(例如，借助于固件)而被配置为执行方法400。
本文中以上描述的功能可以至少部分地由一个或多个硬件逻辑部件来执行。例如，非限制性地，可以使用的示范类型的硬件逻辑部件包括：场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准产品(ASSP)、芯片上系统的系统(SOC)、负载可编程逻辑设备(CPLD)等等。
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其它可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
此外，虽然采用特定次序描绘了各操作，但是这应当理解为要求这样操作以所示出的特定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的 上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (27)

  1. 一种用于版图映射的方法，其特征在于，所述方法包括：
    基于表征第一电路的第一网表文件和用于实现所述第一电路的第一版图，确定与所述第一电路相关联的第一约束信息，所述第一网表文件和所述第一版图与第一工艺相关联，所述第一约束信息至少指示所述第一电路中的器件在所述第一版图中的布局规则和布线规则；
    基于所述第一网表文件和与第二工艺相关联的工艺设计套件，确定与所述第二工艺相关联的第二网表文件，所述第二网表文件表征第二电路，所述第二工艺不同于所述第一工艺，所述第二电路具有与所述第一电路相同的电路拓扑结构；以及
    基于所述第一约束信息和所述第二网表文件，确定与所述第二工艺相关联的、用于实现所述第二电路的第二版图。
  2. 根据权利要求1所述的方法，其特征在于，基于表征第一电路的第一网表文件和用于实现所述第一电路的第一版图确定与所述第一电路相关联的第一约束信息包括：
    将所述第一版图和所述第一网表文件进行比对，以提取所述第一电路中的器件和连线与所述第一版图中的图案的对应关系；以及
    基于所述对应关系，从所述第一版图中提取所述第一约束信息。
  3. 根据权利要求1或2所述的方法，其特征在于，所述布局规则包括所述第一电路中的多个器件在所述第一版图中的相对位置信息，并且所述布线规则包括所述第一电路中的多个器件在所述第一版图中的连线信息。
  4. 根据权利要求2或3所述的方法，其特征在于，所述第一约束信息还指示辅助器件在所述第一版图中的布局规则和布线规则，所述辅助器件未被包括在所述第一电路中、并且与所述辅助器件相对应的图案被包括在所述第一版图中，基于表征第一电路的第一网表文件和用于实现所述第一电路的第一版图确定与所述第一电路相关联的第一约束信息还包括：
    获取所述第一版图的图层信息，所述图层信息指示所述第一版图的相应图层中的图案元素的位置；以及
    分析所述图层信息，以提取所述辅助器件在所述第一版图中的布局规则和布线规则。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，基于所述第一约束信息和所述第二网表文件确定与所述第二工艺相关联的、用于实现所述第二电路的第二版图包括：
    基于所述第一约束信息和所述第二网表文件，确定与所述第二电路相关联的第二约束信息，所述第二约束信息至少指示所述第二电路中的器件的布局规则和布线规则；以及
    基于所述第二约束信息，确定所述第二版图。
  6. 根据权利要求5所述的方法，其特征在于，基于所述第一约束信息和所述第二网表文件确定与所述第二电路相关联的第二约束信息包括：
    从所述第一约束信息中提取与所述第一工艺相关联的第一布局特征，所述第一布局特征至少指示第一器件组的组成、以及所述第一器件组在所述第一版图中的布局规则和布线规则，所述第一器件组包括所述第一版图中的、满足组合条件集中的至少一个组合条件的多个器件，所述组合条件集包括：多个器件属于同一类型的器件、或者多个器件组成功能块；
    参照所述第一布局特征来对所述第二电路中的器件进行分组，以获得与所述第二工艺相关联的第二布局特征，所述第二布局特征至少指示第二器件组的组成、以及所述第二器件组的布局规则和布线规则，所述第二器件组与所述第一器件组相对应，并且所述第二器件组包 括所述第二工艺的多个器件；以及
    基于所述第二布局特征，确定所述第二约束信息。
  7. 根据权利要求6所述的方法，其特征在于，所述第一约束信息还指示辅助器件在所述第一版图中的布局规则和布线规则，所述辅助器件未被包括在所述第一电路中、并且与所述辅助器件相对应的图案被包括在所述第一版图中，所述组合条件集还包括：与所述第一电路中的器件相对应的图案在所述第一版图中被与所述辅助器件相对应的图案围绕。
  8. 根据权利要求6或7所述的方法，其特征在于，基于所述第二布局特征确定所述第二约束信息包括：
    经由用户界面，接收用户对与所述第二布局特征相关联的图形元素的操作；
    基于所述操作，调整所述第二布局特征，以获得目标布局特征；以及
    基于所述目标布局特征，确定所述第二约束信息。
  9. 根据权利要求6至8中任一项所述的方法，其特征在于，基于所述第二约束信息确定所述第二版图包括：
    基于所述第二约束信息，拼接多个器件模板单元以形成所述第二器件组，所述多个器件模板单元分别对应于所述第二工艺中的多个器件；
    基于所述第二约束信息，连接所述第二器件组中的器件模板单元；
    基于所述第二约束信息，布置所述第二器件组和与其它器件相对应的器件模板单元；以及
    基于所述第二约束信息，连接所述第二器件组和与其它器件相对应的器件模板单元。
  10. 根据权利要求5所述的方法，其特征在于，所述第一约束信息还指示所述第一版图中的导线的寄生电容寄生电阻RC参数，所述第二约束信息还指示用于所述第二工艺的多个导线的宽度、长度或者间距，基于所述第一约束信息和所述第二网表文件确定与所述第二电路相关联的第二约束信息包括：
    基于所述RC参数和与所述第二工艺相关联的金属特性，计算用于所述第二工艺的多个导线的宽度、长度或者间距。
  11. 根据权利要求10所述的方法，其特征在于，基于所述第二约束信息确定所述第二版图包括：
    基于所述第二约束信息，确定与所述第二工艺相关联的、用于实现所述第二电路的候选版图；
    如果所述候选版图中的导线的RC参数与所述第一版图中的导线的RC参数的偏差大于预定阈值，则基于所述第一版图中的导线的RC参数，更新所述第二约束信息；以及
    基于经更新的第二约束信息，确定所述第二版图。
  12. 根据权利要求1至11中任一项所述的方法，其特征在于，基于所述第一网表文件和与第二工艺相关联的工艺设计套件确定与所述第二工艺相关联的第二网表文件包括：
    将所述第一网表文件中的器件替换为与所述第二工艺相关联的所述工艺设计套件中的对应器件，以获得所述第二网表文件。
  13. 一种用于版图映射的装置，其特征在于，所述装置包括：
    第一约束信息确定模块，被配置为基于表征第一电路的第一网表文件和用于实现所述第一电路的第一版图，确定与所述第一电路相关联的第一约束信息，所述第一网表文件和所述第一版图与第一工艺相关联，所述第一约束信息至少指示所述第一电路中的器件在所述第一 版图中的布局规则和布线规则；
    第二网表文件确定模块，被配置为基于所述第一网表文件和与第二工艺相关联的工艺设计套件，确定与所述第二工艺相关联的第二网表文件，所述第二网表文件表征第二电路，所述第二工艺不同于所述第一工艺，所述第二电路具有与所述第一电路相同的电路拓扑结构；以及
    第二版图确定模块，被配置为基于所述第一约束信息和所述第二网表文件，确定与所述第二工艺相关联的、用于实现所述第二电路的第二版图。
  14. 根据权利要求13所述的装置，其特征在于，所述第一约束信息确定模块还被配置为：
    将所述第一版图和所述第一网表文件进行比对，以提取所述第一电路中的器件和连线与所述第一版图中的图案的对应关系；以及
    基于所述对应关系，从所述第一版图中提取所述第一约束信息。
  15. 根据权利要求13或14所述的装置，其特征在于，所述布局规则包括所述第一电路中的多个器件在所述第一版图中的相对位置信息，并且所述布线规则包括所述第一电路中的多个器件在所述第一版图中的连线信息。
  16. 根据权利要求14或15所述的装置，其特征在于，所述第一约束信息还指示辅助器件在所述第一版图中的布局规则和布线规则，所述辅助器件未被包括在所述第一电路中、并且与所述辅助器件相对应的图案被包括在所述第一版图中，所述第一约束信息确定模块还被配置为：
    获取所述第一版图的图层信息，所述图层信息指示所述第一版图的相应图层中的图案元素的位置；以及
    分析所述图层信息，以提取所述辅助器件在所述第一版图中的布局规则和布线规则。
  17. 根据权利要求13至16中任一项所述的装置，其特征在于，所述第二版图确定模块还被配置为：
    基于所述第一约束信息和所述第二网表文件，确定与所述第二电路相关联的第二约束信息，所述第二约束信息至少指示所述第二电路中的器件的布局规则和布线规则；以及
    基于所述第二约束信息，确定所述第二版图。
  18. 根据权利要求17所述的装置，其特征在于，基于所述第一约束信息和所述第二网表文件确定与所述第二电路相关联的第二约束信息包括：
    从所述第一约束信息中提取与所述第一工艺相关联的第一布局特征，所述第一布局特征至少指示第一器件组的组成、以及所述第一器件组在所述第一版图中的布局规则和布线规则，所述第一器件组包括所述第一版图中的、满足组合条件集中的至少一个组合条件的多个器件，所述组合条件集包括：多个器件属于同一类型的器件、或者多个器件组成功能块；
    参照所述第一布局特征来对所述第二电路中的器件进行分组，以获得与所述第二工艺相关联的第二布局特征，所述第二布局特征至少指示第二器件组的组成、以及所述第二器件组的布局规则和布线规则，所述第二器件组与所述第一器件组相对应，并且所述第二器件组包括所述第二工艺的多个器件；以及
    基于所述第二布局特征，确定所述第二约束信息。
  19. 根据权利要求18所述的装置，其特征在于，所述第一约束信息还指示辅助器件在所述第一版图中的布局规则和布线规则，所述辅助器件未被包括在所述第一电路中、并且与所述辅助器件相对应的图案被包括在所述第一版图中，所述组合条件集还包括：与所述第一电 路中的器件相对应的图案在所述第一版图中被与所述辅助器件相对应的图案围绕。
  20. 根据权利要求18或19所述的装置，其特征在于，基于所述第二布局特征确定所述第二约束信息包括：
    经由用户界面，接收用户对与所述第二布局特征相关联的图形元素的操作；
    基于所述操作，调整所述第二布局特征，以获得目标布局特征；以及
    基于所述目标布局特征，确定所述第二约束信息。
  21. 根据权利要求18至20中任一项所述的装置，其特征在于，基于所述第二约束信息确定所述第二版图包括：
    基于所述第二约束信息，拼接多个器件模板单元以形成所述第二器件组，所述多个器件模板单元分别对应于所述第二工艺中的多个器件；
    基于所述第二约束信息，连接所述第二器件组中的器件模板单元；
    基于所述第二约束信息，布置所述第二器件组和与其它器件相对应的器件模板单元；以及
    基于所述第二约束信息，连接所述第二器件组和与其它器件相对应的器件模板单元。
  22. 根据权利要求17所述的装置，其特征在于，所述第一约束信息还指示所述第一版图中的导线的寄生电容寄生电阻RC参数，所述第二约束信息还指示用于所述第二工艺的多个导线的宽度、长度或者间距，基于所述第一约束信息和所述第二网表文件确定与所述第二电路相关联的第二约束信息包括：
    基于所述RC参数和与所述第二工艺相关联的金属特性，计算用于所述第二工艺的多个导线的宽度、长度或者间距。
  23. 根据权利要求22所述的装置，其特征在于，基于所述第二约束信息确定所述第二版图包括：
    基于所述第二约束信息，确定与所述第二工艺相关联的、用于实现所述第二电路的候选版图；
    如果所述候选版图中的导线的RC参数与所述第一版图中的导线的RC参数的偏差大于预定阈值，则基于所述第一版图中的导线的RC参数，更新所述第二约束信息；以及
    基于经更新的第二约束信息，确定所述第二版图。
  24. 根据权利要求13至23中任一项所述的装置，其特征在于，所述第二网表文件确定模块还被配置为：
    将所述第一网表文件中的器件替换为与所述第二工艺相关联的所述工艺设计套件中的对应器件，以获得所述第二网表文件。
  25. 一种电子设备，其特征在于，所述电子设备包括：
    至少一个处理器；以及
    至少一个存储器，所述至少一个存储器被耦合到所述至少一个处理器，并且存储用于由所述至少一个处理器执行的指令，所述指令当由所述至少一个处理器执行时，使得所述电子设备执行根据权利要求1至12中任一项所述的方法。
  26. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序在被处理器执行时实现根据权利要求1至12中任一项所述的方法。
  27. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机可执行指令，所述计算机可执行指令在被处理器执行时，使计算机实现根据权利要求1至12中任一项所述 的方法。
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