US20140019931A1 - Systems and methods for fixing pin mismatch in layout migration - Google Patents
Systems and methods for fixing pin mismatch in layout migration Download PDFInfo
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- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Definitions
- the invention relates to circuit design and, more particularly, to systems and methods for fixing pin mismatches from swapping library cells in layout migration.
- Semiconductor chip layout is subject to complex rules governing, among other things, geometry of shapes on process layers. These complex rules may include, for example, width requirements, spacing requirements, overlap requirements, etc. Compliance with these design rules is important to chip functionality and manufacturability.
- Technology migration is another process which gives rise to a large number of design rule violations.
- Migration is the process, which transforms layouts in one technology to a layout in another technology with different design rules.
- the migration process begins with scaling, using commercially available programs, and is sufficient to produce a design-rule-correct layout.
- non-scalable differences in the design rules result in the introduction of design rules violations, which must again be corrected by tedious manual iteration.
- a method in a first aspect of the invention, includes collecting information about at least one first technology pin from at least one library cell in a first technology.
- the method further includes swapping the at least one library cell in the first technology with at least one library cell in a second technology.
- the method further includes collecting information about at least one second technology pin from the at least one library cell in the second technology.
- the method further includes building a pin-mapping table that is configured to map the at least one first technology pin to the at least one second technology pin.
- the method further includes scaling a layout from the first technology to the second technology.
- the method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying the ground rules of the second technology.
- a method implemented in an infrastructure includes collecting information about first technology pins from a first technology.
- the method further includes collecting information about second technology pins from a second technology.
- the method further includes building a pin-mapping table that is configured to map at least one first technology pin to at least one second technology pin, wherein the pin-mapping table is built based on a mapping cost between a first rectangle representative of the at least one first technology pin and a second rectangle representative of the at least one second technology pin.
- the method further includes scaling a layout from the first technology to the second technology.
- the method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying the ground rules of the second technology.
- a computer system in yet another aspect of the invention, includes a CPU, a computer readable memory and a computer readable storage media.
- the system further includes first program instructions to pair each rectangle representative of a pin from a first technology to at least one rectangle representative of at least one pin from a second technology.
- the system further includes second program instructions to calculate a shift in a “y” direction for each of the pairs of rectangles.
- the system further includes third program instructions to compare the calculated shifts in the “y” direction for each pair of rectangles.
- the system further includes fourth program instructions to select a calculated shift with a minimum absolute value as an overall shift in the “y” direction from the compared pairs of rectangles.
- the system further includes fifth program instructions to adjusting coordinates of each rectangle from the first technology based on the selected overall shift in the “y” direction.
- the system further includes sixth program instructions to calculate a mapping cost for each rectangle from the first technology to each rectangle of the second technology using the adjusted coordinates of each rectangle from the first technology.
- the system further includes seventh program instructions to map each rectangle from the first technology to a rectangle from the second technology such that the mapped rectangles comprise a lowest calculated mapping cost.
- the first through seventh program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.
- FIGS. 1-3 show examples of pin mismatches that may occur during technology migration
- FIG. 4 is an illustrative external environment for implementing the invention in accordance with aspects of the invention.
- FIGS. 5 and 6 are flow diagrams of processes in accordance with aspects of the invention.
- FIGS. 7 and 8 show examples of calculating mapping costs between two different layouts or technologies in accordance with aspects of the invention.
- FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
- the invention relates to circuit design and, more particularly, to systems and methods for fixing pin mismatches from swapping library cells in layout migration. More specifically, implementations of the invention provide a system and method to collect pin information for library cells in a first technology, collect pin information for library cells in a second technology, build a pin-mapping table from the collected pin information between the first technology and the second technology, scale the integrated circuit layout with respect to the second technology, and modify the pins in the second technology based on the pin-mapping table.
- geometric relationships are defined on the layout of the integrated circuit utilizing the first technology.
- the defined geometric relationships accurately capture the wire connections with respect to the pins of the library cells for the first technology.
- the pins of the library cells are modified to match pin shapes and locations within the layout of the integrated circuit utilizing the second technology.
- LP linear program
- the systems and methods of the present invention use the original topography of the first technology to reconnect the pins in the second technology.
- FIGS. 1-3 show multiple examples of pin mismatches that may occur between library cells of a first technology and library cells of a second technology.
- the pin mismatches may be caused by location, dimension, and/or topography changes introduced to the pins during the scaling and/or layout migration from the first technology to the second technology.
- FIG. 1 shows a library cell 5 , e.g., a local clock buffer, designed using a first technology, e.g., 32 nm technology.
- the library cell 5 comprises multiple pins 15 for connecting the devices of the library cell 5 to interconnect wiring and or other devices of an integrated circuit.
- FIG. 1 also shows a corresponding library cell 10 designed using the second technology, e.g., 22 nm technology.
- the pin 20 has changed location and dimension due to the scaling and/or layout migration of the library cell between the first technology and the second technology.
- This change in the location and the dimension of pin 20 between the first technology and the second technology may cause a misalignment of interconnect wiring if the changes in the location and the dimension of pin 20 are not accounted for during the layout design phase for the second technology.
- FIG. 2 shows a library cell 25 , e.g., a local clock buffer, designed using a first technology, e.g., 32 nm technology.
- the library cell 25 comprises multiple pins 30 for connecting the devices of the library cell 25 to interconnect wiring and/or devices of the integrated circuit.
- FIG. 2 also shows a corresponding library cell 35 designed using the second technology, e.g., 22 nm.
- the pin 40 has changed location and the pin 45 has changed location and topology due to the scaling and/or layout migration of the library cell between the first technology and the second technology.
- These changes in the location of pin 40 and the location and the topology of pin 45 between the first technology and the second technology may cause a misalignment of interconnect wiring if the changes are not accounted for during the layout design phase for the second technology.
- FIG. 3 shows a library cell 50 , e.g., a logic cell, designed using a first technology, e.g., 32 nm technology.
- the library cell 50 comprises multiple pins 55 for connecting the devices of the library cell 50 to interconnect wiring and/or devices of the integrated circuit.
- FIG. 3 also shows a corresponding library cell 60 designed using the second technology, e.g., 22 nm.
- the pin 65 has changed location and topology due to the scaling and/or layout migration of the library cell between the first technology and the second technology. These changes in the location and the topology of pin 65 between the first technology and the second technology may cause a misalignment of interconnect wiring if the changes in the location and the topology of pin 65 are not accounted for during the layout design phase for the second technology.
- Implementations of the present invention can fix the pin mismatches shown in FIGS. 1-3 .
- aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.”
- aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
- the computer readable medium may be a computer readable signal medium or a computer readable storage medium.
- a computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.
- a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
- Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
- Computer program instructions may also be stored in the computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
- the computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
- FIG. 4 shows an illustrative environment 100 for managing the processes in accordance with the invention.
- the environment 100 includes a server or other computing system 112 that can perform the processes described herein.
- the server 112 includes a computing device 114 .
- the computing device 114 can be resident on a network infrastructure or computing device of a third party service provider (any of which is generally represented in FIG. 4 ).
- the computing device 114 also includes a processor 120 , memory 122 A, an I/0 interface 124 , and a bus 126 .
- the memory 122 A can include local memory employed during actual execution of program code, bulk storage, and cache memories, which provide temporary storage of at least some program code, in order to reduce the number of times code should be retrieved from bulk storage during execution.
- the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S).
- the computing device 114 is in communication with the external I/O device/resource 128 and the storage system 122 B.
- the I/O device 128 can comprise any device that enables an individual to interact with the computing device 114 (e.g., user interface) or any device that enables the computing device 114 to communicate with one or more other computing devices using any type of communications link.
- the external I/O device/resource 128 may be for example, a handheld device, PDA, handset, keyboard, etc.
- the processor 120 executes computer program code (e.g., program control 144 ), which can be stored in the memory 122 A and/or storage system 122 B.
- the program control 144 controls an electronic design automation (EDA) tool 150 to perform the processes described herein.
- the EDA tool 150 can be implemented as one or more program code in the program control 144 stored in memory 122 A as separate or combined modules. Additionally, the EDA tool 150 may be implemented as a separate dedicated processor or several processors to provide the function of this tool.
- the processor 120 can read and/or write data to/from memory 122 A, storage system 122 B, and/or I/O interface 124 .
- the program code executes the processes of the invention.
- the bus 126 provides a communications link between each of the components in the computing device 114 .
- the EDA tool 150 can fix pin mismatches caused from swapping library cells during a layout migration.
- the EDA tool 150 can collect pin information for library cells in a first technology, collect pin information for library cells in a second technology, build a pin-mapping table from the collected pin information between the first technology and the second technology, scale the integrated circuit layout with respect to the second technology, and modify the pins in the second technology based on the pin-mapping table.
- FIGS. 5 and 6 show exemplary flows for performing aspects of the present invention.
- the steps of FIGS. 5 and 6 may be implemented to solve the problem of pin mismatches between different technologies during layout migration.
- the flowcharts and block diagrams in FIGS. 5 and 6 illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention.
- each block in the flowcharts or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).
- the functions noted in the blocks may occur out of the order noted in the figures.
- FIG. 5 depicts an exemplary flow 500 for a layout migration of library cells from a first technology to a second technology.
- an input comprising a netlist or other formatted listing of components and/or circuits and their positions in a first layout (e.g., a first technology layout or an old layout) and ground rules of the second technology is provided.
- pin information for library cells in the netlist of the first layout are collected.
- the pin information includes the name of each pin and the rectangle in a given pin layer that represents each pin. The rectangles are then sorted in a pin-list.
- the rectangles for each of the pins may be sorted in the pin-list based on a center point of each rectangle, and the sorting criteria can be either from left to right (i.e., non-descending order of the “x” coordinate of the center points), or from bottom to top (i.e., non-descending order of the “y” coordinate of the center points), or the non-descending order of the summation of “x” and “y” coordinates of the center points.
- the library cells of the first layout are converted in an initial pass to a second layout (e.g., a second technology layout or a new layout). In embodiments, this is performed by swapping of library cells of the second technology to convert the library cells of the first layout to the second layout.
- pin information for library cells in the second layout is collected.
- the pin information includes the name of each pin, e.g., two matching pins between the library cell in the first layout and its swapped cell in the second layout may have a same name, and the rectangles in a given pin layer that represent each pin. The rectangles are then sorted in a pin-list, as described above with respect to the first layout.
- a pin-mapping table is built to map the pins in library cells of the first layout to pins in library cells of the second layout.
- the number of rectangles for each pin may be different between the library cells of first technology and the library cells of the second technology because of shifts in topology between corresponding library cells.
- the number of rectangles for each library cell of the first technology may increase, decrease, or remain equal as compared to each corresponding library cell of the second technology.
- the rectangles in the first layout are mapped to the rectangles in the second layout based on a mapping cost, e.g., a minimum mapping cost, while taking into consideration an overall shift A in the “y” direction with respect to the gates of each library cell, as discussed in further detail below with respect to FIG. 6 .
- the overall shift A in the “y” direction may be caused by library cell growth during the scaling process in step 515 .
- using the mapping cost and the overall shift A in the “y” direction provides an efficient and effective approach to mapping the pins between the two layouts.
- a geometry database may be built that provides geometrical relationship information regarding elements (e.g., tiles or rectangles) of the first layout.
- elements e.g., tiles or rectangles
- an integrated circuit is generally composed of multiple layers, and each layer typically includes a collection of shapes (e.g., tiles or rectangles).
- the shapes may be wires on a routing layer or may be active regions in a diffusion area. On a given layer, two shapes generally overlap one another only if those two shapes are electrically connected.
- the function of the geometric database is to create an appropriate data structure for each collection of shapes.
- the geometric database allows the wire connections to be captured correctly with respect to the pins of the library cells in the first layout.
- step 540 all components in the first layout are scaled with respect to the second layout using a predetermined scaling factor.
- the pin-mapping table generated in step 525 is used to modify the pins from the first layout to match the pin shapes and locations in the second layout.
- hierarchical constraints are generated in mathematical form.
- the first layout and the ground rule files of the second technology are used to define hierarchical constraints of the first layout in mathematical form.
- Typical ground rules may include spacing rules specifying minimum space between objects, width rules specifying minimum width of some objects, and methodology rules specifying design requirements for assembling library cells. The ground rules ensure manufacturability of the integrated circuit.
- an LP problem is generated and solved, and the first layout is modified based on the LP problem.
- Generating and solving LP problems is a mathematical method for determining a way to achieve a best outcome (e.g., an integrated circuit running with a specified speed or delay) in a given mathematical model for some list of requirements represented as linear relationships.
- generating the LP problem may comprise building the hierarchical constraints in the form of an initial inequality expression and then deriving the LP problem from the inequality expression by relaxing integer constraints and using relaxation variables on infeasible constraints.
- relaxing integer constraints means that certain constraints are not applied and infeasible constraints means constraints that are not satisfied for the given layout.
- the LP problem is then solved to obtain an LP solution.
- the LP problem may be solved by using traditional LP solvers, e.g., interior-point methods or simplex algorithms.
- LP solvers e.g., interior-point methods or simplex algorithms.
- a modified first layout is outputted.
- the modified first layout meets the ground rules and is optimal in terms of predetermined objectives for the second layout.
- the library cells of the first layout are replaced with the corresponding library cells of the second technology.
- each library cell in the first layout is swapped with a new library cell from the second technology.
- the library cells of the first layout are removed from the layout and the new library cells are placed in the layout to generate the second layout.
- the new library cells are placed in the layout with same coordinates, orientation, and magnification.
- the pins are automatically connected to the external wires, as the hierarchical constraints and the LP problem solving in step 550 are configured to modify the wires to connect to the new locations of the modified pins with respect to the library cells in the new layout. Therefore, the library cell swapping is no longer disruptive to reconnecting the wires to the pins.
- the swapping of the library cells results in achievement of the second layout for the integrated circuit at step 560 .
- FIG. 6 depicts an exemplary flow 600 for building a pin-mapping table that takes into consideration a minimum mapping cost and an overall shift A in the “y” direction.
- the rectangles from the pin-list generated for the first layout at step 510 are paired with the rectangles or a set of rectangles in the pin-list generated for the second layout at step 520 (as discussed above with respect to FIG. 5 ).
- the rectangles are compared according to the order in which the rectangles are sorted within each pin-list, e.g., based on a center point of each rectangle or set of rectangles.
- the shift ⁇ in the “y” direction for all pairs of rectangles is computed or calculated.
- the shift ⁇ in the “y” direction may be caused by library cell growth during the scaling process in step 515 (as discussed above with respect to FIG. 5 ).
- the shift ⁇ in the “y” direction for each pair of rectangles may be calculated using equation (1) with respect to the gate(s) of each library cell.
- ⁇ in y (center Y location of n 1 rectangle of pin-list for second layout) ⁇ (center Y location of n 1 rectangle of pin-list for first layout)*the scaling factor (1)
- the calculated shifts ⁇ in the “y” direction for each pair of rectangles are then compared, and the calculated shift ⁇ with the minimum absolute value is selected as the overall shift ⁇ in the “y” direction.
- the position or coordinates of the rectangles from the pin-list generated for the first layout are adjusted based on the scaling factor and the selected overall shift ⁇ using equation (2).
- the mapping costs are computed or calculated for each rectangle in the first layout to each rectangle in the second layout.
- the mapping cost is defined as the amount of minimum movement (e.g., movement in a two dimensional space) that it would take to place a rectangle from the first layout (in embodiments the position of the rectangle being the adjusted position calculated based on equation (2)) over a new rectangle from the second layout.
- the mapping cost may be calculated as a cost in the “x” direction plus a cost in the “y” direction.
- the two dimensions can be treated as independent of one another.
- the rectangle (e.g., a first layout rectangle) may be expressed as (r1: xl1, yl1. xh1, yh1), where xl1 is the “x” coordinate or position of the left bottom corner of the rectangle, yl1 is the “y” coordinate or position of the left bottom corner of the rectangle, xh1 is the “x” coordinate or position of the top right corner of the rectangle, and yh1 is the “y” coordinate or position of the top right corner of the rectangle.
- the new rectangle (e.g., a second layout rectangle) may be expressed as (r2: xl2, yl2 ⁇ xh2, yh2), where xl2 is the “x” coordinate or position of the left bottom corner of the new rectangle, yl2 is the “y” coordinate or position of the left bottom corner of the new rectangle, xh2 is the “x” coordinate or position of the top right corner of the new rectangle, and yh2 is the “y” coordinate or position of the top right corner of the new rectangle.
- the cost in the “x” direction may be calculated using equation (3). Assuming the coordinates or position of the rectangle (e.g., a first layout rectangle) is already adjusted (e.g., adjusted with respect to the scaling factors) based on equation (2).
- the cost in the “y” direction may be calculated using equation (4). Assuming the coordinates or position of the rectangle (e.g., a first layout rectangle) is already adjusted (e.g., adjusted with respect to the scaling factors) based on equation (2).
- the calculated cost in the “x” direction from equation (3) may then be added to the calculated cost in the “y” direction from equation (4) to calculate the mapping cost.
- each rectangle in the pin-list for the first layout is mapped to each rectangle in the pin-list for the second layout based on calculated mapping costs while taking into consideration the calculated overall shift ⁇ in the “y” direction. For example, the pair of rectangles with the minimum mapping cost may be mapped together.
- the mappings for each rectangle are added to a mapping table.
- the rectangle 700 from the pin-list generated for the first layout 705 is paired with a set of rectangles 710 from the pin-list generated for the second layout 715 .
- the shift ⁇ 720 in the “y” direction for each pair of rectangles is calculated using equation (1).
- the calculated shifts ⁇ in the “y” direction for each pair of rectangles are then compared, and the calculated shift ⁇ with the minimum absolute value is selected as the overall shift ⁇ 725 in the “y” direction.
- the mapping location or coordinates of the rectangle 700 is then adjusted based on the scaling factor and the overall shift ⁇ 725 using equation (2).
- the mapping cost from adjusted location of rectangle 700 to each rectangle in the set of rectangles 710 is then calculated using equations (3) and (4).
- the mapping cost of moving the rectangle 700 from the adjusted position of (468,3897 ⁇ 892,3952) to the position of (420,3880 ⁇ 480,3970) for the rectangle 730 is calculated as 447
- the mapping cost of moving the rectangle 700 from the adjusted position of (468,3897 ⁇ 892,3952) to the position of (420,3820 ⁇ 880,3880) for the rectangle 735 is calculated as 125
- the mapping cost of moving the rectangle 700 from the adjusted position of (468,3897 ⁇ 892,3952) to the position of (420,3970 ⁇ 880,4030) for the rectangle 740 is calculated as 126.
- the rectangle 700 is then mapped 745 to the rectangle 735 based on the mapping cost calculated for each pair of rectangles while taking into consideration the calculated overall shift ⁇ in the “y” direction. For example, the lowest calculated mapping cost may be used to identify the corresponding rectangle 735 in the set of rectangles 710 that corresponds with the rectangle 700 .
- the mapping 745 for rectangles 700 and 735 is then added to the mapping table.
- a set of rectangles 800 from the pin-list generated for the first layout 805 are paired with a set of rectangles 810 from the pin-list generated for the second layout 815 .
- the shift ⁇ 820 in the “y” direction for each pair of rectangles is calculated using equation (1).
- the calculated shifts ⁇ in the “y” direction for each pair of rectangles are then compared, and the calculated shift ⁇ with the minimum absolute value is selected as the overall shift ⁇ 825 in the “y” direction.
- the mapping location or coordinates of each rectangle in the set of rectangles 800 is then adjusted based on the scaling factor and the overall shift ⁇ 825 using equation (2).
- the mapping location or coordinates of rectangle 827 are adjusted based on the scaling factor and the overall shift ⁇ 825 using equation (2).
- mapping cost from each rectangle in the set of rectangles 800 to each rectangle in the set of rectangles 810 is then calculated using equations (3) and (4).
- mapping cost of moving the rectangle 827 from the adjusted position of (200,3822 ⁇ 412,3878) to the position of (270,3820 ⁇ 420,3880) for the rectangle 830 is calculated as 74.
- the rectangle 827 is then mapped 835 to the rectangle 830 from the set of rectangles 810 based on the mapping cost calculated for each pair of rectangles while taking into consideration the calculated overall shift ⁇ in the “y” direction. For example, the lowest calculated mapping cost may be used to identify the corresponding rectangle 830 in the set of rectangles 810 that corresponds with the rectangle 827 .
- the mapping 835 for rectangles 827 and 830 is then added to the mapping table.
- FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test used with the system and method of the present invention.
- FIG. 9 shows a block diagram of an exemplary design flow 900 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture.
- Design flow 900 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices.
- the design structures processed and/or generated by design flow 900 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems.
- Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system.
- machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).
- Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
- ASIC application specific IC
- PGA programmable gate array
- FPGA field programmable gate array
- FIG. 9 illustrates multiple such design structures including an input design structure 920 that is preferably processed by a design process 910 .
- Design structure 920 may be a logical simulation design structure generated and processed by design process 910 to produce a logically equivalent functional representation of a hardware device.
- Design structure 920 may also or alternatively comprise data and/or program instructions that when processed by design process 910 , generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 920 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer.
- ECAD electronic computer-aided design
- design structure 920 When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 920 may be accessed and processed by one or more hardware and/or software modules within design process 910 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system, which can be implemented with the method and system of the present invention.
- design structure 920 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system functionally simulate or otherwise represent circuits or other levels of hardware logic design.
- Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.
- HDL hardware-description language
- Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures to generate a netlist 980 which may contain design structures such as design structure 920 .
- Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design.
- Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device.
- netlist 980 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array.
- the medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
- Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980 .
- data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.).
- the data structure types may further include design specifications 940 , characterization data 950 , verification data 960 , design rules 970 , and test data files 985 that may include input test patterns, output test results, and other testing information.
- Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc.
- standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc.
- One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention.
- Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990 .
- logic and physical design tools such as HDL compilers and simulation model build tools
- Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920 , design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more devices. In one embodiment, design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates the devices.
- Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).
- Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure.
- Design structure 990 may then proceed to a stage 995 where, for example, design structure 990 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
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Abstract
Description
- The invention relates to circuit design and, more particularly, to systems and methods for fixing pin mismatches from swapping library cells in layout migration.
- Semiconductor chip layout is subject to complex rules governing, among other things, geometry of shapes on process layers. These complex rules may include, for example, width requirements, spacing requirements, overlap requirements, etc. Compliance with these design rules is important to chip functionality and manufacturability.
- Many processes used to create or alter layouts can introduce design rule violations. Manual layout, for example, inevitably introduces violations due to the difficulty of satisfying a large number of complex design rules by hand. These violations are generally corrected via tedious iterations between design rule checking tool runs and manual layout modifications.
- Technology migration is another process which gives rise to a large number of design rule violations. Migration is the process, which transforms layouts in one technology to a layout in another technology with different design rules. The migration process begins with scaling, using commercially available programs, and is sufficient to produce a design-rule-correct layout. However, in many cases, non-scalable differences in the design rules result in the introduction of design rules violations, which must again be corrected by tedious manual iteration.
- For example, due to the technology difference in technology migration, many library cells grow bigger in terms of pitch. This difference in pitch may potentially create pin mismatches in the new integrated circuit layout. The pin mismatches, if not corrected, may cause the wiring of the integrated circuit to be misaligned.
- Conventional layout migration methodology can perform the placement of grown library cells, but does not address the issue of pin mismatches. Specifically, pin mismatches pose a severe challenge in technology migration, which causes difficulty in reusing the wiring connections during layout migration.
- Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
- In a first aspect of the invention, a method is provided that includes collecting information about at least one first technology pin from at least one library cell in a first technology. The method further includes swapping the at least one library cell in the first technology with at least one library cell in a second technology. The method further includes collecting information about at least one second technology pin from the at least one library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the at least one first technology pin to the at least one second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying the ground rules of the second technology.
- In another aspect of the invention, a method implemented in an infrastructure is provided that includes collecting information about first technology pins from a first technology. The method further includes collecting information about second technology pins from a second technology. The method further includes building a pin-mapping table that is configured to map at least one first technology pin to at least one second technology pin, wherein the pin-mapping table is built based on a mapping cost between a first rectangle representative of the at least one first technology pin and a second rectangle representative of the at least one second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying the ground rules of the second technology.
- In yet another aspect of the invention, a computer system is provided that includes a CPU, a computer readable memory and a computer readable storage media. The system further includes first program instructions to pair each rectangle representative of a pin from a first technology to at least one rectangle representative of at least one pin from a second technology. The system further includes second program instructions to calculate a shift in a “y” direction for each of the pairs of rectangles. The system further includes third program instructions to compare the calculated shifts in the “y” direction for each pair of rectangles. The system further includes fourth program instructions to select a calculated shift with a minimum absolute value as an overall shift in the “y” direction from the compared pairs of rectangles. The system further includes fifth program instructions to adjusting coordinates of each rectangle from the first technology based on the selected overall shift in the “y” direction. The system further includes sixth program instructions to calculate a mapping cost for each rectangle from the first technology to each rectangle of the second technology using the adjusted coordinates of each rectangle from the first technology. The system further includes seventh program instructions to map each rectangle from the first technology to a rectangle from the second technology such that the mapped rectangles comprise a lowest calculated mapping cost. The first through seventh program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.
- The present invention is described in the detailed description, which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
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FIGS. 1-3 show examples of pin mismatches that may occur during technology migration; -
FIG. 4 is an illustrative external environment for implementing the invention in accordance with aspects of the invention; -
FIGS. 5 and 6 are flow diagrams of processes in accordance with aspects of the invention; -
FIGS. 7 and 8 show examples of calculating mapping costs between two different layouts or technologies in accordance with aspects of the invention; and -
FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test. - The invention relates to circuit design and, more particularly, to systems and methods for fixing pin mismatches from swapping library cells in layout migration. More specifically, implementations of the invention provide a system and method to collect pin information for library cells in a first technology, collect pin information for library cells in a second technology, build a pin-mapping table from the collected pin information between the first technology and the second technology, scale the integrated circuit layout with respect to the second technology, and modify the pins in the second technology based on the pin-mapping table.
- In embodiments, geometric relationships are defined on the layout of the integrated circuit utilizing the first technology. The defined geometric relationships accurately capture the wire connections with respect to the pins of the library cells for the first technology. Subsequently, the pins of the library cells are modified to match pin shapes and locations within the layout of the integrated circuit utilizing the second technology. During the layout migration geometric constraints and linear program (LP) solving may modify the interconnect wires to connect the pins with respect to the library cell of the second technology. Advantageously, the systems and methods of the present invention use the original topography of the first technology to reconnect the pins in the second technology.
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FIGS. 1-3 show multiple examples of pin mismatches that may occur between library cells of a first technology and library cells of a second technology. The pin mismatches may be caused by location, dimension, and/or topography changes introduced to the pins during the scaling and/or layout migration from the first technology to the second technology. For example,FIG. 1 shows alibrary cell 5, e.g., a local clock buffer, designed using a first technology, e.g., 32 nm technology. Thelibrary cell 5 comprisesmultiple pins 15 for connecting the devices of thelibrary cell 5 to interconnect wiring and or other devices of an integrated circuit.FIG. 1 also shows acorresponding library cell 10 designed using the second technology, e.g., 22 nm technology. As can be seen betweenlibrary cells pin 20 has changed location and dimension due to the scaling and/or layout migration of the library cell between the first technology and the second technology. This change in the location and the dimension ofpin 20 between the first technology and the second technology may cause a misalignment of interconnect wiring if the changes in the location and the dimension ofpin 20 are not accounted for during the layout design phase for the second technology. -
FIG. 2 shows alibrary cell 25, e.g., a local clock buffer, designed using a first technology, e.g., 32 nm technology. Thelibrary cell 25 comprisesmultiple pins 30 for connecting the devices of thelibrary cell 25 to interconnect wiring and/or devices of the integrated circuit.FIG. 2 also shows acorresponding library cell 35 designed using the second technology, e.g., 22 nm. As can be seen betweenlibrary cells pin 40 has changed location and thepin 45 has changed location and topology due to the scaling and/or layout migration of the library cell between the first technology and the second technology. These changes in the location ofpin 40 and the location and the topology ofpin 45 between the first technology and the second technology may cause a misalignment of interconnect wiring if the changes are not accounted for during the layout design phase for the second technology. -
FIG. 3 shows alibrary cell 50, e.g., a logic cell, designed using a first technology, e.g., 32 nm technology. Thelibrary cell 50 comprisesmultiple pins 55 for connecting the devices of thelibrary cell 50 to interconnect wiring and/or devices of the integrated circuit.FIG. 3 also shows a correspondinglibrary cell 60 designed using the second technology, e.g., 22 nm. As can be seen betweenlibrary cells pin 65 has changed location and topology due to the scaling and/or layout migration of the library cell between the first technology and the second technology. These changes in the location and the topology ofpin 65 between the first technology and the second technology may cause a misalignment of interconnect wiring if the changes in the location and the topology ofpin 65 are not accounted for during the layout design phase for the second technology. - Implementations of the present invention can fix the pin mismatches shown in
FIGS. 1-3 . As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. - Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
- Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
- Computer program instructions may also be stored in the computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
- The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
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FIG. 4 shows anillustrative environment 100 for managing the processes in accordance with the invention. To this extent, theenvironment 100 includes a server orother computing system 112 that can perform the processes described herein. In particular, theserver 112 includes acomputing device 114. Thecomputing device 114 can be resident on a network infrastructure or computing device of a third party service provider (any of which is generally represented inFIG. 4 ). - The
computing device 114 also includes aprocessor 120,memory 122A, an I/0interface 124, and abus 126. Thememory 122A can include local memory employed during actual execution of program code, bulk storage, and cache memories, which provide temporary storage of at least some program code, in order to reduce the number of times code should be retrieved from bulk storage during execution. In addition, the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S). - The
computing device 114 is in communication with the external I/O device/resource 128 and thestorage system 122B. For example, the I/O device 128 can comprise any device that enables an individual to interact with the computing device 114 (e.g., user interface) or any device that enables thecomputing device 114 to communicate with one or more other computing devices using any type of communications link. The external I/O device/resource 128 may be for example, a handheld device, PDA, handset, keyboard, etc. - In general, the
processor 120 executes computer program code (e.g., program control 144), which can be stored in thememory 122A and/orstorage system 122B. Moreover, in accordance with aspects of the invention, theprogram control 144 controls an electronic design automation (EDA)tool 150 to perform the processes described herein. TheEDA tool 150 can be implemented as one or more program code in theprogram control 144 stored inmemory 122A as separate or combined modules. Additionally, theEDA tool 150 may be implemented as a separate dedicated processor or several processors to provide the function of this tool. While executing the computer program code, theprocessor 120 can read and/or write data to/frommemory 122A,storage system 122B, and/or I/O interface 124. The program code executes the processes of the invention. Thebus 126 provides a communications link between each of the components in thecomputing device 114. - In embodiments, the
EDA tool 150 can fix pin mismatches caused from swapping library cells during a layout migration. For example, in accordance with aspects of the invention, theEDA tool 150 can collect pin information for library cells in a first technology, collect pin information for library cells in a second technology, build a pin-mapping table from the collected pin information between the first technology and the second technology, scale the integrated circuit layout with respect to the second technology, and modify the pins in the second technology based on the pin-mapping table. -
FIGS. 5 and 6 show exemplary flows for performing aspects of the present invention. The steps ofFIGS. 5 and 6 may be implemented to solve the problem of pin mismatches between different technologies during layout migration. The flowcharts and block diagrams inFIGS. 5 and 6 illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. -
FIG. 5 depicts anexemplary flow 500 for a layout migration of library cells from a first technology to a second technology. Atstep 505, an input comprising a netlist or other formatted listing of components and/or circuits and their positions in a first layout (e.g., a first technology layout or an old layout) and ground rules of the second technology is provided. Atstep 510, pin information for library cells in the netlist of the first layout are collected. In embodiments, the pin information includes the name of each pin and the rectangle in a given pin layer that represents each pin. The rectangles are then sorted in a pin-list. In embodiments, the rectangles for each of the pins may be sorted in the pin-list based on a center point of each rectangle, and the sorting criteria can be either from left to right (i.e., non-descending order of the “x” coordinate of the center points), or from bottom to top (i.e., non-descending order of the “y” coordinate of the center points), or the non-descending order of the summation of “x” and “y” coordinates of the center points. - At
step 515, the library cells of the first layout are converted in an initial pass to a second layout (e.g., a second technology layout or a new layout). In embodiments, this is performed by swapping of library cells of the second technology to convert the library cells of the first layout to the second layout. Atstep 520, pin information for library cells in the second layout is collected. In embodiments, the pin information includes the name of each pin, e.g., two matching pins between the library cell in the first layout and its swapped cell in the second layout may have a same name, and the rectangles in a given pin layer that represent each pin. The rectangles are then sorted in a pin-list, as described above with respect to the first layout. - At
step 525, a pin-mapping table is built to map the pins in library cells of the first layout to pins in library cells of the second layout. In embodiments, the number of rectangles for each pin may be different between the library cells of first technology and the library cells of the second technology because of shifts in topology between corresponding library cells. For example, the number of rectangles for each library cell of the first technology may increase, decrease, or remain equal as compared to each corresponding library cell of the second technology. - In embodiments, the rectangles in the first layout are mapped to the rectangles in the second layout based on a mapping cost, e.g., a minimum mapping cost, while taking into consideration an overall shift A in the “y” direction with respect to the gates of each library cell, as discussed in further detail below with respect to
FIG. 6 . The overall shift A in the “y” direction may be caused by library cell growth during the scaling process instep 515. Advantageously, using the mapping cost and the overall shift A in the “y” direction provides an efficient and effective approach to mapping the pins between the two layouts. - At
step 530, all the shapes are deleted except for the pins and representative boundary box of the library cell such that only the pins and the representative boundary box are visible in subsequent steps. Atstep 535, geometric relationships are built for the first layout. In embodiments, a geometry database may be built that provides geometrical relationship information regarding elements (e.g., tiles or rectangles) of the first layout. For example, an integrated circuit is generally composed of multiple layers, and each layer typically includes a collection of shapes (e.g., tiles or rectangles). The shapes may be wires on a routing layer or may be active regions in a diffusion area. On a given layer, two shapes generally overlap one another only if those two shapes are electrically connected. The function of the geometric database is to create an appropriate data structure for each collection of shapes. Advantageously the geometric database allows the wire connections to be captured correctly with respect to the pins of the library cells in the first layout. - At
step 540, all components in the first layout are scaled with respect to the second layout using a predetermined scaling factor. Now the pin-mapping table generated instep 525 is used to modify the pins from the first layout to match the pin shapes and locations in the second layout. - At
step 545, hierarchical constraints are generated in mathematical form. In embodiments, the first layout and the ground rule files of the second technology are used to define hierarchical constraints of the first layout in mathematical form. Typical ground rules may include spacing rules specifying minimum space between objects, width rules specifying minimum width of some objects, and methodology rules specifying design requirements for assembling library cells. The ground rules ensure manufacturability of the integrated circuit. - At
step 550, an LP problem is generated and solved, and the first layout is modified based on the LP problem. Generating and solving LP problems is a mathematical method for determining a way to achieve a best outcome (e.g., an integrated circuit running with a specified speed or delay) in a given mathematical model for some list of requirements represented as linear relationships. In embodiments, generating the LP problem may comprise building the hierarchical constraints in the form of an initial inequality expression and then deriving the LP problem from the inequality expression by relaxing integer constraints and using relaxation variables on infeasible constraints. As used herein, relaxing integer constraints means that certain constraints are not applied and infeasible constraints means constraints that are not satisfied for the given layout. - The LP problem is then solved to obtain an LP solution. For example, the LP problem may be solved by using traditional LP solvers, e.g., interior-point methods or simplex algorithms. Once the LP problem is solved, then a modified first layout is outputted. The modified first layout meets the ground rules and is optimal in terms of predetermined objectives for the second layout.
- At
step 555, the library cells of the first layout are replaced with the corresponding library cells of the second technology. In embodiments, each library cell in the first layout is swapped with a new library cell from the second technology. The library cells of the first layout are removed from the layout and the new library cells are placed in the layout to generate the second layout. The new library cells are placed in the layout with same coordinates, orientation, and magnification. Once the new library cells are in position in the layout, the pins are automatically connected to the external wires, as the hierarchical constraints and the LP problem solving instep 550 are configured to modify the wires to connect to the new locations of the modified pins with respect to the library cells in the new layout. Therefore, the library cell swapping is no longer disruptive to reconnecting the wires to the pins. The swapping of the library cells results in achievement of the second layout for the integrated circuit atstep 560. -
FIG. 6 depicts anexemplary flow 600 for building a pin-mapping table that takes into consideration a minimum mapping cost and an overall shift A in the “y” direction. Atstep 605, the rectangles from the pin-list generated for the first layout at step 510 (as discussed above with respect toFIG. 5 ) are paired with the rectangles or a set of rectangles in the pin-list generated for the second layout at step 520 (as discussed above with respect toFIG. 5 ). In embodiments, the rectangles are compared according to the order in which the rectangles are sorted within each pin-list, e.g., based on a center point of each rectangle or set of rectangles. Atstep 610, the shift Δ in the “y” direction for all pairs of rectangles is computed or calculated. The shift Δ in the “y” direction may be caused by library cell growth during the scaling process in step 515 (as discussed above with respect toFIG. 5 ). In embodiments, the shift Δ in the “y” direction for each pair of rectangles may be calculated using equation (1) with respect to the gate(s) of each library cell. -
Δ in y=(center Y location of n 1 rectangle of pin-list for second layout)−(center Y location of n 1 rectangle of pin-list for first layout)*the scaling factor (1) - At
step 615, the calculated shifts Δ in the “y” direction for each pair of rectangles are then compared, and the calculated shift Δ with the minimum absolute value is selected as the overall shift Δ in the “y” direction. Atstep 620, the position or coordinates of the rectangles from the pin-list generated for the first layout are adjusted based on the scaling factor and the selected overall shift Δ using equation (2). -
(center Y location of n 1 rectangle of pin-list for first layout)*the scaling factor+overall shift Δ in y (2) - At
step 625, the mapping costs are computed or calculated for each rectangle in the first layout to each rectangle in the second layout. The mapping cost is defined as the amount of minimum movement (e.g., movement in a two dimensional space) that it would take to place a rectangle from the first layout (in embodiments the position of the rectangle being the adjusted position calculated based on equation (2)) over a new rectangle from the second layout. In embodiments, the mapping cost may be calculated as a cost in the “x” direction plus a cost in the “y” direction. In accordance with aspects of the invention, the two dimensions can be treated as independent of one another. - The rectangle (e.g., a first layout rectangle) may be expressed as (r1: xl1, yl1. xh1, yh1), where xl1 is the “x” coordinate or position of the left bottom corner of the rectangle, yl1 is the “y” coordinate or position of the left bottom corner of the rectangle, xh1 is the “x” coordinate or position of the top right corner of the rectangle, and yh1 is the “y” coordinate or position of the top right corner of the rectangle. The new rectangle (e.g., a second layout rectangle) may be expressed as (r2: xl2, yl2−xh2, yh2), where xl2 is the “x” coordinate or position of the left bottom corner of the new rectangle, yl2 is the “y” coordinate or position of the left bottom corner of the new rectangle, xh2 is the “x” coordinate or position of the top right corner of the new rectangle, and yh2 is the “y” coordinate or position of the top right corner of the new rectangle.
- In embodiments, the cost in the “x” direction may be calculated using equation (3). Assuming the coordinates or position of the rectangle (e.g., a first layout rectangle) is already adjusted (e.g., adjusted with respect to the scaling factors) based on equation (2).
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If (xl2−xl1) and (xh2+xh1) have the same sign (+/−), then Cost=max(|xl2−xl1|,|xh2+xh1|), else Cost=|xl2−xl1|+|xh2+xh1| where |a−b| denotes the absolute value of (a−b). (3) - In embodiments, the cost in the “y” direction may be calculated using equation (4). Assuming the coordinates or position of the rectangle (e.g., a first layout rectangle) is already adjusted (e.g., adjusted with respect to the scaling factors) based on equation (2).
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If (yl2−yl1) and (yh2+yh1) have the same sign (+/−), then Cost=max (|yl2−yl1|,|yh2+yh1|), else Cost=|yl2−yl1|+|yh2+yh1| where |a−b| denotes the absolute value of (a−b). (4) - In embodiments, the calculated cost in the “x” direction from equation (3) may then be added to the calculated cost in the “y” direction from equation (4) to calculate the mapping cost.
- At
step 630, each rectangle in the pin-list for the first layout is mapped to each rectangle in the pin-list for the second layout based on calculated mapping costs while taking into consideration the calculated overall shift Δ in the “y” direction. For example, the pair of rectangles with the minimum mapping cost may be mapped together. Atstep 635, the mappings for each rectangle are added to a mapping table. - For example, as shown in
FIG. 7 , therectangle 700 from the pin-list generated for thefirst layout 705 is paired with a set ofrectangles 710 from the pin-list generated for thesecond layout 715. The shift Δ 720 in the “y” direction for each pair of rectangles is calculated using equation (1). The calculated shifts Δ in the “y” direction for each pair of rectangles are then compared, and the calculated shift Δ with the minimum absolute value is selected as the overall shift Δ 725 in the “y” direction. The mapping location or coordinates of therectangle 700 is then adjusted based on the scaling factor and the overall shift Δ 725 using equation (2). - The mapping cost from adjusted location of
rectangle 700 to each rectangle in the set ofrectangles 710 is then calculated using equations (3) and (4). For example, the mapping cost of moving therectangle 700 from the adjusted position of (468,3897♦892,3952) to the position of (420,3880♦480,3970) for therectangle 730 is calculated as 447, the mapping cost of moving therectangle 700 from the adjusted position of (468,3897♦892,3952) to the position of (420,3820♦880,3880) for therectangle 735 is calculated as 125, and the mapping cost of moving therectangle 700 from the adjusted position of (468,3897♦892,3952) to the position of (420,3970♦880,4030) for therectangle 740 is calculated as 126. - The
rectangle 700 is then mapped 745 to therectangle 735 based on the mapping cost calculated for each pair of rectangles while taking into consideration the calculated overall shift Δ in the “y” direction. For example, the lowest calculated mapping cost may be used to identify thecorresponding rectangle 735 in the set ofrectangles 710 that corresponds with therectangle 700. Themapping 745 forrectangles - By way of additional example, as shown in
FIG. 8 , a set ofrectangles 800 from the pin-list generated for thefirst layout 805 are paired with a set ofrectangles 810 from the pin-list generated for thesecond layout 815. Theshift Δ 820 in the “y” direction for each pair of rectangles is calculated using equation (1). The calculated shifts Δ in the “y” direction for each pair of rectangles are then compared, and the calculated shift Δ with the minimum absolute value is selected as theoverall shift Δ 825 in the “y” direction. The mapping location or coordinates of each rectangle in the set ofrectangles 800 is then adjusted based on the scaling factor and theoverall shift Δ 825 using equation (2). For example, the mapping location or coordinates ofrectangle 827 are adjusted based on the scaling factor and theoverall shift Δ 825 using equation (2). - The mapping cost from each rectangle in the set of
rectangles 800 to each rectangle in the set ofrectangles 810 is then calculated using equations (3) and (4). For example, the mapping cost of moving therectangle 827 from the adjusted position of (200,3822♦412,3878) to the position of (270,3820♦420,3880) for therectangle 830 is calculated as 74. - The
rectangle 827 is then mapped 835 to therectangle 830 from the set ofrectangles 810 based on the mapping cost calculated for each pair of rectangles while taking into consideration the calculated overall shift Δ in the “y” direction. For example, the lowest calculated mapping cost may be used to identify thecorresponding rectangle 830 in the set ofrectangles 810 that corresponds with therectangle 827. Themapping 835 forrectangles -
FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test used with the system and method of the present invention.FIG. 9 shows a block diagram of anexemplary design flow 900 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture.Design flow 900 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices. The design structures processed and/or generated bydesign flow 900 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array). -
Design flow 900 may vary depending on the type of representation being designed. For example, adesign flow 900 for building an application specific IC (ASIC) may differ from adesign flow 900 for designing a standard component or from adesign flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc. -
FIG. 9 illustrates multiple such design structures including aninput design structure 920 that is preferably processed by adesign process 910.Design structure 920 may be a logical simulation design structure generated and processed bydesign process 910 to produce a logically equivalent functional representation of a hardware device.Design structure 920 may also or alternatively comprise data and/or program instructions that when processed bydesign process 910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features,design structure 920 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium,design structure 920 may be accessed and processed by one or more hardware and/or software modules withindesign process 910 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system, which can be implemented with the method and system of the present invention. As such,design structure 920 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. -
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures to generate anetlist 980 which may contain design structures such asdesign structure 920.Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design.Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein,netlist 980 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means. -
Design process 910 may include hardware and software modules for processing a variety of input data structuretypes including netlist 980. Such data structure types may reside, for example, withinlibrary elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further includedesign specifications 940,characterization data 950,verification data 960,design rules 970, and test data files 985 that may include input test patterns, output test results, and other testing information.Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used indesign process 910 without deviating from the scope and spirit of the invention.Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. -
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to processdesign structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate asecond design structure 990. -
Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to designstructure 920,design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more devices. In one embodiment,design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates the devices. -
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure.Design structure 990 may then proceed to astage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
If (xl2−xl1) and (xh2+xh1) have the same sign (+/−), then Cost=max (|xl2−xl1|,|xh2+xh1|), else Cost=|xl2−xl1|+|xh2+xh1|
If (yl2−yl1) and (yh2+yh1) have the same sign (+/−), then Cost=max (|yl2−yl1|,|yh2+yh1|), else Cost=|yl2−yl1|+|yh2+yh1|
the shift in the “y” direction=(a center Y location of a n 1 rectangle for the second technology)−(a center Y location of a n 1 rectangle for first technology)*a scaling factor between the first technology and the second technology.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150067616A1 (en) * | 2013-08-28 | 2015-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell layout design and method |
US20160092627A1 (en) * | 2014-09-26 | 2016-03-31 | Synopsys, Inc. | Method for organizing, controlling, and reporting on design mismatch information in ic physical design data |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9064081B1 (en) * | 2013-12-11 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Generating database for cells routable in pin layer |
US9697310B2 (en) * | 2015-11-02 | 2017-07-04 | Winbond Electronics Corporation | Level faults interception in integrated circuits |
CN113011122A (en) | 2019-12-19 | 2021-06-22 | 台湾积体电路制造股份有限公司 | Method and system for reducing migration errors |
CN116090392B (en) * | 2023-03-01 | 2023-12-26 | 上海合见工业软件集团有限公司 | gDS file-based pin physical attribute matching method and system |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6189132B1 (en) | 1998-04-09 | 2001-02-13 | International Business Machines Corporation | Design rule correction system and method |
US6473885B1 (en) * | 1998-07-17 | 2002-10-29 | Mentor Graphics Corporation | Digital circuit layout techniques using circuit decomposition and pin swapping |
US6360352B2 (en) * | 1998-07-17 | 2002-03-19 | David E. Wallace | Digital circuit layout techniques |
GB9914380D0 (en) * | 1999-06-21 | 1999-08-18 | Regan Timothy J | Method of scaling an integrated circuit |
GB9929084D0 (en) | 1999-12-08 | 2000-02-02 | Regan Timothy J | Modification of integrated circuits |
US6986109B2 (en) | 2003-05-15 | 2006-01-10 | International Business Machines Corporation | Practical method for hierarchical-preserving layout optimization of integrated circuit layout |
US7111269B2 (en) | 2003-10-23 | 2006-09-19 | Lsi Logic Corporation | Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout |
US7363601B2 (en) * | 2004-10-15 | 2008-04-22 | International Business Machines Corporation | Integrated circuit selective scaling |
US7730433B2 (en) | 2005-09-29 | 2010-06-01 | Sherif Ahmed Abdel-Wahab Hammouda | Analog design retargeting |
JP2008084205A (en) * | 2006-09-28 | 2008-04-10 | Fujitsu Ltd | Cad data processing program |
US7774735B1 (en) | 2007-03-07 | 2010-08-10 | Cadence Design Systems, Inc | Integrated circuit netlist migration |
US7783995B2 (en) | 2007-03-08 | 2010-08-24 | International Business Machines Corporation | System and method for circuit design scaling |
US7568173B2 (en) | 2007-06-14 | 2009-07-28 | International Business Machines Corporation | Independent migration of hierarchical designs with methods of finding and fixing opens during migration |
US20100205573A1 (en) | 2007-07-06 | 2010-08-12 | Sagantiec Israel Ltd. | Layout modification engine for modifying a circuit layout comprising fixed and free layout entities |
US8543958B2 (en) | 2009-12-11 | 2013-09-24 | Synopsys, Inc. | Optical proximity correction aware integrated circuit design optimization |
US8745554B2 (en) * | 2009-12-28 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Practical approach to layout migration |
-
2012
- 2012-07-11 US US13/546,562 patent/US8627247B1/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150067616A1 (en) * | 2013-08-28 | 2015-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell layout design and method |
US9087170B2 (en) * | 2013-08-28 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell layout design and method |
US20160092627A1 (en) * | 2014-09-26 | 2016-03-31 | Synopsys, Inc. | Method for organizing, controlling, and reporting on design mismatch information in ic physical design data |
US10339259B2 (en) * | 2014-09-26 | 2019-07-02 | Synopsys, Inc. | Method for organizing, controlling, and reporting on design mismatch information in IC physical design data |
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