WO2023106268A1 - 紫外発光素子及びその製造方法 - Google Patents
紫外発光素子及びその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000000903 blocking effect Effects 0.000 claims abstract description 95
- 238000005253 cladding Methods 0.000 claims abstract description 78
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
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- 230000008569 process Effects 0.000 description 7
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- 150000004767 nitrides Chemical class 0.000 description 4
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 4
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
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- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
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- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
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- 230000001771 impaired effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Definitions
- the present invention relates to an ultraviolet light emitting device and a manufacturing method thereof.
- a light-emitting element mainly composed of aluminum gallium nitride (AlGaN) can emit light of about 250 to 360 nm.
- Ultraviolet light emitting elements having emission center wavelengths of UVC ( ⁇ 280 nm) and UVB (280 to 320 nm) are sometimes used for sterilization and the like, so development of deep ultraviolet light emitting elements in these wavelength ranges is particularly active.
- Patent Document 1 describes a light-emitting element that emits deep ultraviolet light of 240 to 320 nm.
- the electron block layer preferably has a thickness of 1 to 10 nm
- the p-type clad layer preferably has a thickness of 10 to 100 nm
- the p-type contact layer has a thickness of more than 500 nm. It also describes that the flatness of the p-type contact layer can be improved by increasing the thickness of the p-type contact layer.
- Patent Document 2 describes a nitride semiconductor ultraviolet light emitting device. In this light-emitting device, it is described that output is improved when the surface of the active layer is rough enough to have an average roughness equal to or greater than the thickness of the well layer. Also, the electron block layer is 15 to 30 nm, the p-type cladding layer is 500 to 600 nm, and the p-type contact layer is 100 to 300 nm.
- Patent Document 3 describes an ultraviolet light emitting device and a method for manufacturing the same.
- the electron blocking layer when the wavelength is shorter than 350 nm, has a thickness of 1 to 50 nm and an Al composition of 50% or more.
- UVA ultraviolet light emitting device
- UVA ultraviolet light emitting device suitable for UVA.
- UVA ultraviolet light-emitting device capable of obtaining a large light emission output with an emission center wavelength of more than 330 nm and less than 350 nm.
- the present invention has been made in view of such circumstances, and an object of the present invention is to provide an ultraviolet light emitting device capable of obtaining a large emission output at a central emission wavelength of more than 320 nm and less than 350 nm, particularly more than 330 nm and less than 350 nm, and a method for producing the same. to provide.
- the ultraviolet light emitting device for achieving the above objects is as follows.
- a p-type cladding layer made of AlzGa1 -zN having an Al composition ratio z and a p-type GaN contact layer are provided in this order,
- the p-type electron blocking layer is
- the Al composition ratio y is 0.35 or more and 0.45 or less,
- the thickness is 11 nm or more and 70 nm or less,
- the total thickness of the p-type electron blocking layer and the p-type cladding layer is 73 nm or more and 100 nm or less
- the ultraviolet light emitting device, wherein the p-type GaN contact layer has a thickness of 5 nm or more and 15 nm or less.
- the surface of the p-type GaN contact layer is The maximum surface roughness is 9 nm or less
- the ultraviolet light emitting device according to (1) which has an average surface roughness of 1 nm or less.
- the ultraviolet light emitting device according to any one of (1) to (4), wherein the surface of the n-type semiconductor layer has an average surface roughness of 1 nm or less.
- the ultraviolet light emitting device according to any one of (1) to (5), wherein the (10-12) plane of the n-type semiconductor layer has a half width of 350 seconds or less in X-ray diffraction.
- the n-type semiconductor layer is The Al composition ratio x is 0.2 or more and 0.35 or less
- the ultraviolet light emitting device according to any one of (1) to (6), wherein the Al composition ratio z of the p-type cladding layer is equal to or less than the Al composition ratio x of the n-type semiconductor layer.
- the ultraviolet light emitting device according to any one of (1) to (8), which has an emission central wavelength of 331 nm or more and 349 nm or less.
- the manufacturing method of the ultraviolet light emitting element which concerns on this invention for achieving the said objective is as follows. (10) an n-type semiconductor layer forming step of forming an n-type semiconductor layer composed of Al x Ga 1-x N having an Al composition ratio x; A light-emitting layer forming step for forming a quantum well-type light-emitting layer, a p-type electron blocking layer forming step of forming a p-type electron blocking layer made of Al y Ga 1-y N having an Al composition ratio y; a p-type clad layer forming step of forming a p-type clad layer made of Al z Ga 1-z N having an Al composition ratio z; including a p-type GaN contact layer forming step of forming a p-type GaN contact layer; performing the n-type semiconductor layer forming step, the light emitting layer forming step, the p-type electron blocking layer forming step, the p-type cladding layer forming step, and the p
- the p-type GaN contact layer forming step includes: The maximum surface roughness of the surface of the p-type GaN contact layer is 9 nm or less, The method for producing an ultraviolet light emitting device according to (10), wherein the p-type GaN contact layer has an average surface roughness of 1 nm or less. (12) The method for manufacturing an ultraviolet light emitting device according to (9) or (10), further including a p-side electrode forming step of forming a p-side electrode on the p-type GaN contact layer.
- an ultraviolet light-emitting element capable of obtaining a large emission output with an emission center wavelength of more than 320 nm and less than 350 nm, particularly more than 330 nm and less than 350 nm, and a method of manufacturing the same.
- FIG. 3 is a diagram showing respective thicknesses in Examples and Comparative Examples, with the vertical axis representing the thickness of the p-type cladding layer and the horizontal axis representing the thickness of the p-type electron blocking layer.
- the history of the development of the ultraviolet light emitting device according to the embodiment of the present invention will be described.
- the thicker the electron blocking layer or cladding layer that transmits light the more light is extracted and the higher the output is.
- the Al composition ratio and thickness of the block layer are set within a specific range, and the combination of the thicknesses of the p-type electron block layer and the p-type cladding layer is set within a specific range, based on knowledge of the prior art, Contrary to the expectation, the inventors have found that the output of the ultraviolet light emitting device is improved.
- the thickness of these p-type layers can be easily controlled, the variation between lots can be reduced, and the light emission output can be increased within the wafer plane compared to thick p-type layers. It was found that the yield was stably improved. Then, when the Al composition ratio and thickness of the p-type electron blocking layer are set within a specific range, and the combination of the thicknesses of the p-type electron blocking layer and the p-type cladding layer is set within a specific range, p It has been found that even if the thickness of the type contact layer is thin, the flatness of the surface of the p-type contact layer forming the electrode can be ensured.
- FIG. 1 shows an ultraviolet light emitting device 100 (hereinafter referred to as the light emitting device 100) according to this embodiment.
- the light-emitting device 100 includes an AlN layer 11, a buffer layer 2, an n-type semiconductor layer 3 made of AlxGa1 -xN having an Al composition ratio x, an n-type guide layer 31, and a quantum well light-emitting layer on a substrate 1. 4 (hereinafter referred to as a light-emitting layer 4), an i-type guide layer 5, a p-type electron blocking layer 6 made of Al y Ga 1-y N having an Al composition ratio y, and Al z Ga 1 having an Al composition ratio z.
- a p-type cladding layer 7 made of -zN and a p-type GaN contact layer 8 (hereinafter referred to as contact layer 8) are provided in this order.
- contact layer 8 a p-type GaN contact layer 8
- the thicknesses of the respective layers of the light-emitting element 100 shown in FIG. 1 are shown by changing the ratio of the thicknesses of the respective layers on the drawing for convenience of explanation.
- the thickness ratio of each layer on the drawing shown in FIG. 1 differs from the actual thickness ratio of each layer in the light emitting device 100 .
- the light-emitting device 100 includes a p-side electrode 91 (as a reflective electrode) on the surface of the contact layer 8 opposite to the surface facing the p-type cladding layer 7 .
- an n-side electrode 92 is provided on the same surface as the light emitting layer 4 .
- the emission center wavelength suitable for the light emitting device 100 is 331 nm or more and 349 nm or less.
- the light emitting device 100 can be manufactured, for example, by the following manufacturing method. That is, an example of the method for manufacturing the light emitting device 100 includes an n-type semiconductor layer forming step for forming the n-type semiconductor layer 3, a light emitting layer forming step for forming the light emitting layer 4, a p-type electron blocking layer 6 for forming the p-type electron blocking layer 6, and a A block layer forming step, a p-type cladding layer forming step for forming the p-type cladding layer 7, and a p-type GaN contact layer forming step for forming the contact layer 8 are included.
- the n-type semiconductor layer forming step, the light emitting layer forming step, the p-type electron blocking layer forming step, the p-type cladding layer forming step, and the p-type GaN contact layer forming step are performed in this order.
- the Al composition ratio y is set to 0.35 to 0.45
- the thickness of the p-type electron blocking layer 6 is set to 11 nm to 70 nm
- the p-type electron blocking layer forming step and the p-type In the cladding layer forming step the total thickness of the p-type electron blocking layer 6 and the p-type cladding layer 7 is 73 nm or more and 100 nm or less.
- the thickness of each layer of the light emitting device 100 is measured based on an image taken with a TEM-EDS (transmission electron microscope). That is, as the thickness of each layer, the average value of the thickness of each layer in the cross-sectional image of the light emitting element 100 is used.
- the thickness of the substrate a value measured by an SEM (scanning electron microscope) is used.
- AlGaN in this embodiment means Al ⁇ Ga 1- ⁇ N, where ⁇ is the Al composition ratio.
- the value of the Al composition ratio ⁇ of AlGaN in this embodiment is specified from the wavelength observed by photoluminescence measurement performed on the surface of each layer when growing each layer.
- the Al composition ratio ⁇ is in the range of 0 or more and 1 or less unless otherwise specified.
- EDS Electronic Dispersive X-ray Spectroscopy
- GaN and AlN in this embodiment mean that the composition ratio of Ga and Al is 1.0, respectively.
- GaN, AlN, and AlGaN are allowed if the composition ratio of other group III elements not listed including indium is 0.04 or less (4% or less in mole fraction).
- the value of the surface roughness in this embodiment is obtained by performing AFM (atomic force microscope) measurement on a rectangular area of 5 ⁇ m ⁇ 5 ⁇ m.
- the average arithmetic roughness (Ra) and the maximum surface roughness (Rmax) are determined according to JIS (B0601-2001) based on the surface profile obtained by AFM measurement.
- the average arithmetic roughness (Ra) and the maximum surface roughness (Rmax) may be obtained by automatic calculation by application software attached to the AFM device.
- the evaluation of crystallinity in this embodiment is the value of the half width (arcsec) of the X-ray rocking curve obtained by an X-ray diffractometer.
- the half-value width may be obtained by automatic calculation using application software attached to the X-ray diffraction device.
- the (0001) plane and the (10-12) plane to be evaluated are each irradiated with X-rays to evaluate their diffraction profiles.
- the measurement result on the (10-12) plane is an index of the threading dislocation density (mixed spiral and edge dislocations) in the crystal.
- a known substrate capable of epitaxially growing group III nitrides can be used.
- a sapphire substrate, AlN substrate, GaN substrate, SiC substrate, etc. can be used.
- the case where the substrate 1 is a sapphire substrate will be described below as an example.
- the AlN layer 11 is formed on the substrate 1, and the (10-12) plane of the AlN layer 11 is formed by heat-treating the AlN layer 11 at a high temperature. It is more preferable to use an AlN template substrate in which dislocations are reduced to 400 seconds or less in the half width of the X-ray rocking curve.
- the substrate 1 having the AlN layer 11 formed thereon will be referred to as an AlN template substrate.
- a buffer layer 2 is formed on the AlN template substrate.
- the buffer layer 2 is located between the AlN layer 11 on the substrate 1 and the n-type semiconductor layer 3, and is a layer that relaxes the lattice constant difference between the substrate 1 and the AlN layer 11 and the n-type semiconductor layer 3.
- the buffer layer 2 is preferably composed of a layer in which a plurality of AlGaN layers having different Al compositions are laminated, or an Al composition gradient layer.
- the buffer layer 2 is preferably undoped.
- the thickness of the buffer layer 2 is preferably, for example, 500 nm or more and 2000 nm or less.
- the buffer layer 2 is a layer in which a first buffer layer 21 and a second buffer layer 22, which are AlGaN layers with different Al compositions, are laminated.
- the n-type semiconductor layer 3 is a layer that functions as an n-type semiconductor by containing an n-type dopant such as Si in Al x Ga 1-x N having an Al composition ratio x.
- the concentration of the n-type dopant is preferably about 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 .
- the n-type semiconductor layer 3 is formed on the surface of the buffer layer 2 opposite to the surface facing the AlN template substrate (an example of the n-type semiconductor layer forming process).
- the average surface roughness (Ra) of the surface of the n-type semiconductor layer 3 in the 5 ⁇ m square range is preferably 1 nm or less. Since the surface of the n-type semiconductor layer 3 is flat, the layers grown thereon can also maintain flatness.
- the half width of the (10-12) plane of the n-type semiconductor layer 3 in X-ray diffraction is preferably 350 seconds or less, more preferably 300 seconds or less.
- the Al composition ratio x of the n-type semiconductor layer 3 is preferably 0.2 or more and 0.35 or less.
- the Al composition ratio x is larger than the Al composition ratio w of the well layer 41 described later, and w ⁇ x.
- the thickness of the n-type semiconductor layer 3 may be sufficient to supply carriers, and is preferably, for example, 300 nm or more and 3000 nm or less.
- an n-side electrode 92 is formed on part of the exposed n-type semiconductor layer 3 .
- an AlGaN layer having an Al composition lower than that of the n-type semiconductor layer 3 and having an Al composition of 0 or more and 0.2 or less may be provided between the n-type semiconductor layer 3 and the n-side electrode 92. good.
- AlGaN having the same Al composition ratio as that of the n-type semiconductor layer 3 contains an n-type dopant such as Si, and functions as an n-type semiconductor.
- a thinner n-type guide layer 31 may be formed.
- the light emitting layer 4 is a layer including a layer made of AlGaN.
- the light-emitting layer 4 has a plurality of well layers 41 and a plurality of barrier layers 42 (barrier layers), which are alternately laminated. That is, the light-emitting layer 4 has a well layer 41 having an Al composition ratio corresponding to the central wavelength of light emission, and barrier layers 42 sandwiching the well layers 41, 41.
- a combination of the well layer 41 and the barrier layer 42 is one pair It has a configuration that repeats the above. Both sides of the light-emitting layer 4 are barrier layers 42 .
- the light-emitting layer 4 is formed on the surface of the n-type semiconductor layer 3 opposite to the surface facing the AlN template substrate (an example of the light-emitting layer forming process). .
- the well layer 41 of this embodiment is a layer made of AlwGa1 -wN having an Al composition ratio w.
- the Al composition ratio w is preferably w ⁇ 0.3 when the emission center wavelength exceeds 320 nm, for example. Further, when the emission center wavelength is 331 nm or more, it is preferable to satisfy w ⁇ 0.15. Further, when the emission center wavelength is 349 nm or less, it is preferable to satisfy 0.07 ⁇ w.
- the thickness of the well layer 41 is preferably 1 nm or more and 5 nm or less. Well layer 41 is preferably undoped.
- the barrier layer 42 is a layer made of Al b Ga 1-b N having an Al composition ratio b.
- the Al composition ratio b of the barrier layer 42 is preferably within the range of w+0.05 ⁇ b ⁇ w+0.3.
- the thickness of the barrier layer 42 is preferably 3 nm or more and 20 nm or less.
- Barrier layer 42 may be undoped or n-type with an n-type dopant such as Si.
- the i-type guide layer 5 is an i-type layer having an Al composition ratio higher than that of the barrier layer 42 and a thickness of 0.7 nm or more and 1.3 nm or less.
- the Al composition ratio of the i-type guide layer 5 is preferably higher than the Al composition ratio y of the p-type electron blocking layer 6, which will be described later, and is most preferably AlN.
- the i-type guide layer 5 is formed on the side of the light-emitting layer 4 opposite to the side facing the AlN template substrate (an example of the light-emitting layer forming step).
- the i-type guide layer 5 There are two types of manufacturing methods for the i-type guide layer 5 .
- One is a method of directly forming the i-type guide layer 5 having the above thickness and Al composition.
- the other is that after forming an AlGaN layer having a thickness equal to or greater than the above thickness, in the process of changing the carrier gas from nitrogen to hydrogen, Ga in the AlGaN layer volatilizes due to a decrease in nitrogen partial pressure, and the Al composition changes.
- the i-type guide layer 5 having the thickness and Al composition described above is obtained. Either method can be adopted in this embodiment.
- the p-type electron blocking layer 6 is a layer functioning as a p-type semiconductor made of Al y Ga 1-y N having an Al composition ratio y.
- the p-type dopant (p-type impurity) with which the p-type electron block layer 6 is doped is Mg, for example.
- the p-type dopant concentration may be on the order of 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 .
- the Al composition ratio y is 0.35 or more and 0.45 or less.
- the p-type electron blocking layer 6 has a thickness of 11 nm or more and 70 nm or less. By having such Al composition ratio y and thickness, the p-type electron blocking layer 6 suppresses the deterioration of its surface roughness and fulfills the role of an electron blocking layer to achieve an improvement in light emission output. A thickness of 60 nm or less is more preferable for improving the light emission output.
- the surface roughness (especially the maximum surface roughness) of the p-type electron blocking layer 6 and the contact layer 8 are likely to increase significantly. If the Al composition ratio y is less than 0.35 or if the thickness of the p-type electron blocking layer 6 is less than 10 nm or more than 70 nm, the reliability may deteriorate or the light emission output may decrease.
- the p-type electron blocking layer 6 may be composed of a single layer or multiple layers. When the p-type electron blocking layer 6 is composed of a plurality of layers, it may have layers with different Al compositions, layers with different dopant concentrations, Si-doped layers, and co-doped layers of Si and Mg.
- the p-type cladding layer 7 is a layer functioning as a p-type semiconductor made of Al z Ga 1-z N having an Al composition ratio z.
- the Al composition ratio z is preferably 0.17 or more and 0.27 or less.
- the p-type dopant with which the p-type cladding layer 7 is doped is Mg, for example.
- the p-type dopant concentration may be on the order of 1 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 .
- the p-type clad layer 7 is formed on the surface of the p-type electron block layer 6 opposite to the surface facing the AlN template substrate (p-type clad layer 7). An example of the layer forming process).
- the Al composition ratio z of the p-type cladding layer 7 is less than the Al composition ratio y of the p-type electron blocking layer 6 (z ⁇ y).
- the Al composition ratio z of the p-type cladding layer 7 is preferably 0.48 to 0.60 times the Al composition ratio y of the p-type electron blocking layer 6 .
- the ratio of the Al composition ratio z of the p-type cladding layer 7 to the Al composition ratio y of the p-type electron blocking layer 6 may be referred to as the Al ratio.
- the Al composition ratio z is preferably equal to or less than the Al composition ratio x of the n-type semiconductor layer 3 (z ⁇ x).
- the Al composition ratio z is larger than the Al composition ratio w of the well layer 41 (w ⁇ z).
- the thickness of the p-type cladding layer 7 is preferably adjusted according to the thickness of the p-type electron blocking layer 6 as follows.
- the total thickness of the p-type electron blocking layer 6 and the p-type cladding layer 7 should be 73 nm or more and 100 nm or less. By setting the thickness within this range, both light emission output and flatness can be achieved. It is more preferable to set the total thickness of the p-type electron blocking layer 6 and the p-type cladding layer 7 to 79 nm or more in order to improve the light emission output.
- the thickness of the electron blocking layer is 60 nm or less, when the thickness of the electron blocking layer is constant, the output tends to be larger when the total thickness is thicker, so the effect of improving the output is remarkable. More preferably, the thickness of the electron blocking layer is 11 nm or more and 60 nm or less, and the total thickness of the p-type electron blocking layer 6 and the p-type cladding layer 7 is 79 nm or more and less than 100 nm.
- the value obtained by dividing the thickness of the p-type cladding layer 7 by the thickness of the p-type electron blocking layer 6 should be at least 0.1 or more.
- the layer thickness ratio is preferably 0.4 or more, more preferably 0.55 or more.
- the upper limit of the layer thickness ratio can be 6.0 or less. If the layer thickness ratio is less than 0.4, the surface flatness of the p-type cladding layer 7 tends to deteriorate and the Rmax of the contact layer 8 tends to increase.
- the contact layer 8 is a layer made of GaN and functioning as a p-type semiconductor.
- the p-type dopant with which the contact layer 8 is doped is Mg, for example.
- the p-type dopant concentration may be on the order of 1 ⁇ 10 19 cm ⁇ 3 to 5 ⁇ 10 21 cm ⁇ 3 .
- the contact layer 8 is formed on the surface of the p-type cladding layer 7 opposite to the surface facing the AlN template substrate (p-type GaN contact layer forming step example).
- the thickness of the contact layer 8 is 5 nm or more and 15 nm or less.
- the thickness of the contact layer 8 is more preferably 5 nm or more and 10 nm or less.
- the maximum surface roughness (Rmax) of a rectangular area of 5 ⁇ m ⁇ 5 ⁇ m on the surface of the contact layer 8 is 9 nm or less, preferably 8 nm or less, and more preferably less than 6.5 nm.
- the maximum surface roughness of the contact layer 8 is 8 nm.
- the maximum surface roughness of the surface of the contact layer 8 is can be less than 6.5 nm.
- the reliability of the p-side electrode 91 may be impaired when the p-side electrode 91 is formed on the surface having the maximum surface roughness. As a result, the p-side electrode 91 may break when the light emitting element 100 is energized, and the light emitting element 100 may suddenly stop emitting light.
- the average surface roughness (Ra) of a rectangular area of 5 ⁇ m ⁇ 5 ⁇ m on the surface of the contact layer 8 is preferably 1 nm or less, more preferably 0.01 to 0.6 nm.
- the contact layer 8 may be composed of a single layer or multiple layers. When composed of a plurality of layers, it may have layers with different Al compositions, layers with different dopant concentrations, Si-doped layers, and co-doped layers of Si and Mg. It is also preferable that the outermost surface of the contact layer 8 on the side where the p-side electrode 91 is formed has a region with a high p-type dopant concentration of about 1 ⁇ 10 20 cm ⁇ 3 to 5 ⁇ 10 21 cm ⁇ 3 . .
- the n-type guide layer 31 above the n-type semiconductor layer 3 and a portion from the light emitting layer 4 to the contact layer 8 are dry-etched.
- the n-side electrode 92 on the exposed n-type semiconductor layer 3 (on the same side as the light emitting layer 4 in this embodiment) ) to form an n-side electrode 92 .
- a p-side electrode 91 is formed on a part of the contact layer 8 (on the surface of the contact layer 8 opposite to the surface facing the AlN template substrate) (an example of the p-side electrode forming step).
- an Al composition ratio lower than that of the n-type semiconductor layer 3 and having an Al composition ratio of 0 is formed on the exposed n-type semiconductor layer 3 .
- a layer made of AlGaN having a thickness of 0.2 or less may be formed, and the n-side electrode 92 may be formed thereon.
- a known electrode that can be used for the contact layer 8 may be selected as the p-side electrode 91 .
- the p-side electrode 91 is preferably a reflective electrode having a reflectance of 50% or more at the emission central wavelength.
- a combination of a first metal (Ni) and a second metal (Au, Rh) or a conductive metal nitride can be used.
- the p-side electrode 91 is used as a reflective electrode, it is preferable that the p-side electrode 91 contains Rh.
- a known electrode that can be used for the contact layer 8 may be selected as the n-side electrode 92 .
- the n-side electrode 92 for example, a combination of a first metal (Ti) and a second metal (Al, Rh) or a conductive metal nitride can be used.
- each layer on the substrate When singulating the wafer into individual chips of the light emitting elements 100, it is preferable to remove each layer on the substrate at the positions to be separated using dry etching or the like. At that time, a mesa (inclined portion) may be formed on the side surface of each layer.
- the chip size of the light-emitting device 100 can be a square, rectangle, or hexagon with one side of 200 ⁇ m to 2000 ⁇ m. Scribing or laser dicing can be used to singulate the substrate. The thickness of the substrate may be adjusted by grinding or the like before singulation.
- a vertical device may be used as another embodiment of the light emitting device 100.
- a vertical device can be obtained by using a conductive substrate as a substrate for epitaxial growth or by removing the substrate used for epitaxial growth.
- a p-side electrode 91 is formed on the contact layer 8, and a conductive layer having a thickness sufficient to be handled as the light emitting device 100 is formed thereon.
- an n-side electrode 92 is formed on a part of the n-type semiconductor layer 3 exposed by removing the growth substrate (sapphire substrate) by a known method.
- the MOCVD method can be adopted as the epitaxial growth method for each layer.
- raw material gases consisting of trimethylaluminum gas (TMA gas), trimethylgallium gas (TMG gas), and ammonia gas ( NH3 gas).
- TMA gas trimethylaluminum gas
- TMG gas trimethylgallium gas
- NH3 gas ammonia gas
- the growth temperature for epitaxial growth is preferably 1000° C. or higher and 1400° C. or lower although it depends on the Al composition ratio.
- the growth pressure in the chamber for epitaxial growth can be, for example, 10 Torr to 760 Torr. Since there is an optimum molar ratio of the group V element to the group III element (V/III ratio) depending on the growth temperature and growth pressure, it is preferable to appropriately set the flow rate of the raw material gas.
- the light-emitting device 100 will be described below with reference to examples.
- Example 1 A sapphire substrate (diameter 2 inches, thickness 430 ⁇ m, plane orientation (0001), m-axis direction off angle ⁇ : 0.5 degrees) was prepared, and an AlN layer having a central thickness of 600 nm was formed on the sapphire substrate by MOCVD. grew up. After that, it was heated at 1650° C. for 4 hours in a nitrogen gas atmosphere in a heat treatment furnace to obtain an AlN template substrate.
- the half width of the X-ray rocking curve of (10-12) measured by an X-ray diffractometer (D8 DISCOVER AUTOWAFS; Bruker AXS, CuK ⁇ 1 line) of the AlN layer of the AlN template substrate was 288 seconds, which was 300 seconds or less. .
- the surface roughness of the AlN template substrate was measured in a rectangular area of 5 ⁇ m ⁇ 5 ⁇ m with respect to the center of the wafer. 23 nm, and the maximum surface roughness (Rmax) was 3 nm.
- a first buffer layer with a thickness of 30 nm made of undoped Al 0.4 Ga 0.6 N is formed on the AlN template substrate by MOCVD.
- a second buffer layer of 0.25 Ga 0.75 N with a thickness of 1000 nm was formed.
- a Si-doped n-type semiconductor layer with a thickness of 2400 nm was formed on the second buffer layer.
- the half width of the X-ray rocking curve of the (10-12) plane was 270 seconds. and was 300 seconds or less.
- the surface roughness of the n-type semiconductor layer was measured in a rectangular area of 5 ⁇ m ⁇ 5 ⁇ m with respect to the center of the wafer.
- the surface roughness (Rmax) was 7.4 nm.
- the Si concentration of the n-type semiconductor layer was 1.0 ⁇ 10 19 atoms/cm 3 .
- an n-type guide layer with a thickness of 25 nm made of Si-doped Al 0.25 Ga 0.75 N was formed on the n-type semiconductor layer.
- a 12-nm-thick barrier layer made of Si-doped Al 0.25 Ga 0.75 N and a 2.4-nm-thick well layer made of undoped Al 0.10 Ga 0.90 N are formed. was repeated three times to form a quantum well structure.
- the group V source gas was continued to be supplied.
- the supply of the group III source gas is stopped while the supply of the group III source gas is stopped, the nitrogen gas as the carrier gas is stopped, the carrier gas is changed to hydrogen gas, and one minute after the start of the supply of the hydrogen gas, the supply of the group III source gas is started, A 54 nm thick p-type electron blocking layer made of Mg-doped Al 0.4 Ga 0.6 N was formed, and a 29 nm thick p-type cladding layer made of Mg doped Al 0.22 Ga 0.78 N was formed.
- a p-type contact layer (p-type GaN contact layer) having a thickness of 8 nm made of Mg-doped GaN was formed.
- the Ga component volatilizes and decomposes, and the i-type guide layer is transformed into an i-type guide layer having an Al composition ratio of about 1 and a thickness of 1.0 nm.
- the surface roughness of the p-type contact layer was measured in a rectangular area of 5 ⁇ m ⁇ 5 ⁇ m with respect to the center of the wafer immediately after epitaxial formation. ) was 0.39 nm, and the maximum surface roughness (Rmax) was 7.4 nm.
- the Mg concentrations of the p-type electron blocking layer, the p-type cladding layer, and the p-type contact layer are 1.0 ⁇ 10 19 atoms/cm 3 , 5.0 ⁇ 10 19 atoms/cm 3 , and 2, respectively. 0 ⁇ 10 20 atoms/cm 3 .
- Table 1 shows the Al composition ratio, the type of dopant, and the thickness of each layer in Example 1.
- the thickness measurements shown in Table 1 are based on the results of TEM measurements.
- the Al composition of each layer is specified from the wavelength observed by photoluminescence measurement.
- a mask was formed on the p-type contact layer, mesa etching was performed by dry etching, and part of the n-type semiconductor layer was exposed. After that, the mask on the p-type contact layer was removed.
- a 7 nm thick Ni layer and a 50 nm thick Rh layer were formed on the p-type contact layer to form a p-side electrode as a reflective electrode.
- a 20 nm-thick Ti layer and a 150 nm-thick Al layer were formed as an n-type electrode on the exposed portion of the n-type semiconductor layer to form an n-type electrode.
- a sputtering method was used for stacking the p-side electrode and the n-type electrode.
- a lift-off method using a resist was used to form the electrode patterns of the p-side electrode and the n-type electrode.
- a laser scriber is used to separate rectangular individual devices with a chip size of 1000 ⁇ m ⁇ 1000 ⁇ m.
- a device hereinafter simply referred to as a light-emitting device
- the thickness of the sapphire substrate after separation was 430 ⁇ m.
- Example 2 was prepared in the same manner as in Example 1, except that the Al composition ratio and layer thickness of the p-type electron blocking layer and the p-type clad layer in Example 1 were changed as shown in Tables 2 and 3. 16, Comparative Examples 1 to 6, and conventional light emitting devices were fabricated.
- Example 2 is the same as Example 1, except that the thickness of the p-type cladding layer is 35 nm.
- Example 3 is the same as Example 1, except that the thickness of the p-type cladding layer is 41 nm.
- Example 4 is the same as Example 1 except that the thickness of the p-type blocking layer is 22 nm and the thickness of the p-type cladding layer is 64 nm.
- Example 5 is the same as Example 1, except that the thickness of the p-type blocking layer is 38 nm and the thickness of the p-type cladding layer is 41 nm.
- Example 6 is the same as Example 1 except that the thickness of the p-type blocking layer is 38 nm and the thickness of the p-type cladding layer is 35 nm.
- Example 7 is the same as Example 1 except that the thickness of the p-type blocking layer was 11 nm and the thickness of the p-type cladding layer was 64 nm.
- Example 8 is the same as Example 1 except that the thickness of the p-type blocking layer is 54 nm and the thickness of the p-type cladding layer is 23 nm.
- Example 9 is the same as Example 1, except that the thickness of the p-type blocking layer is 70 nm and the thickness of the p-type cladding layer is 29 nm.
- Example 10 is the same as Example 1 except that the thickness of the p-type blocking layer is 70 nm and the thickness of the p-type cladding layer is 12 nm.
- Example 11 is the same as Example 1 except that the thickness of the p-type blocking layer is 11 nm and the thickness of the p-type cladding layer is 76 nm.
- Example 12 is the same as Example 1 except that the thickness of the p-type blocking layer is 11 nm and the thickness of the p-type cladding layer is 70 nm.
- Example 13 is the same as Example 1 except that the thickness of the p-type blocking layer is 11 nm and the thickness of the p-type cladding layer is 89 nm.
- Example 14 is the same as Example 1 except that the thickness of the p-type blocking layer was 22 nm and the thickness of the p-type cladding layer was 78 nm.
- Example 15 is the same as Example 1 except that the thickness of the p-type blocking layer is 38 nm and the thickness of the p-type cladding layer is 62 nm.
- Example 16 is the same as Example 1 except that the thickness of the p-type blocking layer is 70 nm and the thickness of the p-type cladding layer is 3 nm.
- Comparative Example 1 is the same as Example 1, except that the thickness of the p-type cladding layer is 18 nm.
- Comparative Example 2 is the same as Example 1 except that the thickness of the p-type blocking layer is 38 nm and the thickness of the p-type cladding layer is 29 nm.
- Comparative Example 3 is the same as Example 1 except that the thickness of the p-type blocking layer is 86 nm and the thickness of the p-type cladding layer is 29 nm.
- Comparative Example 4 is the same as Example 1, except that the thickness of the p-type blocking layer is 22 nm and the thickness of the p-type cladding layer is 41 nm.
- Comparative Example 5 is the same as Example 1 except that the thickness of the p-type blocking layer is 11 nm and the thickness of the p-type cladding layer is 53 nm.
- Comparative Example 6 is the same as Example 1, except that the thickness of the p-type blocking layer is 5 nm and the thickness of the p-type cladding layer is 64 nm.
- the conventional example is the same as Example 1 except that the thickness of the p-type clad layer is set to 350 nm.
- BL and CL in Tables 2 and 3 are abbreviations that mean a p-type electron blocking layer and a p-type cladding layer, respectively.
- the "Al ratio” is the ratio of the Al composition ratio of the type cladding layer to the Al composition ratio of the p-type electron blocking layer.
- the "layer thickness ratio CL/BL” is a value obtained by dividing the thickness of the p-type cladding layer by the thickness of the p-type electron blocking layer.
- Total thickness BL+CL is the total thickness of the p-type electron blocking layer and the p-type cladding layer.
- the p-type electron blocking layer and the p-type It defines the thickness of the clad layer.
- the conventional light-emitting element is simply referred to as the conventional example for convenience of explanation when the total thickness of the p-type electron blocking layer and the p-type cladding layer is extremely thick. This example is positioned as a comparative example.
- the light-emitting elements of the examples, comparative examples, and conventional examples were mounted on AlN submounts (size 2 mm x 2 mm, thickness 0.2 mm) using spherical Au bumps by a flip-chip method. Furthermore, with the Al heat sink connected to the AlN submount, a current of 350 mA was applied using a constant current power supply, and the forward voltage (Vf) at that time was measured and an integrating sphere placed on the sapphire substrate side. The luminous output (Po) of the total luminous flux was measured.
- the emission central wavelengths ( ⁇ p) of the chips of Examples, Comparative Examples, and Conventional Examples were measured with a spectroscope, the emission central wavelengths of all chips were within the range of 340 nm ⁇ 5 nm.
- the light-emitting elements of each example have a higher average light emission output than the light-emitting elements of the conventional example and the comparative example. That is, when the thickness of the p-type electron blocking layer is 11 nm or more and 70 nm or less, and the total thickness of the p-type AlGaN electron blocking layer and the p-type AlGaN cladding layer is 73 nm or more and 100 nm or less, as in this embodiment, The light-emitting element has a higher light output than the light-emitting element otherwise.
- Example 5 shows an example and a comparative example where the vertical axis represents the thickness of the p-type cladding layer and the horizontal axis represents the thickness of the p-type electron blocking layer.
- the numerical values in the figure are Po average (mW) values.
- Comparative Example 6 since the thickness of the p-type electron blocking layer is thin, although the initial light output is larger than that of Example 7, the rate of decrease in light output after energization at 600 mA for 500 hours is 80% or less. The reliability is lower than in the example, and is indicated as "reliability deterioration" in Table 2 as well.
- an ultraviolet light emitting device capable of obtaining a large emission output with an emission center wavelength of more than 320 nm and less than 350 nm, particularly more than 330 nm and less than 350 nm.
- the average surface roughness (Ra) of the p-type contact layer is preferably 1 nm or less, more preferably 0.01 or more and 0.6 nm or less. More preferably, it is 0.3 to 0.6 nm. Also, it seems that the maximum surface roughness (Rmax) of the p-type contact layer is preferably 8 nm or less.
- an ultraviolet light-emitting device capable of obtaining a large light emission output with an emission center wavelength of more than 320 nm and less than 350 nm, and a method of manufacturing the same.
- Example 1 For the conventional example and Example 1, a chip sorter was used to measure the chips manufactured from all the light emitting elements obtained in the wafer (that is, all the chips were measured). This total measurement was performed for 20 lots. As for the average of the results of all measurements performed on these 20 lots and the variation between lots, the average output was 77.9 mW and the standard deviation was 16.0 mW in the conventional example, whereas the average output was 16.0 mW in Example 1. It was 89.1 mW with a standard deviation of 12.2 mW. It can be seen that the light-emitting device of Example 1, which has a thinner p-type layer than the conventional example, has a high average light emission output and a small standard deviation value (variation) between lots.
- the present invention can be applied to a light-emitting device and its manufacturing method.
- Reference Signs List 1 substrate 11: AlN layer 100: light emitting element (ultraviolet light emitting element) 2: buffer layer 21: first buffer layer 22: second buffer layer 3: n-type semiconductor layer 31: n-type guide layer 4: light emitting layer (quantum well light emitting layer) 41 : well layer 42 : barrier layer 5 : i-type guide layer 6 : p-type electron block layer 7 : p-type cladding layer 8 : p-type contact layer (p-type GaN contact layer) 91: p-side electrode 92: n-side electrode
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Abstract
Description
(1) Al組成比xを有するAlxGa1-xNからなるn型半導体層、
量子井戸型発光層、
Al組成比yを有するAlyGa1-yNからなるp型電子ブロック層、
Al組成比zを有するAlzGa1-zNからなるp型クラッド層、及び
p型GaNコンタクト層を、この順に備え、
前記p型電子ブロック層は、
前記Al組成比yが0.35以上0.45以下で、
その厚さが11nm以上70nm以下であり、
前記p型電子ブロック層と前記p型クラッド層との合計厚さは、73nm以上100nm以下であり、
前記p型GaNコンタクト層の厚さは、5nm以上15nm以下である紫外発光素子。
(2) 前記p型GaNコンタクト層の表面は、
最大表面粗さが9nm以下であり、
平均表面粗さが、1nm以下である(1)に記載の紫外発光素子。
(3) 前記p型クラッド層は、前記Al組成比zが0.17以上0.27以下である(1)又は(2)に記載の紫外発光素子。
(4) 前記p型クラッド層の厚さを前記p型電子ブロック層の厚さで割った値が0.4以上である(1)から(3)の何れか一項に記載の紫外発光素子。
(5) 前記n型半導体層の表面は、平均表面粗さが、1nm以下である(1)から(4)の何れか一項に記載の紫外発光素子。
(6) 前記n型半導体層の(10-12)面のX線回折での半値幅が350秒以下である(1)から(5)の何れか一項に記載の紫外発光素子。
(7) 前記n型半導体層は、
前記Al組成比xが0.2以上0.35以下であり、
前記p型クラッド層の前記Al組成比zは前記n型半導体層の前記Al組成比x以下で
ある(1)から(6)の何れか一項に記載の紫外発光素子。
(8) 反射電極を更に備え、
前記反射電極は、前記p型GaNコンタクト層における、前記p型クラッド層に対向する側の面とは反対側の面上に配置されている(1)から(7)の何れか一項に記載の紫外発光素子。
(9) 発光中心波長が331nm以上349nm以下である(1)から(8)の何れか一項に記載の紫外発光素子。
(10) Al組成比xを有するAlxGa1-xNからなるn型半導体層を形成するn型半導体層形成工程、
量子井戸型発光層を形成する発光層形成工程、
Al組成比yを有するAlyGa1-yNからなるp型電子ブロック層を形成するp型電子ブロック層形成工程、
Al組成比zを有するAlzGa1-zNからなるp型クラッド層を形成するp型クラッド層形成工程、及び、
p型GaNコンタクト層を形成するp型GaNコンタクト層形成工程を含み、
前記n型半導体層形成工程、前記発光層形成工程、前記p型電子ブロック層形成工程、前記p型クラッド層形成工程、及び、前記p型GaNコンタクト層形成工程をこの順に行い、
前記p型電子ブロック層形成工程は、
前記Al組成比yを0.35以上0.45以下とし、
前記p型電子ブロック層の厚さを11nm以上70nm以下とし、
前記p型電子ブロック層形成工程とp型クラッド層形成工程とは、前記p型電子ブロック層と前記p型クラッド層との合計厚さを73nm以上100nm以下とし、
前記p型GaNコンタクト層形成工程は、前記p型GaNコンタクト層の厚さを、5nm以上15nm以下とする紫外発光素子の製造方法。
(11) 前記p型GaNコンタクト層形成工程は、
前記p型GaNコンタクト層の表面の最大表面粗さを9nm以下とし、
前記p型GaNコンタクト層の表面の平均表面粗さを、1nm以下とする(10)に記載の紫外発光素子の製造方法。
(12) 前記p型GaNコンタクト層上にp側電極を形成するp側電極形成工程を更に含む(9)又は(10)に記載の紫外発光素子の製造方法。
本実施形態において、発光素子100の各層の厚さは、TEM―EDS(透過電子顕微鏡)で撮影した像に基づいて計測する。すなわち、各層の厚さは、発光素子100の断面を撮影した像における各層厚さの平均値を用いる。なお、基板1の厚さは、SEM(走査型電子顕微鏡)により計測した値を用いる。
本実施形態における「AlGaN」は、Al組成比をαとするとAlαGa1-αNであることを意味する。本実施形態におけるAlGaNのAl組成比αの値は、各層を成長した際に各層表面に対して行ったフォトルミネッセンス測定により観測された波長から特定する。Al組成比αは、規定がなければ0以上1以下の範囲内である。発光素子100の断面からAl組成を特定する方法としては、例えばEDS(エネルギー分散型X線分光)を使用することができる。
本実施形態における表面粗さの値は、5μm×5μmの矩形状の範囲に対してAFM(原子間力顕微鏡)測定を行って求める。平均算術粗さ(Ra)及び最大表面粗さ(Rmax)は、AFM測定により取得した表面プロファイルに基づいて、JIS(B0601-2001)の定めに従って求める。平均算術粗さ(Ra)及び最大表面粗さ(Rmax)は、AFM装置に付属するアプリケーション・ソフトウェアにより自動計算して求めてよい。
本実施形態における結晶性の評価は、X線回折装置によるX線ロッキングカーブの半値幅(arcsec)の値とする。半値幅は、X線回折装置に付属するアプリケーション・ソフトウェアにより自動計算してもとめてよい。本実施形態では、評価対象の(0001)面と(10-12)面のそれぞれに対してX線を照射してその回折プロファイルを評価する。特に(10-12)面における測定結果は、結晶内の貫通転位密度(螺旋及び刃状の混合転位)の指標となる。
本発明におけるドーパント濃度は、SIMS(二次イオン質量分析)により測定した値を用いる。なお、アンドープとはMOCVD成長時にMgやSi等の特定のドーパントの原料ガスを意図的には供給しないことをいい、製造過程におけるC、H、Oのような不可避的な不純物が含まれていても良い。また、本発明におけるi型とは、アンドープであって、キャリア密度が4×1016cm-3以下であることをいう。
次に、図1、図3に示すように、AlNテンプレート基板上にバッファ層2を形成する。バッファ層2は、基板1上のAlN層11とn型半導体層3との間に位置し、基板1及びAlN層11とn型半導体層3との間の格子定数差を緩和する層である。バッファ層2はAl組成の異なる複数のAlGaN層を積層させた層により、又は、Al組成傾斜層により構成されることが好ましい。また、バッファ層2は、アンドープとすることが好ましい。バッファ層2の厚さは、例えば500nm以上2000nm以下であることが好ましい。
n型半導体層3は、Al組成比xを有するAlxGa1-xNにSiなどのn型ドーパントを含有してn型半導体として機能する層である。n型ドーパントの濃度は1×1018cm-3から5×1019cm-3程度であることが好ましい。n型半導体層3はバッファ層2を形成した後に、バッファ層2における、AlNテンプレート基板に対向する側の面とは反対側の面側に形成される(n型半導体層形成工程の一例)。
発光層4は、AlGaNからなる層を含む層である。発光層4は、複数の井戸層41と複数の障壁層42(バリア層)とを有し、これらが交互に積層された層である。すなわち、発光層4は、発光中心波長に応じたAl組成比を有する井戸層41と、井戸層41,41を挟む障壁層42とを有し、井戸層41と障壁層42の組み合わせを1ペア以上繰り返す構成を有する。発光層4の両面は障壁層42である。発光層4は、n型半導体層3を形成した後に、n型半導体層3における、AlNテンプレート基板に対向する側の面とは反対側の面側に形成される(発光層形成工程の一例)。
i型ガイド層5は、障壁層42よりも高いAl組成比を有し、厚さが0.7nm以上1.3nm以下のi型層である。i型ガイド層5のAl組成比は、後述するp型電子ブロック層6のAl組成比yよりも高いことが好ましく、最も好ましくはAlNである。i型ガイド層5は、発光層4を形成した後に、発光層4における、AlNテンプレート基板に対向する側の面とは反対側の面側に形成される(発光層形成工程の一例)。
p型電子ブロック層6は、Al組成比yを有するAlyGa1-yNからなるp型半導体として機能する層である。p型電子ブロック層6にドープされるp型ドーパント(p型不純物)は、例えばMgである。p型ドーパントの濃度は1×1018cm-3から5×1019cm-3程度であってよい。p型電子ブロック層6は、i型ガイド層5を形成した後に、i型ガイド層5における、AlNテンプレート基板に対向する側の面とは反対側の面側に形成される。
p型クラッド層7は、Al組成比zを有するAlzGa1-zNからなるp型半導体として機能する層である。Al組成比zは0.17以上0.27以下であることが好ましい。p型クラッド層7にドープされるp型ドーパントは、例えばMgである。p型ドーパントの濃度は1×1018cm-3から5×1019cm-3程度であってよい。p型クラッド層7は、p型電子ブロック層6を形成した後に、p型電子ブロック層6における、AlNテンプレート基板に対向する側の面とは反対側の面側に形成される(p型クラッド層形成工程の一例)。
コンタクト層8は、GaNからなる、p型半導体として機能する層である。コンタクト層8にドープされるp型ドーパントは、例えばMgである。p型ドーパントの濃度は1×1019cm-3から5×1021cm-3程度であってよい。コンタクト層8は、p型クラッド層7を形成した後に、p型クラッド層7における、AlNテンプレート基板に対向する側の面とは反対側の面側に形成される(p型GaNコンタクト層形成工程の一例)。
サファイア基板(直径2インチ、厚さ430μm、面方位(0001)、m軸方向オフ角θ:0.5度)を用意して、MOCVD法により、上記サファイア基板上に中心膜厚600nmのAlN層を成長させた。その後、熱処理炉により窒素ガス雰囲気で1650℃で4時間加熱して、AlNテンプレート基板を得た。
実施例1におけるp型電子ブロック層とP型クラッド層のAl組成比及び層の厚さを表2及び表3に記載の通りに変えた以外は、実施例1と同様にして、実施例2から16、比較例1から6及び従来例に係る発光素子を作成した。
11 :AlN層
100 :発光素子(紫外線発光素子)
2 :バッファ層
21 :第一バッファ層
22 :第二バッファ層
3 :n型半導体層
31 :n型ガイド層
4 :発光層(量子井戸型発光層)
41 :井戸層
42 :障壁層
5 :i型ガイド層
6 :p型電子ブロック層
7 :p型クラッド層
8 :p型コンタクト層(p型GaNコンタクト層)
91 :p側電極
92 :n側電極
Claims (12)
- Al組成比xを有するAlxGa1-xNからなるn型半導体層、
量子井戸型発光層、
Al組成比yを有するAlyGa1-yNからなるp型電子ブロック層、
Al組成比zを有するAlzGa1-zNからなるp型クラッド層、及び
p型GaNコンタクト層を、この順に備え、
前記p型電子ブロック層は、
前記Al組成比yが0.35以上0.45以下で、
その厚さが11nm以上70nm以下であり、
前記p型電子ブロック層と前記p型クラッド層との合計厚さは、73nm以上100nm以下であり、
前記p型GaNコンタクト層の厚さは、5nm以上15nm以下である紫外発光素子。 - 前記p型GaNコンタクト層の表面は、
最大表面粗さが9nm以下であり、
平均表面粗さが、1nm以下である請求項1に記載の紫外発光素子。 - 前記p型クラッド層は、前記Al組成比zが0.17以上0.27以下である請求項1又は2に記載の紫外発光素子。
- 前記p型クラッド層の厚さを前記p型電子ブロック層の厚さで割った値が0.4以上である請求項1又は2に記載の紫外発光素子。
- 前記n型半導体層の表面は、平均表面粗さが、1nm以下である請求項1又は2に記載の紫外発光素子。
- 前記n型半導体層の(10-12)面のX線回折での半値幅が350秒以下である請求項1又は2に記載の紫外発光素子。
- 前記n型半導体層は、
前記Al組成比xが0.2以上0.35以下であり、
前記p型クラッド層の前記Al組成比zは前記n型半導体層の前記Al組成比x以下である請求項1又は2に記載の紫外発光素子。 - 反射電極を更に備え、
前記反射電極は、前記p型GaNコンタクト層における、前記p型クラッド層に対向する側の面とは反対側の面上に配置されている請求項1又は2に記載の紫外発光素子。 - 発光中心波長が331nm以上349nm以下である請求項1又は2に記載の紫外発光素子。
- Al組成比xを有するAlxGa1-xNからなるn型半導体層を形成するn型半導体層形成工程、
量子井戸型発光層を形成する発光層形成工程、
Al組成比yを有するAlyGa1-yNからなるp型電子ブロック層を形成するp型電子ブロック層形成工程、
Al組成比zを有するAlzGa1-zNからなるp型クラッド層を形成するp型クラッド層形成工程、及び、
p型GaNコンタクト層を形成するp型GaNコンタクト層形成工程を含み、
前記n型半導体層形成工程、前記発光層形成工程、前記p型電子ブロック層形成工程、前記p型クラッド層形成工程、及び、前記p型GaNコンタクト層形成工程をこの順に行い、
前記p型電子ブロック層形成工程は、
前記Al組成比yを0.35以上0.45以下とし、
前記p型電子ブロック層の厚さを11nm以上70nm以下とし、
前記p型電子ブロック層形成工程とp型クラッド層形成工程とは、前記p型電子ブロック層と前記p型クラッド層との合計厚さを73nm以上100nm以下とし、
前記p型GaNコンタクト層形成工程は、前記p型GaNコンタクト層の厚さを、5nm以上15nm以下とする紫外発光素子の製造方法。 - 前記p型GaNコンタクト層形成工程は、
前記p型GaNコンタクト層の表面の最大表面粗さを9nm以下とし、
前記p型GaNコンタクト層の表面の平均表面粗さを、1nm以下とする請求項10に記載の紫外発光素子の製造方法。 - 前記p型GaNコンタクト層上にp側電極を形成するp側電極形成工程を更に含む請求項9又は10に記載の紫外発光素子の製造方法。
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