WO2023098775A1 - Ldmos集成器件的制作方法 - Google Patents

Ldmos集成器件的制作方法 Download PDF

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WO2023098775A1
WO2023098775A1 PCT/CN2022/135755 CN2022135755W WO2023098775A1 WO 2023098775 A1 WO2023098775 A1 WO 2023098775A1 CN 2022135755 W CN2022135755 W CN 2022135755W WO 2023098775 A1 WO2023098775 A1 WO 2023098775A1
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region
layer
nldmos
pldmos
dielectric layer
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PCT/CN2022/135755
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English (en)
French (fr)
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许超奇
陈淑娴
马春霞
张仪
徐鹏龙
林峰
曹瑞彬
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无锡华润上华科技有限公司
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Publication of WO2023098775A1 publication Critical patent/WO2023098775A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a manufacturing method of an LDMOS integrated device.
  • DMOS Bipolar transistor
  • BJT Bipolar Junction Transistor
  • CMOS complementary metal oxide semiconductor
  • DMOS double diffused metal oxide semiconductor
  • LDMOS devices can include lateral double-diffused metal-oxide-semiconductor field-effect (LDMOS) devices and vertical double-diffused metal-oxide-semiconductor field-effect (VDMOS) devices. Since LDMOS devices are more compatible with CMOS processes than VDMOS devices, they are widely used in integrated circuit design.
  • LDMOS lateral double-diffused metal-oxide-semiconductor field-effect
  • VDMOS vertical double-diffused metal-oxide-semiconductor field-effect
  • LDMOS integrated devices include N-channel LDMOS (NLDMOS) devices and P-channel LDMOS (PLDMOS) devices.
  • NLDMOS N-channel LDMOS
  • PLDMOS P-channel LDMOS
  • the invention provides a manufacturing method of an LDMOS integrated device, which can improve the performance of the LDMOS integrated device.
  • the present invention provides a method for manufacturing an LDMOS device. Described preparation method comprises:
  • a semiconductor substrate is provided, the semiconductor substrate has an NLDMOS region and a PLDMOS region; a P-type body region and an N-type drift region are formed in the NLDMOS region, and an N-type source region is formed on the top of the P-type body region, so An N-type drain region is formed on the top of the N-type drift region, and a first gate structure is formed on the NLDMOS region; an N-type body region and a P-type drift region are formed in the PLDMOS region, and the N-type body A P-type source region is formed on the top of the region, a P-type drain region is formed on the top of the P-type drift region, and a second gate structure is formed on the PLDMOS region;
  • the stress material layer is removed.
  • the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region are formed on the semiconductor substrate, and the dielectric layer on the NLDMOS region and/or the dielectric layer on the PLDMOS region forming a stress material layer on the NLDMOS region, the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, including: forming a tensile stress material layer only on the dielectric layer on the NLDMOS region.
  • the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region are formed on the semiconductor substrate, and the dielectric layer on the NLDMOS region and/or the dielectric layer on the PLDMOS region A stress material layer is formed on the NLDMOS region, the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, including:
  • the first mask layer exposes at least the tensile stress material layer on the PLDMOS region, using the first mask layer as a mask, removing the tensile material layer on the PLDMOS region, and the remaining tensile material layer on the NLDMOS region at least covers the N-type drift region;
  • the first mask layer exposes at least the dielectric material layer on the PLDMOS region, etch and remove a partial thickness of the dielectric material layer, so that at least the N on the NLDMOS region
  • the thickness of the dielectric material layer on the type drift region is greater than the thickness of the remaining dielectric material layer on the PLDMOS region
  • the remaining dielectric material layer on the NLDMOS region is the dielectric layer on the NLDMOS region
  • the PLDMOS region The remaining dielectric material layer is the dielectric layer on the PLDMOS region.
  • a patterned first mask layer is formed on the tensile stress material layer, the first mask layer exposes at least the tensile stress material layer on the PLDMOS region, and the first mask layer As a mask, remove the tensile stress material layer on the PLDMOS region, and the remaining tensile stress material layer on the NLDMOS region at least covers the N-type drift region, including:
  • the remaining tensile stress material layer on the NLDMOS region also extends from the N-type source region to cover the N-type drain region through the first gate structure.
  • the dielectric layer on the PLDMOS region has a thickness of 600 angstroms to 1200 angstroms.
  • the thickness of the dielectric material layer is 1000 angstroms to 1800 angstroms.
  • the thickness of the tensile stress material layer is 150 angstroms to 600 angstroms.
  • the bottom of the suspended conductive plug stays in the P-type drift region and/or the N-type drift region and a preset distance from the upper surface of the P-type drift region and/or the N-type drift region.
  • a metal silicide layer is formed on the surface;
  • the suspension type conductive plug is formed at the same time as the contact type conductive plug is formed, the bottom of the suspension type conductive plug stays on the upper surface of the silicide barrier layer, and the diameter of the suspension type conductive plug is The radial dimension is larger than the radial dimension of the contact-type conductive plug.
  • the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region are formed on the semiconductor substrate, and the dielectric layer on the NLDMOS region and/or the dielectric layer on the PLDMOS region forming a stress material layer on the NLDMOS region, the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, including: forming a compressive stress material layer only on the dielectric layer on the PLDMOS region.
  • the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region are formed on the semiconductor substrate, and the dielectric layer on the NLDMOS region and/or the dielectric layer on the PLDMOS region A stress material layer is formed on the NLDMOS region, the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, including:
  • the second mask layer exposes at least the compressive stress material layer on the NLDMOS region, using the second mask layer as a mask, removing the compressive stress material layer on the NLDMOS region, and the remaining compressive stress material layer on the PLDMOS region at least covers the P-type drift region;
  • the second mask layer removing the second mask layer, and forming an additional dielectric material layer on the dielectric material layer on the NLDMOS region, so that the total thickness of the dielectric material layer on the NLDMOS region and the additional dielectric material layer is greater than that of the PLDMOS
  • the thickness of the dielectric material layer on the NLDMOS region, the dielectric material layer on the NLDMOS region and the additional dielectric material layer together become the dielectric layer on the NLDMOS region, and the dielectric material layer on the PLDMOS region is the PLDMOS region upper medium layer.
  • the semiconductor substrate has an NLDMOS region and a PLDMOS region, and a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region are formed on the semiconductor substrate, and on the dielectric layer on the NLDMOS region and /or forming a stress material layer on the dielectric layer on the PLDMOS region, and then performing heat treatment to adjust the stress of the stress material layer, which can improve the electron mobility of the NLDMOS device and/or the PLDMOS device, thereby improving the performance of the LDMOS integrated device; and , the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, that is, the thickness of the dielectric layer under the Big contact of the NLDMOS region can meet its RESURF requirements, and the Big contact of the PLDMOS region can be The thickness of the lower dielectric layer meets its RESURF requirements, which can improve the RESURF
  • the injection conditions of the LDMOS integrated device can be readjusted to reduce the on-resistance of the LDMOS integrated device, which helps to further improve the LDMOS
  • the performance of the PLDMOS device in the integrated device finally realizes the simultaneous preparation of high-performance NLDMOS and high-performance PLDMOS in the same process flow.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an LDMOS integrated device according to an embodiment of the present invention.
  • FIG. 2 to FIG. 5 are schematic cross-sectional schematic diagrams of the process structure of manufacturing an LDMOS integrated device using the method for manufacturing an LDMOS integrated device according to an embodiment of the present invention.
  • 10-semiconductor substrate 100a-NLDMOS region; 100b-PLDMOS region; 101-N-type drain region; 102-N-type source region; 103-first gate structure; 104-P-type body region lead-out region ; 105-P-type drain region; 106-P-type source region; 107-second gate structure; 108-N-type body region lead-out region; 109-dielectric material layer; 110-tensile stress material layer; 111-silicide barrier layer; 112-interlayer dielectric layer; 113a-suspension type conductive plug; 113b-contact type conductive plug; 114-metal silicide.
  • the inventors have found that the NLDMOS can only be used to adjust the process flow first, and then the PLDMOS can be developed with the same process flow. Make PLDMOS achieve optimal characteristics.
  • RESURF reduced surface electric field
  • the inventors also found that RESURF (reduced surface electric field) technology is commonly used in the BCD process to reduce the surface electric field in the drift region of PLDMOS or NLDMOS to improve the withstand voltage performance of PLDMOS or NLDMOS.
  • the thickness of the dielectric layer under the Big contact determines the RESURF effect.
  • SiN introduced above will have an additional impact on the device performance of PLDMOS or NLDMOS. Because when SiN is annealed, the change of SiN stress will produce a large (+5%) current positive gain for NLDMOS, but a greater current negative gain (-10% or more or even failure) for the corresponding PLDMOS current. .
  • this embodiment provides a method for manufacturing an LDMOS integrated device .
  • Fig. 1 shows the flow process of the manufacturing method of the LDMOS integrated device of this embodiment, as shown in Fig. 1, the manufacturing method of described LDMOS integrated device comprises:
  • the semiconductor substrate has an NLDMOS region and a PLDMOS region; a P-type body region and an N-type drift region are formed in the NLDMOS region, and an N-type source region is formed on the top of the P-type body region , an N-type drain region is formed on the top of the N-type drift region, and a first gate structure is formed on the NLDMOS region; an N-type body region and a P-type drift region are formed in the PLDMOS region, and the N-type drain region is formed in the NLDMOS region.
  • a P-type source region is formed on the top of the P-type body region, a P-type drain region is formed on the top of the P-type drift region, and a second gate structure is formed on the PLDMOS region;
  • FIG. 2 to FIG. 5 are schematic cross-sectional schematic diagrams of the process structure of manufacturing an LDMOS integrated device using the method for manufacturing an LDMOS integrated device according to an embodiment of the present invention.
  • the fabrication method of the LDMOS integrated device of this embodiment will be described below with reference to FIG. 1 to FIG. 5 .
  • the semiconductor substrate 10 may be a silicon substrate. But not limited thereto, the semiconductor substrate 10 may also be a germanium substrate, a silicon germanium substrate, or silicon-on-insulator. In this embodiment, the semiconductor substrate 10 is P-type. In other embodiments, the semiconductor substrate 10 may be N-type.
  • the semiconductor substrate 10 has an NLDMOS region 100a and a PLDMOS region 100b.
  • the NLDMOS region 100a can be used to form NLDMOS devices.
  • the PLDMOS region 100b can be used to form a PLDMOS device.
  • a P-type body region (Pbody) and an N-type drift region (N-Drift-Area) are formed in the NLDMOS region 100a, and an N-type source region 102 is formed on the top of the P-type body region, and the N-type drift region
  • An N-type drain region 101 is formed on the top of the region, and a first gate structure 103 is formed on the NLDMOS region 100a.
  • the first gate structure 103 is at least formed on the upper surface of the semiconductor substrate between the N-type source region 102 and the N-type drift region.
  • the N-type source region 102 can protrude laterally under the first gate structure 103 .
  • the N-type drift region surrounds the P-type body region.
  • the P-type body region is adjacent to the N-type drift region.
  • the P-type body region and the N-type drift region are arranged at intervals.
  • N-type body region Nbody and a P-type drift region (P-Drift-Area) are formed in the PLDMOS region 100b, and a P-type source region 106 is formed on the top of the N-type body region, and the P-type drift region A P-type drain region 105 is formed on the top of the region, and a second gate structure 107 is formed on the PLDMOS region 100b.
  • the second gate structure 107 is formed at least on the upper surface of the semiconductor substrate between the P-type source region 106 and the P-type drift region.
  • the P-type source region 106 can protrude laterally under the second gate structure 107 .
  • the P-type drift region surrounds the N-type body region.
  • the P-type body region is adjacent to the N-type drift region.
  • the N-type body region and the P-type drift region are spaced apart.
  • a P-type body region lead-out region 104 may also be formed on the top of the P-type body region, and the P-type body region lead-out region 104 is located on the side of the N-type source region 102 away from the first gate.
  • One side of the structure 103, and the doping concentration of the P-type body region lead-out region 104 is greater than the doping concentration of the P-type body region.
  • An N-type body region lead-out region 108 may also be formed on the top of the N-type body region, and the N-type body region lead-out region 108 is located on a side of the P-type drain region 105 away from the second gate structure 107, and N The doping concentration of the lead-out region 108 of the body region is greater than the doping concentration of the N-type body region.
  • the NLDMOS region 100 a and the PLDMOS region 100 b can be isolated by an isolation structure 11 .
  • the isolation structure 11 may be shallow trench isolation (STI), junction isolation or local oxidation of silicon isolation (LOCOS).
  • a tensile stress material layer may only be formed on the dielectric layer on the NLDMOS region.
  • the step S2 is only to form a tensile stress material layer on the dielectric layer on the NLDMOS region" will be described as an example.
  • step S2 may include sub-steps S21 to S24.
  • a dielectric material layer 109 covering the semiconductor substrate 10 and the first gate structure 103 and the second gate structure 107 is formed.
  • the material of the dielectric material layer 109 may include silicon oxide.
  • the thickness of the dielectric material layer 109 may range from 1000 angstroms to 1800 angstroms. But not limited thereto, the thickness of the dielectric material layer 109 can be adjusted according to the actual situation of the NLDMOS device.
  • a tensile stress material layer 110 covering the dielectric material layer 109 is formed.
  • the material of the tensile stress material layer 110 may include at least one of silicon nitride and silicon oxynitride.
  • the thickness of the tensile stress material layer 110 may range from 150 angstroms to 600 angstroms. But not limited thereto, the thickness of the tensile stress material layer 110 can be adjusted according to the actual situation of the NLDMOS device.
  • Sub-step S23 as shown in FIG. 3 , forming a patterned first mask layer (not shown in the figure) on the tensile stress material layer 110, the first mask layer at least exposes the PLDMOS region 100b using the first mask layer as a mask to remove the tensile material layer on the PLDMOS region 100b, and the remaining tensile material layer on the NLDMOS region 100a at least covers the N type drift zone.
  • the remaining tensile stress material layer on the NLDMOS region 100a may extend from the N-type source region 102 to cover the N-type drain region 101 through the first gate structure 103 In this way, when heat treatment is performed subsequently, the remaining tensile stress material layer 110 can apply tensile stress to both the N channel region (located below the first gate structure 103 ) and the N-type drift region of the NLDMOS device, thereby improving the performance of the NLDMOS device.
  • the electron mobility of the N-type drift region and the N-channel region helps to reduce the on-resistance of the NLDMOS device without reducing the breakdown voltage of the NLDMOS, improve the saturation current capability of the NLDMOS device, and improve the performance of the NLDMOS device.
  • Sub-step S24 as shown in FIG. 3 , based on the first mask layer, the first mask layer at least exposes the dielectric material layer on the PLDMOS region 100b, and etches and removes a part of the thickness of the dielectric material layer,
  • the thickness of the dielectric material layer on at least the N-type drift region on the NLDMOS region 100a is greater than the thickness of the remaining dielectric material layer on the PLDMOS region 100b, and the remaining dielectric material layer on the NLDMOS region 100a is The dielectric layer 109a on the NLDMOS region, and the remaining dielectric material layer on the PLDMOS region 100b is the dielectric layer 109b on the PLDMOS region.
  • the NLDMOS region 100a is not The dielectric material layer covered by the first mask layer is also etched to remove part of its thickness.
  • step S23 and step S24 the tensile stress material layer on the NLDMOS region 100a can be retained and the tensile stress material layer on the PLDMOS region 100b can be removed by using only one photolithography (using the first mask layer as a mask) and a corresponding etching process.
  • the tensile stress material layer does not negatively affect the device performance of the PLDMOS while improving the electron mobility of the NLDMOS.
  • Photolithography and etching process that is, one photolithography and one etching of SiN for NLDMOS, one photolithography and one etching of SiN for PLDMOS.
  • step S23 and step S24 of this implementation only one additional photolithography and etching is required, which can not only improve the RESURF capability of the Big contact of the LDMOS integrated device, but also improve the device performance of NLDMOS and PLDMOS at the same time.
  • the injection conditions of the PLDMOS device can be readjusted (for example, the doping concentration of the P-type drift region in the PLDMOS device is appropriately increased), The on-resistance of the PLDMOS device can be reduced, and the performance of the PLDMOS device can be improved. In this way, the performance of the NLDMOS device and the PLDMOS device can be improved simultaneously.
  • part of the thickness of the dielectric material layer 109 on the PLDMOS region 100b can be etched and removed by an over-etching process, so that the thickness of the dielectric layer 109b on the PLDMOS region is smaller than that of the dielectric layer on the NLDMOS region 109a thickness.
  • the over etching process can be realized by running the OVER ETCH program in the etching machine.
  • the removed thickness of the dielectric material layer 109 on the PLDMOS region 100 b can be controlled by adjusting the over-etching time.
  • a part of the thickness of the dielectric material layer 109 may be etched and removed by other known etching methods in the art.
  • the dielectric layer 109b on the PLDMOS region has a thickness of 600 angstroms to 1200 angstroms. But not limited thereto, the remaining thickness of the dielectric layer 109b on the PLDMOS region can be adjusted according to the actual situation of the PLDMOS device.
  • the first mask layer on the tensile stress material layer 110 may be removed.
  • the first mask layer may be removed by using a mask removal process known in the art.
  • step S3 is performed, including: performing heat treatment to adjust the stress of the remaining tensile stress material layer 110 and improve the electron mobility of the NLDMOS device.
  • the heat treatment process may be rapid thermal treatment (RTA) process or laser anneal (Laser anneal) process.
  • RTA rapid thermal treatment
  • Laser anneal laser anneal
  • other heat treatment processes known in the art may also be used to heat treat the tensile stress material layer 110 (or the semiconductor substrate 10 ).
  • step S4 may include: removing the tensile stress material layer 110 .
  • a wet etching process or a dry etching process may be used to remove the tensile stress material layer 110 .
  • a compressive stress material layer may be formed only on the dielectric layer on the PLDMOS region.
  • Step S2 may specifically include: forming a dielectric material layer covering the semiconductor substrate 10 and the first gate structure 103 and the second gate structure 107; forming a compressive stress material layer covering the dielectric material layer; A patterned second mask layer is formed on the compressive stress material layer, the second mask layer at least exposes the compressive stress material layer on the NLDMOS region 100a, using the second mask layer as a mask, removing the compressive stress material layer on the NLDMOS region 100a, and the remaining compressive stress material layer on the PLDMOS region 100b covers at least the P-type drift region; removing the second mask layer, in the NLDMOS region 100a An additional dielectric material layer is formed on the dielectric material layer above, so that the total thickness of the dielectric material layer and the additional dielectric material layer on the NLDMOS region 100a is greater than the thickness of the dielectric material layer on the PLDMOS region
  • the compressive stress material layer on the subsequent PLDMOS region 100b can at least apply compressive stress to the P-type drift region, which helps to improve the electron mobility of the PLDMOS device without negatively affecting the device performance of the NLDMOS, and improves the integration of LDMOS. device performance.
  • the thickness of the dielectric layer on the NLDMOS region can be greater than the thickness of the dielectric layer on the PLDMOS region, so that the thickness of the dielectric layer under the Big contact of the NLDMOS region and the thickness of the dielectric layer under the Big contact of the PLDMOS region can meet their respective RESURF requirements , so that the RESURF capability of the Big contact of the LDMOS integrated device can be improved as a whole.
  • step S3 may include: performing heat treatment to adjust the stress of the compressive stress material layer.
  • step S4 may include: removing the compressive stress material layer.
  • the manufacturing method of the LDMOS integrated device may further include steps S5 to S6.
  • Step S5 patterning the dielectric layer 109a on the NLDMOS region and the dielectric layer 109b on the PLDMOS region to expose the N-type source region 102, the N-type drain region 101, and part of the first gate structure 103 , the P-type source region 106 , the P-type drain region 105 and part of the second gate structure 107 .
  • Step S6 as shown in FIG. 5, forming a suspended conductive plug 113a above the P-type drift region and/or the N-type drift region, and the bottom of the suspended conductive plug 113 stays on the P-type drift region. above the drift region and/or the N-type drift region, and at a preset distance from the upper surface of the P-type drift region and/or the N-type drift region.
  • the manufacturing method of the LDMOS integrated device may further include: as shown in FIG. 5 , on the patterned dielectric layer 109a on the NLDMOS and on the dielectric A silicide barrier layer 111 is formed on the layer 109b, that is, a silicide barrier layer 111 is formed on the dielectric layer 109a on the remaining NLDMOS region and on the dielectric layer 109b on the remaining PLDMOS region; in the exposed N-type source region 102, the upper surface of the N-type drain region 101, part of the first gate structure 103, the P-type source region 106, the P-type drain region 105 and part of the second gate structure 107 is formed with metal Silicide layer 114 (FIG.
  • an interlayer dielectric layer 112 is formed on the semiconductor substrate 10, and the N-type source region 102 penetrating through the interlayer dielectric layer 112 is formed , the N-type drain region 101 , the first gate structure 103 , the P-type source region 106 , the P-type drain region 105 and the contact-type conductive plug 113 b of the second gate structure 107 .
  • the suspension type conductive plug 113a is formed at the same time as the contact type conductive plug 113b is formed, the bottom of the suspension type conductive plug 113a rests on the upper surface of the silicide barrier layer 111, and the suspension type conductive plug 113a
  • the radial dimension of the set-type conductive plug 113a is larger than the radial dimension of the contact-type conductive plug 113b.
  • the silicide barrier layer 111 may have a thickness of 200 angstroms to 300 angstroms. But not limited thereto, the thickness of the silicide barrier layer 111 can be adjusted as required.
  • the material of the interlayer dielectric layer 112 may include silicon oxide.
  • the hovering conductive plug 113a can be called a field plate (Field Plating, FP), which can be used to reduce the surface electric field of the N-type drift region and/or the P-type drift region.
  • the radial dimension of the hovering type conductive plug 113a is greater than the radial dimension of the contact type conductive plug 113b, and the thickness of the dielectric layer 109b on the PLDMOS region is smaller than that of the dielectric layer 109a on the NLDMOS region, which can effectively reduce the N-type
  • the surface electric field of the drift region and the P-type drift region helps to improve the performance of the NLDMOS device and the PLDMOS device.
  • the performance of the PLDMOS device can be further improved by adjusting the injection conditions of the P-type drift region of the PLDMOS device.
  • Both the contact-type conductive plug 113b and the hover-type conductive plug 113a can be made of metal materials such as tungsten or aluminum or metal alloys.
  • the semiconductor substrate 10 has an NLDMOS region 100a and a PLDMOS region 100b, and a dielectric layer 109a on the NLDMOS region and a dielectric layer 109b on the PLDMOS region are formed on the semiconductor substrate 10, and a dielectric layer 109b is formed on the NLDMOS region.
  • the thickness of the dielectric layer 109a on the NLDMOS region is greater than the thickness of the dielectric layer 109b on the PLDMOS region, that is, the thickness of the dielectric layer under the Big contact of the NLDMOS region can meet its RESURF Requirements, and the thickness of the dielectric layer under the Big contact in the PLDMOS region can meet its RESURF requirements, which can improve the RESURF capability of the Big contact of the LDMOS integrated device as a whole.
  • the thickness of the dielectric layer 109a on the NLDMOS region or the described The thickness of the dielectric layer 109b on the PLDMOS region can readjust the injection conditions of the PLDMOS device, reduce the on-resistance of the LDMOS integrated device, and help to further improve the performance of the PLDMOS device in the LDMOS integrated device, and finally realize simultaneous Preparation of high-performance NLDMOS and high-performance PLDMOS.

Abstract

本发明提供的LDMOS集成器件的制作方法中，提供的半导体基底具有NLDMOS区和PLDMOS区；接着，于半导体基底上形成NLDMOS区上的介质层和PLDMOS区上的介质层，于NLDMOS区上的介质层上和/或PLDMOS区上的介质层上形成应力材料层，NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度；然后，执行热处理，以调整应力材料层的应力，提升器件的电子迁移率；再去除应力材料层。如此，能够提升NLDMOS器件和/或PLDMOS器件的电子迁移率，实现在同一工艺流程中同时制备高性能NLDMOS和高性能PLDMOS；而且，NLDMOS区上的介质层的厚度大于PLDMOS区上的介质层的厚度，即既能使NLDMOS区的Big contact下的介质层厚度满足其RESURF需求，又能使PLDMOS区的Big contact下的介质层厚度满足其RESURF需求，可以整体提升LDMOS集成器件的Big contact的RESURF能力。

Description

LDMOS集成器件的制作方法 技术领域
本发明涉及半导体技术领域，特别涉及一种LDMOS集成器件的制作方法。
背景技术
在BCD工艺开发中，涉及双极型晶体管(Bipolar Junction Transistor，BJT)、互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)器件和双扩散金属氧化物半导体(Diffused Metal Oxide Semiconductor，DMOS)器件等多项器件的共同开发。DMOS器件可以包括横向双扩散金属氧化物半导体场效应(LDMOS)器件和纵向双扩散金属氧化物半导体场效应(VDMOS)器件，由于LDMOS器件比VDMOS器件更容易与CMOS工艺兼容，因而被广泛用于集成电路设计中。
LDMOS集成器件包括N沟道LDMOS(NLDMOS)器件和P沟道LDMOS(PLDMOS)器件。在LDMOS集成器件的设计过程中，如何提高LDMOS集成器件的性能有待解决。
发明内容
本发明提供一种LDMOS集成器件的制作方法，可以提高LDMOS集成器件的性能。
为了实现上述目的，本发明提供一种LDMOS器件的制作方法。所述制作方法包括：
提供一半导体基底，所述半导体基底具有NLDMOS区和PLDMOS区；所述NLDMOS区中形成有P型体区和N型漂移区，所述P型体区内的顶部形成有N型源区，所述N型漂移区内的顶部形成有N型漏区，所述NLDMOS区上形成有第一栅极结构；所述PLDMOS区中形成有N型体区和P型漂移区，所述N型体区内的顶部形成有P型源区，所述P型漂移区内的顶部形成有P型漏区，所述PLDMOS区上形成有第二栅极结构；
于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度；
执行热处理，以调整所述应力材料层的应力，提升器件的电子迁移率；
去除所述应力材料层。
可选的，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：仅于所述NLDMOS区上的介质层上形成张应力材料层。
可选的，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：
形成覆盖所述半导体基底和所述第一栅极结构和所述第二栅极结构的介质材料层；
形成覆盖所述介质材料层的张应力材料层；
在所述张应力材料层上形成图形化的第一掩模层，所述第一掩模层至少暴露所述PLDMOS区上的张应力材料层，以所述第一掩模层为掩模，去除所述PLDMOS区上的张应力材料层，所述NLDMOS区上的剩余的张应力材料层至少覆盖所述N型漂移区；
继续基于所述第一掩模层，所述第一掩模层至少暴露所述PLDMOS区上的介质材料层，刻蚀去除部分厚度的介质材料层，使得所述NLDMOS区上的至少所述N型漂移区上的介质材料层的厚度大于所述PLDMOS区上的剩余介质材料层的厚度，所述NLDMOS区上的剩余的介质材料层为所述NLDMOS区上的介质层，所述PLDMOS区上的剩余介质材料层为所述PLDMOS区上的介质层。
可选的，在所述张应力材料层上形成图形化的第一掩模层，所述第一掩模层至少暴露所述PLDMOS区上的张应力材料层，以所述第一掩模层为掩模，去除所述PLDMOS区上的张应力材料层，所述NLDMOS区上的剩余的张应力材料层至少覆盖所述N型漂移区，包括：
所述NLDMOS区上的剩余的张应力材料层还从所述N型源区经所述第一栅极结构延伸覆盖至所述N型漏区。
可选的，所述PLDMOS区上的介质层的厚度为600埃～1200埃。
可选的，所述介质材料层的厚度为1000埃～1800埃。
可选的，所述张应力材料层的厚度为150埃～600埃。
可选的，在所述去除所述应力材料层后，包括：
图形化所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，以露出所述N型源区、所述N型漏区、部分所述第一栅极结构、所述P型源区、所述P型漏区和部分所述第二栅极结构；
在所述P型漂移区和/或所述N型漂移区上方形成悬置型导电插塞，所述悬置型导电插塞的底部停留在所述P型漂移区和/或所述N型漂移区的上方，且与所述P型漂移区和/或所述N型漂移区的上表面间隔预设距离。
可选的，在所述图形化所述NLDMOS上的介质层和所述PLDMOS区上的介质层，以露出所述N型源区、所述N型漏区、部分所述第一栅极结构、所述P型源区、所述P型漏区和部分所述第二栅极结构后，
以及在所述P型漂移区和/或所述N型漂移区上方形成悬置型导电插塞之前，包括：
在图形化后的所述NLDMOS上的介质层上和所述PLDMOS区上的介质层上形成硅化物阻挡层；
在露出的所述N型源区、所述N型漏区、部分所述第一栅极结构、所述P型源区、所述P型漏区和部分所述第二栅极结构的上表面形成金属硅化物层；
在所述半导体基底上形成层间介质层，形成贯穿所述层间介质层的所述N型源区、所述N型漏区、所述第一栅极结构、所述P型源区、所述P型漏区 和所述第二栅极结构的接触型导电插塞；
在形成所述接触型导电插塞的同时形成所述悬置型导电插塞，所述悬置型导电插塞的底部停留在所述硅化物阻挡层的上表面，所述悬置型导电插塞的径向尺寸大于所述接触型导电插塞的径向尺寸。
可选的，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：仅于所述PLDMOS区上的介质层上形成压应力材料层。
可选的，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：
形成覆盖所述半导体基底和所述第一栅极结构和所述第二栅极结构的介质材料层；
形成覆盖所述介质材料层的压应力材料层；
在所述压应力材料层上形成图形化的第二掩模层，所述第二掩模层至少暴露所述NLDMOS区上的压应力材料层，以所述第二掩模层为掩模，去除所述NLDMOS区上的压应力材料层，所述PLDMOS区上的剩余的压应力材料层至少覆盖所述P型漂移区；
去除所述第二掩模层，在所述NLDMOS区上的介质材料层上形成附加介质材料层，使得所述NLDMOS区上的介质材料层与所述附加介质材料层的总厚度大于所述PLDMOS区上的介质材料层的厚度，所述NLDMOS区上的介质材料层与所述附加介质材料层共同成为所述NLDMOS区上的介质层，所述PLDMOS区上的介质材料层为所述PLDMOS区上的介质层。
本发明的LDMOS集成器件的制作方法中，半导体基底具有NLDMOS区和PLDMOS区，于所述半导体基底上形成NLDMOS区上的介质层和PLDMOS区上的介质层，于NLDMOS区上的介质层上和/或PLDMOS区上的 介质层上形成应力材料层，再执行热处理，以调整应力材料层的应力，能够提升NLDMOS器件和/或PLDMOS器件的电子迁移率，进而能够提高LDMOS集成器件的性能；而且，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，即既能使NLDMOS区的Big contact下的介质层厚度满足其RESURF需求，又能使PLDMOS区的Big contact下的介质层厚度满足其RESURF需求，可以整体提升LDMOS集成器件的Big contact的RESURF能力。此外，针对所述NLDMOS区上的介质层的厚度或所述PLDMOS区上的介质层的厚度，可以重新调整LDMOS集成器件的注入条件，降低LDMOS集成器件的导通电阻，有助于进一步提高LDMOS集成器件中PLDMOS器件的性能，最终实现在同一工艺流程中同时制备高性能NLDMOS和高性能PLDMOS。
附图说明
图1为本发明一实施例的LDMOS集成器件的制作方法的流程示意图。
图2至图5为利用本发明一实施例的LDMOS集成器件的制作方法制作LDMOS集成器件的过程结构剖面示意图。
附图标记说明：10-半导体基底；100a-NLDMOS区；100b-PLDMOS区；101-N型漏区；102-N型源区；103-第一栅极结构；104-P型体区引出区；105-P型漏区；106-P型源区；107-第二栅极结构；108-N型体区引出区；109-介质材料层；109a-NLDMOS区上的介质层；109b-PLDMOS区上的介质层；110-张应力材料层；111-硅化物阻挡层；112-层间介质层；113a-悬停型导电插塞；113b-接触型导电插塞；114-金属硅化物。
具体实施方式
以下结合附图和具体实施例对本发明提出的LDMOS集成器件的制作方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、 明晰地辅助说明本发明实施例的目的。
在LDMOS集成器件的设计和制备过程中，发明人研究发现只能先以NLDMOS为主调节工艺流程，再以相同的工艺流程去开发PLDMOS，这样往往仅能够使NLDMOS开发到最优特性，而无法使PLDMOS达到最优特性。
此外，发明人还研究发现，BCD工艺制程中常用RESURF(降低表面电场)技术来降低PLDMOS或NLDMOS漂移区的表面电场以提高PLDMOS或NLDMOS的耐压性能。其中，对于使用Big contact(大接触孔，用于设置导电插塞)降低表面电场的方式，Big contact下的介质层厚度决定了RESURF效果。为了确保RESURF效果不受影响，这就需要在SAB OX(硅化物阻挡氧化层)后长一层SiN作为悬停Big contact的刻蚀阻挡层，也即Big contact的底部需悬停在SiN上，避免Big contact下的介质层不被过刻蚀，以增强RESURF效果，提高PLDMOS或NLDMOS的耐压性能。
然而，上述引入的SiN又会对PLDMOS或NLDMOS的器件性能产生额外的影响。因为对SiN进行退火处理时，由于SiN应力的变化会对NLDMOS产生较大(+5％)的电流正增益，但对相应的PLDMOS电流产生更大的电流负增益(-10％以上甚至失效)。也即，在LDMOS集成器件制备过程中，虽然引入SiN提升了NLDMOS的Big contact的RESURF能力，以及利用SAB OX层次对晶圆施加应力也提升了NLDMOS性能，但是会使其他器件(例如PLDMOS)的性能退化并失效，无法满足实际工艺生产中同时制备高性能NLDMOS和高性能PLDMOS的需求。
为了在提高LDMOS集成器件的性能的同时，既能提升LDMOS集成器件的Big contact的RESURF能力，又能实现高性能NLDMOS和高性能PLDMOS的同时制备，本实施例提供一种LDMOS集成器件的制作方法。
图1示出了本实施例的LDMOS集成器件的制作方法的流程，如图1所示，所述LDMOS集成器件的制作方法包括：
S1，提供一半导体基底，所述半导体基底具有NLDMOS区和PLDMOS区；所述NLDMOS区中形成有P型体区和N型漂移区，所述P型体区内的顶部形成有N型源区，所述N型漂移区内的顶部形成有N型漏区，所述 NLDMOS区上形成有第一栅极结构；所述PLDMOS区中形成有N型体区和P型漂移区，所述N型体区内的顶部形成有P型源区，所述P型漂移区内的顶部形成有P型漏区，所述PLDMOS区上形成有第二栅极结构；
S2，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度；
S3，执行热处理，以调整所述应力材料层的应力，提升器件的电子迁移率；
S4，去除所述应力材料层。
图2至图5为利用本发明一实施例的LDMOS集成器件的制作方法制作LDMOS集成器件的过程结构剖面示意图。以下结合图1至图5对本实施例的LDMOS集成器件的制作方法进行说明。
如图2所述，所述半导体基底10可以是硅基底。但不限于此，所述半导体基底10还可以为锗基底、硅锗基底或绝体上硅等。本实施例中，所述半导体基底10为P型。在其它实施例中，所述半导体基底10可以为N型。
所述半导体基底10具有NLDMOS区100a和PLDMOS区100b。所述NLDMOS区100a可以用于形成NLDMOS器件。所述PLDMOS区100b可以用于形成PLDMOS器件。
所述NLDMOS区100a中形成有P型体区(Pbody)和N型漂移区(N-Drift-Area)，所述P型体区内的顶部形成有N型源区102，所述N型漂移区内的顶部形成有N型漏区101，所述NLDMOS区100a上形成有第一栅极结构103。所述第一栅极结构103至少形成在所述N型源区102与所述N型漂移区之间的半导体基底的上表面。所述N型源区102可以侧向伸入到所述第一栅极结构103的下方。本实施例中，所述N型漂移区包围所述P型体区。在其他实施例中，所述P型体区和所述N型漂移区相邻。在其他实施例中，P型体区与N型漂移区间隔设置。
所述PLDMOS区100b中形成有N型体区(Nbody)和P型漂移区 (P-Drift-Area)，所述N型体区内的顶部形成有P型源区106，所述P型漂移区内的顶部形成有P型漏区105，所述PLDMOS区100b上形成有第二栅极结构107。所述第二栅极结构107至少形成在所述P型源区106与所述P型漂移区之间的半导体基底的上表面。所述P型源区106可以侧向伸入到所述第二栅极结构107的下方。本实施例中，所述P型漂移区包围所述N型体区。在其他实施例中，所述P型体区和所述N型漂移区相邻。在其他实施例中，N型体区与P型漂移区间隔设置。
如图2所示，所述P型体区顶部还可以形成有P型体区引出区104，所述P型体区引出区104位于所述N型源区102的远离所述第一栅极结构103的一侧，且所述P型体区引出区104的掺杂浓度大于所述P型体区的掺杂浓度。所述N型体区顶部还可以形成有N型体区引出区108，所述N型体区引出区108位于所述P型漏区105的远离第二栅极结构107的一侧，且N型体区引出区108的掺杂浓度大于所述N型体区的掺杂浓度。
参考图2，所述NLDMOS区100a和所述PLDMOS区100b之间可以通过隔离结构11隔离。所述隔离结构11可以为浅沟槽隔离(STI)、结隔离或局部硅氧化隔离(LOCOS)。
一实施例中，对于步骤S2，可以仅于所述NLDMOS区上的介质层上形成张应力材料层。以下以“步骤S2仅于所述NLDMOS区上的介质层上形成张应力材料层”为例进行说明。
参考图2至图3，步骤S2可以包括子步骤S21至S24。
子步骤S21，如图2所示，形成覆盖所述半导体基底10和所述第一栅极结构103和所述第二栅极结构107的介质材料层109。
所述介质材料层109的材料可以包括氧化硅。所述介质材料层109的厚度可以为1000埃～1800埃。但不限于此，介质材料层109的厚度可以根据NLDMOS器件的实际情况调整。
子步骤S22，如图2所示，形成覆盖所述介质材料层109的张应力材料层110。
所述张应力材料层110的材料可以包括氮化硅和氮氧化硅中的至少一种。 所述张应力材料层110的厚度可以为150埃～600埃。但不限于此，张应力材料层110的厚度可以根据NLDMOS器件的实际情况调整。
子步骤S23，如图3所示，在所述张应力材料层110上形成图形化的第一掩模层(图中未示出)，所述第一掩模层至少暴露所述PLDMOS区100b上的张应力材料层，以所述第一掩模层为掩模，去除所述PLDMOS区100b上的张应力材料层，所述NLDMOS区100a上的剩余的张应力材料层至少覆盖所述N型漂移区。
一实施例中，于步骤S23，所述NLDMOS区100a上的剩余的张应力材料层可以从所述N型源区102经所述第一栅极结构103延伸覆盖至所述N型漏区101，如此后续在执行热处理时，剩余的张应力材料层110可以对NLDMOS器件的N沟道区(位于第一栅极结构103下方)和N型漂移区均施加张应力，进而可以提高NLDMOS器件的N型漂移区和N沟道区的电子迁移率，有助于在不降低关态击穿电压的前提下降低NLDMOS器件的导通电阻，提升NLDMOS器件的饱和电流能力，提高NLDMOS器件的性能。
子步骤S24，如图3所示，继续基于所述第一掩模层，所述第一掩模层至少暴露所述PLDMOS区100b上的介质材料层，刻蚀去除部分厚度的介质材料层，使得所述NLDMOS区100a上的至少所述N型漂移区上的介质材料层的厚度大于所述PLDMOS区100b上的剩余介质材料层的厚度，所述NLDMOS区100a上的剩余的介质材料层为所述NLDMOS区上的介质层109a，所述PLDMOS区100b上的剩余介质材料层为所述PLDMOS区上的介质层109b。
需要说明的是，当所述第一掩模层仅覆盖所述N型漂移区而露出NLDMOS区的其它区域，再基于所述第一掩模层刻蚀介质材料层109时，NLDMOS区100a未被第一掩模层覆盖的介质材料层也会被刻蚀去除部分厚度。
步骤S23和步骤S24中，仅利用一次光刻(以第一掩模层为掩模)以及配合相应的一次刻蚀工艺，可以保留NLDMOS区100a上的张应力材料层且去除PLDMOS区100b上的张应力材料层，在提升NLDMOS的电子迁移率的同时不会对PLDMOS的器件性能产生负面影响。同时利用同样的第一掩模层 刻蚀去除PLDMOS区100b上的介质材料层的部分厚度，实现NLDMOS区上的介质层109a的厚度大于PLDMOS区上的介质层109b的厚度，使得NLDMOS区的Big contact下的介质层厚度和PLDMOS区的Big contact下的介质层厚度均满足各自的RESURF需求。也即，既能使NLDMOS区的Big contact下的介质层厚度满足其RESURF需求，又能使PLDMOS区的Big contact下的介质层厚度满足其RESURF需求。
已有的LDMOS集成器件的制备工艺中，如果既要提升LDMOS集成器件的Big contact的RESURF能力，又要同时提升NLDMOS和PLDMOS的器件性能，需要对NLDMOS和PLDMOS分开制备，则需要额外增加两次光刻和刻蚀制程，也即NLDMOS的SiN的一次光刻和一次刻蚀，PLDMOS的SiN的一次光刻和一次刻蚀。本实施步骤S23和步骤S24中，只需新增一次光刻和刻蚀，既能提升LDMOS集成器件的Big contact的RESURF能力，又能同时提升NLDMOS和PLDMOS的器件性能。
此外，由于NLDMOS区上的介质层109a的厚度大于PLDMOS区上的介质层109b的厚度，从而可以重新调整PLDMOS器件的注入条件(例如适当增加PLDMOS器件中的P型漂移区的掺杂浓度)，能够降低PLDMOS器件的导通电阻，提高PLDMOS器件的性能，如此，有助于实现NLDMOS器件和PLDMOS器件性能的同时提高。
一实施例中，可以通过过刻蚀工艺刻蚀去除所述PLDMOS区100b上的介质材料层109的部分厚度，使得所述PLDMOS区上的介质层109b的厚度小于所述NLDMOS区上的介质层109a的厚度。所述过刻蚀工艺可以通过运行刻蚀机台中的OVER ETCH程式来实现。作为示例，通过调控过刻蚀的时间可以控制PLDMOS区100b上的介质材料层109被去除的厚度。在其它实施例中，可以利用本领域其它公知的刻蚀方法刻蚀去除介质材料层109的部分厚度。
一实施例中，所述PLDMOS区上的介质层109b的厚度为600埃～1200埃。但不限于此，可以根据PLDMOS器件的实际情况调整PLDMOS区上的介质层109b的剩余厚度。
在步骤S24后，可以去除张应力材料层110上的第一掩模层。本实施例中，可以采用本领域公知的去除掩模版的工艺去除所述第一掩模层。
接着，执行步骤S3，包括：执行热处理，以调整剩余的张应力材料层110的应力，提升NLDMOS器件的电子迁移率。
本实施例中，所述热处理采用的工艺可以为快速热处理(RTA)工艺或镭射回火(Laser anneal)工艺。但不限于此，还可以采用本领域公知的其它热处理工艺对张应力材料层110(或者说半导体基体10)进行热处理。
如图4所示，步骤S4可以包括：去除张应力材料层110。本实施例中可以采用湿法刻蚀工艺或干法刻蚀工艺去除张应力材料层110。
另一实施例中，于步骤S2，可以仅于所述PLDMOS区上的介质层上形成压应力材料层。步骤S2具体可以包括：形成覆盖所述半导体基底10和所述第一栅极结构103和所述第二栅极结构107的介质材料层；形成覆盖所述介质材料层的压应力材料层；在所述压应力材料层上形成图形化的第二掩模层，所述第二掩模层至少暴露所述NLDMOS区100a上的压应力材料层，以所述第二掩模层为掩模，去除所述NLDMOS区100a上的压应力材料层，所述PLDMOS区100b上的剩余的压应力材料层至少覆盖所述P型漂移区；去除所述第二掩模层，在所述NLDMOS区100a上的介质材料层上形成附加介质材料层，使得所述NLDMOS区100a上的介质材料层与所述附加介质材料层的总厚度大于所述PLDMOS区100b上的介质材料层的厚度，所述NLDMOS区100a上的介质材料层与所述附加介质材料层共同成为所述NLDMOS区上的介质层，所述PLDMOS区上的介质材料层为所述PLDMOS区上的介质层。
如此，后续PLDMOS区100b上的压应力材料层至少可以向所述P型漂移区施加压应力，有助于提升PLDMOS器件的电子迁移率且不会对NLDMOS的器件性能产生负面影响，提高LDMOS集成器件的性能。同时，可以实现NLDMOS区上的介质层的厚度大于PLDMOS区上的介质层的厚度，使得NLDMOS区的Big contact下的介质层厚度和PLDMOS区的Big contact下的介质层厚度均满足各自的RESURF需求，从而能够整体提升LDMOS集成器件的Big contact的RESURF能力。此外，可以配合调整PLDMOS器件的注 入条件，降低PLDMOS器件的导通电阻，有助于进一步提高LDMOS集成器件中PLDMOS器件的性能。该实施例中，步骤S3可以包括：执行热处理，以调整压应力材料层的应力。步骤S4可以包括：去除所述压应力材料层。
在步骤S4之后，所述LDMOS集成器件的制作方法还可以包括步骤S5至S6。
步骤S5，图形化所述NLDMOS区上的介质层109a和所述PLDMOS区上的介质层109b，以露出所述N型源区102、所述N型漏区101、部分所述第一栅极结构103、所述P型源区106、所述P型漏区105和部分第二栅极结构107。
步骤S6，如图5所示，在所述P型漂移区和/或所述N型漂移区上方形成悬置型导电插塞113a，所述悬置型导电插塞113的底部停留在所述P型漂移区和/或所述N型漂移区的上方，且与所述P型漂移区和/或所述N型漂移区的上表面间隔预设距离。
在步骤S5后且在步骤S6前，所述LDMOS集成器件的制作方法还可以包括：如图5所示，在图形化后的所述NLDMOS上的介质层109a上和所述PLDMOS区上的介质层109b上形成硅化物阻挡层111，即在剩余的NLDMOS区上的介质层109a上和在剩余的PLDMOS区上的介质层109b上形成硅化物阻挡层111；在露出的所述N型源区102、所述N型漏区101、部分所述第一栅极结构103、所述P型源区106、所述P型漏区105和部分所述第二栅极结构107的上表面形成金属硅化物层114(图5仅示出了部分金属硅化物层114)；在所述半导体基底10上形成层间介质层112，形成贯穿所述层间介质层112的所述N型源区102、所述N型漏区101、所述第一栅极结构103、所述P型源区106、所述P型漏区105和所述第二栅极结构107的接触型导电插塞113b。
其中，在形成所述接触型导电插塞113b的同时形成所述悬置型导电插塞113a，所述悬置型导电插塞113a的底部停留在所述硅化物阻挡层111的上表面，所述悬置型导电插塞113a的径向尺寸大于所述接触型导电插塞113b的径向尺寸。
所述硅化物阻挡层111的厚度可以为200埃～300埃。但不限于此，所述 硅化物阻挡层111的厚度可以根据需要调整。所述层间介质层112的材料可以包括氧化硅。
需要说明的是，所述悬停型导电插塞113a可以称为场板(Field Plating，FP)，能够用于降低N型漂移区和/或P型漂移区的表面电场。所述悬停型导电插塞113a的径向尺寸大于接触型导电插塞113b的径向尺寸，且PLDMOS区上的介质层109b的厚度小于NLDMOS区上的介质层109a，可以有效的降低N型漂移区和P型漂移区的表面电场，有助于提高NLDMOS器件和PLDMOS器件的性能。而且，通过配合调整PLDMOS器件的P型漂移区的注入条件，可以进一步提高PLDMOS器件的性能。
所述接触型导电插塞113b和悬停型导电插塞113a的材料均可以为钨或铝等金属材料或金属合金。
本发明的LDMOS集成器件的制作方法中，半导体基底10具有NLDMOS区100a和PLDMOS区100b，于所述半导体基底10上形成NLDMOS区上的介质层109a和PLDMOS区上的介质层109b，于NLDMOS区上的介质层109a上和/或PLDMOS区上的介质层109b上形成应力材料层，再执行热处理，以调整应力材料层的应力，能够提升NLDMOS器件和/或PLDMOS器件的电子迁移率，进而能够提高LDMOS集成器件的性能；而且，所述NLDMOS区上的介质层109a的厚度大于所述PLDMOS区上的介质层109b的厚度，即既能使NLDMOS区的Big contact下的介质层厚度满足其RESURF需求，又能使PLDMOS区的Big contact下的介质层厚度满足其RESURF需求，可以整体提升LDMOS集成器件的Big contact的RESURF能力，此外，针对所述NLDMOS区上的介质层109a的厚度或所述PLDMOS区上的介质层109b的厚度，可以重新调整PLDMOS器件的注入条件，降低LDMOS集成器件的导通电阻，有助于进一步提高LDMOS集成器件中PLDMOS器件的性能，最终实现在同一工艺流程中同时制备高性能NLDMOS和高性能PLDMOS。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此， 凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (12)

  1. 一种LDMOS集成器件的制作方法，其特征在于，包括：
    提供一半导体基底，所述半导体基底具有NLDMOS区和PLDMOS区；所述NLDMOS区中形成有P型体区和N型漂移区，所述P型体区内的顶部形成有N型源区，所述N型漂移区内的顶部形成有N型漏区，所述NLDMOS区上形成有第一栅极结构；所述PLDMOS区中形成有N型体区和P型漂移区，所述N型体区内的顶部形成有P型源区，所述P型漂移区内的顶部形成有P型漏区，所述PLDMOS区上形成有第二栅极结构；
    于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度；
    执行热处理，以调整所述应力材料层的应力，提升器件的电子迁移率；
    去除所述应力材料层。
  2. 如权利要求1所述的制作方法，其特征在于，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：仅于所述NLDMOS区上的介质层上形成张应力材料层。
  3. 如权利要求2所述的制作方法，其特征在于，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：
    形成覆盖所述半导体基底和所述第一栅极结构和所述第二栅极结构的介质材料层；
    形成覆盖所述介质材料层的张应力材料层；
    在所述张应力材料层上形成图形化的第一掩模层，所述第一掩模层至少 暴露所述PLDMOS区上的张应力材料层，以所述第一掩模层为掩模，去除所述PLDMOS区上的张应力材料层，所述NLDMOS区上的剩余的张应力材料层至少覆盖所述N型漂移区；
    继续基于所述第一掩模层，所述第一掩模层至少暴露所述PLDMOS区上的介质材料层，刻蚀去除部分厚度的介质材料层，使得所述NLDMOS区上的至少所述N型漂移区上的介质材料层的厚度大于所述PLDMOS区上的剩余介质材料层的厚度，所述NLDMOS区上的剩余的介质材料层为所述NLDMOS区上的介质层，所述PLDMOS区上的剩余介质材料层为所述PLDMOS区上的介质层。
  4. 如权利要求3所述的制作方法，其特征在于，在所述张应力材料层上形成图形化的第一掩模层，所述第一掩模层至少暴露所述PLDMOS区上的张应力材料层，以所述第一掩模层为掩模，去除所述PLDMOS区上的张应力材料层，所述NLDMOS区上的剩余的张应力材料层至少覆盖所述N型漂移区，包括：
    所述NLDMOS区上的剩余的张应力材料层还从所述N型源区经所述第一栅极结构延伸覆盖至所述N型漏区。
  5. 如权利要求2或3所述的制作方法，其特征在于，所述PLDMOS区上的介质层的厚度为600埃～1200埃。
  6. 如权利要求3所述的制作方法，其特征在于，所述介质材料层的厚度为1000埃～1800埃。
  7. 如权利要求2或3所述的制作方法，其特征在于，所述张应力材料层的厚度为150埃～600埃。
  8. 如权利要求1所述的制作方法，其特征在于，在所述去除所述应力材料层后，包括：
    图形化所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，以露出所述N型源区、所述N型漏区、部分所述第一栅极结构、所述P型源区、所述P型漏区和部分所述第二栅极结构；
    在所述P型漂移区和/或所述N型漂移区上方形成悬置型导电插塞，所述 悬置型导电插塞的底部停留在所述P型漂移区和/或所述N型漂移区的上方，且与所述P型漂移区和/或所述N型漂移区的上表面间隔预设距离。
  9. 如权利要求8所述的制作方法，其特征在于，在所述图形化所述NLDMOS上的介质层和所述PLDMOS区上的介质层，以露出所述N型源区、所述N型漏区、部分所述第一栅极结构、所述P型源区、所述P型漏区和部分所述第二栅极结构后，
    以及在所述P型漂移区和/或所述N型漂移区上方形成悬置型导电插塞之前，包括：
    在图形化后的所述NLDMOS上的介质层上和所述PLDMOS区上的介质层上形成硅化物阻挡层；
    在露出的所述N型源区、所述N型漏区、部分所述第一栅极结构、所述P型源区、所述P型漏区和部分所述第二栅极结构的上表面形成金属硅化物层；
    在所述半导体基底上形成层间介质层，形成贯穿所述层间介质层的所述N型源区、所述N型漏区、所述第一栅极结构、所述P型源区、所述P型漏区和所述第二栅极结构的接触型导电插塞；
    在形成所述接触型导电插塞的同时形成所述悬置型导电插塞，所述悬置型导电插塞的底部停留在所述硅化物阻挡层的上表面，所述悬置型导电插塞的径向尺寸大于所述接触型导电插塞的径向尺寸。
  10. 如权利要求1所述的制作方法，其特征在于，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的厚度，包括：仅于所述PLDMOS区上的介质层上形成压应力材料层。
  11. 如权利要求10所述的制作方法，其特征在于，于所述半导体基底上形成所述NLDMOS区上的介质层和所述PLDMOS区上的介质层，于所述NLDMOS区上的介质层上和/或所述PLDMOS区上的介质层上形成应力材料层，所述NLDMOS区上的介质层的厚度大于所述PLDMOS区上的介质层的 厚度，包括：
    形成覆盖所述半导体基底和所述第一栅极结构和所述第二栅极结构的介质材料层；
    形成覆盖所述介质材料层的压应力材料层；
    在所述压应力材料层上形成图形化的第二掩模层，所述第二掩模层至少暴露所述NLDMOS区上的压应力材料层，以所述第二掩模层为掩模，去除所述NLDMOS区上的压应力材料层，所述PLDMOS区上的剩余的压应力材料层至少覆盖所述P型漂移区；
    去除所述第二掩模层，在所述NLDMOS区上的介质材料层上形成附加介质材料层，使得所述NLDMOS区上的介质材料层与所述附加介质材料层的总厚度大于所述PLDMOS区上的介质材料层的厚度，所述NLDMOS区上的介质材料层与所述附加介质材料层共同成为所述NLDMOS区上的介质层，所述PLDMOS区上的介质材料层为所述PLDMOS区上的介质层。
  12. 如权利要求9所述的制作方法，其特征在于，所述硅化物阻挡层的厚度为200埃～300埃。
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US20170222042A1 (en) * 2016-01-28 2017-08-03 Texas Instruments Incorporated Soi power ldmos device
CN108574014A (zh) * 2017-03-13 2018-09-25 中芯国际集成电路制造(上海)有限公司 Ldmos器件及其制造方法
CN110556388A (zh) * 2019-09-07 2019-12-10 电子科技大学 一种可集成功率半导体器件及其制造方法
CN112825327A (zh) * 2019-11-21 2021-05-21 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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Publication number Priority date Publication date Assignee Title
US20170222042A1 (en) * 2016-01-28 2017-08-03 Texas Instruments Incorporated Soi power ldmos device
CN108574014A (zh) * 2017-03-13 2018-09-25 中芯国际集成电路制造(上海)有限公司 Ldmos器件及其制造方法
CN110556388A (zh) * 2019-09-07 2019-12-10 电子科技大学 一种可集成功率半导体器件及其制造方法
CN112825327A (zh) * 2019-11-21 2021-05-21 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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