WO2023097909A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023097909A1
WO2023097909A1 PCT/CN2022/078090 CN2022078090W WO2023097909A1 WO 2023097909 A1 WO2023097909 A1 WO 2023097909A1 CN 2022078090 W CN2022078090 W CN 2022078090W WO 2023097909 A1 WO2023097909 A1 WO 2023097909A1
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Prior art keywords
layer
region
interconnection
interconnection layer
forming
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PCT/CN2022/078090
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English (en)
French (fr)
Inventor
王晓光
李辉辉
章纬
曹堪宇
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Changxin Memory Technologies Inc
Beijing Superstring Academy of Memory Technology
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Changxin Memory Technologies Inc
Beijing Superstring Academy of Memory Technology
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Priority to US17/827,799 priority Critical patent/US20230171969A1/en
Publication of WO2023097909A1 publication Critical patent/WO2023097909A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
  • Magnetic Random Access Memory is based on the integration of silicon-based complementary oxide semiconductor and magnetic tunnel junction technology. It is a non-volatile memory with Static Random Access Memory (SRAM) , referred to as SRAM) high-speed read and write capabilities, and dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) high integration.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • a first aspect of an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, which includes:
  • the substrate comprising a peripheral circuit area adjacently arranged and an array area having memory cells, the peripheral circuit area including a first region and a second region adjacently arranged;
  • a logic device is formed in the first region and a magnetic storage device is formed in the second region by using the same manufacturing process, the manufacturing process is a process for manufacturing a dynamic random access memory, wherein the logic device and the The memory cells are connected to control the memory cells, and the magnetic memory device includes an access transistor and a magnetic tunnel junction connected to the access transistor.
  • the steps of forming logic devices in the first region and forming magnetic storage devices in the second region by using the same manufacturing process include:
  • a first interconnection structure is formed on the substrate located in the first region and the second region, the first interconnection structure includes a first interconnection layer and a second interconnection layer, and the first interconnection layer connected to the logic transistor, the second interconnection layer connected to the access transistor;
  • a second interconnection structure is formed over the first interconnection layer and the magnetic tunnel junction, the second interconnection structure includes a third interconnection layer and a fourth interconnection layer, the third interconnection layer and The first interconnection layer is electrically connected, the fourth interconnection layer is electrically connected to the magnetic tunnel junction, wherein the logic transistor, the first interconnection layer and the third interconnection layer
  • the logic device is constituted, and the access transistor, the second interconnection layer, the magnetic tunnel junction and the fourth interconnection layer constitute a magnetic storage device.
  • the step of providing the base includes:
  • the steps of forming logic transistors in the first region and forming access transistors in the second region include:
  • the active region, the gate oxide layer, the gate and the protective layer in the second region constitute the access transistor.
  • the preparation method further includes:
  • a plurality of conductive plugs are formed in the first dielectric layer, the conductive plugs located in the first region are used to connect the first interconnection layer and logic transistors, and the conductive plugs located in the second region The conductive plug is used to connect the first interconnection layer and the access transistor.
  • the step of forming a plurality of conductive plugs in the first dielectric layer includes:
  • first dielectric layer patterning the first dielectric layer to form a plurality of first through holes spaced apart in the first dielectric layer, each of the first through holes exposing a source region or a drain region of the active region ;
  • a conductive material is deposited in each of the first via holes to form the conductive plug.
  • the step of forming the first interconnect structure on the substrates of the first region and the second region includes:
  • the remaining first conductive layer constitutes a first interconnection layer in the first region, and the remaining first conductive layer in the second region A second interconnection layer is formed therein, and the first interconnection layer and the second interconnection layer are respectively electrically connected to the conductive plugs.
  • the projections of the first interconnection layer and the second interconnection layer respectively cover the projections of the electrically connected conductive plugs.
  • the step of forming a magnetic tunnel junction on the second interconnection layer includes:
  • a part of the magnetic layer is removed to retain a magnetic layer on one of the second interconnection layers above the second region, and the retained magnetic layer forms a magnetic tunnel junction.
  • the The preparation method after the step of forming a magnetic tunnel junction on the second interconnect layer and before the step of forming a second interconnect structure over the first interconnect layer and the magnetic tunnel junction, the The preparation method also includes:
  • First through-silicon vias and second through-silicon vias arranged at intervals are formed in the third dielectric layer, the first through-silicon vias are located above the first region and connected to one of the first interconnection layers Electrically connected, the second TSV is located above the second region and electrically connected to the magnetic tunnel junction.
  • the step of forming a second interconnect structure over the first interconnect layer and the magnetic tunnel junction includes:
  • the remaining second conductive layer forms a third interconnection layer in the first region, and the remaining second conductive layer forms a third interconnection layer in the second region
  • a fourth interconnection layer is formed inside.
  • the step of forming a stacked gate oxide layer and a gate on the first region and the second region of the substrate includes:
  • the second aspect of the embodiments of the present disclosure provides a semiconductor structure, which is manufactured by the method for preparing the semiconductor structure in the above embodiments, including:
  • the substrate includes a peripheral circuit area adjacently arranged and an array area having memory cells, and the peripheral circuit area includes a first area and a second area adjacently arranged;
  • the logic device is arranged in the first region and connected to the storage unit to control the storage unit;
  • a magnetic storage device the magnetic storage device is disposed in the second region, wherein the magnetic storage device includes an access transistor and a magnetic tunnel junction connected to the access transistor.
  • the logic device includes a logic transistor, a first interconnection layer, and a third interconnection layer, and the first interconnection layer and the third interconnection layer are stacked on the logic transistor;
  • the first interconnection layer is connected to the logic transistor through a conductive plug located above the first region, and the third interconnection layer is connected to the first interconnection layer through a first through-silicon via.
  • the magnetic memory device further includes a second interconnection layer and a fourth interconnection layer, the second interconnection layer is disposed between the access transistor and the magnetic tunnel junction, so that The access transistor is electrically connected to the magnetic tunnel junction;
  • the fourth interconnection layer is disposed on the magnetic tunnel junction and is electrically connected to the magnetic tunnel junction.
  • the second interconnection layer is connected to the access transistor through a conductive plug on the second region, and the fourth interconnection layer is connected to the magnetic tunnel junction through a second silicon via. connect.
  • FIG. 1 is a process flow diagram 1 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a distribution diagram of an array region and a peripheral circuit region in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a substrate in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4 is a second process flow diagram of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of logic transistors and access transistors formed in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a first dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of forming a first through hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of forming a conductive plug in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of forming a first conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a first interconnection structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of forming a second dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Fig. 12 is a schematic structural diagram of forming a magnetic layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of forming a magnetic tunnel junction in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of forming a third dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 15 is a schematic structural diagram of forming a first through-silicon via and a second through-silicon via in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of forming a second conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of forming a second interconnection structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • 50 first interconnection structure
  • 51 first interconnection layer
  • 52 second interconnection layer
  • 53 first conductive layer
  • 80 the third dielectric layer; 81: the first TSV; 82: the second TSV;
  • 110 a logic device
  • 120 a magnetic storage device.
  • MRAM magnetic random access memory
  • logic devices and magnetic storage devices used to control memory cells are simultaneously prepared in the peripheral circuit area, so that the same semiconductor structure has two storage structures at the same time.
  • the production can be simplified. steps to reduce production costs; in addition, the magnetic storage device is prepared through the process of preparing the dynamic random access memory, which can improve the integration degree of the magnetic storage device and facilitate the development of the semiconductor structure towards integration.
  • the method for preparing a semiconductor structure includes the following steps:
  • Step S100 providing a substrate, the substrate includes an adjacent peripheral circuit area and an array area with memory cells, the peripheral circuit area includes a first area and a second area adjacent to each other.
  • the substrate 10 includes a peripheral circuit area 11 and an array area 12 arranged adjacently.
  • the storage function of the memory is realized, wherein the storage unit may be a DRAM device, that is, a storage unit includes a read transistor and a capacitor.
  • a plurality of active regions 13 and isolation structures 14 for separating each active region 13 are formed in the substrate 10, that is to say, the active regions 13 exist in both the peripheral circuit region 11 and the array region. within 12.
  • the preparation process of the isolation structure 14 may be as follows: first pattern the substrate 10 to form an isolation trench in the substrate 10, and then use a deposition process to deposit an insulating material in the isolation trench to form the isolation structure 14, but this is not intended to be limit.
  • the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • the material of the isolation structure 14 is an insulating material, and the insulating material includes silicon oxide, nitrogen Any one or any combination of silicon oxide, silicon oxynitride or silicon carbonitride.
  • the peripheral circuit area 11 includes a first area 111 and a second area 112 that are adjacently arranged, wherein the adjacent arrangement can be understood as the first area 111 and the second area 112 are arranged side by side in a certain direction, and it can also be understood that the first area 111 and the second area 112 are arranged side by side.
  • a region 111 is arranged around the second region 112 , or the second region 112 surrounds the first region 111 .
  • Step S200 using the same preparation process to form a logic device in the first region and a magnetic storage device in the second region, the preparation process is a process for preparing a dynamic random access memory, wherein the logic device is connected to the storage unit for storage The unit is controlled, and the magnetic storage device includes an access transistor and a magnetic tunnel junction connected with the access transistor.
  • the logic device and the magnetic storage device for controlling the storage unit are simultaneously prepared in the peripheral circuit area by using the process of preparing a dynamic random access memory, so that the same semiconductor structure has two storage structures at the same time, which is different from preparing two storage structures separately.
  • the manufacturing steps can be simplified and the manufacturing cost can be reduced;
  • the magnetic memory device can be prepared by the process of preparing the dynamic random access memory, which can improve the integration degree of the magnetic memory device and facilitate the development of the semiconductor structure in the direction of integration.
  • the steps of forming logic devices in the first region and forming magnetic storage devices in the second region using the same manufacturing process include the following steps:
  • Step S210 forming logic transistors in the first region, and forming access transistors in the second region.
  • the logic transistor 20 and the access transistor 30 are formed in the same process step, and their structures are shown in FIG. 5 .
  • a channel region and a source region and a drain region respectively disposed on both sides of the channel region may be formed in the active region 13 by using an ion doping process, wherein the doping ions of the source region and the drain region are of the same type , the type of doping ions in the channel region is different from the type of doping ions in the source region.
  • a stacked gate oxide layer 21 and a gate 22 are formed on the first region 111 and the second region 112 of the substrate 10, and the gate 22 is projected on the substrate 10 to cover part of the active region 13, that is, the gate 22
  • the projection on the substrate 10 at least covers the channel region, so that the gate 22 applies a voltage to the channel region.
  • a stacked gate oxide material layer and a gate material layer may be formed on the substrate 10 located in the first region 111 and the second region 112 by using a deposition process, and the gate oxide material layer is disposed on the substrate 10, wherein
  • the material of the gate oxide material layer may include silicon oxide or other materials with a high dielectric constant, such as aluminum oxide; the material of the gate material layer may include polysilicon.
  • a conductive material layer is formed on the gate material layer, wherein the material of the conductive material layer includes copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride ( One or any combination of TiN), cobalt silicide (CoSi) and titanium aluminide (TiAl).
  • the material of the conductive material layer includes copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride ( One or any combination of TiN), cobalt silicide (CoSi) and titanium aluminide (TiAl).
  • a mask layer is formed on the conductive material layer, and the mask layer is patterned, and the patterned mask layer is used as a mask to sequentially etch the conductive material layer, the gate oxide material layer and the gate material layer, A stacked gate oxide layer 21 and a gate 22 are formed, and a word line 100 formed on the gate 22 is formed, and the gate oxide layer 21 is located on the upper surface of the substrate 10 .
  • a protective layer 23 wrapping the sides of the gate 22, the gate oxide layer 21 and the word line 100 is formed, for example, it can be deposited on the active region 13
  • An initial protection layer is formed, and the initial protection layer covers the sides of the gate oxide layer 21, the sides of the gate 22, and the sides and the top surface of the word line 100, and then uses etching gas or etching solution to remove the top surface of the word line 100.
  • the initial protection layer on the surface, the remaining initial protection layer constitutes the protection layer 23, and the isolation between the gate 22 and the word line 100 and other devices can be realized through the setting of the protection layer 23, wherein the material of the protection layer 23 can be Single-layer or multi-layer insulating material composed of silicon oxide, silicon nitride or silicon oxynitride.
  • the active region 13 located in the first region 111, the gate oxide layer 21, the gate 22, and the protection layer 23 form a logic transistor 20, and the active region 13 located in the second region 112, the gate oxide layer 21.
  • the gate 22 and the protection layer 23 form the access transistor 30, and the logic transistor 20 and the access transistor 30 are manufactured in the same process step, which can have the advantage of simplifying the manufacturing process.
  • Step S220 forming a first dielectric layer covering the logic transistor and the access transistor on the substrate.
  • a first dielectric layer 40 can be deposited on the substrate 10 by a deposition process, and the first dielectric layer 40 covers the logic transistor 20 and the access transistor 30, wherein the material of the first dielectric layer 40 can include silicon oxide Or insulating materials such as silicon nitride.
  • Step S230 forming a plurality of conductive plugs in the first dielectric layer, the conductive plugs in the first area are used to connect the first interconnection layer and logic transistors, and the conductive plugs in the second area are used to connect the first An interconnect layer and access transistors.
  • the first dielectric layer 40 is patterned to form a plurality of first through holes 41 spaced apart in the first dielectric layer 40, and each first through hole 41 exposes the active area.
  • source region or drain region for example, the number of the first through hole 41 is four, from left to right, the first first through hole 41 is used to expose the source of the active region 13 located in the first region 111 region, the second first through hole 41 is used to expose the drain region of the active region 13 located in the first region 111, and the first first through hole 41 and the second first through hole 41 are located in one Above the active region 13, the third first through hole 41 is used to expose the source region of the active region 13 located in the second region 112, and the fourth first through hole 41 is used to expose the source region located in the second region 112. 112 in the drain region of the active region 13 , and the third first through hole 41 and the fourth first through hole 41 are located above one active region 13 .
  • a conductive material is deposited in each of the first through holes 41 to form a conductive plug 42, which is used to realize the subsequent formation of the first interconnection layer and the second interconnection layer respectively connected with the source region 13 connections.
  • Step S240 forming a first interconnection structure on the substrate located in the first region and the second region, the first interconnection structure includes a first interconnection layer and a second interconnection layer, the first interconnection layer is connected to a logic transistor, The second interconnection layer is connected with the access transistor.
  • a first conductive layer 53 is formed on the first dielectric layer 40 by a deposition process, wherein the material of the first conductive layer 53 may include metal tungsten, metal aluminum, metal copper or metal titanium. kind of.
  • the first conductive layer 53 is patterned, part of the first conductive layer 53 is removed, and the first conductive layer 53 above each conductive plug 42 remains, and the remaining first conductive layer 53 is placed on the
  • the first interconnection layer 51 is formed in the first region 111, and the retained first conductive layer 53 constitutes the second interconnection layer 52 in the second region 112.
  • the first interconnection layer 51 and the second interconnection layer 52 A first interconnection structure 50 is formed, wherein the first interconnection layer 51 and the second interconnection layer 52 are respectively electrically connected to the conductive plugs 42 .
  • first interconnection layers 51 in this embodiment is two, wherein one first interconnection layer 51 is connected to the active region 13 in the first region 111 through one conductive plug 42 The source region is electrically connected, and the other first interconnection layer 51 is electrically connected to the drain region of the active region 13 located in the second region 112 through a conductive plug 42.
  • each of the second interconnection layer 52 The number is two, and its connection mode with the active region 13 located in the second region 112 is similar to the connection method between the two first interconnection layers 51 and the active region 13 located in the first region 111. In this embodiment No more details here.
  • the projections of the first interconnection layer 51 and the second interconnection layer 52 respectively cover the projections of the electrically connected conductive plugs 42 .
  • the projected area of the first interconnection layer 51 on the substrate 10 is larger than the projected area of the conductive plug 42 on the substrate 10 , so that the contact area between the first interconnection layer 51 and the conductive plug 42 can be increased, the contact resistance between the two can be reduced, and the performance of the semiconductor structure can be improved.
  • the first A second dielectric layer 60 is disposed between an interconnection layer 51 and the second interconnection layer 52 , between adjacent first interconnection layers 51 , and adjacent second interconnection layers 52 .
  • Step S250 forming a magnetic tunnel junction on the second interconnection layer.
  • a magnetic layer 71 is formed on the first interconnection structure 50 and the second dielectric layer 60 by a deposition process, and then the magnetic layer 71 is patterned to remove part of the magnetic layer 71 , the magnetic layer 71 on the second interconnection layer 52 on the second region 112 is retained, and the retained part of the magnetic layer 71 forms a magnetic tunnel junction 70, wherein the magnetic tunnel junction 70 includes a stacked fixed layer, a tunneling Layer and free layer, when the semiconductor structure is working normally, the magnetization direction of the free layer can be changed, while the magnetization direction of the fixed layer remains unchanged.
  • the magnetic storage device The resistance value of the corresponding change, corresponding to different storage information.
  • the magnetic tunnel junction 70 when the magnetic tunnel junction 70 is connected to the drain region of the access transistor 30, correspondingly, the magnetic tunnel junction 70 is formed on the conductive plug 42 connected to the drain region, and when the magnetic tunnel junction 70 is connected to the drain region of the access transistor When the source region of 30 is connected, correspondingly, a magnetic tunnel junction 70 is formed on the conductive plug 42 connected to the source region.
  • the magnetic tunnel junction 70 is formed on the second interconnection layer in the first interconnection structure by utilizing the preparation process for forming a dynamic random access memory.
  • the magnetic tunnel junction 70 is formed on the fourth interconnection layer. Compared with the solution on the connection structure, the number of magnetic storage devices per unit area can be increased, thereby improving the integration degree of the magnetic storage devices.
  • Step S260 forming a second interconnection structure above the first interconnection layer and the magnetic tunnel junction, the second interconnection structure includes a third interconnection layer and a fourth interconnection layer, the third interconnection layer and the first interconnection layer Electrically connected, the fourth interconnection layer is electrically connected to the magnetic tunnel junction, wherein the logic transistor, the first interconnection layer and the third interconnection layer form a logic device, and the access transistor, the second interconnection layer, and the magnetic tunnel junction And the fourth interconnection layer constitutes a magnetic memory device.
  • a third dielectric layer 80 is formed on the first interconnection structure 50 and the magnetic tunnel junction 70 by a deposition process, and the material of the third dielectric layer 80 may include silicon oxide and silicon nitride.
  • a first through-silicon via 81 and a second through-silicon via 82 are formed in the third dielectric layer 80 at intervals.
  • the first through-silicon via 81 is located above the first region 111 and is interconnected with the first
  • the layer 51 is electrically connected to the second TSV 82 located above the second region 112 and electrically connected to the magnetic tunnel junction 70 .
  • first TSVs 81 there are two first TSVs 81 , and the two first TSVs 81 correspond to the two first interconnection layers 51 one by one.
  • a second conductive layer 93 is formed on the third dielectric layer 80 .
  • part of the second conductive layer 93 is removed, and the remaining second conductive layer 93 forms the third interconnection layer 91 in the first region 111, and the remaining second conductive layer 93 forms the third interconnection layer 91 in the second
  • a fourth interconnection layer 92 is formed in the region, and the third interconnection layer 91 and the fourth interconnection layer 92 form a second interconnection structure 90, wherein the third interconnection layer 91 is electrically connected to the first through-silicon via 81, The fourth interconnection layer 92 is electrically connected to the second TSV 82 , and the fourth interconnection layer 92 can be used as a bit line structure of the magnetic storage device 120 .
  • the number of the third interconnection layer 91 in this embodiment is two, corresponding to the number of the first TSVs 81, taking the orientation shown in FIG. 17 as an example, from left to right , the first third interconnection layer 91 is connected to the first first interconnection layer 51 through the first first through-silicon via 81, and the second third interconnection layer 91 is also connected through the second first through-silicon via.
  • the hole 81 is connected to the second first interconnection layer 51 to avoid crosstalk in signal transmission.
  • the third interconnection layer 91 and the fourth interconnection layer 92 may be formed in other exemplary embodiments, for example, after the first through-silicon via 81 and the second through-silicon via 82 are formed, the third dielectric layer 80 An insulating layer is formed on the insulating layer, and the insulating layer is patterned to form a trench. The trench exposes the top of the first TSV 81 and the top of the second TSV 82. Conductive material is deposited in the trench, and the first TSV The conductive material electrically connected to 81 forms the third interconnection layer 91 , and the conductive material electrically connected to the second TSV 82 forms the fourth interconnection layer 92 .
  • the insulating layer is located between the third interconnection layer 91 and the fourth interconnection layer 92 for isolating the third interconnection layer 91 and the fourth interconnection layer 92 to play the role of insulation.
  • the logic transistor 20, the first interconnection layer 51 and the third interconnection layer 91 form a logic device 110
  • the access transistor 30, the second interconnection layer 52, the magnetic tunnel junction 70 and the fourth interconnection layer 92 constitutes a magnetic memory device 120 .
  • the logic device and the magnetic storage device for controlling the storage unit are simultaneously prepared in the peripheral circuit area by using the process of preparing a dynamic random access memory, so that the same semiconductor structure has two storage structures at the same time, which is different from the method of separately preparing the two storage structures.
  • the manufacturing steps can be simplified and the manufacturing cost can be reduced; in addition, the magnetic storage device can be prepared through the process of preparing the dynamic random access memory, which can improve the integration degree of the magnetic storage device and facilitate the development of the semiconductor structure towards the integration direction.
  • Embodiments of the present disclosure also provide a semiconductor structure, which is manufactured by the method for preparing the semiconductor structure in the above embodiments.
  • the semiconductor structure includes a substrate 10, a logic device 110 and a magnetic storage device 120, wherein the substrate 10 includes a peripheral circuit area 11 and an array area 12 with memory cells adjacently arranged, and the peripheral circuit area 11 includes adjacent
  • the first area 111 and the second area 112 are provided, wherein the area of the first area 111 and the area of the second area 112 may be the same or different.
  • the logic device 110 is disposed in the first region 111 and connected to the memory cells disposed in the array region 12 to control the memory cells.
  • the magnetic storage device 120 is disposed in the second region 112 , wherein the magnetic storage device includes an access transistor 30 and a magnetic tunnel junction 70 connected to the access transistor 30 .
  • the semiconductor structure has both the storage unit of the DRAM and the magnetic tunnel junction of the MRAM, so that the same semiconductor structure has two different types of storage devices, which can increase the diversity of the semiconductor structure.
  • the logic device 110 includes a logic transistor 20, a first interconnection layer 51, and a third interconnection layer 91, and the first interconnection layer 51 and the third interconnection layer 91 are stacked on the logic transistor 20, wherein , the first interconnection layer 51 is connected to the logic transistor 20 through the conductive plug 42 above the first region 111, for example, the first first interconnection layer 51 is connected to the logic transistor 20 through the first conductive plug above the first region 111 42 is connected to the source region of the logic transistor 20 , and the second first interconnection layer 51 is connected to the drain region of the logic transistor 20 through the second conductive plug 42 located above the first region 111 .
  • the third interconnection layer 91 is connected to the first interconnection layer 51 through the first through-silicon via 81, so as to realize the transmission of electrical signals between the first interconnection layer 51 and the third interconnection layer 91, wherein the first silicon
  • the material of the through hole 81 may include copper.
  • the magnetic memory device 120 further includes a second interconnection layer 52 and a fourth interconnection layer 92, the second interconnection layer 52 is disposed between the access transistor 30 and the magnetic tunnel junction 70, so that the access The transistor 30 is electrically connected to the magnetic tunnel junction 70 , that is, the upper surface of the second interconnection layer 52 is connected to the magnetic tunnel junction 70 , and the lower surface of the second interconnection layer 52 is electrically connected to the access transistor 30 .
  • the lower surface of the second interconnection layer 52 may be directly connected to the access transistor 30, or may be indirectly connected, for example, the connection between the second interconnection layer 52 and the access transistor is through the conductive plug 42 located on the second region 112. .
  • the fourth interconnection layer 92 is disposed on the magnetic tunnel junction 70 and is electrically connected to the magnetic tunnel junction 70.
  • the fourth interconnection layer 92 is connected to the magnetic tunnel junction 70 through the second silicon via 82.
  • the The second TSV 82 and the conductive plug located on the second region 112 realize the electrical connection between various components in the magnetic storage device.

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Abstract

本公开提供一种半导体结构及其制备方法，涉及半导体技术领域，该半导体结构的制备方法包括提供基底，基底包括外围电路区和具有存储单元的阵列区，外围电路区包括第一区域和第二区域；本公开利用制备动态随机存储器的工艺在外围电路区内同时制备出用于控制存储单元的逻辑器件和磁性存储器件，使得同一半导体结构同时具有两种存储结构，与单独制备两种存储结构的技术相比，可以简化制作步骤，降低制作成本；此外，通过制备动态随机存储器的工艺来制备磁性存储器件，可以提高磁性存储器件的集成度，便于半导体结构向集成化方向发展。

Description

半导体结构及其制备方法
本公开要求于2021年11月30日提交中国专利局、申请号为202111448141.6、申请名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法。
背景技术
磁性随机存取存储器(Magnetic Random Access Memory，简称MRAM)是基于硅基互补氧化物半导体与磁性隧道结技术的集成，是一种非易失性的存储器，它具有静态随机存储器(Static Random Access Memory，简称SRAM)的高速读写能力，以及动态随机存储器(Dynamic Random Access Memory，简称DRAM)的高集成度。
但是，受制备工艺的限制，在形成磁性随机存取存储器时，很难提高其集成度，不利于半导体结构向集成化方向发展。
发明内容
本公开实施例的第一方面提供一种半导体结构的制备方法，其包括：
提供基底，所述基底包括相邻设置的外围电路区和具有存储单元的阵列区，所述外围电路区包括相邻设置的第一区域和第二区域；
采用同一制备工艺在所述第一区域内形成逻辑器件和在所述第二区域内形成磁性存储器件，所述制备工艺为用于制备动态随机存储器的工艺，其中，所述逻辑器件与所述存储单元连接，以对所述存储单元进行控制，所述磁性存储器件包括存取晶体管以及与所述存取晶体管连接的磁性隧道结。
在一些实施例中，采用同一制备工艺在所述第一区域内形成逻辑器件和在所述第二区域内形成磁性存储器件的步骤中包括：
在所述第一区域内形成逻辑晶体管，以及在所述第二区域内形成存取晶体管；
在位于所述第一区域和所述第二区域的基底上形成第一互连结构，所述第一互连结构包括第一互连层和第二互连层，所述第一互连层与所述逻辑晶体管连接，所述第二互连层与存取晶体管连接；
在所述第二互连层上形成磁性隧道结；
在所述第一互连层和所述磁性隧道结上方形成第二互连结构，所述第二互连结构包括第三互连层和第四互连层，所述第三互连层与所述第一互连层电性连接，所述第四互连层与所述磁性隧道结电性连接，其中，所述逻辑晶体管、所述第一互连层以及所述第三互连层构成所述逻辑器件，所述存取晶体管、所述第二互连层、所述磁性隧道结以及所述第四互连层构成磁性存储器件。
在一些实施例中，提供基底的步骤中，包括：
在所述基底内形成多个有源区以及用于分隔各个所述有源区的隔离结构；
在所述第一区域内形成逻辑晶体管，以及在所述第二区域内形成存取晶体管的步骤中，包括：
在所述基底的第一区域和所述第二区域上形成层叠设置的栅氧化层和栅极，所述栅极在所述基底上投影覆盖部分所述有源区；
形成包裹在所述栅极和所述栅氧化层的侧面的保护层，其中，位于所述第一区域内的有源区、栅氧化层、栅极以及保护层构成所述逻辑晶体管，位于第二区域内的有源区、栅氧化层、栅极以及保护层构成所述存取晶体管。
在一些实施例中，在所述第一区域内的基底内形成逻辑晶体管，以及在所述第二区域内形成存取晶体管的步骤之后，在位于所述第一区域和所述第二区域的基底上形成第一互连结构的步骤之前，所述制备方法还包括：
在所述基底上形成覆盖所述逻辑晶体管和所述存取晶体管的第一介质层；
在所述第一介质层内形成多个导电插塞，位于所述第一区域内的所述 导电插塞用于连接所述第一互连层与逻辑晶体管，位于所述第二区域内的所述导电插塞用于连接所述第一互连层与存取晶体管。
在一些实施例中，在所述第一介质层内形成多个导电插塞的步骤中包括：
图形化所述第一介质层，以在所述第一介质层内形成间隔设置的多个第一通孔，每个所述第一通孔暴露出所述有源区的源区或者漏区；
在每个所述第一通孔内沉积导电材料，以形成所述导电插塞。
在一些实施例中，位于所述第一区域和第二区域的基底上形成第一互连结构的步骤中包括：
在所述第一介质层上形成第一导电层；
去除部分所述第一导电层，被保留下来的所述第一导电层在所述第一区域内构成第一互连层，以及被保留下来的所述第一导电层在所述第二区域内构成第二互连层，所述第一互连层和所述第二互连层分别与所述导电插塞电性连接。
在一些实施例中，在平行于所述基底的平面上，所述第一互连层和所述第二互连层的投影分别覆盖各自电性连接的所述导电插塞的投影。
在所述第二互连层上形成磁性隧道结的步骤中包括：
在所述第一互连结构上形成磁性层；
去除部分所述磁性层，以保留位于所述第二区域上方的其中一个所述第二互连层上的磁性层，被保留下来的所述磁性层构成磁性隧道结。
在一些实施例中，在所述第二互连层上形成磁性隧道结的步骤之后，在所述第一互连层和所述磁性隧道结上方形成第二互连结构的步骤之前，所述制备方法还包括：
在所述第一互连结构和所述磁性隧道结上形成第三介质层；
在所述第三介质层内形成间隔设置的第一硅通孔和第二硅通孔，所述第一硅通孔位于所述第一区域上方，并与其中一个所述第一互连层电性连接，所述第二硅通孔位于所述第二区域上方，并与所述磁性隧道结电性连接。
在一些实施例中，在所述第一互连层和所述磁性隧道结上方形成第二互连结构的步骤中，包括：
在所述第三介质层上形成第二导电层；
去除部分所述第二导电层，被保留下来的所述第二导电层在所述第一区域内形成第三互连层，以及被保留下来的所述第二导电层在所述第二区域内形成第四互连层。
在一些实施例中，在所述基底的第一区域和所述第二区域上形成层叠设置的栅氧化层和栅极的步骤，包括：
在所述基底的第一区域和所述第二区域上形成层叠设置的栅氧材料层和栅极材料层；
在所述栅极材料层上形成导电材料层；
图案化所述导电材料层、栅氧材料层和栅极材料层，形成层叠设置的栅氧化层和栅极，以及形成在所述栅极上的字线。
本公开实施例的第二方面提供一种半导体结构，半导体结构通过上述实施例中的所述的半导体结构的制备方法制得，包括：
基底，所述基底包括相邻设置的外围电路区和具有存储单元的阵列区，所述外围电路区包括相邻设置的第一区域和第二区域；
逻辑器件，所述逻辑器件设置在所述第一区域内，并与所述存储单元连接，以对所述存储单元进行控制；
磁性存储器件，所述磁性存储器件设置在所述第二区域内，其中，所述磁性存储器件包括存取晶体管以及与所述存取晶体管连接的磁性隧道结。
在一些实施例中，所述逻辑器件包括逻辑晶体管、第一互连层和第三互连层，所述第一互连层和所述第三互连层层叠设置在所述逻辑晶体管上；
所述第一互连层通过位于第一区域上方的导电插塞与所述逻辑晶体管连接，所述第三互连层通过第一硅通孔与所述第一互连层连接。
在一些实施例中，所述磁性存储器件还包括第二互连层和第四互连层，所述第二互连层设置在所述存取晶体管和所述磁性隧道结之间，以使所述存取晶体管和所述磁性隧道结电性连接；
所述第四互连层设置在所述磁性隧道结上，并与所述磁性隧道结电性连接。
在一些实施例中，所述第二互连层通过位于第二区域上的导电插塞与所述存取晶体管连接，所述第四互连层通过第二硅通孔与所述磁性隧道结连接。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技 术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施例提供的半导体结构及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的制备方法的工艺流程图一；
图2为本公开实施例提供的半导体结构的制备方法中阵列区和外围电路区的分布图；
图3为本公开实施例提供的半导体结构的制备方法中的基底的结构示意图；
图4为本公开实施例提供的半导体结构的制备方法的工艺流程图二；
图5为本公开实施例提供的半导体结构的制备方法中形成逻辑晶体管和存取晶体管的结构示意图；
图6为本公开实施例提供的半导体结构的制备方法中形成第一介质层的结构示意图；
图7为本公开实施例提供的半导体结构的制备方法中形成第一通孔的结构示意图；
图8为本公开实施例提供的半导体结构的制备方法中形成导电插塞的结构示意图；
图9为本公开实施例提供的半导体结构的制备方法中形成第一导电层的结构示意图；
图10为本公开实施例提供的半导体结构的制备方法中形成第一互连结构的结构示意图；
图11为本公开实施例提供的半导体结构的制备方法中形成第二介质层的结构示意图；
图12为本公开实施例提供的半导体结构的制备方法中形成磁性层的 结构示意图；
图13为本公开实施例提供的半导体结构的制备方法中形成磁性隧道结的结构示意图；
图14为本公开实施例提供的半导体结构的制备方法中形成第三介质层的结构示意图；
图15为本公开实施例提供的半导体结构的制备方法中形成第一硅通孔和第二硅通孔的结构示意图；
图16为本公开实施例提供的半导体结构的制备方法中形成第二导电层的结构示意图；
图17为本公开实施例提供的半导体结构的制备方法中形成第二互连结构的结构示意图。
附图标记：
10：基底；11：外围电路区；111：第一区域；112：第二区域；12：阵列区；13：有源区；14：隔离结构；
20：逻辑晶体管；21：栅氧化层；22：栅极；23：保护层；
30：存取晶体管；
40：第一介质层；41：第一通孔；42：导电插塞；
50：第一互连结构；51：第一互连层；52：第二互连层；53：第一导电层；
60：第二介质层；
70：磁性隧道结；71：磁性层；
80：第三介质层；81：第一硅通孔；82：第二硅通孔；
90：第二互连结构；91：第三互连层；92：第四互连层；93：第二导电层；
100：字线；
110：逻辑器件；120：磁性存储器件。
具体实施方式
相关技术中，磁性随机存储器(MRAM)受制备工艺的限制，很难提高其集成度，不利于半导体结构向集成化方向发展，基于上述的技术问题， 在公开本实施例中，利用制备动态随机存储器的工艺在外围电路区内同时制备出用于控制存储单元的逻辑器件和磁性存储器件，使得同一半导体结构同时具有两种存储结构，与单独制备两种存储结构的技术相比，可以简化制作步骤，降低制作成本；此外，通过制备动态随机存储器的工艺来制备磁性存储器件，可以提高磁性存储器件的集成度，便于半导体结构向集成化方向发展。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
如图1所示，本公开实施例提供的半导体结构的制备方法，包括如下的步骤：
步骤S100：提供基底，基底包括相邻设置的外围电路区和具有存储单元的阵列区，外围电路区包括相邻设置的第一区域和第二区域。
示例性地，如图2所示，基底10包括相邻设置的外围电路区11和阵列区12，比如，外围电路区11通常围绕阵列区12设置，阵列区12通常用于设置存储单元，以实现存储器的存储功能，其中，存储单元可以为动态随机存储器的器件，即，一个存储单元包括一个读取晶体管和一个电容器。
如图3所示，基底10内形成多个有源区13以及用于分隔各个有源区13的隔离结构14，也就是说，有源区13既存在外围电路区11内，也存在阵列区12内。
隔离结构14的制备工艺可以为：先图形化基底10，以在基底10内形成隔离沟槽，然后利用沉积工艺在隔离沟槽内沉积绝缘材质，以形成隔离结构14，但并不以此为限。
其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种，隔离结构14的材质为绝缘材料，绝缘材料包括氧化硅、氮化硅、氮氧化硅或碳氮化硅中的任一种或其任一组合。
外围电路区11包括相邻设置的第一区域111和第二区域112，其中，相邻设置可以理解为按一定的方向，第一区域111和第二区域112并排设置，也可以理解为，第一区域111围绕第二区域112设置，又或者是，第二区域112围绕第一区域111。
步骤S200：采用同一制备工艺在第一区域内形成逻辑器件和在第二区域内形成磁性存储器件，制备工艺为用于制备动态随机存储器的工艺，其中，逻辑器件与存储单元连接，以对存储单元进行控制，磁性存储器件包括存取晶体管以及与存取晶体管连接的磁性隧道结。
本实施例通过利用制备动态随机存储器的工艺在外围电路区内同时制备出用于控制存储单元的逻辑器件和磁性存储器件，使得同一半导体结构同时具有两种存储结构，与单独制备两种存储结构的技术相比，可以简化制作步骤，降低制作成本；此外，通过制备动态随机存储器的工艺来制备磁性存储器件，可以提高磁性存储器件的集成度，便于半导体结构向集成化方向发展。
在一些实施例中，如图4所示，采用同一制备工艺在第一区域内形成逻辑器件和在第二区域内形成磁性存储器件的步骤中包括如下的几个步骤：
步骤S210：在第一区域内形成逻辑晶体管，以及在第二区域内形成存取晶体管。
其中，逻辑晶体管20和存取晶体管30是在同一工艺步骤中形成的，其结构如图5所示。
示例性地，可以利用离子掺杂工艺在有源区13内形成沟道区以及分别设置在沟道区两侧的源区和漏区，其中，源区和漏区的掺杂离子的类型相同，沟道区的掺杂离子的类型与源区的掺杂离子的类型不同。
之后，在基底10的第一区域111和第二区域112上形成层叠设置的栅氧化层21和栅极22，栅极22在基底10上投影覆盖部分有源区13，也就是，栅极22在基底10上的投影至少覆盖沟道区，以便于栅极22对沟道区施加电压。
在此步骤中，可以先利用沉积工艺在位于第一区域111和第二区域112的基底10上形成层叠设置的栅氧材料层和栅极材料层，栅氧材料层设置在基底10上，其中，栅氧材料层的材质可以包括氧化硅或者其他具有高介电常数的材质，比如，氧化铝；栅极材料层的材质包括多晶硅。
之后，在栅极材料层上形成导电材料层，其中，导电材料层的材质包括铜(Cu)、钨(W)、钛(Ti)、钽(Ta)、钴(Co)、氮化钛(TiN)、硅化钴(CoSi)和铝化钛(TiAl)中的一种或者任意组合。
最后，在导电材料层上形成掩膜层，对掩膜层进行图案化处理，以图案化后的掩膜层为掩膜，依次刻蚀导电材料层、栅氧材料层和栅极材料层，形成层叠设置的栅氧化层21和栅极22，以及形成在栅极22上的字线100，栅氧化层21位于基底10的上表面上。
待形成栅氧化层21、栅极22以及字线100之后，形成包裹在栅极22、栅氧化层21以及字线100的侧面的保护层23，比如，可以通过沉积工艺在有源区13上形成初始保护层，该初始保护层覆盖在栅氧化层21的侧面、栅极22的侧面以及字线100的侧面和顶面上，然后利用刻蚀气体或者刻蚀液去除位于字线100的顶面上的初始保护层，保留下来的初始保护层构成保护层23，通过保护层23的设置可以实现栅极22和字线100与其他器件之间的隔离，其中，保护层23的材质可以为氧化硅、氮化硅或者氮氧化硅构成的单层或者多层结构的绝缘材质。
在本实施例中，位于第一区域111内的有源区13、栅氧化层21、栅极22以及保护层23构成逻辑晶体管20，位于第二区域112内的有源区13、栅氧化层21、栅极22以及保护层23构成存取晶体管30，且逻辑晶体管20和存取晶体管30是在同一工艺步骤下制备的，可以起到简化制备工艺的优势。
步骤S220：在基底上形成覆盖逻辑晶体管和存取晶体管的第一介质层。
如图6所示，可以利用沉积工艺在基底10上第一介质层40，第一介质层40覆盖在逻辑晶体管20和存取晶体管30上，其中，第一介质层40的材质可以包括氧化硅或者氮化硅等绝缘材质。
步骤S230：在第一介质层内形成多个导电插塞，位于第一区域内的导电插塞用于连接第一互连层与逻辑晶体管，位于第二区域内的导电插塞用于连接第一互连层与存取晶体管。
示例性地，如图7所示，图形化第一介质层40，以在第一介质层40内形成间隔设置多个第一通孔41，每个第一通孔41暴露出有源区的源区或者漏区；比如，第一通孔41的个数为四个，从左往右，第一个第一通孔41用于暴露出位于第一区域111内的有源区13的源区，第二个第一通孔 41用于暴露出位于第一区域111内的有源区13的漏区，且第一个第一通孔41和第二个第一通孔41均位于一个有源区13的上方，第三个第一通孔41用于暴露出位于第二区域112内的有源区13的源区，第四个第一通孔41用于暴露出位于第二区域112内的有源区13的漏区，且第三个第一通孔41和第四个第一通孔41均位于一个有源区13的上方。
之后，如图8所示，在每个第一通孔41沉积导电材料，以形成导电插塞42，导电插塞42用于实现后续形成第一互连层和第二互连层分别与有源区13的连接。
步骤S240：在位于第一区域和第二区域的基底上形成第一互连结构，第一互连结构包括第一互连层和第二互连层，第一互连层与逻辑晶体管连接，第二互连层与存取晶体管连接。
示例性地，如图9所示，利用沉积工艺在第一介质层40上形成第一导电层53，其中，第一导电层53的材质可以包括金属钨、金属铝、金属铜或金属钛中的一种。
之后，如图10所示，图形化第一导电层53，去除部分第一导电层53，保留位于每个导电插塞42上方的第一导电层53，被保留下来的第一导电层53在第一区域111内构成第一互连层51，以及被保留下来的第一导电层53在第二区域112内构成第二互连层52，第一互连层51和第二互连层52构成第一互连结构50，其中，第一互连层51和第二互连层52分别与导电插塞42电性连接。
需要说明的是，本实施例中第一互连层51的个数为两个，其中，一个第一互连层51通过一个导电插塞42与位于第一区域111内的有源区13的源区电性连接，另一个第一互连层51通过一个导电插塞42与位于第二区域112内的有源区13的漏区电性连接，相应地，第二互连层52的个数为两个，其与位于第二区域112内的有源区13的连接方式与两个第一互连层51与位于第一区域111内的有源区13的连接方式相似，本实施例在此不再多加赘述。
在本实施例中，在平行于基底10的平面上，第一互连层51和第二互连层52的投影分别覆盖各自电性连接的导电插塞42的投影。
以第一个第一互连层51和与其电性连接的导电插塞42为例进行说明，第一互连层51在基底10上的投影面积大于导电插塞42在基底10上的投 影面积，如此设置，可以增加第一互连层51与导电插塞42的接触面积，降低上述两者的接触电阻，提高了半导体结构的性能。
如图11所示，为了实现第一互连层51与第二互连层52，以及相邻的第一互连层51或者相相邻的第二互连层52之间的绝缘设置，第一互连层51与第二互连层52之间、相邻的第一互连层51、以及相邻的第二互连层52之间设置有第二介质层60。
步骤S250：在第二互连层上形成磁性隧道结。
示例性地，如图12和图13所示，利用沉积工艺在第一互连结构50和第二介质层60上形成磁性层71，然后对磁性层71进行图形化处理，去除部分磁性层71，保留位于第二区域112上的第二互连层52上的磁性层71，被保留下来的部分磁性层71构成磁性隧道结70，其中，磁性隧道结70包括层叠设置的固定层、隧穿层以及自由层，在半导体结构正常工作时，自由层的磁化方向可以改变，而固定层的磁化方向保持不变，当自由层的磁化方向相对于固定层的磁化方向发生改变时，磁性存储器件的电阻值相应改变，对应于不同的存储信息。
需要说明的是，当磁性隧道结70与存取晶体管30的漏区连接时，相应地，磁性隧道结70形成在与漏区连接的导电插塞42上，当磁性隧道结70与存取晶体管30的源区连接时，相应地，磁性隧道结70形成在与源区连接的导电插塞42上。
在本实施例中，通过利用形成动态随机存储器的制备工艺，将磁性隧道结70形成在第一互连结构中第二互连层上，与相关技术中，磁性隧道结70形成在第四互连结构上的方案相比，可以提高单位面积内磁性存储器件的个数，进而提高了磁性存储器件的集成度。
步骤S260：在第一互连层和磁性隧道结上方形成第二互连结构，第二互连结构包括第三互连层和第四互连层，第三互连层与第一互连层电性连接，第四互连层与磁性隧道结电性连接，其中，逻辑晶体管、第一互连层以及第三互连层构成逻辑器件，存取晶体管、第二互连层、磁性隧道结以及第四互连层构成磁性存储器件。
示例性地，如图14所示，利用沉积工艺在第一互连结构50和磁性隧道结70上形成第三介质层80，第三介质层80的材质可以包括氧化硅和氮化硅。
如图15所示，在第三介质层80内形成间隔设置的第一硅通孔81和第二硅通孔82，第一硅通孔81位于第一区域111上方，并与第一互连层51电性连接，第二硅通孔82位于第二区域112上方，并与磁性隧道结70电性连接。
以图15所示的方位为例，第一硅通孔81的个数为两个，两个第一硅通孔81与两个第一互连层51一一对应设置。
待形成第一硅通孔81和第二硅通孔82之后，如图16所示，在第三介质层80上形成第二导电层93。
如图17所示，去除部分第二导电层93，被保留下来的第二导电层93在第一区域111内形成第三互连层91，以及被保留下来的第二导电层93在第二区域内形成第四互连层92，第三互连层91和第四互连层92构成第二互连结构90，其中，第三互连层91与第一硅通孔81电性连接，第四互连层92与第二硅通孔82电性连接，第四互连层92可以用作磁性存储器件120的位线结构。
需要说明的是，本实施例中的第三互连层91的个数为两个，与第一硅通孔81的个数相对应，以图17所示的方位为例，从左往右，第一个第三互连层91通过第一个第一硅通孔81和第一个第一互连层51连接，第二个第三互连层91也通过第二个第一硅通孔81与第二个第一互连层51连接，以避免信号传递出现串扰。
第三互连层91和第四互连层92的形成方式还可以有其他示例性实施例，比如，待形成第一硅通孔81和第二硅通孔82之后，在第三介质层80上形成绝缘层，图案化绝缘层，形成沟槽，沟槽暴露出第一硅通孔81的顶部和第二硅通孔82的顶部，在沟槽中沉积导电材料，与第一硅通孔81电性连接的导电材料构成第三互连层91，与第二硅通孔82电性连接的导电材料构成第四互连层92。绝缘层位于第三互连层91与第四互连层92之间，用于隔离第三互连层91与第四互连层92，起到绝缘的作用。
在本实施例中，逻辑晶体管20、第一互连层51以及第三互连层91构成逻辑器件110，存取晶体管30、第二互连层52、磁性隧道结70以及第四互连层92构成磁性存储器件120。
本实施例利用制备动态随机存储器的工艺在外围电路区内同时制备出用于控制存储单元的逻辑器件和磁性存储器件，使得同一半导体结构同时 具有两种存储结构，与单独制备两种存储结构的技术相比，可以简化制作步骤，降低制作成本；此外，通过制备动态随机存储器的工艺来制备磁性存储器件，可以提高磁性存储器件的集成度，便于半导体结构向集成化方向发展。
本公开实施例还提供了一种半导体结构，该半导体结构通过上述实施例中的半导体结构的制备方法制得的。
如图17所示，半导体结构包括基底10、逻辑器件110和磁性存储器件120，其中，基底10包括相邻设置的外围电路区11和具有存储单元的阵列区12，外围电路区11包括相邻设置的第一区域111和第二区域112，其中，第一区域111的面积与第二区域112的面积可以相同，也可以不同。
逻辑器件110设置在第一区域111内，并与设置在阵列区12内的存储单元连接，以对存储单元进行控制。
磁性存储器件120设置在第二区域112内，其中，磁性存储器件包括存取晶体管30以及与存取晶体管30连接的磁性隧道结70。
在本实施例中，半导体结构中既具有动态随机存储器的存储单元，也具有磁性随机存储器的磁性隧道结，使得同一半导体结构具备两种不同形式的存储器件，可以提高半导体结构的多样性。
在一些实施例中，逻辑器件110包括逻辑晶体管20、第一互连层51和第三互连层91，第一互连层51和第三互连层91层叠设置在逻辑晶体管20上，其中，第一互连层51通过位于第一区域111上方的导电插塞42与逻辑晶体管20连接，比如，第一个第一互连层51通过位于第一区域111上方的第一个导电插塞42与逻辑晶体管20的源区连接，第二个第一互连层51通过位于第一区域111上方的第二个导电插塞42与逻辑晶体管20的漏区连接。
第三互连层91通过第一硅通孔81与第一互连层51连接，以实现第一互连层51和第三互连层91之间的电信号的传递，其中，第一硅通孔81的材质可以包括铜。
在一些实施例中，磁性存储器件120还包括第二互连层52和第四互连层92，第二互连层52设置在存取晶体管30和磁性隧道结70之间，以使存取晶体管30和磁性隧道结70电性连接，也就是说，第二互连层52的上 表面与磁性隧道结70连接，第二互连层52的下表面与存取晶体管30电性连接。
第二互连层52的下表面与存取晶体管30可以直接连接，也可以间接连接，比如，第二互连层52与存取晶体管之间通过位于第二区域112上的导电插塞42连接。
第四互连层92设置在磁性隧道结70上，并与磁性隧道结70电性连接，比如，第四互连层92通过第二硅通孔82与磁性隧道结70连接，本实施例通过第二硅通孔82、位于第二区域112上的导电插塞实现了磁性存储器件中各个部件之间的电性连接。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底包括相邻设置的外围电路区和具有存储单元的阵列区，所述外围电路区包括相邻设置的第一区域和第二区域；
    采用同一制备工艺在所述第一区域内形成逻辑器件和在所述第二区域内形成磁性存储器件，所述制备工艺为用于制备动态随机存储器的工艺，其中，所述逻辑器件与所述存储单元连接，以对所述存储单元进行控制，所述磁性存储器件包括存取晶体管以及与所述存取晶体管连接的磁性隧道结。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，采用同一制备工艺在所述第一区域内形成逻辑器件和在所述第二区域内形成磁性存储器件的步骤中包括：
    在所述第一区域内形成逻辑晶体管，以及在所述第二区域内形成存取晶体管；
    在位于所述第一区域和所述第二区域的基底上形成第一互连结构，所述第一互连结构包括第一互连层和第二互连层，所述第一互连层与所述逻辑晶体管连接，所述第二互连层与存取晶体管连接；
    在所述第二互连层上形成磁性隧道结；
    在所述第一互连层和所述磁性隧道结上方形成第二互连结构，所述第二互连结构包括第三互连层和第四互连层，所述第三互连层与所述第一互连层电性连接，所述第四互连层与所述磁性隧道结电性连接，其中，所述逻辑晶体管、所述第一互连层以及所述第三互连层构成所述逻辑器件，所述存取晶体管、所述第二互连层、所述磁性隧道结以及所述第四互连层构成磁性存储器件。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，提供基底的步骤中，包括：
    在所述基底内形成多个有源区以及用于分隔各个所述有源区的隔离结构；
    在所述第一区域内形成逻辑晶体管，以及在所述第二区域内形成存取晶体管的步骤中，包括：
    在所述基底的第一区域和所述第二区域上形成层叠设置的栅氧化层和栅极，所述栅极在所述基底上投影覆盖部分所述有源区；
    形成包裹在所述栅极和所述栅氧化层的侧面的保护层，其中，位于所述第一区域内的有源区、栅氧化层、栅极以及保护层构成所述逻辑晶体管，位于第二区域内的有源区、栅氧化层、栅极以及保护层构成所述存取晶体管。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，在所述第一区域内的基底内形成逻辑晶体管，以及在所述第二区域内形成存取晶体管的步骤之后，在位于所述第一区域和所述第二区域的基底上形成第一互连结构的步骤之前，所述制备方法还包括：
    在所述基底上形成覆盖所述逻辑晶体管和所述存取晶体管的第一介质层；
    在所述第一介质层内形成多个导电插塞，位于所述第一区域内的所述导电插塞用于连接所述第一互连层与逻辑晶体管，位于所述第二区域内的所述导电插塞用于连接所述第一互连层与存取晶体管。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，在所述第一介质层内形成多个导电插塞的步骤中包括：
    图形化所述第一介质层，以在所述第一介质层内形成间隔设置的多个第一通孔，每个所述第一通孔暴露出所述有源区的源区或者漏区；
    在每个所述第一通孔内沉积导电材料，以形成所述导电插塞。
  6. 根据权利要求4或5所述的半导体结构的制备方法，其中，位于所述第一区域和第二区域的基底上形成第一互连结构的步骤中包括：
    在所述第一介质层上形成第一导电层；
    去除部分所述第一导电层，被保留下来的所述第一导电层在所述第一区域内构成第一互连层，以及被保留下来的所述第一导电层在所述第二区域内构成第二互连层，所述第一互连层和所述第二互连层分别与所述导电插塞电性连接。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，在平行于所述基底的平面上，所述第一互连层和所述第二互连层的投影分别覆盖各自电性连接的所述导电插塞的投影。
  8. 根据权利要求6所述的半导体结构的制备方法，其中，在所述第二 互连层上形成磁性隧道结的步骤中包括：
    在所述第一互连结构上形成磁性层；
    去除部分所述磁性层，以保留位于所述第二区域上方的其中一个所述第二互连层上的磁性层，被保留下来的所述磁性层构成磁性隧道结。
  9. 根据权利要求7所述的半导体结构的制备方法，其中，在所述第二互连层上形成磁性隧道结的步骤之后，在所述第一互连层和所述磁性隧道结上方形成第二互连结构的步骤之前，所述制备方法还包括：
    在所述第一互连结构和所述磁性隧道结上形成第三介质层；
    在所述第三介质层内形成间隔设置的第一硅通孔和第二硅通孔，所述第一硅通孔位于所述第一区域上方，并与其中一个所述第一互连层电性连接，所述第二硅通孔位于所述第二区域上方，并与所述磁性隧道结电性连接。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，在所述第一互连层和所述磁性隧道结上方形成第二互连结构的步骤中，包括：
    在所述第三介质层上形成第二导电层；
    去除部分所述第二导电层，被保留下来的所述第二导电层在所述第一区域内形成第三互连层，以及被保留下来的所述第二导电层在所述第二区域内形成第四互连层。
  11. 根据权利要求3-5任一项所述的半导体结构的制备方法，其中，在所述基底的第一区域和所述第二区域上形成层叠设置的栅氧化层和栅极的步骤，包括：
    在所述基底的第一区域和所述第二区域上形成层叠设置的栅氧材料层和栅极材料层；
    在所述栅极材料层上形成导电材料层；
    图案化所述导电材料层、栅氧材料层和栅极材料层，形成层叠设置的栅氧化层和栅极，以及形成在所述栅极上的字线。
  12. 一种半导体结构，所述半导体结构通过如权利要求1-11任一项所述的半导体结构的制备方法制得，包括：
    基底，所述基底包括相邻设置的外围电路区和具有存储单元的阵列区，所述外围电路区包括相邻设置的第一区域和第二区域；
    逻辑器件，所述逻辑器件设置在所述第一区域内，并与所述存储单元 连接，以对所述存储单元进行控制；
    磁性存储器件，所述磁性存储器件设置在所述第二区域内，其中，所述磁性存储器件包括存取晶体管以及与所述存取晶体管连接的磁性隧道结。
  13. 根据权利要求12所述的半导体结构，其中，所述逻辑器件包括逻辑晶体管、第一互连层和第三互连层，所述第一互连层和所述第三互连层层叠设置在所述逻辑晶体管上；
    所述第一互连层通过位于第一区域上方的导电插塞与所述逻辑晶体管连接，所述第三互连层通过第一硅通孔与所述第一互连层连接。
  14. 根据权利要求13所述的半导体结构，其中，所述磁性存储器件还包括第二互连层和第四互连层，所述第二互连层设置在所述存取晶体管和所述磁性隧道结之间，以使所述存取晶体管和所述磁性隧道结电性连接；
    所述第四互连层设置在所述磁性隧道结上，并与所述磁性隧道结电性连接。
  15. 根据权利要求14所述的半导体结构，其中，所述第二互连层通过位于第二区域上的导电插塞与所述存取晶体管连接，所述第四互连层通过第二硅通孔与所述磁性隧道结连接。
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