WO2023097728A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2023097728A1
WO2023097728A1 PCT/CN2021/136695 CN2021136695W WO2023097728A1 WO 2023097728 A1 WO2023097728 A1 WO 2023097728A1 CN 2021136695 W CN2021136695 W CN 2021136695W WO 2023097728 A1 WO2023097728 A1 WO 2023097728A1
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via hole
layer
electrode
array
insulating layer
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PCT/CN2021/136695
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English (en)
French (fr)
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艾飞
宋德伟
罗成志
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武汉华星光电技术有限公司
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Priority to US17/621,257 priority Critical patent/US20240038765A1/en
Publication of WO2023097728A1 publication Critical patent/WO2023097728A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • LTPS Low Temperature Poly-Silicon
  • AMOLED active matrix organic light-emitting Diode
  • Embodiments of the present application provide an array substrate and a display panel to solve the technical problem of a large number of photomasks used in the existing LTPS array technology.
  • An embodiment of the present application provides an array substrate, which includes:
  • an array layer disposed on one side of the substrate, the array layer including a source and a drain;
  • an inorganic insulating layer disposed on a side of the array layer away from the substrate;
  • a conductive electrode disposed on a side of the inorganic insulating layer away from the array layer;
  • a passivation layer disposed on a side of the conductive electrode away from the inorganic insulating layer
  • a pixel electrode disposed on a side of the passivation layer away from the conductive electrode
  • a first via hole is opened in the array substrate, the first via hole penetrates through the passivation layer and the inorganic insulating layer and exposes the drain electrode, and the pixel electrode is The hole is connected to the drain.
  • the first via hole includes a first sub-via hole and a second sub-via hole connected to the first sub-via hole, and the first sub-via hole is located at The drain electrode is exposed in the inorganic insulating layer, the second sub-via hole is located in the passivation layer, and the pixel electrode is connected to the wall of the first sub-via hole and the second via hole respectively.
  • the hole wall of the sub-via is in contact.
  • the conductive electrodes are multiplexed as touch electrodes
  • the array substrate further includes touch traces on the same layer as the drain electrodes and arranged at intervals, and the connecting electrodes Located on a side of the passivation layer away from the conductive electrodes, the touch electrodes are electrically connected to the touch traces through the connection electrodes.
  • an opening is opened in the touch electrode, and the opening is set corresponding to the touch wiring; a second via hole is opened in the inorganic insulating layer, so that The second via hole exposes the touch trace, a third via hole is opened in the passivation layer, the third via hole is connected to the opening and the second via hole, and the connecting electrode filling in the second via hole, the opening and the third via hole, and in contact with the sidewall of the opening.
  • the third via holes expose the surface of the touch electrode away from the substrate.
  • openings are opened in the touch electrodes, the openings are arranged corresponding to the touch traces, and the passivation layer is filled in the openings;
  • a second via hole is opened in the inorganic insulating layer, the aperture of the second via hole is smaller than the aperture of the opening, the second via hole exposes the touch trace, and a spacer is opened in the passivation layer.
  • a third via hole and a fourth via hole are provided, the third via hole communicates with the opening and the second via hole, the fourth via hole exposes the touch electrode, and the connection electrode fills In the second via hole, the third via hole, the fourth via hole and part of the opening, the part of the connecting electrode located in the opening is insulated from the touch electrode.
  • the second via hole and the third via hole are formed under the same photomask.
  • the connecting electrode and the pixel electrode are arranged in the same layer and are insulated.
  • the array layer further includes:
  • an active layer disposed on one side of the substrate, the active layer having a channel region
  • a gate insulating layer disposed on a side of the active layer away from the substrate
  • a gate disposed on a side of the gate insulating layer away from the active layer
  • an interlayer dielectric layer disposed on a side of the gate away from the gate insulating layer, and the interlayer dielectric layer is located on a side of the drain away from the inorganic insulating layer;
  • the thickness of the active layer is 30nm-45nm.
  • the array layer further includes:
  • an active layer disposed on one side of the substrate, the active layer having a channel region
  • a gate insulating layer disposed on a side of the active layer away from the substrate
  • a gate disposed on a side of the gate insulating layer away from the active layer
  • an interlayer dielectric layer disposed on a side of the gate away from the gate insulating layer, and the interlayer dielectric layer is located on a side of the drain away from the inorganic insulating layer;
  • the width of the channel region is 1.5 ⁇ m-2.5 ⁇ m.
  • the array substrate further includes a buffer layer, the buffer layer is arranged between the base and the array layer, and a side of the buffer layer close to the base is in contact with The substrate contacts.
  • the embodiment of the present application also provides an array substrate, which includes:
  • an array layer disposed on one side of the substrate, the array layer including a source and a drain;
  • an inorganic insulating layer disposed on a side of the array layer away from the substrate;
  • a conductive electrode disposed on a side of the inorganic insulating layer away from the array layer;
  • a passivation layer disposed on a side of the conductive electrode away from the inorganic insulating layer
  • a pixel electrode disposed on a side of the passivation layer away from the conductive electrode
  • a first via hole is opened in the array substrate, the first via hole penetrates through the passivation layer and the inorganic insulating layer and exposes the drain electrode, and the pixel electrode is The hole is connected to the drain;
  • the first via hole includes a first sub-via hole and a second sub-via hole connected to the first sub-via hole, and the first sub-via hole is located in the inorganic insulating layer and expose the drain electrode, the second sub-via hole is located in the passivation layer, and the pixel electrode is connected to the hole wall of the first sub-via hole and the second sub-via hole respectively. Hole walls are in contact, and the first sub-via and the second sub-via are formed under the same photomask.
  • the display panel includes an array substrate disposed opposite to each other, a color filter substrate, and a liquid crystal arranged between the array substrate and the color filter substrate.
  • the array substrate includes:
  • an array layer disposed on one side of the substrate, the array layer including a source and a drain;
  • an inorganic insulating layer disposed on a side of the array layer away from the substrate;
  • a conductive electrode disposed on a side of the inorganic insulating layer away from the array layer;
  • a passivation layer disposed on a side of the conductive electrode away from the inorganic insulating layer
  • a pixel electrode disposed on a side of the passivation layer away from the conductive electrode
  • a first via hole is opened in the array substrate, the first via hole penetrates through the passivation layer and the inorganic insulating layer and exposes the drain electrode, and the pixel electrode is The hole is connected to the drain.
  • the first via hole includes a first sub-via hole and a second sub-via hole connected to the first sub-via hole, and the first sub-via hole is located at The drain electrode is exposed in the inorganic insulating layer, the second sub-via hole is located in the passivation layer, and the pixel electrode is connected to the wall of the first sub-via hole and the second via hole respectively.
  • the hole wall of the sub-via is in contact.
  • the conductive electrodes are multiplexed as touch electrodes
  • the array substrate further includes touch traces on the same layer as the drain electrodes and arranged at intervals, and the connecting electrodes Located on a side of the passivation layer away from the conductive electrodes, the touch electrodes are electrically connected to the touch traces through the connection electrodes.
  • an opening is opened in the touch electrode, and the opening is set corresponding to the touch wiring; a second via hole is opened in the inorganic insulating layer, so that The second via hole exposes the touch trace, a third via hole is opened in the passivation layer, the third via hole is connected to the opening and the second via hole, and the connecting electrode filling in the second via hole, the opening and the third via hole, and in contact with the sidewall of the opening.
  • the third via holes expose the surface of the touch electrode away from the substrate.
  • openings are opened in the touch electrodes, the openings are arranged corresponding to the touch traces, and the passivation layer is filled in the openings;
  • a second via hole is opened in the inorganic insulating layer, the aperture of the second via hole is smaller than the aperture of the opening, the second via hole exposes the touch trace, and a spacer is opened in the passivation layer.
  • a third via hole and a fourth via hole are provided, the third via hole communicates with the opening and the second via hole, the fourth via hole exposes the touch electrode, and the connection electrode fills In the second via hole, the third via hole, the fourth via hole and part of the opening, the part of the connecting electrode located in the opening is insulated from the touch electrode.
  • the second via hole and the third via hole are formed under the same photomask.
  • the array substrate further includes a buffer layer, the buffer layer is arranged between the base and the array layer, and a side of the buffer layer close to the base is in contact with The substrate contacts.
  • the array substrate provided by the present application replaces the planarized organic layer in the traditional array structure with an inorganic insulating layer by setting an inorganic insulating layer between the array layer and the conductive electrodes, due to passivation layer is also an inorganic film layer, therefore, in the preparation process of the array substrate, the passivation layer and the inorganic insulating layer can be opened under the same photomask to form the first via hole connecting the pixel electrode and the drain electrode, thereby The photomask required to separately open holes in the planarized organic layer in the traditional manufacturing process is omitted, and the number of photomasks used in the array substrate preparation process is reduced.
  • FIG. 1 is a schematic structural diagram of an array substrate in the prior art.
  • FIG. 2 is a schematic structural diagram of the array substrate provided by the first embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an array substrate provided in a second embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an array substrate provided by a third embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an array substrate provided by a fourth embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a method for preparing an array substrate provided in Example 1 of the present application.
  • FIG. 7A to FIG. 7L are structural schematic diagrams obtained sequentially at various stages in the method for manufacturing an array substrate provided in Example 1 of the present application.
  • 8A to 8D are schematic structural diagrams obtained in some stages of the method for preparing the array substrate provided in Example 2 of the present application.
  • FIG. 9A and FIG. 9B are schematic structural diagrams obtained in some stages of the method for preparing an array substrate provided in Example 3 of the present application.
  • FIG. 10A and FIG. 10B are schematic structural diagrams obtained in some stages of the method for preparing an array substrate provided in Example 4 of the present application.
  • FIG. 11 is a schematic structural diagram of a display panel provided by the present application.
  • Embodiments of the present application provide an array substrate and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • an array substrate 100' in the prior art includes a substrate 10', a light shielding layer 101', a buffer layer 11', an array layer 12', a planarized organic layer 13', and a touch electrode 14' arranged in sequence. , a passivation layer 15' and a pixel electrode 16'.
  • the planarized organic layer 13' there is a first opening 131' that exposes the drain electrode (not marked in the figure), and in the passivation layer 15', there is a second opening 151', and the first opening 131' is sleeved outside the second opening 151'.
  • the pixel electrode 16' is electrically connected to the drain through the second opening 151'.
  • the array substrate 100' also includes a touch trace 17', the touch trace 17' is arranged on the same layer as the drain, and a third opening 132' is opened in the planarized organic layer 13', and the touch electrode 14' passes through the first The three openings 132' are electrically connected to the touch traces 17'.
  • the planarizing organic layer 13' is an organic film layer and the passivation layer 15' is an inorganic film layer
  • the first opening 131' in the planarizing organic layer 13' and the second hole in the passivation layer 15' requires a photomask to be formed. Specifically, after using a photomask to open the first opening 131' exposing the drain in the planarized organic layer 13', another photomask is used to open the second opening 151' in the passivation layer 15'.
  • the diameter of the second opening 151' will be smaller than the diameter of the first opening 131', and in the first opening 131', the first opening 131' will be formed to be sleeved in the second opening 131'.
  • an array substrate which includes a substrate, an array layer, an inorganic insulating layer, a conductive electrode, a passivation layer, and a pixel electrode.
  • the array layer is arranged on one side of the substrate, and the array layer includes a source electrode and a drain electrode; the inorganic insulating layer is arranged on the side of the array layer away from the substrate; the conductive electrode is arranged on the side of the inorganic insulating layer away from the array layer; the passivation layer is arranged on The conductive electrode is away from the side of the inorganic insulating layer; the pixel electrode is arranged on the side of the passivation layer away from the conductive electrode; wherein, a first via hole is opened in the array substrate, and the first via hole penetrates the passivation layer and the inorganic insulating layer and is exposed out of the drain, and the pixel electrode is connected to the drain in the first via hole.
  • the array substrate replaces the planarized organic layer in the traditional array structure with an inorganic insulating layer by providing an inorganic insulating layer between the array layer and the conductive electrodes. Since the passivation layer is also an inorganic film layer, the , in the preparation process of the array substrate, the passivation layer and the inorganic insulating layer can be opened under the same photomask to form the first via hole connecting the pixel electrode and the drain electrode, thereby eliminating the need for a separate via hole in the traditional process.
  • the photomask required to planarize the holes in the organic layer reduces the number of photomasks used in the array substrate preparation process.
  • the array substrate 100 provided by the first embodiment of the present application includes a substrate 10 , a buffer layer 11 , an array layer 12 , an inorganic insulating layer 13 , a conductive electrode 14 , a passivation layer 15 and a pixel electrode 16 .
  • the substrate 10 may be a rigid substrate, such as a glass substrate; or, the substrate 10 may also be a flexible substrate, such as a polyimide substrate, and the material of the substrate 10 is not specifically limited in this application.
  • the buffer layer 11 is disposed on one side of the substrate 10 .
  • a side of the buffer layer 11 close to the substrate 10 is in contact with the substrate 10 .
  • the material of the buffer layer 11 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the array layer 12 is disposed on a side of the buffer layer 11 away from the substrate 10 .
  • the array layer 12 includes an active layer 121 , a gate insulating layer 122 , a gate 123 , an interlayer dielectric layer 124 , a source 125 and a drain 126 .
  • the active layer 121 is disposed on a side of the buffer layer 11 away from the substrate 10 .
  • the material of the active layer 121 includes low temperature polysilicon.
  • the active layer 121 has a channel region 121a, a first lightly doped region 121b, a second lightly doped region 121c, a first heavily doped region 121d and a second heavily doped region 121e.
  • the first lightly doped region 121b and the second lightly doped region 121c are located on opposite sides of the channel region 121a.
  • the first heavily doped region 121d is located on a side of the first lightly doped region 121b away from the channel region 121a.
  • the second heavily doped region 121e is located on a side of the second lightly doped region 121c away from the channel region 121a.
  • the first lightly doped region 121b and the second lightly doped region 121c are formed by lightly doping the active layer 121 with ions.
  • the first heavily doped region 121d and the second heavily doped region 121e are formed by heavily doping the active layer 121 with ions.
  • the ion heavy doping and the ion light doping are both N-type ion doping, and the doped ions are phosphorus (P) ions or other N-type element ions.
  • the ion heavy doping and the ion light doping are both P-type ion doping, and the doped ions are boron (B) ions or other P-type element ions .
  • the gate insulating layer 122 is disposed on a side of the active layer 121 away from the buffer layer 11 .
  • the material of the gate insulating layer 122 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the gate 123 is disposed on a side of the gate insulating layer 122 away from the active layer 121 .
  • the gate 123 is disposed corresponding to the channel region 121a.
  • the orthographic projection of the gate 123 on the plane of the substrate 10 covers the orthographic projection of the channel region 121 a on the plane of the substrate 10 .
  • the material of the gate 123 may include one or more of copper, aluminum, molybdenum and titanium.
  • the interlayer dielectric layer 124 is disposed on a side of the gate 123 away from the gate insulating layer 122 .
  • the interlayer dielectric layer 124 is located on a side of the drain electrode 126 away from the inorganic insulating layer 13 .
  • the material of the interlayer dielectric layer 124 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the source 125 and the drain 126 are disposed on a side of the interlayer dielectric layer 124 away from the gate 123 .
  • the source electrode 125 is in contact with the part of the active layer 121 located in the first heavily doped region 121d.
  • the drain 126 is in contact with the portion of the active layer 121 located in the second heavily doped region 121e.
  • the materials of the source electrode 125 and the drain electrode 126 are the same, and both may include one or more of copper, aluminum, molybdenum and titanium.
  • the inorganic insulating layer 13 is disposed on a side of the array layer 12 away from the interlayer dielectric layer 124 .
  • the material of the inorganic insulating layer 13 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the thickness of the inorganic insulating layer 13 is 100nm-1000nm, such as 100nm, 200nm, 500nm, 600nm, 700nm, 800nm, 900nm or 1000nm.
  • the inorganic insulating layer 13 may have a single-layer structure, a double-layer structure or a multi-layer structure. In this embodiment, the single-layer structure of the inorganic insulating layer 13 is used as an example for illustration, but it is not limited thereto.
  • the conductive electrode 14 is disposed on a side of the inorganic insulating layer 13 away from the array layer 12 .
  • the conductive electrodes 14 are provided on the entire surface.
  • the conductive electrode 14 may be a common electrode.
  • the material of the conductive electrode 14 may include transparent conductive materials such as indium tin oxide.
  • the passivation layer 15 is disposed on a side of the conductive electrode 14 away from the inorganic insulating layer 13 .
  • the material of the passivation layer 15 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the pixel electrode 16 is disposed on a side of the passivation layer 15 away from the conductive electrode 14 .
  • the material of the pixel electrode 16 may include transparent conductive materials such as indium tin oxide.
  • a first via hole 10A is opened in the array substrate 100 .
  • the first via hole 10A penetrates through the passivation layer 15 and the inorganic insulating layer 13 and exposes the drain electrode 126 .
  • the pixel electrode 16 is connected to the drain electrode 126 in the first via hole 10A.
  • the first via 10A includes a first sub-via 131 and a second sub-via 151 connected to the first sub-via 131 .
  • the first sub-via hole 131 is located in the inorganic insulating layer 13 and exposes the drain electrode 126 .
  • the second sub-via 151 is located in the passivation layer 15 .
  • the first sub-via 131 and the second sub-via 151 are formed under the same mask. Therefore, in this embodiment, the inorganic insulating layer 13 is used to replace the planarized organic layer in the traditional array structure. Since the passivation layer 15 is also an inorganic film layer, the first sub-via hole 131 and the passivation layer in the inorganic insulating layer 13 The second sub-via hole 151 in the organic layer 15 can be formed under the same photomask to realize the connection between the pixel electrode 16 and the drain electrode 126, thereby eliminating the need to separately open a hole in the planarized organic layer in the traditional process.
  • the photomask reduces the number of photomasks used in the manufacturing process of the array substrate 100, effectively reduces the production cycle of the array substrate 100, improves production capacity, reduces process costs, and improves the market competitiveness of display products.
  • the thickness of the active layer 121 is 30nm-45nm.
  • the width of the channel region 121a is 1.5 ⁇ m-2.5 ⁇ m.
  • a light-shielding layer is usually provided on the side of the active layer 121 close to the substrate 10 to block external ambient light, so as to ensure that the thin film transistor has a low light-induced leakage current.
  • a photomask is added on the basis of the original manufacturing process, thereby increasing the number of photomasks used in the manufacturing process of the array substrate 100 .
  • the present application omits the setting of the light-shielding layer, thereby reducing the number of photomasks used in the array process. Furthermore, the inventors of the present application have found through experimental research that the photo-induced leakage current of the thin film transistor is positively correlated with the thickness of the active layer 121 and the width of the channel region 121a. In the traditional design, in order to ensure the driving performance of the thin film transistor, the thickness of the active layer 121 is usually set above 45nm, and the width of the channel region 121a is usually set above 2.5 ⁇ m.
  • the thickness of the active layer 121 is set at 30nm-45nm, and the width of the channel region 121a is set at 1.5 ⁇ m-2.5 ⁇ m. Within the above range, the photogenerated leakage current of the thin film transistor can be significantly improved. reduce.
  • the thickness of the active layer 121 may be 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, 41nm, 42nm, 43nm, 44nm or 45nm.
  • the width of the channel region 121 a may be 1.5 ⁇ m, 1.6 ⁇ m, 1.7 ⁇ m, 1.8 ⁇ m, 1.9 ⁇ m, 2.0 ⁇ m, 2.1 ⁇ m, 2.2 ⁇ m, 2.3 ⁇ m, 2.4 ⁇ m, or 2.5 ⁇ m.
  • Table 1 shows the values of photo-induced leakage currents of thin film transistors under different thicknesses of the active layer 121 and widths of the channel region 121a.
  • the thickness of the active layer 121 by setting the thickness of the active layer 121 to 30nm-45nm and the width of the channel region 121a to 1.5 ⁇ m-2.5 ⁇ m, the defect of increased photo-induced leakage current caused by the omission of the light-shielding layer can be compensated, and further in On the premise of ensuring the driving performance of the thin film transistor, the number of photomasks used in the preparation process of the array substrate 100 is saved, and the process cost is reduced.
  • the thickness of the active layer 121 can also be set at 30nm-45nm, and the width of the channel region 121a can be set at more than 2.5 ⁇ m; or, the thickness of the channel region 121a can also be set at 1.5 ⁇ m-2.5 ⁇ m, the thickness of the active layer 121 is set above 45 nm.
  • the above arrangement can also achieve the effect of saving the photomask and reducing the photo-induced leakage current of the thin film transistor.
  • the second embodiment of the present application provides an array substrate 100 .
  • the array substrate 100 provided by the second embodiment of the present application is different from the first embodiment in that: when the array substrate 100 has a touch function, the conductive electrodes 14 can be reused as touch electrodes.
  • the array substrate 100 also includes touch wires 17 and connection electrodes 18 .
  • the touch wire 17 is on the same layer as the drain 126 and is arranged at intervals.
  • a second via hole 132 is opened in the inorganic insulating layer 13 .
  • the second via hole 132 exposes the touch trace 17 .
  • An opening 141 is opened in the conductive electrode 14 .
  • the opening 141 is provided corresponding to the touch trace 17 .
  • a third via hole 152 is opened in the passivation layer 15 .
  • the third via hole 152 communicates with the opening 141 and the second via hole 132 .
  • the connection electrode 18 is located on a side of the passivation layer 15 away from the conductive electrode 14 and is insulated from the pixel electrode 16 .
  • the connection electrode 18 is filled in the second via hole 132 , the opening 141 and the third via hole 152 , and is in contact with the sidewall of the opening 141 .
  • the touch electrodes are connected to the touch traces 17 through the conductive electrodes 14 .
  • the second via hole 132 and the third via hole 152 are formed under the same photomask.
  • the inorganic insulating layer 13 is used to replace the planarized organic layer in the traditional array structure. Since the passivation layer 15 is also an inorganic film layer, when it is necessary to prepare the array substrate 100 with an embedded touch function, The second via hole 132 in the inorganic insulating layer 13 and the third via hole 152 in the passivation layer 15 can be formed under a photomask, and the touch trace 17 and the touch electrode can be realized under the overlap of the connecting electrode 18 conduction.
  • the multiplexing of the conductive electrodes 14 as touch electrodes in this embodiment means that the conductive electrodes 14 can be used as touch electrodes when touch operations need to be performed. In addition, when no touch operation is required, the conductive electrode 14 can be used as a common electrode to form a storage capacitor with the pixel electrode 16 .
  • the conductive electrode 14 can be used as a common electrode to form a storage capacitor with the pixel electrode 16 .
  • the touch wire 17 is disposed on a side of the source 125 away from the drain 126 .
  • the touch trace 17 , the source 125 and the drain 126 can be prepared by using the same photomask. It should be noted that, in some embodiments, the touch wiring 17 may also be arranged on the side of the drain 126 away from the source 125 , and the position of the touch wiring 17 is not specifically limited in this embodiment.
  • the orthographic projection of the touch wire 17 on the plane where the touch electrode is located is at least partially located in the opening 141 , so that the touch electrode can be connected to the touch wire 17 through the connection electrode 18 .
  • the connecting electrode 18 and the pixel electrode 16 are arranged on the same layer.
  • the connection electrode 18 and the pixel electrode 16 can be prepared by using the same photomask, thus, this embodiment can form the connection electrode 18 on the basis of the original manufacturing process without increasing the manufacturing cost.
  • the connection electrodes 18 and the pixel electrodes 16 may also be arranged in different layers, which will not be repeated here.
  • the third embodiment of the present application provides an array substrate 100 .
  • the array substrate 100 provided by the third embodiment of the present application is different from the second embodiment in that: the third via hole 152 exposes the surface of the touch electrodes away from the substrate 10 .
  • the aperture of the third via hole 152 is larger than the aperture of the opening 141, so that the surface of the touch electrode is exposed, so that the connection electrode 18 can contact the upper surface of the touch electrode, thereby increasing the contact between the connection electrode 18 and the touch electrode.
  • the contact area of the touch electrodes is conducive to improving the conduction effect between the touch electrodes and the touch traces 17 and improving the touch sensitivity.
  • the fourth embodiment of the present application provides an array substrate 100 .
  • the array substrate 100 provided by the fourth embodiment of the present application is different from the third embodiment in that: the passivation layer 15 is filled in the opening 141 .
  • the diameter of the second via hole 132 is smaller than the diameter of the opening 141 .
  • a fourth via hole 153 is also opened in the passivation layer 15 .
  • the fourth via hole 153 and the third via hole 152 are arranged at intervals.
  • the fourth via hole 153 exposes the touch electrodes.
  • the connection electrodes 18 are filled in the second via hole 132 , the third via hole 152 , the fourth via hole 153 and part of the opening 141 .
  • the portion of the connection electrode 18 located in the opening 141 is insulated from the touch electrode.
  • the fourth opening 153 is added in the passivation layer 15, so that the connecting electrode 18 passes through the second opening 132, the third opening 152 and the fourth opening 153 to realize the touch electrode and the touch wiring 17. conduction, thereby increasing the conduction effect and further improving touch sensitivity.
  • Example 1 of the present application provides a method for preparing an array substrate, which includes the following steps:
  • B2 forming an array layer on one side of the substrate, and the array layer includes a source electrode and a drain electrode;
  • the preparation method of the array substrate forms an inorganic insulating layer between the array layer and the conductive electrode, and replaces the planarized organic layer in the traditional array structure with the inorganic insulating layer.
  • the passivation layer is also an inorganic film layer, therefore, in the preparation process of the array substrate, the passivation layer and the inorganic insulating layer can be opened under the same photomask to form the first via hole connecting the pixel electrode and the drain electrode, thereby eliminating the traditional process
  • the photomask required for opening holes in the planarized organic layer alone reduces the number of photomasks used in the array substrate preparation process.
  • FIG. 6 and FIG. 7A to FIG. 7L Please refer to FIG. 6 and FIG. 7A to FIG. 7L together, and the preparation method of the array substrate 100 provided by this embodiment will be described in detail below.
  • B1 Provide a base 10, as shown in FIG. 7A.
  • the substrate 10 may be a rigid substrate, such as a glass substrate; or, the substrate 10 may also be a flexible substrate, such as a polyimide substrate, and the material of the substrate 10 is not specifically limited in this application.
  • An array layer 12 is formed on one side of the substrate 10 , and the array layer 12 includes a drain 126 .
  • step B2 specifically includes:
  • B21 sequentially forming a buffer layer 11 and an active layer 121 on one side of the substrate 10, as shown in FIG. 7B.
  • the buffer layer 11 is formed by chemical vapor deposition process.
  • the material of the buffer layer 11 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • low-temperature polysilicon is deposited on the buffer layer 11, and laser annealing is performed to form an entire active base layer (not shown in the figure), and then the active base layer is patterned through exposure, development and etching processes in sequence , to form the active layer 121 .
  • the thickness of the active layer 121 is 30nm-45nm.
  • the gate insulating layer 122 is formed by chemical vapor deposition process.
  • the material of the gate insulating layer 122 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • a gate metal layer (not shown in the figure) is formed on the gate insulating layer 122 by using a physical vapor deposition process, and then the gate metal layer is patterned through exposure, development and etching processes in order to form The gate pattern 123A.
  • the material of the gate 123 may include one or more of copper, aluminum, molybdenum and titanium.
  • the active layer 121 includes a first region 1211 and a second region 1212 disposed on opposite sides of the first region 1211 .
  • the first region 1211 is disposed corresponding to the gate pattern 123A.
  • the orthographic projection of the gate pattern 123A on the plane of the substrate 10 completely covers the orthographic projection of the portion of the active layer 121 located in the first region 1211 on the plane of the substrate 10 .
  • the portion of the active layer 121 located in the second region 1212 is heavily doped with ions to form a first heavily doped region 121d and a second heavily doped region 121e respectively.
  • the ion heavy doping is N-type ion doping
  • the doped ions are phosphorus (P) ions or other N-type element ions.
  • the gate pattern 123A is patterned by an etching process to form the gate 123 .
  • the area of the active layer 121 corresponding to the gate 123 is the channel region 121a, that is, the orthographic projection of the gate 123 on the plane of the substrate 10 completely covers the part of the active layer 121 located in the channel region 121a on the plane of the substrate 10. projection.
  • the width of the channel region 121a is 1.5 ⁇ m-2.5 ⁇ m.
  • the active layer 121 further includes a third region 1213 located on opposite sides of the channel region 121a.
  • the third region 1213 on one side of the channel region 121a is located between the channel region 121a and the first heavily doped region 121d.
  • the third region 1213 on the other side of the channel region 121a is located between the channel region 121a and the second heavily doped region 121e.
  • the part of the active layer 121 located in the third region 1213 is lightly doped with ions, and the third region 1213 on the side of the channel region 121a close to the first heavily doped region 121d is formed as the first lightly doped region 121d.
  • the doped region 121b and the third region 1213 on the side of the channel region 121a close to the second heavily doped region 121e are formed as the second lightly doped region 121c.
  • the ion light doping is N-type ion doping
  • the doped ions are phosphorus (P) ions or other N-type element ions.
  • the interlayer dielectric layer 124 is formed by chemical vapor deposition process.
  • the material of the interlayer dielectric layer 124 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the interlayer dielectric layer 124 is patterned through exposure, development and etching processes in order to form the first opening and the second opening.
  • B27 Form a source 125 and a drain 126 on the side of the interlayer dielectric layer 124 away from the gate 123, as shown in FIG. 7H.
  • a source-drain metal layer (not shown in the figure) is formed by a physical vapor deposition process.
  • the material of the source-drain metal layer may include one or more of copper, aluminum, molybdenum and titanium.
  • the source-drain metal layer is patterned through exposure, development and etching processes in order to form the source electrode 125 and the drain electrode 126 .
  • the active layer 121 , the gate insulating layer 122 , the gate 123 , the interlayer dielectric layer 124 , the source 125 and the drain 126 constitute the array layer 12 .
  • step B3 specifically includes:
  • the material of the inorganic insulating layer 13 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the thickness of the inorganic insulating layer 13 is 100nm-1000nm.
  • the inorganic insulating layer 13 may have a single-layer structure, a double-layer structure or a multi-layer structure. In this embodiment, the single-layer structure of the inorganic insulating layer 13 is used as an example for illustration, but it is not limited thereto.
  • a conductive electrode layer is formed on the entire surface of the inorganic insulating layer 13 , and the conductive electrode layer is patterned to form the conductive electrode 14 .
  • an opening corresponding to the drain electrode 126 is formed in the conductive electrode 14 (not marked in the figure).
  • the conductive electrode 14 may be a common electrode.
  • the material of the conductive electrode 14 may include transparent conductive materials such as indium tin oxide.
  • the passivation layer 15 is formed by a chemical vapor deposition process.
  • the material of the passivation layer 15 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the passivation layer 15 and the inorganic insulating layer 13 are etched to form the first via hole 10A, and the drain electrode 126 is exposed through the first via hole 10A, as shown in FIG. 7K .
  • the passivation layer 15 and the inorganic insulating layer 13 are etched through exposure, development and etching processes in sequence, so as to form the first sub-via hole 131 exposing the drain electrode 126 in the inorganic insulating layer 13 , forming a second sub-via 151 connected to the first sub-via 131 in the passivation layer 15 , and the second sub-via 151 of the first sub-via 131 constitutes the first via 10A.
  • a conductive layer (not shown in the figure) is formed by a physical vapor deposition process, and the conductive layer is patterned through exposure, development and etching processes in sequence to form the pixel electrode 16 .
  • the inorganic insulating layer 13 is formed between the array layer 12 and the conductive electrode 14, and the planarized organic layer in the traditional array structure is replaced by the inorganic insulating layer 13. Since the passivation layer 15 is also an inorganic film layer , so that the passivation layer 15 and the inorganic insulating layer 13 can be opened under the same photomask to form the first via hole 10A connecting the pixel electrode 16 and the drain electrode 126, thereby eliminating the need for separate planarization in the traditional process.
  • the photomask required for opening holes in the organic layer reduces the number of photomasks used in the manufacturing process of the array substrate 100 .
  • the array substrate 100 provided in the first embodiment of the present application can be prepared by using the method for preparing the array substrate 100 provided in the above embodiments.
  • Example 2 of the present application provides a method for preparing an array substrate 100.
  • the conductive electrodes 14 can be reused as common electrodes.
  • the difference between the preparation method provided by Example 2 and Example 1 lies in the following steps:
  • step B27 a step of forming a touch wire 17 is also included, as shown in FIG. 8A .
  • the touch wire 17 and the drain 126 are in the same layer and are insulated.
  • the touch wire 17 is located on a side of the source 125 away from the drain 126 .
  • the touch wire 17 , the source 125 and the drain 126 can be prepared by using the same photomask.
  • step B31 a step of forming an opening 141 in the conductive electrode 14 is also included, as shown in FIG. 8B .
  • the opening 141 is provided corresponding to the touch trace 17 .
  • Step B4 includes: under the same photomask, respectively etch the area of the passivation layer 15 and the inorganic insulating layer 13 corresponding to the drain electrode 126 and the area corresponding to the touch wiring 17 to form the first via hole 10A, the second via hole
  • the hole 132 and the third via hole 152, the second via hole 132 penetrates the inorganic insulating layer 13 and exposes the touch trace 17, the third via hole 152 penetrates the passivation layer 15 and communicates with the opening 141 and the second via hole 132, As shown in Figure 8C.
  • connection electrodes 18 is also included, as shown in FIG. 8D .
  • the connecting electrodes 18 are filled in the second via hole 132, the opening 141 and the third via hole 152, and are connected to the opening 141.
  • the side walls are in contact, and the touch electrodes are connected to the touch traces 17 through the connecting electrodes 18 .
  • Example 3 of the present application provides a method for manufacturing the array substrate 100 . Please refer to Figure 9A and Figure 9B, the difference between the preparation method provided by Example 3 and Example 2 lies in the following steps:
  • step B4 the third via hole 152 exposes the surface of the touch electrode away from the substrate 10 .
  • the diameter of the third via hole 152 is larger than that of the opening 141 , so that the surface of the touch electrode is exposed.
  • connection electrodes 18 respectively contact the sidewalls of the opening 141 and the surface of the touch electrodes away from the substrate 10 .
  • Example 4 of the present application provides a method for manufacturing the array substrate 100 . Please refer to Figure 10A and Figure 10B, the difference between the preparation method provided by Example 4 and Example 3 lies in the following steps:
  • Step B4 includes: under the same photomask, respectively etch the area of the passivation layer 15 and the inorganic insulating layer 13 corresponding to the drain electrode 126 and the area corresponding to the touch wiring 17 to form the first via hole 10A, the second via hole hole 132, a third via hole 152 and a fourth via hole 153, the second via hole 132 penetrates the inorganic insulating layer 13 and exposes the touch trace 17, the third via hole 152 penetrates the passivation layer 15 and communicates with the opening 141 and The second via hole 132, the aperture of the second via hole 132 is smaller than the aperture of the opening 141, the fourth via hole 153 is spaced apart from the third via hole 152, the fourth via hole 153 penetrates the passivation layer 15 and exposes the touch electrode, As shown in Figure 10A.
  • connection electrodes 18 is also included, as shown in FIG. 10B .
  • the connection electrodes 18 are filled in the second via hole 132, the third via hole 152, the fourth via hole 153 and part of the opening 141.
  • the part of the connection electrode 18 located in the opening 141 is insulated from the touch electrode, and the touch electrode is connected to the touch trace 17 through the connection electrode 18 .
  • the present application also provides a display panel 1000 .
  • the display panel 1000 includes an array substrate 100 disposed opposite to each other, a color filter substrate 200 and a liquid crystal 300 disposed between the array substrate 100 and the color filter substrate 200 .
  • the array substrate 100 may be the array substrate 100 described in any one of the foregoing embodiments, and the specific structure of the array substrate 100 may refer to the description of the foregoing embodiments, and details are not repeated here.

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Abstract

本申请公开了一种阵列基板及显示面板。所述阵列基板包括依次设置的基底、阵列层、无机绝缘层、导电电极、钝化层以及像素电极；所述阵列层包括源极和漏极，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏极连接。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display,TFT-LCD)具有耗电量小、对比度高以及节省空间等优点，已成为市场上主流的显示装置。与传统A-Si技术相比，低温多晶硅(Low Temperature Poly-Silicon,LTPS)技术具有更高的载流子迁移率，被广泛用于中小尺寸高分辨率的TFT-LCD和有源矩阵有机发光二极管(Active-Matrix Organic Light-Emitting Diode,AMOLED)显示面板的制作，但相应的TFT阵列基板制作所需的光罩数量更多，产品制作周期更长。因此，如何有效地降低LTPS阵列基板的制作周期，提升生产产能及降低成本，以增加市场竞争力，是目前面板行业关注的重点，而改善上述问题的有效方法是开发新型的LTPS阵列基板结构，减少阵列基板制作所需的光罩数量。
技术问题
在传统的LTPS阵列技术中，通常采用10道以上光罩的技术，由此带来较高的成本。
技术解决方案
本申请实施例提供一种阵列基板及显示面板，以解决现有的LTPS阵列技术中所用光罩数量较多的技术问题。
本申请实施例提供一种阵列基板，其包括：
基底；
阵列层，设置于所述基底的一侧，所述阵列层包括源极和漏极；
无机绝缘层，设置于所述阵列层远离所述基底的一侧；
导电电极，设置于所述无机绝缘层远离所述阵列层的一侧；
钝化层，设置于所述导电电极远离所述无机绝缘层的一侧；以及
像素电极，设置于所述钝化层远离所述导电电极的一侧；
其中，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏 极连接。
可选的，在本申请的一些实施例中，所述第一过孔包括第一子过孔和连通于所述第一子过孔的第二子过孔，所述第一子过孔位于所述无机绝缘层中并裸露出所述漏极，所述第二子过孔位于所述钝化层中，所述像素电极分别与所述第一子过孔的孔壁和所述第二子过孔的孔壁接触。
可选的，在本申请的一些实施例中，所述导电电极复用为触控电极，所述阵列基板还包括与所述漏极同层且间隔设置的触控走线，所述连接电极位于所述钝化层远离所述导电电极的一侧，所述触控电极通过所述连接电极与所述触控走线电连接。
可选的，在本申请的一些实施例中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置；所述无机绝缘层中开设有第二过孔，所述第二过孔裸露出所述触控走线，所述钝化层中开设有第三过孔，所述第三过孔连通于所述开口和所述第二过孔，所述连接电极填充在所述第二过孔、所述开口以及所述第三过孔内，并与所述开口的侧壁接触。
可选的，在本申请的一些实施例中，所述第三过孔裸露出所述触控电极远离所述基底的表面。
可选的，在本申请的一些实施例中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置，所述钝化层填充在所述开口内；所述无机绝缘层中开设有第二过孔，所述第二过孔的孔径小于所述开口的孔径，所述第二过孔裸露出所述触控走线，所述钝化层中开设有间隔设置的第三过孔和第四过孔，所述第三过孔连通于所述开口和所述第二过孔，所述第四过孔裸露出所述触控电极，所述连接电极填充在所述第二过孔、所述第三过孔、所述第四过孔以及部分所述开口内，所述连接电极位于所述开口内的部分与所述触控电极绝缘。
可选的，在本申请的一些实施例中，所述第二过孔和所述第三过孔在同一道光罩下形成。
可选的，在本申请的一些实施例中，所述连接电极与所述像素电极同层且绝缘设置。
可选的，在本申请的一些实施例中，所述阵列层还包括：
有源层，设置于所述基底的一侧，所述有源层具有沟道区；
栅极绝缘层，设置于所述有源层远离所述基底的一侧；
栅极，设置于所述栅极绝缘层远离所述有源层的一侧；以及
层间介质层，设置于所述栅极远离所述栅极绝缘层的一侧，所述层间介质层位于所述漏极远离所述无机绝缘层的一侧；
其中，所述有源层的厚度为30nm-45nm。
可选的，在本申请的一些实施例中，所述阵列层还包括：
有源层，设置于所述基底的一侧，所述有源层具有沟道区；
栅极绝缘层，设置于所述有源层远离所述基底的一侧；
栅极，设置于所述栅极绝缘层远离所述有源层的一侧；以及
层间介质层，设置于所述栅极远离所述栅极绝缘层的一侧，所述层间介质层位于所述漏极远离所述无机绝缘层的一侧；
其中，所述沟道区的宽度为1.5μm-2.5μm。
可选的，在本申请的一些实施例中，所述阵列基板还包括缓冲层，所述缓冲层设置在所述基底和所述阵列层之间，所述缓冲层靠近所述基底的一面与所述基底接触。
本申请实施例还提供一种阵列基板，其包括：
基底；
阵列层，设置于所述基底的一侧，所述阵列层包括源极和漏极；
无机绝缘层，设置于所述阵列层远离所述基底的一侧；
导电电极，设置于所述无机绝缘层远离所述阵列层的一侧；
钝化层，设置于所述导电电极远离所述无机绝缘层的一侧；以及
像素电极，设置于所述钝化层远离所述导电电极的一侧；
其中，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏极连接；所述第一过孔包括第一子过孔和连通于所述第一子过孔的第二子过孔，所述第一子过孔位于所述无机绝缘层中并裸露出所述漏极，所述第二子过孔位于所述钝化层中，所述像素电极分别与所述第一子过孔的孔壁和所述第二子过孔的孔壁接触，所述第一子过孔和所述第二子过孔在同一光罩下形成。
本申请实施例提供一种显示面板，所述显示面板包括相对设置的阵列基板、彩膜基板以及设置在所述阵列基板和所述彩膜基板之间的液晶，所述阵列基板包括：
基底；
阵列层，设置于所述基底的一侧，所述阵列层包括源极和漏极；
无机绝缘层，设置于所述阵列层远离所述基底的一侧；
导电电极，设置于所述无机绝缘层远离所述阵列层的一侧；
钝化层，设置于所述导电电极远离所述无机绝缘层的一侧；以及
像素电极，设置于所述钝化层远离所述导电电极的一侧；
其中，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏极连接。
可选的，在本申请的一些实施例中，所述第一过孔包括第一子过孔和连通于所述第一子过孔的第二子过孔，所述第一子过孔位于所述无机绝缘层中并裸露出所述漏极，所述第二子过孔位于所述钝化层中，所述像素电极分别与所述第一子过孔的孔壁和所述第二子过孔的孔壁接触。
可选的，在本申请的一些实施例中，所述导电电极复用为触控电极，所述阵列基板还包括与所述漏极同层且间隔设置的触控走线，所述连接电极位于所述钝化层远离所述导电电极的一侧，所述触控电极通过所述连接电极与所述触控走线电连接。
可选的，在本申请的一些实施例中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置；所述无机绝缘层中开设有第二过孔，所述第二过孔裸露出所述触控走线，所述钝化层中开设有第三过孔，所述第三过孔连通于所述开口和所述第二过孔，所述连接电极填充在所述第二过孔、所述开口以及所述第三过孔内，并与所述开口的侧壁接触。
可选的，在本申请的一些实施例中，所述第三过孔裸露出所述触控电极远离所述基底的表面。
可选的，在本申请的一些实施例中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置，所述钝化层填充在所述开口内；所述无机绝缘层中开设有第二过孔，所述第二过孔的孔径小于所述开口的孔径，所述第二过孔裸露出所述触控走线，所述钝化层中开设有间隔设置的第三过孔和第四过孔，所述第三过孔连通于所述开口和所述第二过孔，所述第四过孔裸露出所述触控电极，所述连接电极填充在所述第二过孔、所述第三过孔、所述第四过孔以及 部分所述开口内，所述连接电极位于所述开口内的部分与所述触控电极绝缘。
可选的，在本申请的一些实施例中，所述第二过孔和所述第三过孔在同一道光罩下形成。
可选的，在本申请的一些实施例中，所述阵列基板还包括缓冲层，所述缓冲层设置在所述基底和所述阵列层之间，所述缓冲层靠近所述基底的一面与所述基底接触。
有益效果
相较于现有技术中的阵列基板，本申请提供的阵列基板通过在阵列层和导电电极之间设置无机绝缘层，以无机绝缘层来代替传统阵列结构中的平坦化有机层，由于钝化层也为无机膜层，因此，在阵列基板的制备工艺中，能够在同一道光罩下对钝化层和无机绝缘层进行开孔，以形成连接像素电极和漏极的第一过孔，从而省去了传统制程中单独对平坦化有机层开孔所需的光罩，减少了阵列基板制备工艺中所用的光罩数量。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的阵列基板的结构示意图。
图2是本申请第一实施例提供的阵列基板的结构示意图。
图3是本申请第二实施例提供的阵列基板的结构示意图。
图4是本申请第三实施例提供的阵列基板的结构示意图。
图5是本申请第四实施例提供的阵列基板的结构示意图。
图6是本申请示例一提供的阵列基板的制备方法的流程示意图。
图7A至图7L是本申请示例一提供的阵列基板的制备方法中各阶段依次得到的结构示意图。
图8A至图8D是本申请示例二提供的阵列基板的制备方法中部分阶段得到的结构示意图。
图9A和图9B是本申请示例三提供的阵列基板的制备方法中部分阶段得到的结构示意图。
图10A和图10B是本申请示例四提供的阵列基板的制备方法中部分阶段得到的结构示意图。
图11是本申请提供的显示面板的结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种阵列基板及显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
如图1所示，现有技术中的阵列基板100’包括依次设置的基底10’、遮光层101’、缓冲层11’、阵列层12’、平坦化有机层13’、触控电极14’、钝化层15’以及像素电极16’。平坦化有机层13’中开设有裸露出漏极(图中未标识)的第一开孔131’，钝化层15’中开设有第二开孔151’，第一开孔131’套设在第二开孔151’的外侧。像素电极16’通过第二开孔151’与漏极电连接。阵列基板100’还包括触控走线17’，触控走线17’与漏极同层设置，平坦化有机层13’中还开设有第三开孔132’，触控电极14’通过第三开孔132’与触控走线17’电连接。
然而，由于平坦化有机层13’为有机膜层，钝化层15’为无机膜层，因此，平坦化有机层13’中的第一开孔131’和钝化层15’中的第二开孔151’各自需要一道光罩才能形成。具体的，当采用一道光罩在平坦化有机层13’中开设裸露出漏极的第一开孔131’之后，在采用另一道光罩在钝化层15’中开设第二开孔151’时，受到工艺制程的限制，第二开孔151’的孔径会小于第一开孔131’的孔径，进而在第一开孔131’内，会形成第一开孔131’套设在第二开孔151’外侧的嵌套结构。综上，在上述阵列基板100’的制程中，由于需要两道光罩才能形成像素电极16’和漏极电连接的过孔结构，故而会增加阵列基板 100’制程中所用的光罩总量。
针对现有技术中存在的上述技术问题，本申请提供一种阵列基板，其包括基底、阵列层、无机绝缘层、导电电极、钝化层以及像素电极。阵列层设置于基底的一侧，阵列层包括源极和漏极；无机绝缘层设置于阵列层远离基底的一侧；导电电极设置于无机绝缘层远离阵列层的一侧；钝化层设置于导电电极远离无机绝缘层的一侧；像素电极设置于钝化层远离导电电极的一侧；其中，阵列基板中开设有第一过孔，第一过孔贯穿钝化层和无机绝缘层并裸露出漏极，像素电极在第一过孔内与漏极连接。
由此，本申请提供的阵列基板通过在阵列层和导电电极之间设置无机绝缘层，以无机绝缘层来代替传统阵列结构中的平坦化有机层，由于钝化层也为无机膜层，因此，在阵列基板的制备工艺中，能够在同一道光罩下对钝化层和无机绝缘层进行开孔，以形成连接像素电极和漏极的第一过孔，从而省去了传统制程中单独对平坦化有机层开孔所需的光罩，减少了阵列基板制备工艺中所用的光罩数量。
请参照图2，本申请第一实施例提供的阵列基板100包括基底10、缓冲层11、阵列层12、无机绝缘层13、导电电极14、钝化层15以及像素电极16。
具体的，基底10可以为硬质基板，如可以为玻璃基板；或者，基底10也可以为柔性基板，如可以为聚酰亚胺基板，本申请对基底10的材质不作具体限定。
缓冲层11设置在基底10的一侧。缓冲层11靠近基底10的一面与基底10接触。缓冲层11的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
阵列层12设置于缓冲层11远离基底10的一侧。阵列层12包括有源层121、栅极绝缘层122、栅极123、层间介质层124、源极125以及漏极126。
其中，有源层121设置于缓冲层11远离基底10的一侧。有源层121的材料包括低温多晶硅。具体的，有源层121具有沟道区121a、第一轻掺杂区121b、第二轻掺杂区121c、第一重掺杂区121d以及第二重掺杂区121e。第一轻掺杂区121b和第二轻掺杂区121c位于沟道区121a的相对两侧。第一重掺杂区121d位于第一轻掺杂区121b远离沟道区121a的一侧。第二重掺杂区121e位于第二轻掺杂区121c远离沟道区121a的一侧。
具体的，第一轻掺杂区121b和第二轻掺杂区121c是通过对有源层121进 行离子轻掺杂而形成。第一重掺杂区121d以及第二重掺杂区121e是通过对有源层121进行离子重掺杂而形成。以NMOS型LTPS TFT基板为例，所述离子重掺杂和所述离子轻掺杂均为N型离子掺杂，所掺入的离子为磷(P)离子或其他N型元素离子。同理，以PMOS型LTPS TFT基板为例，所述离子重掺杂和所述离子轻掺杂均为P型离子掺杂，所掺入的离子为硼(B)离子或其他P型元素离子。
栅极绝缘层122设置于有源层121远离缓冲层11的一侧。栅极绝缘层122的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
栅极123设置于栅极绝缘层122远离有源层121的一侧。栅极123与沟道区121a对应设置。具体来说，栅极123于基底10所在平面的正投影覆盖沟道区121a于基底10所在平面的正投影。其中，栅极123的材料可以包括铜、铝、钼和钛中的一种或多种。
层间介质层124设置于栅极123远离栅极绝缘层122的一侧。层间介质层124位于漏极126远离无机绝缘层13的一侧。其中，层间介质层124的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
源极125和漏极126设置于层间介质层124远离栅极123的一侧。其中，源极125与有源层121位于第一重掺杂区121d的部分接触。漏极126与有源层121位于第二重掺杂区121e的部分接触。源极125和漏极126的材料相同，均可以包括铜、铝、钼和钛中的一种或多种。
无机绝缘层13设置于阵列层12远离层间介质层124的一侧。无机绝缘层13的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。在本实施例中，无机绝缘层13的厚度为100nm-1000nm，如可以为100nm、200nm、500nm、600nm、700nm、800nm、900nm或1000nm。其中，无机绝缘层13可以为单层结构、双层结构或多层结构，本实施例仅以无机绝缘层13为单层结构为例进行说明，但并不限于此。
导电电极14设置于无机绝缘层13远离阵列层12的一侧。在本实施例中，导电电极14整面设置。其中，导电电极14可以为公共电极。导电电极14的材料可以包括氧化铟锡等透明导电材料。
钝化层15设置于导电电极14远离无机绝缘层13的一侧。钝化层15的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
像素电极16设置于钝化层15远离导电电极14的一侧。像素电极16的材料可以包括氧化铟锡等透明导电材料。
在本实施例中，阵列基板100中开设有第一过孔10A。第一过孔10A贯穿钝化层15和无机绝缘层13并裸露出漏极126。像素电极16在第一过孔10A内与漏极126连接。
具体的，第一过孔10A包括第一子过孔131和连通于第一子过孔131的第二子过孔151。其中，第一子过孔131位于无机绝缘层13中并裸露出漏极126。第二子过孔151位于钝化层15中。
在本实施例中，第一子过孔131和第二子过孔151在同一光罩下形成。由此，本实施例通过采用无机绝缘层13来替代传统阵列结构中的平坦化有机层，由于钝化层15也为无机膜层，使得无机绝缘层13中的第一子过孔131和钝化层15中的第二子过孔151能够在同一光罩下形成，以实现像素电极16和漏极126的连接，从而省去了传统制程中单独对平坦化有机层开孔所需的一道光罩，减少了阵列基板100制备工艺中所用的光罩数量，有效降低了阵列基板100的制作周期，提升了生产产能，降低了工艺成本，提高了显示产品的市场竞争力。
进一步的，在本实施例中，有源层121的厚度为30nm-45nm。沟道区121a的宽度为1.5μm-2.5μm。
传统设计中通常在有源层121靠近基底10的一侧设置遮光层来遮挡外界环境光，以保证薄膜晶体管具有较低的光生漏电流。然而，由于上述设置需要额外设置图案化的遮光层，因而需要在原有制程的基础上增加一道光罩，由此增加了阵列基板100制备工艺所用的光罩数量。
针对上述技术问题，由于本申请中的缓冲层11靠近基底10的一面直接与基底10接触，也即，本申请省去了遮光层的设置，进而可以减少阵列制程所用的光罩数量。进一步的，本申请的发明人在实验探究中发现，薄膜晶体管的光生漏电流与有源层121的厚度以及沟道区121a的宽度正相关。在传统设计中，为了保证薄膜晶体管的驱动性能，有源层121的厚度通常设置在45nm以上，沟道区121a的宽度通常设置在2.5μm以上，对此，为了避免因省略遮光层而增加薄膜晶体管的光生漏电流，本实施例将有源层121的厚度设置在30nm-45nm，沟道区121a的宽度设置在1.5μm-2.5μm，在上述范围内，薄膜晶体管的光生漏电流能够得到显著降低。
在一些具体实施方式中，有源层121的厚度可以为30nm、31nm、32nm、33nm、34nm、35nm、36nm、37nm、38nm、39nm、40nm、41nm、42nm、43nm、44nm或45nm。沟道区121a的宽度可以为1.5μm、1.6μm、1.7μm、1.8μm、1.9μm、2.0μm、2.1μm、2.2μm、2.3μm、2.4μm或2.5μm。
请参考表1，表1为薄膜晶体管的光生漏电流在不同有源层121厚度和沟道区121a宽度下的数值。
表1
Figure PCTCN2021136695-appb-000001
由表1可知，在有源层121的厚度不变，如有源层121的厚度为45nm时，通过减小沟道区121a的宽度，光生漏电流的数值明显下降；在沟道区121a的宽度不变，如沟道区121a的宽度为2.5μm时，通过减小有源层121的厚度，光生漏电流的数值明显下降。因此，本实施例通过将有源层121的厚度为30nm-45nm、沟道区121a的宽度为1.5μm-2.5μm能够弥补因省略遮光层而带来的光生漏电流增大的缺陷，进而在保证薄膜晶体管驱动性能的前提下，节省了阵列基板100制备工艺所用的光罩数量，降低了工艺成本。
在一些实施例中，也可以将有源层121的厚度设置在30nm-45nm，沟道区121a的宽度设置在2.5μm以上；或者，还可以将沟道区121a的厚度设置在1.5μm-2.5μm，有源层121的厚度设置在45nm以上。上述设置同样能达到节省光罩并降低薄膜晶体管的光生漏电流的效果。
请参照图3，本申请第二实施例提供一种阵列基板100。本申请第二实施例提供的阵列基板100与第一实施例的不同之处在于：当阵列基板100具有触控功能时，导电电极14可以复用为触控电极。阵列基板100还包括触控走线17和连接电极18。触控走线17与漏极126同层且间隔设置。无机绝缘层13中开设有第二过孔132。第二过孔132裸露出触控走线17。导电电极14中开设有开 口141。开口141与触控走线17对应设置。钝化层15中开设有第三过孔152。第三过孔152连通于开口141和第二过孔132。连接电极18位于钝化层15远离导电电极14的一侧，且与像素电极16绝缘。连接电极18填充在第二过孔132、开口141以及第三过孔152内，并与开口141的侧壁接触。触控电极通过导电电极14与触控走线17相连。
其中，第二过孔132和第三过孔152在同一道光罩下形成。本实施例通过采用无机绝缘层13来替代传统阵列结构中的平坦化有机层，由于钝化层15也为无机膜层，因此，当需要制备具有内嵌式触控功能的阵列基板100时，能够在一道光罩下形成无机绝缘层13中的第二过孔132和钝化层15中的第三过孔152，并在连接电极18的搭接下实现触控走线17和触控电极的导通。
需要说明的是，本实施例中导电电极14复用为触控电极是指当需要执行触控操作时，导电电极14可以作为触控电极使用。另外，当不需要执行触控操作时，导电电极14可以作为公共电极使用，以与像素电极16之间形成存储电容，相关技术均可以参照现有技术，在此不再赘述。
具体的，在本实施例中，触控走线17设置在源极125远离漏极126的一侧。触控走线17、源极125以及漏极126可以采用同一道光罩制备得到。需要说明的是，在一些实施例中，触控走线17也可以设置在漏极126远离源极125的一侧，本实施例对触控走线17的位置不作具体限定。
其中，触控走线17于触控电极所在平面的正投影至少部分位于开口141内，以使得触控电极能够通过连接电极18与触控走线17连接。
在本实施例中，连接电极18与像素电极16同层设置。具体来说，连接电极18和像素电极16可以采用同一道光罩制备得到，由此，本实施例能够在原有制程的基础上形成连接电极18，不会增加工艺制造成本。另外，在一些实施例中，连接电极18和像素电极16也可以异层设置，在此不再赘述。
请参照图4，本申请第三实施例提供一种阵列基板100。本申请第三实施例提供的阵列基板100与第二实施例的不同之处在于：第三过孔152裸露出触控电极远离基底10的表面。
在本实施例中，第三过孔152的孔径大于开口141的孔径，以使触控电极的表面裸露，使得连接电极18能够与触控电极的上表面接触，从而增大了连接电极18与触控电极的接触面积，有利于提高触控电极和触控走线17的导通效 果，提高触控灵敏度。
请参照图5，本申请第四实施例提供一种阵列基板100。本申请第四实施例提供的阵列基板100与第三实施例的不同之处在于：钝化层15填充在开口141内。第二过孔132的孔径小于开口141的孔径。钝化层15中还开设有第四过孔153。第四过孔153和第三过孔152间隔设置。第四过孔153裸露出触控电极。连接电极18填充在第二过孔132、第三过孔152、第四过孔153以及部分开口141内。连接电极18位于开口141内的部分与触控电极绝缘。
本实施例通过在钝化层15中增设第四开孔153，使得连接电极18通过第二开孔132、第三开孔152以及第四开孔153来实现触控电极和触控走线17的导通，进而能够增加导通效果，进一步提高触控灵敏度。
请参照图6，本申请示例一提供一种阵列基板的制备方法，其包括以下步骤：
B1：提供一基底；
B2：在基底的一侧形成阵列层，阵列层包括源极和漏极；
B3：在阵列层远离基底的一侧依次形成无机绝缘层、导电电极以及钝化层；
B4：在同一光罩下，对钝化层和无机绝缘层进行蚀刻，以形成第一过孔，第一过孔裸露出漏极；
B5：在钝化层远离导电电极的一侧形成像素电极，像素电极在第一过孔内与漏极连接。
由此，本申请提供的阵列基板的制备方法通过在阵列层和导电电极之间形成无机绝缘层，以无机绝缘层来代替传统阵列结构中的平坦化有机层，由于钝化层也为无机膜层，因此，在阵列基板的制备工艺中，能够在同一道光罩下对钝化层和无机绝缘层进行开孔，以形成连接像素电极和漏极的第一过孔，从而省去了传统制程中单独对平坦化有机层开孔所需的光罩，减少了阵列基板制备工艺中所用的光罩数量。
请一并参照图6以及图7A至图7L，下面对本实施例提供的阵列基板100的制备方法进行详细的阐述。
B1：提供一基底10，如图7A所示。
其中，基底10可以为硬质基板，如可以为玻璃基板；或者，基底10也可以为柔性基板，如可以为聚酰亚胺基板，本申请对基底10的材质不作具体限定。
B2：在基底10的一侧形成阵列层12，阵列层12包括漏极126。
其中，步骤B2具体包括：
B21：在基底10的一侧依次形成缓冲层11和有源层121，如图7B所示。
首先，采用化学气相沉积工艺形成缓冲层11。其中，缓冲层11的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
其次，在缓冲层11上沉积低温多晶硅，并进行激光镭射退火，以形成整面的有源基层(图中未示出)，然后依次通过曝光、显影和蚀刻工艺对有源基层进行图案化处理，以形成有源层121。其中，有源层121的厚度为30nm-45nm。
B22：在有源层121远离缓冲层11的一侧依次形成栅极绝缘层122和栅极图案123A，如图7C所示。
首先，采用化学气相沉积工艺形成栅极绝缘层122。其中，栅极绝缘层122的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
其次，采用物理气相沉积工艺在栅极绝缘层122上形成一层栅极金属层(图中未示出)，然后依次通过曝光、显影和蚀刻工艺对栅极金属层进行图案化处理，以形成栅极图案123A。具体的，栅极123的材料可以包括铜、铝、钼和钛中的一种或多种。
其中，有源层121包括第一区域1211和设置在第一区域1211相对两侧的第二区域1212。第一区域1211与栅极图案123A对应设置。具体来说，栅极图案123A于基底10所在平面的正投影完全覆盖有源层121位于第一区域1211的部分于基底10所在平面的正投影。
B23：在有源层121中形成第一重掺杂区121d和第二重掺杂区121e，如图7D所示。
以栅极图案123A为掩膜，对有源层121位于第二区域1212的部分进行离子重掺杂，以分别形成第一重掺杂区121d和第二重掺杂区121e。具体的，以NMOS型LTPS TFT基板为例，所述离子重掺杂为N型离子掺杂，所掺入的离子为磷(P)离子或其他N型元素离子。
B24：对栅极图案123A进行蚀刻处理，以形成栅极123，如图7E所示。
其中，采用蚀刻工艺对栅极图案123A进行图案化，以形成栅极123。有源层121对应栅极123的区域为沟道区121a，也即，栅极123于基底10所在平面的正投影完全覆盖有源层121位于沟道区121a的部分于基底10所在平面的 正投影。
在本实施例中，沟道区121a的宽度为1.5μm-2.5μm。有源层121还包括位于沟道区121a相对两侧的第三区域1213。沟道区121a一侧的第三区域1213位于沟道区121a和第一重掺杂区121d之间。沟道区121a另一侧的第三区域1213位于沟道区121a和第二重掺杂区121e之间。
B25：在有源层121中形成第一轻掺杂区121b和第二轻掺杂区121c，如图7F所示。
以栅极123为掩膜，对有源层121位于第三区域1213的部分进行离子轻掺杂，沟道区121a靠近第一重掺杂区121d一侧的第三区域1213形成为第一轻掺杂区121b，沟道区121a靠近第二重掺杂区121e一侧的第三区域1213形成为第二轻掺杂区121c。具体的，以NMOS型LTPS TFT基板为例，所述离子轻掺杂为N型离子掺杂，所掺入的离子为磷(P)离子或其他N型元素离子。
B26：在栅极123远离栅极绝缘层122的一侧形成层间介质层124，并对层间介质层124进行图案化处理，以形成裸露出第一重掺杂区121d的第一开孔(图中未标识)和裸露出第二重掺杂区121e的第二开孔(图中未标识)，如图7G所示。
首先，采用化学气相沉积工艺形成层间介质层124。其中，层间介质层124的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
其次，依次通过曝光、显影和蚀刻工艺对层间介质层124进行图案化处理，以形成所述第一开孔和所述第二开孔。
B27：在层间介质层124远离栅极123的一侧形成源极125和漏极126，如图7H所示。
首先，采用物理气相沉积工艺形成源漏金属层(图中未示出)。其中，源漏金属层的材料可以包括铜、铝、钼和钛中的一种或多种。
其次，依次通过曝光、显影和蚀刻工艺对源漏金属层进行图案化处理，以形成源极125和漏极126。
在本实施例中，有源层121、栅极绝缘层122、栅极123、层间介质层124、源极125以及漏极126构成阵列层12。
B3：在阵列层12远离基底10的一侧依次形成无机绝缘层13、导电电极14以及钝化层15。
其中，步骤B3具体包括：
B31：在阵列层12远离基底10的一侧依次形成无机绝缘层13和导电电极14，如图7I所示。
首先，采用化学气相沉积工艺形成一层无机绝缘层13。其中，无机绝缘层13的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。无机绝缘层13的厚度为100nm-1000nm。其中，无机绝缘层13可以为单层结构、双层结构或多层结构，本实施例仅以无机绝缘层13为单层结构为例进行说明，但并不限于此。
接着，在无机绝缘层13上形成整面的导电电极层，并对导电电极层进行图案化处理以形成导电电极14。其中，导电电极14中形成有对应漏极126的开口(图中未标识)。在本实施例中，导电电极14可以为公共电极。导电电极14的材料可以包括氧化铟锡等透明导电材料。
B32：在所述导电电极14远离无机绝缘层13的一侧形成钝化层15，如图7J所示。
具体的，采用化学气相沉积工艺形成钝化层15。其中，钝化层15的材料可以包括氧化硅、氮化硅和氮氧化硅中的一种或多种。
B4：在同一光罩下，对钝化层15和无机绝缘层13进行蚀刻，以形成第一过孔10A，第一过孔10A裸露出漏极126，如图7K所示。
具体的，在一道光罩下，依次通过曝光、显影和蚀刻工艺对钝化层15和无机绝缘层13进行蚀刻，以在无机绝缘层13中形成裸露出漏极126的第一子过孔131，在钝化层15中形成连通于第一子过孔131的第二子过孔151，第一子过孔131的第二子过孔151构成第一过孔10A。
B5：在钝化层15远离导电电极14的一侧形成像素电极16，像素电极16在第一过孔10A内与漏极126连接，如图7L所示。
具体的，采用物理气相沉积工艺形成一层导电层(图中未示出)，并依次通过曝光、显影和蚀刻工艺对导电层进行图案化处理，以形成像素电极16。
由此，本实施例通过在阵列层12和导电电极14之间形成无机绝缘层13，以无机绝缘层13来代替传统阵列结构中的平坦化有机层，由于钝化层15也为无机膜层，使得能够在同一道光罩下对钝化层15和无机绝缘层13进行开孔，以形成连接像素电极16和漏极126的第一过孔10A，从而省去了传统制程中单 独对平坦化有机层开孔所需的光罩，减少了阵列基板100制备工艺中所用的光罩数量。
需要说明的是，采用上述实施例提供的阵列基板100的制备方法可以制备得到本申请第一实施例提供的阵列基板100。
本申请示例二提供一种阵列基板100的制备方法，在示例二中，当阵列基板100具有触控功能时，导电电极14可以复用为公共电极。请参照图8A至图8D，示例二提供的制备方法与示例一的不同之处在于以下步骤：
在步骤B27中，还包括形成触控走线17的步骤，如图8A所示。其中，触控走线17与漏极126同层且绝缘设置。具体的，触控走线17位于源极125远离漏极126的一侧。在本实施例中，触控走线17、源极125以及漏极126可以采用同一道光罩制备得到。
在步骤B31中，还包括在导电电极14中形成开口141的步骤，如图8B所示。其中，开口141与触控走线17对应设置。
步骤B4包括：在同一光罩下，对钝化层15和无机绝缘层13对应漏极126的区域和对应触控走线17的区域分别进行蚀刻，以形成第一过孔10A、第二过孔132以及第三过孔152，第二过孔132贯穿无机绝缘层13且裸露出触控走线17，第三过孔152贯穿钝化层15且连通于开口141和第二过孔132，如图8C所示。
在步骤B5中，还包括形成连接电极18的步骤，如图8D所示。具体的，在对导电层进行蚀刻时，同时形成相互绝缘的像素电极16和连接电极18，连接电极18填充在第二过孔132、开口141以及第三过孔152内，并与开口141的侧壁接触，触控电极通过连接电极18与触控走线17相连。
本申请示例三提供一种阵列基板100的制备方法。请参照图9A和图9B，示例三提供的制备方法与示例二的不同之处在于以下步骤：
在步骤B4中，第三过孔152裸露出触控电极远离基底10的表面。具体的，在蚀刻时，第三过孔152的孔径大于开口141的孔径，以使触控电极的表面裸露。
在步骤B5中，连接电极18分别与开口141的侧壁以及触控电极远离基底10的表面接触。
本申请示例四提供一种阵列基板100的制备方法。请参照图10A和图10B， 示例四提供的制备方法与示例三的不同之处在于以下步骤：
步骤B4包括：在同一光罩下，对钝化层15和无机绝缘层13对应漏极126的区域和对应触控走线17的区域分别进行蚀刻，以形成第一过孔10A、第二过孔132、第三过孔152以及第四过孔153，第二过孔132贯穿无机绝缘层13且裸露出触控走线17，第三过孔152贯穿钝化层15且连通于开口141和第二过孔132，第二过孔132的孔径小于开口141的孔径，第四过孔153与第三过孔152间隔设置，第四过孔153贯穿钝化层15且裸露出触控电极，如图10A所示。
在步骤B5中，还包括形成连接电极18的步骤，如图10B所示。具体的，在对导电层进行蚀刻时，同时形成相互绝缘的像素电极16和连接电极18，连接电极18填充在第二过孔132、第三过孔152、第四过孔153以及部分开口141内，连接电极18位于开口141内的部分与触控电极绝缘，触控电极通过连接电极18与触控走线17相连。
请参照图11，本申请还提供一种显示面板1000。显示面板1000包括相对设置的阵列基板100、彩膜基板200以及设置在阵列基板100和彩膜基板200之间的液晶300。阵列基板100可以为如前述任一实施例所述的阵列基板100，阵列基板100的具体结构可以参照前述实施例的描述，在此不再赘述。
以上对本申请实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    基底；
    阵列层，设置于所述基底的一侧，所述阵列层包括源极和漏极；
    无机绝缘层，设置于所述阵列层远离所述基底的一侧；
    导电电极，设置于所述无机绝缘层远离所述阵列层的一侧；
    钝化层，设置于所述导电电极远离所述无机绝缘层的一侧；以及
    像素电极，设置于所述钝化层远离所述导电电极的一侧；
    其中，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏极连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一过孔包括第一子过孔和连通于所述第一子过孔的第二子过孔，所述第一子过孔位于所述无机绝缘层中并裸露出所述漏极，所述第二子过孔位于所述钝化层中，所述像素电极分别与所述第一子过孔的孔壁和所述第二子过孔的孔壁接触。
  3. 根据权利要求1所述的阵列基板，其中，所述导电电极复用为触控电极，所述阵列基板还包括与所述漏极同层且间隔设置的触控走线，所述连接电极位于所述钝化层远离所述导电电极的一侧，所述触控电极通过所述连接电极与所述触控走线电连接。
  4. 根据权利要求3所述的阵列基板，其中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置；所述无机绝缘层中开设有第二过孔，所述第二过孔裸露出所述触控走线，所述钝化层中开设有第三过孔，所述第三过孔连通于所述开口和所述第二过孔，所述连接电极填充在所述第二过孔、所述开口以及所述第三过孔内，并与所述开口的侧壁接触。
  5. 根据权利要求4所述的阵列基板，其中，所述第三过孔裸露出所述触控电极远离所述基底的表面。
  6. 根据权利要求3所述的阵列基板，其中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置，所述钝化层填充在所述开口内；所述无机绝缘层中开设有第二过孔，所述第二过孔的孔径小于所述开口的孔径，所述第二过孔裸露出所述触控走线，所述钝化层中开设有间隔设置的第三过孔和第四 过孔，所述第三过孔连通于所述开口和所述第二过孔，所述第四过孔裸露出所述触控电极，所述连接电极填充在所述第二过孔、所述第三过孔、所述第四过孔以及部分所述开口内，所述连接电极位于所述开口内的部分与所述触控电极绝缘。
  7. 根据权利要求4所述的阵列基板，其中，所述第二过孔和所述第三过孔在同一道光罩下形成。
  8. 根据权利要求3所述的阵列基板，其中，所述连接电极与所述像素电极同层且绝缘设置。
  9. 根据权利要求1所述的阵列基板，其中，所述阵列层还包括：
    有源层，设置于所述基底的一侧，所述有源层具有沟道区；
    栅极绝缘层，设置于所述有源层远离所述基底的一侧；
    栅极，设置于所述栅极绝缘层远离所述有源层的一侧；以及
    层间介质层，设置于所述栅极远离所述栅极绝缘层的一侧，所述层间介质层位于所述漏极远离所述无机绝缘层的一侧；
    其中，所述有源层的厚度为30nm-45nm。
  10. 根据权利要求1所述的阵列基板，其中，所述阵列层还包括：
    有源层，设置于所述基底的一侧，所述有源层具有沟道区；
    栅极绝缘层，设置于所述有源层远离所述基底的一侧；
    栅极，设置于所述栅极绝缘层远离所述有源层的一侧；以及
    层间介质层，设置于所述栅极远离所述栅极绝缘层的一侧，所述层间介质层位于所述漏极远离所述无机绝缘层的一侧；
    其中，所述沟道区的宽度为1.5μm-2.5μm。
  11. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括缓冲层，所述缓冲层设置在所述基底和所述阵列层之间，所述缓冲层靠近所述基底的一面与所述基底接触。
  12. 一种阵列基板，其包括：
    基底；
    阵列层，设置于所述基底的一侧，所述阵列层包括源极和漏极；
    无机绝缘层，设置于所述阵列层远离所述基底的一侧；
    导电电极，设置于所述无机绝缘层远离所述阵列层的一侧；
    钝化层，设置于所述导电电极远离所述无机绝缘层的一侧；以及
    像素电极，设置于所述钝化层远离所述导电电极的一侧；
    其中，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏极连接；所述第一过孔包括第一子过孔和连通于所述第一子过孔的第二子过孔，所述第一子过孔位于所述无机绝缘层中并裸露出所述漏极，所述第二子过孔位于所述钝化层中，所述像素电极分别与所述第一子过孔的孔壁和所述第二子过孔的孔壁接触，所述第一子过孔和所述第二子过孔在同一光罩下形成。
  13. 一种显示面板，其中，所述显示面板包括相对设置的阵列基板、彩膜基板以及设置在所述阵列基板和所述彩膜基板之间的液晶，所述阵列基板包括：
    基底；
    阵列层，设置于所述基底的一侧，所述阵列层包括源极和漏极；
    无机绝缘层，设置于所述阵列层远离所述基底的一侧；
    导电电极，设置于所述无机绝缘层远离所述阵列层的一侧；
    钝化层，设置于所述导电电极远离所述无机绝缘层的一侧；以及
    像素电极，设置于所述钝化层远离所述导电电极的一侧；
    其中，所述阵列基板中开设有第一过孔，所述第一过孔贯穿所述钝化层和所述无机绝缘层并裸露出所述漏极，所述像素电极在所述第一过孔内与所述漏极连接。
  14. 根据权利要求13所述的显示面板，其中，所述第一过孔包括第一子过孔和连通于所述第一子过孔的第二子过孔，所述第一子过孔位于所述无机绝缘层中并裸露出所述漏极，所述第二子过孔位于所述钝化层中，所述像素电极分别与所述第一子过孔的孔壁和所述第二子过孔的孔壁接触。
  15. 根据权利要求13所述的显示面板，其中，所述导电电极复用为触控电极，所述阵列基板还包括与所述漏极同层且间隔设置的触控走线，所述连接电极位于所述钝化层远离所述导电电极的一侧，所述触控电极通过所述连接电极与所述触控走线电连接。
  16. 根据权利要求15所述的显示面板，其中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置；所述无机绝缘层中开设有第二过孔，所述第二过孔裸露出所述触控走线，所述钝化层中开设有第三过孔，所述第三过孔 连通于所述开口和所述第二过孔，所述连接电极填充在所述第二过孔、所述开口以及所述第三过孔内，并与所述开口的侧壁接触。
  17. 根据权利要求16所述的显示面板，其中，所述第三过孔裸露出所述触控电极远离所述基底的表面。
  18. 根据权利要求15所述的显示面板，其中，所述触控电极中开设有开口，所述开口与所述触控走线对应设置，所述钝化层填充在所述开口内；所述无机绝缘层中开设有第二过孔，所述第二过孔的孔径小于所述开口的孔径，所述第二过孔裸露出所述触控走线，所述钝化层中开设有间隔设置的第三过孔和第四过孔，所述第三过孔连通于所述开口和所述第二过孔，所述第四过孔裸露出所述触控电极，所述连接电极填充在所述第二过孔、所述第三过孔、所述第四过孔以及部分所述开口内，所述连接电极位于所述开口内的部分与所述触控电极绝缘。
  19. 根据权利要求16所述的显示面板，其中，所述第二过孔和所述第三过孔在同一道光罩下形成。
  20. 根据权利要求13所述的显示面板，其中，所述阵列基板还包括缓冲层，所述缓冲层设置在所述基底和所述阵列层之间，所述缓冲层靠近所述基底的一面与所述基底接触。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104808376A (zh) * 2015-05-11 2015-07-29 厦门天马微电子有限公司 阵列基板及显示装置
CN106775108A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 一种In‑Cell触控阵列基板及其制作方法
CN107479284A (zh) * 2017-08-30 2017-12-15 武汉华星光电技术有限公司 一种阵列基板及其制作方法、显示面板
CN109742088A (zh) * 2018-12-29 2019-05-10 武汉华星光电技术有限公司 一种tft阵列基板
CN109887885A (zh) * 2019-03-01 2019-06-14 武汉华星光电技术有限公司 阵列基板的制作方法及阵列基板
CN110634804A (zh) * 2019-08-09 2019-12-31 武汉华星光电技术有限公司 一种阵列基板及其制备方法、触控显示面板
CN111403338A (zh) * 2020-04-29 2020-07-10 武汉华星光电技术有限公司 阵列基板及其制备方法
US20210225891A1 (en) * 2018-04-28 2021-07-22 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and method for manufacturing same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104808376A (zh) * 2015-05-11 2015-07-29 厦门天马微电子有限公司 阵列基板及显示装置
CN106775108A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 一种In‑Cell触控阵列基板及其制作方法
CN107479284A (zh) * 2017-08-30 2017-12-15 武汉华星光电技术有限公司 一种阵列基板及其制作方法、显示面板
US20210225891A1 (en) * 2018-04-28 2021-07-22 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and method for manufacturing same
CN109742088A (zh) * 2018-12-29 2019-05-10 武汉华星光电技术有限公司 一种tft阵列基板
CN109887885A (zh) * 2019-03-01 2019-06-14 武汉华星光电技术有限公司 阵列基板的制作方法及阵列基板
CN110634804A (zh) * 2019-08-09 2019-12-31 武汉华星光电技术有限公司 一种阵列基板及其制备方法、触控显示面板
CN111403338A (zh) * 2020-04-29 2020-07-10 武汉华星光电技术有限公司 阵列基板及其制备方法

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