WO2023097496A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2023097496A1
WO2023097496A1 PCT/CN2021/134572 CN2021134572W WO2023097496A1 WO 2023097496 A1 WO2023097496 A1 WO 2023097496A1 CN 2021134572 W CN2021134572 W CN 2021134572W WO 2023097496 A1 WO2023097496 A1 WO 2023097496A1
Authority
WO
WIPO (PCT)
Prior art keywords
mask
edge
data line
sub
pole
Prior art date
Application number
PCT/CN2021/134572
Other languages
English (en)
French (fr)
Other versions
WO2023097496A9 (zh
Inventor
付婉霞
李梁梁
陈小龙
陈周煜
林滨
林增杰
李增荣
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/134572 priority Critical patent/WO2023097496A1/zh
Priority to CN202180003730.5A priority patent/CN117377903A/zh
Publication of WO2023097496A1 publication Critical patent/WO2023097496A1/zh
Publication of WO2023097496A9 publication Critical patent/WO2023097496A9/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.
  • amorphous silicon (A-Si) thin film transistors are widely used in the driving backplane of liquid crystal display devices.
  • A-Si amorphous silicon
  • TFTs thin film transistors
  • the same mask is often used for the active semiconductor layer and the source and drain metal
  • the half-exposure process forms thin film transistors.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate, and a semiconductor layer and a conductive layer on the base substrate.
  • the semiconductor layer is located on the base substrate, the semiconductor layer includes the channel region of the transistor and the pattern of the doped region; the conductive layer is stacked with the semiconductor layer, and is located on the semiconductor layer away from the substrate
  • the conductive layer includes a data line and a first pole and a second pole of the transistor electrically connected to the doped region pattern, and the first pole is electrically connected to the data line.
  • the extending direction of the overlapping portion of the semiconductor layer and the data line is the same as the extending direction of the data line, and the semiconductor layer includes a first protrusion that is not covered by the data line and protrudes relative to the edge of the data line part, the first protruding part is arranged on the edge of the data line, the distance between the edge of the first protruding part away from the data line and the edge of the data line is a first dimension, and the first protruding part is A dimension is greater than 0 and less than 3.0 microns.
  • the portion where the edge of the semiconductor layer protrudes relative to the edge of the first pole is a second protrusion, and the second protrusion is disposed on the edge of the first pole, so The distance between the edge of the second protruding portion away from the first pole and the edge of the first pole is a second dimension, and the second dimension is larger than the first dimension.
  • the first protruding portion includes a first step and a second step arranged in layers, and the first step is located between the second step and the base substrate , and the distance between the edge of the first step and the edge of the data line is the first step size, and the distance between the edge of the second step and the edge of the data line is the first step Two step sizes; the ratio of the first step size to the second step size ranges from 2 to 25.
  • the material of the first step includes amorphous silicon
  • the material of the second step includes doped amorphous silicon
  • the data line includes at least one conductive layer
  • the included angle range between the side wall of the data line and the surface of the second-level step away from the base substrate includes 30-80 degrees.
  • the second protrusion includes a third-level step and a fourth-level step arranged in layers, and the third-level step is located between the fourth-level step and the base substrate , and the distance between the edge of the third step and the edge of the first pole is the third step size, and the distance between the edge of the fourth step and the edge of the first pole is is a fourth step size; the first step size is smaller than the third step size.
  • the material of the third step includes amorphous silicon
  • the material of the fourth step includes doped amorphous silicon
  • a ratio of the first step size to the second step size is smaller than a ratio of the third step size to the fourth step size.
  • the transistor further includes a gate, the gate is located between the semiconductor layer and the base substrate, and the positive side of the second protrusion on the base substrate The projection is located within the orthographic projection of the film layer where the gate is located on the base substrate.
  • the display substrate further includes: a plurality of sub-pixels, each sub-pixel includes a pixel electrode, and the pixel electrode is located on a side of the conductive layer away from the base substrate.
  • the second pole is electrically connected to the pixel electrode;
  • the semiconductor layer further includes a third protruding portion overlapping with the second pole and protruding relative to the edge of the second pole, the third protruding portion surrounds At least part of the edge of the second pole, the third protrusion away from the edge of the second pole and the minimum interval between the edge of the second pole is a third dimension, the third dimension is greater than the first dimension.
  • the display substrate further includes: a gate line, which is arranged on the same layer as the gate and is electrically connected to the gate.
  • the plurality of sub-pixels are arranged in an array along the row direction and the column direction, and two adjacent sub-pixel columns form a sub-pixel column group; the data lines extend along the column direction, and the gate lines extend along the row direction, so
  • the gate lines include a plurality of first sub-gate lines and a plurality of second sub-gate lines; the data lines are located between two adjacent sub-pixel column groups, and the two columns of sub-pixels in the sub-pixel column groups are the same
  • the data line is electrically connected;
  • the sub-pixel column group includes multiple rows of sub-pixel rows, and along the column direction, the first sub-gate line and the second sub-gate line are respectively arranged on both sides of each sub-pixel row gate lines, and adjacent rows of sub-pixels include gate line pairs composed of the first sub-gate lines and the second sub-gate lines.
  • the ratio of the second step size to the fourth step size is 0.8 ⁇ 1.2.
  • An embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • An embodiment of the present disclosure provides a method for manufacturing a display substrate, including: providing a base substrate; forming a semiconductor material layer on the base substrate; forming a conductive material on a side of the semiconductor material layer away from the base substrate layer; and forming an etching mask on a side of the conductive material layer away from the semiconductor material layer.
  • the etching mask includes a first mask portion, the first mask portion includes a first sub-mask portion and a second sub-mask portion, the second sub-mask portion is located on the first sub-mask part, and the second sub-mask part is located at the edge of the first mask part, along the direction perpendicular to the base substrate, the thickness of the first sub-mask part is larger than the The thickness of the second sub-mask portion.
  • the manufacturing method further includes: patterning the conductive material layer and the semiconductor material layer using the first mask portion as a mask to form data lines and A first semiconductor pattern between the line and the base substrate, wherein the first semiconductor pattern includes a first protruding portion that is not covered by the data line and protrudes relative to the edge of the data line, the first A protruding portion is disposed on the edge of the data line, and the distance between the first protruding portion away from the edge of the data line and the edge of the data line is a first size; the first size is greater than 0 and Less than 3.0 microns.
  • using the first mask part as a mask to pattern the conductive material layer and the semiconductor material layer includes: using the first mask part as a mask to etch The conductive material layer forms a data line pattern; after the data line pattern is formed, the semiconductor material layer is etched using the first mask part as a mask to form a first semiconductor pattern layer.
  • using the first mask part as a mask to pattern the conductive material layer and the semiconductor material layer includes: using the first mask part as a mask to pattern the The conductive material layer is wet-etched to form the data line pattern, and the semiconductor material layer is dry-etched using the first mask part as a mask so that the edge of the first mask part and the semiconductor The edges of the material layers are simultaneously etched.
  • the etching mask further includes a second mask portion, and the second mask portion includes a third sub-mask portion at an edge position along a direction perpendicular to the base substrate. direction, the thickness of the third sub-mask part is the same as the thickness of the first sub-mask part; after forming the etching mask, the manufacturing method further includes: using the second mask part as a mask Patterning the conductive material layer and the semiconductor material layer to form the first pole and the second pole of the transistor and the first pole between the first pole and the second pole of the transistor and the base substrate Two semiconductor patterns, wherein the second semiconductor pattern includes the channel region of the transistor and the pattern of the doped region, and the protruding portion of the edge of the second semiconductor pattern relative to the edge of the first electrode is the second a protruding portion, the first pole and the second pole are electrically connected to the doped region pattern, the first pole is electrically connected to the data line, and the second protruding portion is far away from the first pole
  • using the second mask part as a mask to pattern the conductive material layer and the semiconductor material layer includes: using the second mask part as a mask to etch The conductive material layer forms a transistor source-drain pattern; after forming the transistor source-drain pattern, the semiconductor material layer is etched using the second mask part as a mask to form a second semiconductor pattern layer.
  • the semiconductor material layer is etched using the first mask portion and the second mask portion as a mask to form the first semiconductor pattern layer and the second semiconductor pattern layer.
  • the manufacturing method further includes: performing ashing treatment on the first mask part and the second mask part at the same time. In a direction perpendicular to the base substrate, the thickness of the ashed first mask portion is smaller than the thickness of the unashed first sub-mask portion.
  • the manufacturing method further includes: using the ashed first mask The part is used as a mask to etch the data line pattern to form the data line; after the data line is formed, use the ashed first mask part as a mask to process the edge of the first semiconductor pattern layer Etching to form a first level step and a second level step.
  • the first semiconductor pattern includes the first-level step and the second-level step, the first-level step is located between the second-level step and the base substrate, and the first-level step
  • the distance between the edge of the step and the edge of the data line is the first step size
  • the distance between the edge of the second step and the edge of the data line is the second step size
  • the ratio of the step size to the second step size ranges from 2-25.
  • the first mask portion in the etching mask is formed using a half tone mask or a slit mask.
  • FIG. 1 is a schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure
  • Fig. 2 is the partial sectional structure schematic diagram cut along the AA ' line shown in Fig. 1;
  • Fig. 3 is the partial sectional structure schematic diagram cut along the BB ' line shown in Fig. 1;
  • FIG. 4 is a schematic diagram of a partial planar structure of a display substrate provided according to an example of an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure.
  • 6A to 6C are schematic diagrams of a method for making a partial cross-sectional structure of a display substrate cut along the DD' line shown in FIG. 1;
  • FIG. 6D includes a plan view of the slit mask shown in FIG. 6B and FIG. 7B;
  • FIG. 7A to 7C are schematic diagrams of a method for making a partial cross-sectional structure of a substrate shown in FIG. 1 along the line EE';
  • Fig. 8 is a schematic diagram of another method of making a partial cross-sectional structure of the substrate shown in Fig. 1 along the EE' line;
  • FIG. 9 is a schematic diagram of patterning and forming data line patterns using the first mask part as a mask
  • FIG. 10 is a schematic diagram of patterning the source and drain patterns of transistors by using the second mask part as a mask
  • FIG. 11 is a schematic diagram of patterning a semiconductor material layer to form a first semiconductor pattern layer by using the first mask part as a mask;
  • FIG. 12 is a schematic diagram of patterning a semiconductor material layer to form a second semiconductor pattern layer by using the second mask part as a mask;
  • FIG. 13 is a schematic diagram of ashing the etched first mask portion
  • FIG. 15 is a schematic diagram of etching a data line pattern using the ashed first mask portion as a mask
  • 16 is a schematic diagram of etching the source and drain patterns of the transistor using the ashed second mask portion as a mask
  • 17 is a schematic diagram of etching the first semiconductor pattern layer using the ashed first mask part as a mask.
  • FIG. 18 is a schematic diagram of etching the second semiconductor pattern layer using the ashed second mask portion as a mask.
  • the inventors of the present application found that the channel of the thin film transistor is manufactured by the data layer semi-exposure (SDT) process, including two wet etching and two dry etching (2W2D) processes, and the above-mentioned 2W2D process is likely to cause source and drain
  • SDT data layer semi-exposure
  • 2W2D dry etching
  • the protruding part of the active layer When the above-mentioned protruding part of the active layer is illuminated (such as being illuminated by a backlight), the protruding part of the active layer will generate photogenerated carriers and become a conductor; when the protruding part of the active layer is not illuminated, the protruding part of the active layer will The part is an insulating layer, and the current value generated by the protruding part of the active layer is different in the dark state and the light state, which is likely to affect the stability of the product. Under the action of the AC backlight, different positions where the protruding part of the active layer is located receive different light conditions, which may easily lead to water moiré defects in the display device.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • the display substrate includes a base substrate and a semiconductor layer and a conductive layer on the base substrate.
  • the semiconductor layer includes the channel region of the transistor and the pattern of the doped region; the conductive layer is stacked with the semiconductor layer and is located on the side of the semiconductor layer away from the substrate; the conductive layer includes the data line and the transistor electrically connected to the pattern of the doped region
  • the first pole and the second pole, the first pole is electrically connected with the data line.
  • the extending direction of the overlapping portion of the semiconductor layer and the data line is the same as the extending direction of the data line
  • the semiconductor layer includes a first protruding portion which is not covered by the data line and protrudes relative to the edge of the data line, and the first protruding portion is arranged on the edge of the data line
  • the distance between the edge of the first protruding portion away from the data line and the edge of the data line is a first size, and the first size is greater than 0 and less than 3.0 microns.
  • the size of the first protruding portion where the edge of the semiconductor layer protrudes relative to the edge of the data line is set to be greater than 0 and less than 3 microns, it is beneficial to reduce the size of the product design margin and improve product performance, and The probability of poor display of the display device is reduced.
  • the extending direction of the overlapping part of the semiconductor layer and the data line is the same as the extending direction of the data line, that is, a semiconductor layer in the same extending direction as the data line is also provided between the data line and the substrate.
  • the semiconductor layer A mask can be used for the data line layer and the data line layer, which saves the mask and improves the production efficiency.
  • Fig. 1 is a schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure
  • Fig. 2 is a schematic diagram of a partial cross-sectional structure taken along line AA' shown in Fig. 1
  • the display substrate includes a base substrate 100 and a semiconductor layer 200 and a conductive layer 400 located on the base substrate 100 .
  • the semiconductor layer 200 is located on the base substrate 100, and the semiconductor layer 200 includes the channel region 310 and the doped region pattern 320 of the transistor 300;
  • the conductive layer 400 includes a data line 410 and a first pole 301 and a second pole 302 of the transistor 300 electrically connected to the doped region pattern 320 , and the first pole 301 is electrically connected to the data line 410 .
  • the extending direction of the overlapping portion of the semiconductor layer 200 and the data line 410 is the same as the extending direction of the data line 410, the semiconductor layer 200 includes a first protrusion 210 not covered by the data line 410 and protruding relative to the edge of the data line 410, the first protrusion The portion 210 is disposed on the edge of the data line 410, and the distance between the edge of the first protruding portion 210 away from the data line 410 and the edge of the data line 410 is a first dimension S1, and the first dimension S1 is greater than 0 and less than 3.0 microns.
  • the size of the first protruding portion where the edge of the semiconductor layer protrudes relative to the edge of the data line is set to be greater than 0 and less than 2 microns, it is beneficial to reduce the size of the product design margin and improve product performance, and The probability of poor display of the display device is reduced.
  • the size of the first protruding portion protruding from the edge of the semiconductor layer relative to the edge of the data line is small, which is beneficial to reduce the impact of the first protruding portion protruding from the edge of the data line on other structures.
  • the probability of the first protruding portion being irradiated by light from the backlight source to generate carriers can be reduced as much as possible, and the stability of the display substrate can be improved.
  • the part of the semiconductor layer 200 overlapping with the data line 410 has the same extension direction as the data line 410, and the part of the semiconductor layer is set in the same layer as the channel region 310 and the doped region pattern 320 of the transistor 300. , but with different shapes.
  • FIG. 1 schematically shows that the conductive layer 400 in the area circled by the dotted line is the first pole 301 of the transistor 300 , and the first pole 301 can be electrically connected to the data line 410 through the connecting portion 330 .
  • the data line 410, the first pole 301 and the connection part 330 may be an integrated structure.
  • the first pole 301 and the second pole 302 of the transistor 300 are arranged at intervals, and the semiconductor layer 200 between the first pole 301 and the second pole 302 may be a channel region, called a channel region.
  • the surface of the conductive layer 400 is in contact with the surface of the semiconductor layer 200 .
  • the orthographic projection of the data line 410 on the base substrate 100 falls within the orthographic projection of the semiconductor layer 200 on the base substrate 100 .
  • the extending direction of the overlapping portion of the semiconductor layer 200 and the data line 410 and the extending direction of the data line 410 may both be the Y direction shown in the figure.
  • the channel region 310 and the doped region pattern 320 of the transistor 300 may be an integrated structure.
  • the doped region pattern 320 may include a source region and a drain region, one of the first electrode 301 and the second electrode 302 is electrically connected to the source region, and the other of the first electrode 301 and the second electrode 302 is connected to the drain. area electrical connection.
  • the doped region pattern 320 is covered by the first pole 301 and the second pole 302 , so that the design increases the ohmic contact between the doped region pattern and the first pole and the second pole.
  • the source region and the drain region of the transistor may be structurally the same, so there may be no structural difference between the source region and the drain region, so the two can be interchanged as required of.
  • the semiconductor layer 200 overlapping with the data line 410 includes a middle portion covered by the data line 410 and an edge portion not covered by the data line 410, and the edge portion not covered by the data line 410
  • the portion includes a first protrusion 210 .
  • the first protruding portion 210 is located at a position other than the edge of the data line 410 .
  • the number of data lines 410 may be multiple, each data line 410 may extend along the Y direction, and a plurality of data lines 410 are arranged along the X direction, and the first protrusion 210 may include The portion located at least one side of the data line 410 in the X direction may also include a portion located at least one side of the data line 410 in the Y direction.
  • the first protruding portion 210 may include parts located on both sides of the data line 410 in the X direction, and the widths of the two parts in the X direction may be the same or different.
  • the first protruding portion 210 may include parts located on both sides of the data line 410 in the Y direction, and the widths of the two parts in the Y direction may be the same or different.
  • the above-mentioned X direction and Y direction can be interchanged.
  • the first protruding portion 210 may extend along the Y direction, and the width of the first protruding portion 210 in the X direction may be a first dimension S1 .
  • the first protruding portion 210 may extend along the X direction, and the width of the first protruding portion 210 may be the first dimension S1.
  • the first dimension S1 may be 0.5-3 microns.
  • the first size S1 may be 1-2 microns.
  • the first dimension S1 is not greater than 1.8 microns.
  • the first dimension S1 is not greater than 1.6 microns.
  • the first dimension S1 is not greater than 1.4 microns.
  • the first dimension S1 is not greater than 1.3 microns.
  • Fig. 3 is a schematic diagram of a partial cross-sectional structure taken along the line BB' shown in Fig. 1 .
  • the protruding portion of the edge of the channel region 310 relative to the edge of the first pole 301 of the transistor 300 is the second protrusion 220
  • the second protrusion 220 is disposed on the edge of the first pole 301 .
  • the edge, the distance between the edge of the second protruding portion 220 away from the first pole 301 and the edge of the first pole 301 is a second dimension S2, and the second dimension S2 is larger than the first dimension S1.
  • the size of the first protruding portion protruding from the edge of the semiconductor layer relative to the edge of the data line is set to be smaller than the size of the second protruding portion protruding from the edge of the semiconductor layer relative to the edge of the first pole of the transistor, which can Without affecting the normal operation of the transistor, reducing the size of the first protruding part on the edge of the data line as much as possible is beneficial to reducing the size of the edge of the product design and solving undesirable problems such as water ripples and afterimages caused by the longer first protruding part , thereby improving product performance.
  • the semiconductor layer included in the transistor is covered by the gate (described later), which can block the light from the backlight from affecting the semiconductor layer at the position of the transistor, while the semiconductor layer overlapping the data line is not blocked by the film layer where the gate is located, and is easily blocked by the backlight.
  • the light from the source affects the electrical properties of the semiconductor layer.
  • setting the size of the first protrusion to be smaller than the size of the second protrusion may not change the shape of the semiconductor layer in the transistor, but reduce the relative The length of the protruding part of the line, thereby reducing the impact of the backlight on the semiconductor layer.
  • the orthographic projection of the first pole 301 of the transistor 300 on the base substrate 100 completely falls within the orthographic projection of the semiconductor layer 200 on the base substrate 100 .
  • the planar shape of the first pole 301 of the transistor 300 includes a U shape
  • the planar shape of the second pole 302 of the transistor 300 includes a strip shape inserted into the U-shaped opening
  • the second protruding portion 220 around the U-shaped perimeter.
  • the second size S2 of the second protrusion 220 may be a dimension of the second protrusion 220 in a direction parallel to the width of the first pole 301 .
  • the semiconductor layer 200 overlapping the first pole 301 of the transistor 300 includes a portion covered by the first pole 301 and two parts not covered by the first pole 301 , which are not covered by the first pole 301 .
  • the two parts covered by the pole 301 include a part located inside the first pole 301 and a part located outside the first pole 301, and the second protruding part 220 is located at the first pole of the two parts of the semiconductor layer 200 not covered by the first pole 301. 301 outer part.
  • the second protruding portion 220 includes a portion located at least one side edge of the first electrode 301 of the transistor 300 .
  • the second protruding part 220 may include two parts located at the edges of both sides of the first pole 301 of the transistor 300, and the widths of the two parts may be the same or different.
  • the second dimension S2 is greater than 3 microns.
  • the second dimension S2 is greater than 2 microns.
  • the second size S2 is 2-2.6 microns.
  • the second size S2 is 3-5 microns.
  • the first protruding portion 210 includes a first-level step 211 and a second-level step 212 stacked, and the first-level step 211 is located between the second-level step 212 and the base substrate 100 , and the distance between the edge of the first step 211 and the edge of the data line 410 is the first step size, that is, the first dimension S1, and the distance between the edge of the second step 212 and the edge of the data line 410 is The size is the second step size S11, and the first step size is larger than the second step size S11.
  • the ratio of the first step size to the second step size ranges from 2-25.
  • the ratio of the first step size to the second step size ranges from 3-20.
  • the ratio of the first step size to the second step size ranges from 5-15.
  • the ratio of the first step size to the second step size ranges from 8-12.
  • the first step 211 and the second step 212 may be an integrated structure.
  • the material of the first-level step 211 includes amorphous silicon (a-Si)
  • the material of the second-level step 212 includes doped amorphous silicon.
  • the second-level step 212 can be N-type doped amorphous silicon ( N+a-Si), for example, the material of the second step 212 can be doped with phosphorus. Doping amorphous silicon can effectively reduce the contact resistance between amorphous silicon (a-Si) and the film layer where the data line is located, and form a good ohmic contact.
  • the thickness of the first step 211 is greater than that of the second step.
  • the thickness of the step 212 is greater than that of the second step.
  • the side wall of the first step 211 away from the data line 410 can be an inclined side wall
  • the side wall of the second step 212 away from the data line 410 can be an inclined side wall.
  • the sidewalls of the first-level steps 211 and the second-level steps 212 have different angles with respect to the main surface (the surface perpendicular to the Z-direction) of the base substrate 100 .
  • the above-mentioned first-level step includes a surface that is substantially parallel to the base substrate and a surface that has a certain angle with the base substrate. surface at a certain angle.
  • the above-mentioned second-level step includes a surface that is substantially parallel to the base substrate and a surface that has a certain angle with the base substrate. surface at a certain angle.
  • the angle between the sidewall of the first step 211 and the substrate 100 is greater than the angle between the sidewall of the second step 212 and the substrate 100 .
  • the angle between the sidewall of the first step 211 and the substrate 100 may also be smaller than the angle between the sidewall of the second step 212 and the substrate 100 .
  • the angle between the side wall of the first step 211 and the base substrate 100 may be 40-60 degrees, and the angle between the side wall of the second step 212 and the base substrate 100 may be 40-60 degrees.
  • the angle can be 20-40 degrees.
  • the angle between the side wall of the first step 211 and the substrate 100 may be 45-55 degrees, and the angle between the side wall of the second step 212 and the substrate 100 may be 30-38 degrees.
  • Spend. For example, the angle between the side wall of the first step 211 and the substrate 100 may be 50-52 degrees, and the angle between the side wall of the second step 212 and the substrate 100 may be 35-37 degrees.
  • the data line 410 includes at least one conductive layer
  • the shape of the cross section of the data line 410 parallel to the XZ plane can be a trapezoid
  • the side of the trapezoid can be that the side wall of the data line 410 is parallel to The line cut by the XZ plane.
  • the included angle range between the sidewall of the data line 410 and the surface of the second-level step 212 away from the base substrate 100 includes 30-80 degrees.
  • the included angle range between the sidewall of the data line 410 and the surface of the second-level step 212 away from the base substrate 100 includes 40-70 degrees.
  • the included angle between the sidewall of the data line 410 and the surface of the second-level step 212 away from the base substrate 100 includes 50-60 degrees.
  • the data line 410 includes a first metal layer 411, a second metal layer 412, and a third metal layer 413 that are sequentially stacked along a direction perpendicular to the base substrate 100, and the first metal layer 411 is located at the Between the second metal layer 412 and the base substrate 100 , the material of the first metal layer 411 is the same as that of the third metal layer 413 , and the materials of the first metal layer 411 and the second metal layer 412 are different.
  • the material of the first metal layer 411 and the third metal layer 413 may both be molybdenum, and the material of the second metal layer 412 may be aluminum.
  • the material of the data line may also be a metal material such as copper.
  • both the thickness of the first metal layer 411 and the thickness of the third metal layer 413 are smaller than the thickness of the second metal layer 412 .
  • the thickness of the third metal layer 413 is greater than the thickness of the first metal layer 411 .
  • the thickness of the data line 410 is 2000 ⁇ 6000 angstroms.
  • the thickness of the semiconductor layer 200 is smaller than the thickness of the conductive layer 400 .
  • the thickness of the semiconductor layer 200 may be 1000 ⁇ 5000 angstroms.
  • the thickness of the semiconductor layer 200 may be 1000 ⁇ 2000 angstroms.
  • the second protrusion 220 includes a third-level step 221 and a fourth-level step 222 stacked, the third-level step 221 is located between the fourth-level step 222 and the base substrate 100, and the third-level step 221 is located between the fourth-level step 222 and the base substrate 100, and the The distance between the edge of the third-level step 221 and the edge of the first pole 301 of the transistor 300 is the third step size, that is, the second dimension S2, and the distance between the edge of the fourth-level step 222 and the edge of the first pole 301
  • the size of is the fourth step size S21, and the fourth step size S21 is smaller than the third step size.
  • the third step 221 and the fourth step 222 may be an integrated structure.
  • the material of the third-level step 221 includes amorphous silicon (a-Si)
  • the material of the fourth-level step 222 includes doped amorphous silicon.
  • the fourth-level step 222 can be N-type doped amorphous silicon ( N+a-Si), for example, the material of the fourth step 222 can be doped with phosphorus. Doping amorphous silicon can effectively reduce the contact resistance between amorphous silicon (a-Si) and the film layer where the data line is located, and form a good ohmic contact.
  • the thickness of the third step 221 is greater than the thickness of the fourth step 222 .
  • the first step 211 and the third step 221 may use the same material, and the second step 212 and the fourth step 222 may use the same material.
  • the thickness of the first step 211 and the third step 221 may be the same, and the thickness of the second step 212 and the fourth step 222 may be the same.
  • the first step size is smaller than the third step size.
  • the size of the first step may be 0.5-2 microns.
  • the first step size is not greater than 1.8 microns.
  • the first step size is not greater than 1.6 microns.
  • the first step size is not greater than 1.4 microns.
  • the size of the first step is not greater than 1.3 microns.
  • the size of the first step is not greater than 1.3 microns.
  • the first step size is greater than 0.5 microns.
  • the first step size is greater than 1 micron.
  • the third step size is greater than 2 microns.
  • the size of the third step is 2-2.6 microns.
  • the size of the third step is 3-4 microns.
  • the ratio of the first step size to the second step size S11 is smaller than the ratio of the third step size to the fourth step size S21 .
  • the ratio of the second step size S11 to the fourth step size S21 is 0.8 ⁇ 1.2.
  • the ratio of the second step size S11 to the fourth step size S21 is 0.9 ⁇ 1.1.
  • the second step size S11 is the same as the fourth step size S21.
  • the second step size S11 and the fourth step size S21 may be 0.1 ⁇ 0.5 ⁇ m.
  • the size of the second step in the first protrusion is set to be the same as the size of the fourth step in the second protrusion, and the size of the first step in the first protrusion is set to be smaller than that in the second protrusion.
  • the size of the third step can reduce the size of the semiconductor layer at the edge of the data line without affecting the contact area between the doped amorphous silicon material and the conductive layer, so as to reduce the impact of the semiconductor layer protruding from the edge of the data line on product performance. Influence.
  • the connecting portion 330 configured to connect the data line 410 and the first pole 301 of the transistor 300 is also stacked with the semiconductor layer 200, and the extending direction of the overlapping portion of the semiconductor layer 200 and the connecting portion 330 is the same as The extending direction of the connecting portion 330 is the same, and the part of the semiconductor layer includes a protruding portion 240 that is not covered by the connecting portion 330 and protrudes relative to the edge of the connecting portion 330.
  • the protruding portion 240 is arranged on at least one side edge of the connecting portion 330, the The distance between the edge of the protruding portion 240 away from the connecting portion 330 and the edge of the connecting portion 330 may be the same as the first dimension of the first protruding portion 210, so as to minimize the influence of the semiconductor layer protruding from the edge of the connecting portion on product performance .
  • the transistor 300 further includes a gate 303 located between the semiconductor layer 200 and the base substrate 100 , and the orthographic projection of the second protruding portion 220 on the base substrate 100 is located at the gate 303 .
  • the film layer where the electrode 303 is located is within the orthographic projection on the base substrate 100 .
  • the gate 303 may overlap with one of the first pole 301 and the second pole 302 of the transistor 300 to form a storage capacitor.
  • the display substrate further includes a gate insulating layer 101 located between the semiconductor layer 200 and the base substrate 100 and located on the side of the gate 303 away from the base substrate 100 .
  • the thickness of the gate insulating layer 101 may be 2500 ⁇ 4000 angstroms.
  • FIG. 4 is a schematic diagram of a partial planar structure of a display substrate provided according to an example of an embodiment of the present disclosure
  • FIG. 1 is an enlarged view of a part C of the display substrate shown in FIG. 4
  • the display substrate includes a plurality of sub-pixels 10 , and each sub-pixel 10 includes a pixel electrode 11 , and the pixel electrode 11 is located on a side of the conductive layer 400 away from the base substrate 100 .
  • the second electrode 302 of the transistor 300 is electrically connected to the pixel electrode 11 .
  • the material of the pixel electrode 11 can be indium tin oxide.
  • the thickness of the pixel electrode 11 may be 400 ⁇ 1100 angstroms.
  • a passivation layer may be provided between the pixel electrode 11 and the second electrode 302 of the transistor 300, and the thickness of the passivation layer may be 1000 ⁇ 6000 angstroms.
  • the display substrate may further include a common electrode.
  • the common electrode can be located on the side of the pixel electrode away from the base substrate, and multiple sub-pixels can share the common electrode.
  • the common electrode may be located between the pixel electrode and the base substrate.
  • one of the pixel electrode and the common electrode may be a plate electrode, and the other may be a slit electrode.
  • the common electrode can be arranged on the same layer as the pixel electrode.
  • the display substrate may be an array substrate, and the common electrode may be disposed on a counter substrate opposite to the display substrate.
  • the embodiment of the present disclosure does not limit the positional relationship and shape of the common electrode and the pixel electrode, which can be set according to product requirements.
  • the semiconductor layer 200 further includes a third protruding portion 230 overlapping with the second pole 302 of the transistor 300 and protruding relative to the edge of the second pole 302 , the third protruding portion 230 surrounds the second pole 302 At least part of the edge of the third protruding portion 230, the dimension of the minimum interval between the edge of the third protrusion 230 away from the second pole 302 and the edge of the second pole 302 is a third dimension, and the third dimension is larger than the first dimension.
  • the third size may be equal to the second size.
  • the embodiments of the present disclosure are not limited to the fact that the third size is greater than the first size, and the third size may also be equal to the first size.
  • the third size may also be equal to the first size.
  • the existing overlapping parts form a storage capacitor, which is beneficial to improve the display effect.
  • the second pole 302 of the transistor 300 includes a portion extending into the U-shaped opening of the first pole 301 of the transistor 300 and another portion configured to be electrically connected to the pixel electrode 11 .
  • another part of the second pole 302 of the transistor 300 configured to be electrically connected to the pixel electrode 11 is stacked with the semiconductor layer 200, and the edge of this part of the semiconductor layer 200 protrudes relative to the edge of the second pole 302 to form a third protrusion. Section 230.
  • a part of the second electrode 302 of the transistor 300 overlaps with the film layer where the gate 303 is located.
  • a part of the second pole 302 of the transistor 300 overlaps with the doped region pattern 320 of the semiconductor layer 200, and another part of the second pole 302 overlaps with the channel-except region of the semiconductor layer 200.
  • 310 overlaps with a part of the region other than the doped region pattern 320 .
  • the display substrate further includes a gate line 500 .
  • the gate line 500 is arranged on the same layer as the gate 303 of the transistor 300 and is electrically connected to the gate 303 .
  • the gate 303 can be integrated with the gate line 500 electrically connected thereto.
  • a plurality of sub-pixels 10 included in the display substrate are arranged in an array along the row direction and the column direction.
  • the embodiment of the present disclosure schematically shows that the X direction is the row direction, and the Y direction is the column direction. But not limited thereto, the row direction and the column direction can be interchanged.
  • two adjacent sub-pixel columns form a sub-pixel column group 010
  • the display substrate includes a plurality of sub-pixel column groups 010 arranged along the row direction, and each sub-pixel column group 010 includes two adjacent sub-pixel column groups. .
  • the plurality of sub-pixels 10 may include a plurality of sub-pixels that emit light of different colors, for example, the plurality of sub-pixels 10 may include a plurality of red sub-pixels that emit red light, a plurality of green sub-pixels that emit green light, and a plurality of blue
  • the blue sub-pixels of the color light, the red sub-pixels, the green sub-pixels and the blue sub-pixels can be arranged repeatedly along the row direction, and the sub-pixels arranged along the column direction can be sub-pixels that emit light of the same color, but are not limited thereto.
  • the sub-pixels arranged in the column direction may also be red sub-pixels, green sub-pixels and blue sub-pixels arranged repeatedly in sequence.
  • the data lines 410 extend along the column direction, and the gate lines 500 extend along the row direction.
  • the above data lines 410 extending along the column direction may mean that the overall extending direction of each data line 410 is extending along the column direction, and each data line 410 may be a straight line extending along the column direction, or a broken line extending along the column direction.
  • the aforementioned extending of the grid lines 500 along the row direction may mean that the overall extension direction of each grid line 500 is extending along the row direction, and each grid line 500 may be a straight line extending along the row direction, or may be a broken line extending along the row direction.
  • the gate line 500 includes a plurality of first sub-gate lines 510 and a plurality of second sub-gate lines 520 .
  • a plurality of first sub-gate lines 510 and a plurality of second sub-gate lines 520 are arranged alternately along the column direction.
  • the data line 410 is located between two adjacent sub-pixel column groups 010 , and the two columns of sub-pixels in the sub-pixel column group 010 are electrically connected to the same data line 410 .
  • the sub-pixel column group 010 includes multiple rows of sub-pixel rows, and along the column direction, a first sub-gate line 510 and a second sub-gate line 520 are respectively arranged on both sides of each sub-pixel row, and A gate line pair composed of a first sub-gate line 510 and a second sub-gate line 520 is included between adjacent sub-pixel rows.
  • An example of an embodiment of the present disclosure provides a display substrate that can adopt dual gate technology, which is a driving technology that reduces the number of data lines in a display device by half and doubles the number of gate lines.
  • the number of source driving integrated circuits (integrated circuit, IC) connected to the data lines is halved, and the number of gate driving integrated circuits connected to the gate lines is doubled. Since the unit price of the gate driver integrated circuit is lower than the unit price of the source driver integrated circuit, cost reduction is achieved.
  • the sub-pixel 10 further includes a common electrode
  • the display substrate further includes a common electrode line 600 connected to the common electrode.
  • the common electrode line 600 may be in a zigzag shape.
  • the meander-shaped common electrode line can guide the liquid crystal to rotate.
  • a spacer may be correspondingly provided at a position with a larger width on the common electrode line 600 .
  • FIG. 5 is a schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure.
  • 5 shows the first protrusion 210 where the edge of the semiconductor layer 200 in the substrate protrudes relative to the edge of the data line 410, the second protrusion 220 where the edge of the semiconductor layer 200 protrudes relative to the edge of the first pole 301, and the data line.
  • the gate line 500, and the pixel electrode 11 may have the same features as the first protrusion 210, the second protrusion 220, the data line 410, the gate line 500, and the pixel electrode 11 in the display substrate shown in FIG. I won't repeat them here.
  • the first pole 301 of the transistor 300 and the data line 410 may have an integrated structure, and the connection portion 330 shown in FIG. 1 is not used for electrical connection.
  • the display substrate provided by the embodiments of the present disclosure may be an array substrate.
  • another embodiment of the present disclosure provides a display device, which includes the display substrate provided in any one of the above examples.
  • the display device may further include a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the display device can be a liquid crystal display device, or any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc. that includes the liquid crystal display device, and this embodiment is not limited thereto .
  • FIGS. 1 to 4 Another embodiment of the present disclosure provides a method for forming the display substrate shown in FIGS. 1 to 4 .
  • 6A to 6C are schematic diagrams of a method for fabricating a partial cross-sectional structure of a display substrate taken along line DD' shown in FIG. 1 .
  • the manufacturing method of the display substrate includes providing a base substrate 100; forming a semiconductor material layer 20 on the base substrate 100; a conductive material layer 40 ; and an etching mask 800 is formed on a side of the conductive material layer 40 away from the semiconductor material layer 20 .
  • the etching mask 800 includes a first mask portion 810, and the first mask portion 810 includes a first sub-mask portion 811 and a second sub-mask portion 812, and the second sub-mask portion 810 includes The mask part 812 is located on at least one side of the first sub-mask part 811, and the second sub-mask part 812 is located on the edge of the first mask part 810.
  • the first sub-mask The thickness of the portion 811 is greater than the thickness of the second sub-mask portion 812 .
  • the manufacturing method further includes: patterning the conductive material layer 40 and the semiconductor material layer 20 using the first mask portion 810 as a mask to form the data line 410 and the data line 410 and the base substrate 100 The first semiconductor pattern 23 between them (the first semiconductor pattern 23 shown in FIG. 17 ).
  • the first semiconductor pattern 23 includes a first protruding portion 210 not covered by the data line 410 and protruding relative to the edge of the data line 410, the first protruding portion 210 is disposed on the edge of the data line 410, and the first protruding portion 210 is away from the data line 410
  • the distance between the edge of the data line 410 and the edge of the data line 410 is a first dimension S1; the first dimension S1 is greater than 0 and less than 3.0 microns.
  • Embodiments of the present disclosure use first mask portions with different thicknesses to pattern the data lines and the first semiconductor patterns overlapping with the data lines, which is beneficial to reduce the size of the first protruding portion, thereby improving product performance. The probability of poor display of the display device is reduced.
  • the first sub-mask portion 811 and the second sub-mask portion 812 are an integrated structure.
  • a half-tone mask (HTM Mask) 910 may be used as a mask to pattern the first mask portion 810 of the etching mask 800 .
  • the etch mask 800 may include photoresist, and the etch mask layer is directly patterned using a half-tone mask process to form a first mask portion 810 having a different thickness, that is, the first mask portion 810 includes The first sub-mask part 811 and the second sub-mask part 812 of different thicknesses.
  • the second sub-mask part 812 is located on both sides of the first sub-mask part 811 .
  • a halftone mask 910 includes a high light transmission portion 911, a low light transmission portion 912, and a light shielding portion 913.
  • the halftone mask 910 can be formed with different thicknesses due to the difference in light transmittance at different positions.
  • the etching mask layer is formed first, and then the etching mask layer is exposed using a half-tone mask 910 to form a fully exposed area 901 at the position where the edge of the etching mask layer of the conductive material layer 40 needs to be exposed.
  • a partially exposed region 902 is formed at the position where the second sub-mask part 812 needs to be formed, and no exposure is performed at the region 903 where the first sub-mask part 811 needs to be formed. Then, the exposed etching mask layer is developed to form the first mask portion 810 with different thicknesses.
  • the etching mask layer is described by using a material including a positive photoresist as an example. This example is not limited thereto, for example, a material including a negative photoresist may also be used.
  • a slit mask (SSM Mask) 920 may be used as a mask to pattern the first mask portion 810 of the etching mask 800 .
  • the etch mask 800 may include photoresist, and the etch mask layer is directly patterned using a slit mask process to form the first mask portion 810 with different thicknesses, that is, the first mask portion 810 includes The first sub-mask part 811 and the second sub-mask part 812 of different thicknesses.
  • the second sub-mask part 812 is located on both sides of the first sub-mask part 811. Referring to FIG.
  • FIG. 6D includes a plan view of the slit mask shown in FIG. 6B and FIG. 7B .
  • the slit mask 920 includes a light-transmitting portion 921 and a light-shielding portion 922
  • the light-transmitting portion 921 may include a slit
  • the slit mask 920 realizes the transmission of a part of the region 904 by using light diffraction.
  • the light rate is lower than the light transmittance of another partial area 905, and the area 905 may be a partially exposed area.
  • the slits may be located on both sides of the slit mask 920 near the edges, so as to form a partial exposure area near the edges of the slit mask 920 .
  • the etching mask layer is formed first, and then the etching mask layer is exposed using the slit mask 920 to form a fully exposed area at the position where the edge of the etching mask layer of the conductive material layer 40 needs to be exposed, A partially exposed region 905 is formed where the second sub-mask portion 812 needs to be formed, and no exposure is performed on the region 904 where the first sub-mask portion 811 needs to be formed. Then, the exposed etching mask layer is developed to form the first mask portion 810 with different thicknesses.
  • the etching mask layer is described by using a material including a positive photoresist as an example. This example is not limited thereto, for example, a material including a negative photoresist may also be used.
  • the width s1 of the slits included in the slit mask 920 may be 0.8 ⁇ 3 ⁇ m.
  • the width s1 of the slits included in the slit mask 920 may be 1 ⁇ 2 ⁇ m.
  • the width w1 of the light shielding portion 922 on the side of the slit away from the center of the slit mask 920 may be 0.5-3 microns.
  • the width w1 of the light shielding portion 922 on the side of the slit away from the center of the slit mask 920 may be 1-2 microns.
  • FIG. 6C schematically shows a schematic diagram of the first mask portion 810 of the etching mask 800 formed by patterning a half-tone mask (HTM Mask) 910 as a mask, but is not limited thereto.
  • a slit mask ( SSM Mask) 920 is a mask that can also be patterned to form the first mask portion 810 of the etching mask 800 shown in FIG. 6C.
  • SSM Mask slit mask
  • the obvious slopes shown in FIGS. 6A-6B can be formed.
  • the second sub-mask portion 812 may also form a second sub-mask portion 812 with a less obvious slope as shown in FIG. 6C .
  • the slope angle of the second sub-mask portion 812 may be 10-30 degrees.
  • the slope angle of the second sub-mask portion 812 may be 15-25 degrees.
  • the slope angle of the second sub-mask part 812 may be 18 degrees.
  • the slope angle of the second sub-mask portion 812 may refer to the angle between the tangent line and the X direction at the intersection of the curve intercepted by the XZ plane and the conductive material layer 40 .
  • the included angle between the tangent line at the midpoint of the curve intercepted by the XZ plane and the X direction of the curved surface of the second sub-mask portion 812 may be 26-46 degrees.
  • the angle between the tangent line at the midpoint of the curve intercepted by the XZ plane and the X direction of the curved surface of the second sub-mask portion 812 may be 30-40 degrees.
  • the included angle between the tangent line at the midpoint of the curve intercepted by the XZ plane and the X direction of the curved surface of the second sub-mask portion 812 may be 36 degrees.
  • the thickness H1 of the first sub-mask portion 811 may be 1.5 ⁇ 3.0 ⁇ m.
  • the thickness H2 of the second sub-mask portion 812 may be 0.2 ⁇ 1.5 ⁇ m.
  • the material of the semiconductor material layer 20 may include amorphous silicon and doped amorphous silicon.
  • the doped amorphous silicon may be located on the side of the amorphous silicon facing the conductive material layer 40 .
  • the thickness of the semiconductor material layer 20 may be 1000 ⁇ 5000 angstroms.
  • the thickness of the semiconductor material layer 20 may be 1000-2000 Angstroms.
  • the conductive material layer 40 may include at least one film layer.
  • the material of the conductive material layer 40 may include metallic materials such as molybdenum, aluminum, and copper.
  • a gate metal layer can be deposited on the base substrate 100, and the gate metal layer can be formed as shown in FIG. The gate 303 and the gate line 500 shown in FIG. 3 and FIG. 4 .
  • a gate insulating layer 101 is deposited on the side of the gate line 500 away from the base substrate.
  • FIG. 7A to FIG. 7C are schematic diagrams of a method for fabricating a partial cross-sectional structure of a substrate taken along line EE' shown in FIG. 1 .
  • the etch mask 800 further includes a second mask portion 820, and the second mask portion 820 includes a third sub-mask portion 821 located at an edge position, along a direction perpendicular to the substrate.
  • the thickness of the third sub-mask portion 821 is the same as the thickness of the first sub-mask portion 811 .
  • the edge positions on both sides of the second mask portion 820 are third sub-mask portions 821, and the edge of the third sub-mask portion 821 away from the second mask portion 820 has no A structure having a thickness smaller than the third sub-mask portion 821 is provided.
  • the second mask portion 820 further includes a fourth sub-mask portion 822 whose thickness is smaller than that of the third sub-mask portion 821 .
  • the second mask portion 820 includes three third sub-mask portions 821 and two fourth sub-mask portions 822, and the third sub-mask portions 821 and the fourth sub-mask portions The mold parts 822 are arranged alternately along the Y direction.
  • the thickness H3 of the third sub-mask portion 821 may be 1.5 ⁇ 3.0 ⁇ m, and the thickness H4 of the fourth sub-mask portion 822 may be 0.2 ⁇ 1.5 ⁇ m.
  • the first pole 301 and the second pole 302 of the transistor 300 can be formed using the third sub-mask portion 821 as a mask, and the fourth sub-mask portion 822 is used as a mask
  • the mold may form the channel region of transistor 300 .
  • a half-tone mask (HTM Mask) 930 can be used as a mask to pattern the second mask portion 820 of the etching mask 800 .
  • the etch mask 800 may include photoresist, and the etch mask layer is directly patterned using a half-tone mask process to form a second mask portion 820 having a different thickness, that is, the second mask portion 820 includes a The third sub-mask part 821 and the fourth sub-mask part 822 having different thicknesses.
  • a halftone mask 930 includes a high light transmission portion 931, a low light transmission portion 932, and a light shielding portion 933.
  • the halftone mask 930 can be formed with different thicknesses due to the difference in light transmittance at different positions.
  • the second mask portion 820 For example, in one example, the etching mask layer is formed first, and then the etching mask layer is exposed by using the half-tone mask 930 to form a fully exposed area 901 at the position where the edge of the etching mask layer of the conductive material layer 40 needs to be exposed.
  • a partially exposed region 902 is formed at the position where the fourth sub-mask part 822 needs to be formed, and no exposure is performed at the region 903 where the third sub-mask part 821 needs to be formed. Then, the exposed etching mask layer is developed to form the second mask portion 820 with different thicknesses.
  • the etching mask layer is described by using a material including a positive photoresist as an example. This example is not limited thereto, for example, a material including a negative photoresist may also be used.
  • a slit mask (SSM Mask) 940 may be used as a mask to pattern the second mask portion 820 of the etching mask 800 .
  • the etch mask 800 may include photoresist, and the etch mask layer is directly patterned using a half-tone mask process to form a second mask portion 820 having a different thickness, that is, the second mask portion 820 includes a The third sub-mask part 821 and the fourth sub-mask part 822 having different thicknesses.
  • the slit mask 940 includes a light-transmitting portion 941 and a light-shielding portion 942.
  • the light-transmitting portion 941 may include a slit.
  • the light rate is lower than the light transmittance of another partial area 905, the area 905 may be a partially exposed area, and the area 904 may be a non-exposed area.
  • the slit can be located at the non-edge position of the slit mask 940, and the middle area and the edge areas on both sides of the slit mask 940 are provided with a larger-sized light shielding portion 942, so as to provide a light shielding portion 942 between the middle area and the edge area of the slit mask 920.
  • Non-exposed regions are formed at the edge regions on both sides, a partially exposed region is formed at the middle of the two non-exposed regions of the slit mask 920, and a fully exposed region is formed at the side of the non-exposed region at the edge position away from the partially exposed region. .
  • the etching mask layer is formed first, and then the etching mask layer is exposed using the slit mask 940 to form a fully exposed area at the position where the edge of the etching mask layer of the conductive material layer 40 needs to be exposed, A partially exposed region 905 is formed where the fourth sub-mask portion 822 needs to be formed, and no exposure is performed on the region 904 where the third sub-mask portion 821 needs to be formed. Then, the exposed etching mask layer is developed to form the second mask portion 820 with different thicknesses.
  • the etching mask layer is described by using a material including a positive photoresist as an example. This example is not limited thereto, for example, a material including a negative photoresist may also be used.
  • the width s2 of each slit included in the slit mask 940 may be larger than 3 micrometers.
  • the width s2 of each slit included in the slit mask 940 may be 3 ⁇ 6 ⁇ m.
  • the width s2 of each slit included in the slit mask 940 may be 4.7 ⁇ 5.2 ⁇ m.
  • the width w2 of the larger light-shielding portion 942 located between two adjacent slits may be 1.5-3 microns.
  • the width w2 of the larger light-shielding portion 942 located between two adjacent slits may be 2.1-2.3 microns.
  • FIG. 7C schematically shows a schematic diagram of the second mask portion 820 of the etching mask 800 formed by patterning a half-tone mask (HTM Mask) 930 as a mask, but is not limited thereto.
  • a slit mask ( SSM Mask) 940 is a mask that can also be patterned to form the second mask portion 820 of the etching mask 800 shown in FIG. 7C.
  • a YZ surface as shown in FIGS. 7A-8B can be formed.
  • the truncated edge of the second mask portion 820 is substantially straight, and the second mask portion 820 whose truncated edge is curved by the YZ plane as shown in FIG. 7C can also be formed.
  • the slope angle of the line intercepted by the YZ plane of the second mask portion 820 may be 35-55 degrees.
  • the slope angle of the line intercepted by the YZ plane of the second mask portion 820 may be 40-50 degrees.
  • the slope angle of the line intercepted by the YZ plane of the second mask portion 820 may be 45 degrees.
  • the slope angle of the second mask portion 820 may refer to the angle between the tangent and the Y direction at the intersection of the curve intercepted by the YZ plane and the conductive material layer 40 .
  • FIG. 8 is a schematic diagram of another method for manufacturing a partial cross-sectional structure of the substrate shown in FIG. 1 taken along line EE'.
  • the difference between FIG. 8 and FIG. 7A and FIG. 7C is that the third sub-mask part 821 in the second mask part 820 is not located at the edge position, and the edge position of the third sub-mask part 821 is provided with a fifth sub-mask part 833 , along the direction perpendicular to the base substrate 100, the thickness of the third sub-mask part 821 is the same as the thickness of the first sub-mask part 811, the thickness of the fifth sub-mask part 833 is the same as the thickness of the second sub-mask part same.
  • the thickness H5 of the fifth sub-mask portion 823 may be 0.2 ⁇ 1.5 ⁇ m.
  • a half-tone mask (HTM Mask) 940 can be used as a mask to pattern the second mask portion 820 of the etching mask 800 .
  • HTM Mask half-tone mask
  • the embodiments of the present disclosure are not limited to patterning the second mask portion 820 shown in FIG. The second mask part 820.
  • the etch mask 800 may include photoresist, and the etch mask layer is directly patterned using a half-tone mask process to form a second mask portion 820 having a different thickness, that is, the second mask portion 820 includes a
  • the third sub-mask portion 821 , the fourth sub-mask portion 822 and the fifth sub-mask portion 823 have different thicknesses.
  • a halftone mask 950 includes a high light transmission portion 951, a low light transmission portion 952, and a light shielding portion 953.
  • the halftone mask 950 can be formed with different thicknesses due to the difference in light transmittance at different positions.
  • the second mask portion 820 For example, in one example, the etching mask layer is formed first, and then the etching mask layer is exposed using a half-tone mask 950 to form a fully exposed area 901 at the position where the edge of the etching mask layer of the conductive material layer 40 needs to be exposed.
  • a partially exposed region 902 is formed where the fourth sub-mask portion 822 and the fifth sub-mask portion 823 need to be formed, and the region 903 where the third sub-mask portion 821 needs to be formed is not exposed.
  • the exposed etching mask layer is developed to form the second mask portion 820 with different thicknesses.
  • the etching mask layer is described by using a material including a positive photoresist as an example. This example is not limited thereto, for example, a material including a negative photoresist may also be used.
  • the difference from the semiconductor layer at the transistor formed by using the second mask portion 820 shown in FIG. 7A is that after forming the second mask portion 820 shown in FIG. 820 is the second dimension of the second protruding part included in the semiconductor layer at the transistor formed by mask patterning is the same as the first dimension of the above-mentioned first protruding part.
  • the method steps of forming the subsequent structure by patterning the second mask portion shown in FIG. 8 reference may be made to the structures formed by corresponding methods in FIG. 10 , FIG. 12 , FIG. 14 , FIG. 16 and FIG. 18 , and details are not repeated here.
  • the length of the second protrusion is greater than the first protrusion corresponding to the position of the semiconductor under the data line, that is, the distance from the edge of the data line layer to the edge of the semiconductor , optionally, the position of the semiconductor layer corresponding to the transistor, and the position of the semiconductor corresponding to the data line, at least one adopts the preparation method shown in Figure 8, that is, the part of the semiconductor layer beyond the data line uses a half-tone mask or SSM mask
  • the stencil realizes that the mask part has a stepped shape at the position where the semiconductor exceeds the data line layer.
  • FIG. 9 is a schematic diagram of patterning a data line pattern by using the first mask part as a mask
  • FIG. 10 is a schematic diagram of patterning a source-drain pattern of a transistor by using the second mask part as a mask.
  • using the first mask part 810 as a mask to pattern the conductive material layer 40 includes using the first mask part 810 as a mask to etch the conductive material layer 40 to form Data line pattern 41 .
  • patterning the conductive material layer 40 by using the first mask part 810 as a mask includes performing wet etching on the conductive material layer 40 by using the first mask part 810 as a mask to form the data line pattern 41 .
  • wet etching can be isotropic etching (such as etching in the X direction, Y direction and Z direction shown in the figure), and the edge of the conductive material layer 40 is indented relative to the edge of the first mask portion 810. A certain size.
  • the conductive material layer 40 is patterned using the second mask portion 820 as a mask to form the transistor source-drain pattern 42 .
  • the transistor source-drain pattern 42 is formed by etching the conductive material layer 40 using the second mask portion 820 as a mask.
  • the conductive material layer 40 is wet-etched using the second mask portion 820 as a mask to form the source-drain pattern 42 of the transistor.
  • the wet etching can be isotropic etching, and the edge of the conductive material layer 40 is indented by a certain size relative to the edge of the second mask portion 820 .
  • the data line pattern 41 and the transistor source-drain pattern 42 are formed by simultaneous etching.
  • Figure 11 is a schematic diagram of patterning the semiconductor material layer to form a first semiconductor pattern layer using the first mask part as a mask
  • Figure 12 is a schematic diagram of patterning the semiconductor material layer to form a second semiconductor material layer using the second mask part as a mask.
  • Schematic diagram of a semiconductor patterned layer For example, as shown in FIG. 9 and FIG. 11 , after the data line pattern 41 is formed, the semiconductor material layer 20 is etched using the first mask portion 810 as a mask to form the first semiconductor pattern layer 21 . For example, as shown in FIG. 9 and FIG.
  • patterning the semiconductor material layer 20 using the first mask portion 810 as a mask includes: performing dry etching on the semiconductor material layer 20 using the first mask portion 810 as a mask to The edge of the first mask portion 810 and the edge of the semiconductor material layer 20 are etched synchronously.
  • dry etching can be anisotropic etching (for example, the etching is mainly in the Z direction shown in the figure, and the etching rate in other lateral directions such as the X direction is small), and the semiconductor is etched using a dry etching process.
  • the edge of the first mask portion 810 is also etched simultaneously.
  • the embodiment of the present disclosure adopts an etching mask with a second sub-mask portion having a smaller thickness at the edge to achieve While the semiconductor material layer is etched by a dry etching process, the etching amount of the second sub-mask portion located at the edge of the etching mask and having a small thickness is relatively large, so that the second sub-mask portion is used as a mask.
  • the size of the edge of the semiconductor material layer etched away by the mold is larger, so as to provide a process basis for the subsequent formation of the first semiconductor pattern with a smaller first protrusion.
  • the edge position of the first semiconductor pattern layer 21 can be approximately the edge position of the first protruding portion (Act tail) in the first semiconductor pattern formed subsequently.
  • the etch mask of the second sub-mask portion affects the size of the first protrusion.
  • the embodiment of the present disclosure uses a dry etching process to simultaneously etch the semiconductor material layer and the first mask.
  • the mold part method can not only provide a process basis for the subsequent formation of the first semiconductor pattern with a smaller first protrusion, but also save a one-step ashing process.
  • the first sub-mask portion 811 with a relatively large thickness is also etched simultaneously.
  • the etched first mask portion 810' is obtained by etching the first mask portion 810 while etching the semiconductor material layer 20 using a dry etching process.
  • the thickness of each position of the etched first mask portion 810' is smaller than the thickness of the corresponding position of the first mask portion 810 (shown by the dotted line in FIG. 11 ).
  • the edge of the gate insulating layer 101 away from the base substrate 100 will also be etched away with a partial thickness of material.
  • using the second mask portion 820 as a mask to pattern the semiconductor material layer 20 includes: after forming the transistor source-drain pattern 42 , using the second mask portion 820 as a mask The semiconductor material layer 20 is mold etched to form a second semiconductor pattern layer 22 .
  • using the second mask part 820 as a mask to pattern the semiconductor material layer 20 includes: using the second mask part 820 as a mask to dry-etch the semiconductor material layer 20 so that the edge of the second mask part 820 and the edge of the semiconductor material layer 20 are etched simultaneously.
  • the second mask portion 820 is etched while the semiconductor material layer 20 is etched by a dry etching process to obtain an etched second mask portion 820'.
  • the thickness of each position of the etched second mask portion 820' is smaller than the thickness of the corresponding position of the second mask portion 820 (shown by the dotted line in FIG. 12 ).
  • the first semiconductor pattern layer 21 and the second semiconductor pattern layer 22 are formed by simultaneous etching.
  • the first mask portion 810 and the second mask portion 820 are etched simultaneously to form an etched first mask portion 810' and an etched second mask portion 820', respectively.
  • FIG. 13 is a schematic diagram of ashing the etched first mask portion
  • FIG. 14 is a schematic diagram of ashing the etched second mask portion.
  • the manufacturing method further includes: performing ashing treatment on the first mask part 810 and the second mask part 820 at the same time.
  • performing ashing treatment on the first mask portion 810 includes performing ashing treatment on the etched first mask portion 810 ′ to form an ashed first mask. part 810".
  • performing ashing treatment on the second mask part 820 includes performing ashing treatment on the etched second mask part 820' to form an ashed The second mask portion 820".
  • the slope angle of the edge of the first mask part 810" after ashing may be 35-55 degrees.
  • the slope angle of the edge of the first mask part 810" after ashing may be 45 degrees.
  • the slope angle of the edge of the ashed second mask portion 820 ′′ may be 60 ⁇ 80 degrees.
  • the slope angle of the edge of the ashed second mask portion 820 ′′ may be 70 degrees.
  • the thickness of the ashed first mask portion 810 ′′ is smaller than the thickness of the unashed first sub-mask portion 811 .
  • the thickness of the first mask part 810" after ashing is smaller than the thickness of the first sub-mask part after etching.
  • the edge of the ashed first mask portion 810 ′′ obtained by ashing the etched first mask portion may be flush with the edge of the data line pattern 41 .
  • the edge of the ashed first mask portion 820 ′′ obtained after performing ashing treatment on the etched second mask portion can be aligned with the edge of the source-drain pattern 42 of the transistor. flat.
  • the thickness of the ashed second mask portion 820 ′′ is smaller than the thickness of the unashed third sub-mask portion 830 .
  • the thickness of the first mask part 810" after ashing is smaller than the thickness of the third sub-mask part after etching.
  • the ashed second mask portion 820′′ includes a plurality of sub-mask portions arranged at intervals, and the interval between adjacent sub-mask portions is configured to expose the channel region of the transistor.
  • the sub-mask portions are configured to shield one of the first and second electrodes of the transistor.
  • Figure 15 is a schematic diagram of etching the data line pattern using the ashed first mask part as a mask
  • Figure 16 is a schematic diagram of etching the source and drain patterns of the transistor using the ashed second mask part as a mask Schematic diagram after etching.
  • the manufacturing method further includes: using the ashed first mask part 810" as a mask Etching the data line pattern 41 to form the data line 410.
  • using the ashed first mask part 810" as a mask to etch the data line pattern 41 to form the data line 410 includes: using the ashed first mask The mold part 810" is used as a mask to wet-etch the data line pattern 41 to form the data line 410, and the edge of the data line 410 is indented by a certain size relative to the edge of the ashed first mask part 810".
  • the manufacturing method further includes etching the source and drain of the transistor using the ashed second mask portion 820′′ as a mask.
  • pole pattern 42 to form the first pole 301 and the second pole 302 of the transistor.
  • the first pole 301 and the second pole 302 of the transistor can be formed by wet etching, and the edges of the first pole 301 and the second pole 302 All of them are set back by a certain size relative to the edge of the ashed second mask portion 820 ′′.
  • the first pole 301 and the second pole 302 are arranged at intervals.
  • the interval between the first pole 301 and the second pole 302 is configured to expose a portion of the second semiconductor pattern layer 22 .
  • Figure 17 is a schematic diagram of etching the first semiconductor pattern layer using the ashed first mask part as a mask
  • Figure 18 is a schematic diagram of etching the second semiconductor pattern layer using the ashed second mask part as a mask.
  • Schematic diagram of the layer after etching For example, as shown in FIG. 15 and FIG. 17, after forming the data line 410, the part of the edge of the first semiconductor pattern layer 21 away from the base substrate 10 is etched away using the ashed first mask portion 810′′ as a mask. thick material to form the first semiconductor pattern 23 .
  • the first semiconductor pattern 23 includes a first-level step 211 and a second-level step 212, the first-level step 211 is located between the second-level step 212 and the base substrate 100, and the second
  • the distance between the edge of the first step 211 and the edge of the data line 410 is the first step size S1
  • the distance between the edge of the second step 212 and the edge of the data line 410 is the second step size S11;
  • the ratio of the first step size S1 to the second step size S11 is in a range of 2-25.
  • the ratio of the first step size to the second step size ranges from 3-20.
  • the ratio of the first step size to the second step size ranges from 5-15.
  • the ratio of the first step size to the second step size ranges from 8-12.
  • the first step 211 and the second step 212 may be an integrated structure.
  • the material of the first-level step 211 includes amorphous silicon (a-Si), and the material of the second-level step 212 includes doped amorphous silicon.
  • the second-level step 212 can be N-type doped amorphous silicon ( N+a-Si), for example, the material of the second step 212 can be doped with phosphorus.
  • the material of the etched part of the first semiconductor pattern layer 21 includes at least doped amorphous silicon.
  • the material of the etched part of the first semiconductor pattern layer 21 may also include amorphous silicon.
  • the fabrication method further includes: The conductive material layer 40 and the semiconductor material layer 20 are patterned to form the first pole 301 and the second pole 302 of the transistor 300 and the first pole 301 and the second pole 302 located between the first pole 301 and the second pole 302 of the transistor 300 and the base substrate 100. Two semiconductor patterns 24 .
  • the second semiconductor pattern 24 includes the channel region 310 and the doped region pattern 320 of the transistor 300, and the edge of the second semiconductor pattern 24 is relative to the edge of the first pole 301 (such as the side where the first pole 301 is away from the second pole 302
  • the protruding protruding portion is the second protruding portion 220, the first pole 301 and the second pole 302 are electrically connected to the doped region pattern 320, the first pole 301 is electrically connected to the data line 410, and the second protruding portion 220 is away from
  • the size of the minimum interval between the edge of the first pole 301 and the edge of the first pole 301 is a second size, and the second size is larger than the first size.
  • the size of the first protruding portion protruding from the edge of the first semiconductor pattern relative to the edge of the data line is set to be smaller than the second protruding portion protruding from the edge of the second semiconductor pattern relative to the edge of the first pole of the transistor.
  • the size of the first protruding part on the edge of the data line can be reduced without affecting the normal operation of the transistor, which is beneficial to solve the problems such as water ripples and afterimages caused by the longer first protruding part, thereby improving the product quality. performance.
  • the second protruding portion 220 includes a third-level step 221 and a fourth-level step 222 stacked, and the third-level step 221 is located between the fourth-level step 222 and the base substrate 100 , and the distance between the edge of the third-level step 221 and the edge of the first pole 301 of the transistor 300 is the third step size, that is, the second dimension S2, the edge of the fourth-level step 222 and the edge of the first pole 301 The size of the space between them is the fourth step size S21, and the fourth step size S21 is smaller than the third step size.
  • the third step 221 and the fourth step 222 may be an integrated structure.
  • the material of the third-level step 221 includes amorphous silicon (a-Si), and the material of the fourth-level step 222 includes doped amorphous silicon.
  • the fourth-level step 222 can be N-type doped amorphous silicon ( N+a-Si), for example, the material of the fourth step 222 can be doped with phosphorus.
  • the material of the etched part of the second semiconductor pattern layer 22 includes at least doped amorphous silicon.
  • the material of the etched part of the second semiconductor pattern layer 22 may also include amorphous silicon.
  • the method for manufacturing the display substrate forms the first mask portion with the second sub-mask portion by using a half-tone mask or a slit mask.
  • One mask part, the size of the first protruding part of the subsequently formed first semiconductor pattern can be reduced without additional mask process, so as to save cost.
  • the smaller-sized first protrusion (Act Tail) formed under the two-time wet etching and two-time dry etching (2W2D) process will form less photogenerated carriers under the illumination of the backlight, which is conducive to improving the quality of the product. performance.
  • the edge of the etching mask used to form the semiconductor layer overlapping with the data line includes a second sub-mask portion with a smaller thickness (or a smaller slope angle of the edge of the etching mask), which is used to form the transistor position
  • the edge of the etching mask of the semiconductor layer at the location does not include a sub-mask portion with a smaller thickness (or the edge of the etching mask has a larger slope angle), so that the semiconductor layer at the position of the transistor formed protrudes from the conductive layer.
  • the size is larger than the size of the first protruding portion formed to protrude relative to the data line from the semiconductor layer overlapping the data line.
  • the semiconductor layer included in the transistor is covered by the gate, which can block the light from the backlight from affecting the semiconductor layer at the position of the transistor, while the semiconductor layer overlapping the data line is not blocked by the film layer where the gate is located, and is easily irradiated by the light from the backlight , resulting in an impact on the electrical properties of the semiconductor layer.
  • setting the size of the first protrusion to be smaller than the size of the second protrusion may not change the shape of the semiconductor layer in the transistor, but reduce the relative The length of the protruding part of the line, thereby reducing the impact of the backlight on the semiconductor layer.
  • the manufacturing method further includes removing the ashed etching mask to expose the data line 410 and the first transistor of the transistor. pole 301 and a second pole 302.
  • a passivation layer is formed on the side of the film layer where the data line 410 is located away from the base substrate 100 .
  • the manufacturing method further includes forming a pixel electrode on a side of the passivation layer away from the substrate.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示基板及其制作方法以及显示装置。显示基板包括衬底基板（100）以及位于衬底基板（100）上的半导体层（200）和导电层（400）。半导体层（200）包括晶体管（300）的沟道区（310）和掺杂区图案（320）；导电层（400）与半导体层（200）层叠设置，且位于半导体层（200）远离衬底基板（100）的一侧，导电层（400）包括数据线（410）以及晶体管（300）的第一极（301）和第二极（302），第一极（301）与数据线（410）电连接。半导体层（200）与数据线（410）交叠部分的延伸方向和数据线（410）延伸方向相同，半导体层（200）包括未被数据线（410）覆盖且相对于数据线（410）的边缘突出的第一突出部（210），第一突出部（210）设置在数据线（410）的边缘，第一突出部（210）远离数据线（410）的边缘与数据线（410）的边缘之间间隔的尺寸（S1）大于0且小于3.0微米。通过减小半导体层（200）相对于数据线（410）边缘突出的第一突出部（210）的尺寸（S1），有利于提高产品性能。

Description

显示基板及其制作方法、显示装置 技术领域
本公开实施例涉及一种显示基板及其制作方法、显示装置。
背景技术
目前，非晶硅(A-Si)薄膜晶体管(TFT)广泛地应用于液晶显示装置的驱动背板中，为了提高生产节拍，往往对有源半导体层与源漏金属层采用同一个掩模进行半曝光工艺形成薄膜晶体管。
发明内容
本公开实施例提供一种显示基板及其制作方法、显示装置。
本公开实施例提供一种显示基板，包括：衬底基板以及位于衬底基板上的半导体层和导电层。所述半导体层位于所述衬底基板上，所述半导体层包括晶体管的沟道区和掺杂区图案；所述导电层与所述半导体层层叠设置，且位于所述半导体层远离所述衬底基板的一侧，所述导电层包括数据线以及与所述掺杂区图案电连接的所述晶体管的第一极和第二极，所述第一极与所述数据线电连接。所述半导体层与所述数据线交叠部分的延伸方向和所述数据线延伸方向相同，所述半导体层包括未被所述数据线覆盖且相对于所述数据线的边缘突出的第一突出部，所述第一突出部设置在所述数据线的边缘，所述第一突出部远离所述数据线的边缘与所述数据线的边缘之间间隔的尺寸为第一尺寸，所述第一尺寸大于0且小于3.0微米。
例如，根据本公开的实施例，所述半导体层的边缘相对于所述第一极的边缘突出的部分为第二突出部，所述第二突出部设置在所述第一极的边缘，所述第二突出部远离所述第一极的边缘与所述第一极的边缘之间的间隔的尺寸为第二尺寸，所述第二尺寸大于所述第一尺寸。
例如，根据本公开的实施例，所述第一突出部包括层叠设置的第一级台阶和第二级台阶，所述第一级台阶位于所述第二级台阶与所述衬底基板之间，且所述第一级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第一台阶尺寸，所述第二级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第二台阶尺寸； 所述第一台阶尺寸与所述第二台阶尺寸的比例范围为2-25。
例如，根据本公开的实施例，所述第一级台阶的材料包括非晶硅，所述第二级台阶的材料包括掺杂非晶硅。
例如，根据本公开的实施例，所述数据线包括至少一层导电层，所述数据线的侧壁与所述第二级台阶远离所述衬底基板一侧表面之间的夹角范围包括30～80度。
例如，根据本公开的实施例，所述第二突出部包括层叠设置的第三级台阶和第四级台阶，所述第三级台阶位于所述第四级台阶与所述衬底基板之间，且所述第三级台阶的边缘与所述第一极的边缘之间间隔的尺寸为第三台阶尺寸，所述第四级台阶的边缘与所述第一极的边缘之间间隔的尺寸为第四台阶尺寸；所述第一台阶尺寸小于所述第三台阶尺寸。
例如，根据本公开的实施例，所述第三级台阶的材料包括非晶硅，所述第四级台阶的材料包括掺杂非晶硅。
例如，根据本公开的实施例，所述第一台阶尺寸与所述第二台阶尺寸的比值小于所述第三台阶尺寸与所述第四台阶尺寸的比值。
例如，根据本公开的实施例，所述晶体管还包括栅极，所述栅极位于所述半导体层与所述衬底基板之间，所述第二突出部在所述衬底基板上的正投影位于所述栅极所在膜层在所述衬底基板上的正投影内。
例如，根据本公开的实施例，显示基板还包括：多个子像素，每个子像素包括像素电极，所述像素电极位于所述导电层远离所述衬底基板的一侧。所述第二极与所述像素电极电连接；所述半导体层还包括与所述第二极交叠且相对于所述第二极边缘突出的第三突出部，所述第三突出部围绕所述第二极的至少部分边缘，所述第三突出部远离所述第二极的边缘与所述第二极的边缘之间的最小间隔的尺寸为第三尺寸，所述第三尺寸大于所述第一尺寸。
例如，根据本公开的实施例，显示基板还包括：栅线，所述栅线与所述栅极同层设置，且与所述栅极电连接。所述多个子像素沿行方向和列方向阵列排布，相邻两列子像素列组成子像素列组；所述数据线沿所述列方向延伸，所述栅线沿所述行方向延伸，所述栅线包括多条第一子栅线和多条第二子栅线；所述数据线位于相邻两个子像素列组之间，且所述子像素列组中的两列子像素与同一条数据线电连接；所述子像素列组包括多行子像素行，且沿所述列方向，每个所述子像素行的两侧分别设置所述第一子栅线和所述第二子栅线，且相邻 的所述子像素行之间包括所述第一子栅线和所述第二子栅线组成的栅线对。
例如，根据本公开的实施例，所述第二台阶尺寸与所述第四台阶尺寸的比值为0.8～1.2。
本公开实施例提供一种显示装置，包括上述显示基板。
本公开实施例提供一种显示基板的制作方法，包括：提供衬底基板；在所述衬底基板上形成半导体材料层；在所述半导体材料层远离所述衬底基板的一侧形成导电材料层；以及在所述导电材料层远离所述半导体材料层的一侧形成蚀刻掩模。所述蚀刻掩模包括第一掩模部，所述第一掩模部包括第一子掩模部和第二子掩模部，所述第二子掩模部位于所述第一子掩模部的至少一侧，且所述第二子掩模部位于所述第一掩模部的边缘，沿垂直于所述衬底基板的方向，所述第一子掩模部的厚度大于所述第二子掩模部的厚度。形成所述蚀刻掩模后，所述制作方法还包括：以所述第一掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化以形成数据线以及位于所述数据线与所述衬底基板之间的第一半导体图案，其中，所述第一半导体图案包括未被所述数据线覆盖且相对于所述数据线的边缘突出的第一突出部，所述第一突出部设置在所述数据线的边缘，所述第一突出部远离所述数据线的边缘与所述数据线的边缘之间间隔的尺寸为第一尺寸；所述第一尺寸大于0且小于3.0微米。
例如，根据本公开的实施例，以所述第一掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化包括：以所述第一掩模部为掩模刻蚀所述导电材料层形成数据线图案；形成所述数据线图案后，以所述第一掩模部为掩模刻蚀所述半导体材料层以形成第一半导体图案层。
例如，根据本公开的实施例，以所述第一掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化包括：以所述第一掩模部为掩模对所述导电材料层进行湿刻以形成所述数据线图案，以所述第一掩模部为掩模对所述半导体材料层进行干刻以使所述第一掩模部的边缘和所述半导体材料层的边缘被同步刻蚀。
例如，根据本公开的实施例，所述蚀刻掩模还包括第二掩模部，所述第二掩模部包括位于边缘位置的第三子掩模部，沿垂直于所述衬底基板的方向，所述第三子掩模部的厚度与所述第一子掩模部的厚度相同；形成所述蚀刻掩模后，所述制作方法还包括：以所述第二掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化以形成晶体管的第一极和第二极以及位于所述晶体 管的第一极和第二极与所述衬底基板之间的第二半导体图案，其中，所述第二半导体图案包括所述晶体管的沟道区和掺杂区图案，所述第二半导体图案的边缘相对于所述第一极的边缘突出的突出部分为第二突出部，所述第一极和所述第二极均与所述掺杂区图案电连接，所述第一极与所述数据线电连接，所述第二突出部远离所述第一极的边缘与所述第一极的边缘之间的最小间隔的尺寸为第二尺寸，所述第二尺寸大于所述第一尺寸。
例如，根据本公开的实施例，以所述第二掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化包括：以所述第二掩模部为掩模刻蚀所述导电材料层形成晶体管源漏极图案；形成所述晶体管源漏极图案后，以所述第二掩模部为掩模刻蚀所述半导体材料层形成第二半导体图案层。
例如，根据本公开的实施例，以所述第一掩模部和所述第二掩模部为掩模刻蚀所述半导体材料层以形成所述第一半导体图案层和所述第二半导体图案层之后，所述制作方法还包括：对所述第一掩模部和所述第二掩模部同时进行灰化处理。在垂直于所述衬底基板的方向上，灰化后的所述第一掩膜部的厚度小于未灰化的所述第一子掩模部的厚度。
例如，根据本公开的实施例，对所述第一掩模部和所述第二掩模部同时进行灰化处理后，所述制作方法还包括：以灰化后的所述第一掩模部为掩模刻蚀所述数据线图案以形成所述数据线；形成所述数据线后，以灰化后的所述第一掩模部为掩模对所述第一半导体图案层边缘进行刻蚀以形成第一级台阶和第二级台阶。所述第一半导体图案包括所述第一级台阶和所述第二级台阶，所述第一级台阶位于所述第二级台阶与所述衬底基板之间，且所述第一级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第一台阶尺寸，所述第二级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第二台阶尺寸；所述第一台阶尺寸与所述第二台阶尺寸比例范围为2-25。
例如，根据本公开的实施例，采用半色调掩模或者狭缝掩模形成所述蚀刻掩模中的所述第一掩模部。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为根据本公开实施例提供的显示基板的局部平面结构示意图；
图2为沿图1所示的AA’线所截的局部截面结构示意图；
图3为沿图1所示的BB’线所截的局部截面结构示意图；
图4为根据本公开实施例的一示例提供的显示基板的局部平面结构示意图；
图5为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图；
图6A至图6C为制作沿图1所示的DD’线所截显示基板的局部截面结构的方法的示意图；
图6D包括图6B以及图7B所示狭缝掩模的平面结构图；
图7A至图7C为制作沿图1所示的EE’线所截显示基板的局部截面结构的方法的示意图；
图8为另一种制作沿图1所示的EE’线所截显示基板的局部截面结构的方法的示意图；
图9为以第一掩模部为掩模图案化形成数据线图案的示意图；
图10为以第二掩模部为掩模图案化形成晶体管源漏极图案的示意图；
图11为以第一掩模部为掩模对半导体材料层进行图案化形成第一半导体图案层的示意图；
图12为以第二掩模部为掩模对半导体材料层进行图案化形成第二半导体图案层的示意图；
图13为对刻蚀后的第一掩模部进行灰化后的示意图；
图14为对刻蚀后的第二掩模部进行灰化后的示意图；
图15为以灰化后的第一掩模部为掩模对数据线图案进行刻蚀后的示意图；
图16为以灰化后的第二掩模部为掩模对晶体管源漏极图案进行刻蚀后的示意图；
图17为以灰化后的第一掩模部为掩模对第一半导体图案层进行刻蚀后的示意图；以及
图18为以灰化后的第二掩模部为掩模对第二半导体图案层进行刻蚀后的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本公开实施例中使用的“平行”、“垂直”以及“相同”等特征均包括严格意义的“平行”、“垂直”、“相同”等特征，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“大致”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。在本公开实施例的下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。
在研究中，本申请的发明人发现：采用数据层半曝光(SDT)工艺制造薄膜晶体管的沟道包括两次湿刻和两次干刻(2W2D)工艺，上述2W2D工艺的过程容易造成源漏金属层图案(如数据线)的边缘存在较长的有源层突出部(可以称为有源层尾巴Act Tail)。如果上述有源层突出部的尺寸超过2微米，可能会影响产品设计边缘(margin)的尺寸及产品性能。
在上述有源层突出部的尺寸较长时，容易导致与数据线交叠的信号线和该数据线之间的寄生电容增大，造成信号传输的延迟(RC Dely)，还容易导致线残像、充电率不足等不良现象的产生。
在上述有源层突出部受到光照(如受到背光源的光照)时，有源层突出部会产生光生载流子，变为导体；在上述有源层突出部没有受到光照时，有源层突出部为绝缘层，有源层突出部在暗态和光照态时产生的电流值不同，容易影响产品的稳定性。在交流背光源的作用下，有源层突出部所在的不同位置受光 照情况存在差异，容易导致显示装置发生水波纹不良。
本公开实施例提供一种显示基板及其制作方法，以及显示装置。显示基板包括衬底基板以及位于衬底基板上的半导体层和导电层。半导体层包括晶体管的沟道区和掺杂区图案；导电层与半导体层层叠设置，且位于半导体层远离衬底基板的一侧，导电层包括数据线以及与掺杂区图案电连接的晶体管的第一极和第二极，第一极与数据线电连接。半导体层与数据线交叠部分的延伸方向和数据线延伸方向相同，半导体层包括未被数据线覆盖且相对于数据线的边缘突出的第一突出部，第一突出部设置在数据线的边缘，第一突出部远离数据线的边缘与数据线的边缘之间间隔的尺寸为第一尺寸，第一尺寸大于0且小于3.0微米。本公开实施例通过将半导体层的边缘相对于数据线的边缘突出的第一突出部的尺寸设置为大于0且小于3微米，有利于减少产品设计边缘(margin)的尺寸，提高产品性能，且降低显示装置发生显示不良的几率。此外，本案通过半导体层与数据线交叠部分的延伸方向和数据线延伸方向相同，即在数据线和衬底基板之间也设置与数据线延伸方向相同的半导体层，在工艺上，半导体层和数据线层可以利用一道掩模板，节省掩模板，提高生产效率。
下面结合附图对本公开实施例提供的显示基板及其制作方法、以及显示装置进行描述。
图1为根据本公开实施例提供的显示基板的局部平面结构示意图，图2为沿图1所示的AA’线所截的局部截面结构示意图。如图1和图2所示，显示基板包括衬底基板100以及位于衬底基板100上的半导体层200和导电层400。半导体层200位于衬底基板100上，半导体层200包括晶体管300的沟道区310和掺杂区图案320；导电层400与半导体层200层叠设置，且位于半导体层200远离衬底基板100的一侧，导电层400包括数据线410以及与掺杂区图案320电连接的晶体管300的第一极301和第二极302，第一极301与数据线410电连接。半导体层200与数据线410交叠部分的延伸方向和数据线410延伸方向相同，半导体层200包括未被数据线410覆盖且相对于数据线410的边缘突出的第一突出部210，第一突出部210设置在数据线410的边缘，第一突出部210远离数据线410的边缘与数据线410的边缘之间间隔的尺寸为第一尺寸S1，第一尺寸S1大于0且小于3.0微米。本公开实施例通过将半导体层的边缘相对于数据线的边缘突出的第一突出部的尺寸设置为大于0且小于2微米，有利于减少产品设计边缘(margin)的尺寸，提高产品性能，且降低显示装置发生显示 不良的几率。
例如，半导体层的边缘相对于数据线的边缘突出的第一突出部的尺寸较小，有利于降低相对于数据线边缘突出的第一突出部对其他结构产生的影响。此外，通过减小第一突出部的尺寸，可以尽量降低第一突出部被背光源的光线照射而产生载流子的几率，提高显示基板的稳定性。
例如，如图1所示，与数据线410交叠的部分半导体层200具有与数据线410相同的延伸方向，该部分半导体层与晶体管300的沟道区310和掺杂区图案320同层设置，但是形状不同。
例如，图1示意性的示出虚线框圈出区域内的导电层400为晶体管300的第一极301，第一极301可以通过连接部330与数据线410电连接。例如，数据线410、第一极301以及连接部330可以为一体化的结构。例如，晶体管300的第一极301与第二极302间隔设置，且第一极301与第二极302之间的半导体层200可以为沟道区，称为沟道区。
例如，如图1和图2所示，导电层400的表面与半导体层200的表面接触。
例如，如图1和图2所示，数据线410的至少部分在衬底基板100上的正投影落入半导体层200在衬底基板100上的正投影内。例如，半导体层200与数据线410交叠部分的延伸方向与数据线410的延伸方向可以均为图中所示的Y方向。
例如，如图1所示，晶体管300的沟道区310和掺杂区图案320可以为一体化的结构。例如，掺杂区图案320可以包括源极区域和漏极区域，第一极301和第二极302之一与源极区域电连接，第一极301和第二极302的另一个与漏极区域电连接。例如，掺杂区图案320被第一极301和第二极302覆盖，这样设计增加掺杂区图案和第一极以及第二极的欧姆接触。本公开实施例中，晶体管的源极区域和漏极区域在结构上可以是相同的，所以其源极区域和漏极区域在结构上可以是没有区别的，因此根据需要二者是可以互换的。
例如，如图1和图2所示，与数据线410交叠的半导体层200包括被数据线410覆盖的中间部分以及未被数据线410覆盖的边缘部分，该未被数据线410覆盖的边缘部分包括第一突出部210。例如，第一突出部210位于数据线410的边缘以外的位置。
例如，如图1和图2所示，数据线410的数量可以为多条，每条数据线410可以沿Y方向延伸，且多条数据线410沿X方向排列，第一突出部210可以 包括在X方向上位于数据线410至少一侧的部分，也可以包括在Y方向上位于数据线410至少一侧的部分。例如，第一突出部210可以包括在X方向上位于数据线410两侧的部分，这两部分在X方向上的宽度可以相同，也可以不同。例如，第一突出部210可以包括在Y方向上位于数据线410两侧的部分，这两部分在Y方向上的宽度可以相同，也可以不同。上述X方向和Y方向可以互换。
例如，如图1和图2所示，第一突出部210可以沿Y方向延伸，该第一突出部210在X方向上的宽度可以为第一尺寸S1。例如，第一突出部210可以沿X方向延伸，该第一突出部210的宽度可以为第一尺寸S1。
例如，第一尺寸S1可以为0.5～3微米。例如，第一尺寸S1可以为1～2微米。例如，第一尺寸S1不大于1.8微米。例如，第一尺寸S1不大于1.6微米。例如，第一尺寸S1不大于1.4微米。例如，第一尺寸S1不大于1.3微米。
图3为沿图1所示的BB’线所截的局部截面结构示意图。例如，如图1至图3所示，沟道区310的边缘相对于晶体管300的第一极301的边缘突出的部分为第二突出部220，第二突出部220设置在第一极301的边缘，第二突出部220远离第一极301的边缘与第一极301的边缘之间的间隔的尺寸为第二尺寸S2，第二尺寸S2大于第一尺寸S1。本公开实施例中，通过半导体层的边缘相对于数据线边缘突出的第一突出部的尺寸设置为小于半导体层的边缘相对于晶体管的第一极的边缘突出的第二突出部的尺寸，可以在不影响晶体管正常工作的情况下，尽量降低数据线边缘的第一突出部的尺寸，有利于减少产品设计边缘的尺寸，解决尺寸较长的第一突出部产生的水波纹、残像等不良问题，进而提高产品性能。晶体管包括的半导体层被栅极(后续描述)覆盖，可以阻挡背光源的光线对晶体管位置的半导体层产生影响，而与数据线交叠的半导体层没有被栅极所在膜层遮挡，容易被背光源的光线照射，造成对半导体层的电学性能产生影响。本公开实施例提供的显示基板中，将第一突出部的尺寸设置为小于第二突出部的尺寸，可以不改变晶体管中半导体层的形貌，但是减小数据线下的半导体层相对于数据线突出部分的长度，从而减小背光对半导体层产生的影响。
例如，如图1至图3所示，晶体管300的第一极301在衬底基板100上的正投影完全落入半导体层200在衬底基板100上的正投影内。
例如，如图1至图3所示，晶体管300的第一极301的平面形状包括U形， 晶体管300的第二极302的平面形状包括插入U形的开口的长条形，第二突出部220围绕U形外围。例如，第二突出部220的第二尺寸S2可以为第二突出部220的沿平行于第一极301的宽度的方向的尺寸。
例如，如图1至图3所示，与晶体管300的第一极301交叠的半导体层200包括被第一极301覆盖的部分以及未被第一极301覆盖的两部分，未被第一极301覆盖的两部分包括位于第一极301内侧的部分以及位于第一极301外侧的部分，第二突出部220为半导体层200未被第一极301覆盖的两部分中的位于第一极301外侧的部分。
例如，如图1至图3所示，第二突出部220包括位于晶体管300的第一极301两侧边缘的至少一侧边缘的部分。例如，第二突出部220可以包括位于晶体管300的第一极301两侧边缘的两部分，这两部的宽度可以相同，也可以不同。
例如，如图1至图3所示，第二尺寸S2大于3微米。例如，第二尺寸S2大于2微米。例如，第二尺寸S2为2～2.6微米。例如，第二尺寸S2为3～5微米。
例如，如图1和图2所示，第一突出部210包括层叠设置的第一级台阶211和第二级台阶212，第一级台阶211位于第二级台阶212与衬底基板100之间，且第一级台阶211的边缘与数据线410的边缘之间间隔的尺寸为第一台阶尺寸，即为第一尺寸S1，第二级台阶212的边缘与数据线410的边缘之间间隔的尺寸为第二台阶尺寸S11，第一台阶尺寸大于第二台阶尺寸S11。
例如，如图2所示，第一台阶尺寸与第二台阶尺寸比例范围为2-25。例如，第一台阶尺寸与第二台阶尺寸比例范围为3-20。例如，第一台阶尺寸与第二台阶尺寸比例范围为5-15。例如，第一台阶尺寸与第二台阶尺寸比例范围为8-12。
例如，如图1和图2所示，第一级台阶211和第二级台阶212可以为一体化的结构。例如，第一级台阶211的材料包括非晶硅(a-Si)，第二级台阶212的材料包括掺杂非晶硅，例如，第二级台阶212可以为N型掺杂非晶硅(N+a-Si)，例如第二级台阶212的材料可以掺杂磷元素。掺杂非晶硅可有效降低非晶硅(a-Si)和数据线所在膜层的接触电阻，形成良好欧姆接触。
例如，如图2所示，沿垂直于衬底基板100的主表面的方向(也可以称为垂直于衬底基板100的方向)，如Z方向，第一级台阶211的厚度大于第二级台阶212的厚度。
例如，如图2所示，第一级台阶211远离数据线410一侧的侧壁可以为倾斜侧壁，第二级台阶212远离数据线410一侧的侧壁可以为倾斜侧壁，第一级台阶211的侧壁与第二级台阶212的侧壁相对于衬底基板100的主表面(垂直于Z方向的表面)的角度不同。上述第一级台阶包括基本平行于衬底基板的表面以及与衬底基板之间具有一定夹角的表面，上述第一级台阶的侧壁可以指第一级台阶的与衬底基板之间具有一定夹角的表面。上述第二级台阶包括基本平行于衬底基板的表面以及与衬底基板之间具有一定夹角的表面，上述第二级台阶的侧壁可以指第二级台阶的与衬底基板之间具有一定夹角的表面。
例如，如图2所示，第一级台阶211的侧壁与衬底基板100之间的夹角大于第二级台阶212的侧壁与衬底基板100之间的夹角。但不限于此，第一级台阶211的侧壁与衬底基板100之间的夹角也可以小于第二级台阶212的侧壁与衬底基板100之间的夹角。
例如，如图2所示，第一级台阶211的侧壁与衬底基板100之间的夹角可以为40～60度，第二级台阶212的侧壁与衬底基板100之间的夹角可以为20～40度。例如，第一级台阶211的侧壁与衬底基板100之间的夹角可以为45～55度，第二级台阶212的侧壁与衬底基板100之间的夹角可以为30～38度。例如，第一级台阶211的侧壁与衬底基板100之间的夹角可以为50～52度，第二级台阶212的侧壁与衬底基板100之间的夹角可以为35～37度。
例如，如图2所示，数据线410包括至少一层导电层，数据线410被平行于XZ面所截的截面的形状可以为梯形，梯形的侧边可以为数据线410侧壁被平行于XZ面所截的线。例如，数据线410的侧壁与第二级台阶212远离衬底基板100一侧表面之间的夹角范围包括30～80度。例如，数据线410的侧壁与第二级台阶212远离衬底基板100一侧表面之间的夹角范围包括40～70度。例如，数据线410的侧壁与第二级台阶212远离衬底基板100一侧表面之间的夹角范围包括50～60度。
例如，如图2所示，数据线410包括沿垂直于衬底基板100的方向依次层叠设置的第一金属层411，第二金属层412和第三金属层413，第一金属层411位于第二金属层412与衬底基板100之间，且第一金属层411的材料与第三金属层413的材料相同，第一金属层411与第二金属层412的材料不同。例如，第一金属层411和第三金属层413的材料可以均为钼，第二金属层412的材料可以为铝。本公开实施例不限于此，数据线的材料还可以采用铜等金属材料。
例如，如图2所示，第一金属层411的厚度和第三金属层413的厚度均小于第二金属层412的厚度。例如，第三金属层413的厚度大于第一金属层411的厚度。例如，数据线410的厚度为2000～6000埃。
例如，如图2所示，半导体层200的厚度小于导电层400的厚度。例如，半导体层200的厚度可以为1000～5000埃。例如，半导体层200的厚度可以为1000～2000埃。
例如，如图3所示，第二突出部220包括层叠设置的第三级台阶221和第四级台阶222，第三级台阶221位于第四级台阶222与衬底基板100之间，且第三级台阶221的边缘与晶体管300的第一极301的边缘之间间隔的尺寸为第三台阶尺寸，即第二尺寸S2，第四级台阶222的边缘与第一极301的边缘之间间隔的尺寸为第四台阶尺寸S21，第四台阶尺寸S21小于第三台阶尺寸。
例如，如图1和图3所示，第三级台阶221和第四级台阶222可以为一体化的结构。例如，第三级台阶221的材料包括非晶硅(a-Si)，第四级台阶222的材料包括掺杂非晶硅，例如，第四级台阶222可以为N型掺杂非晶硅(N+a-Si)，例如第四级台阶222的材料可以掺杂磷元素。掺杂非晶硅可有效降低非晶硅(a-Si)和数据线所在膜层的接触电阻，形成良好欧姆接触。
例如，如图3所示，沿垂直于衬底基板100的方向，如Z方向，第三级台阶221的厚度大于第四级台阶222的厚度。
例如，如图1至图3所示，第一级台阶211与第三级台阶221可以采用相同的材料，第二级台阶212与第四级台阶222可以采用相同的材料。例如，第一级台阶211与第三级台阶221的厚度可以相同，第二级台阶212与第四级台阶222的厚度可以相同。
例如，如图1至图3所示，第一台阶尺寸小于第三台阶尺寸。
例如，第一台阶尺寸可以为0.5～2微米。例如，第一台阶尺寸不大于1.8微米。例如，第一台阶尺寸不大于1.6微米。例如，第一台阶尺寸不大于1.4微米。例如，第一台阶尺寸不大于1.3微米。第一台阶尺寸不大于1.3微米。例如，第一台阶尺寸大于0.5微米。例如，第一台阶尺寸大于1微米。例如，第三台阶尺寸大于2微米。例如，第三台阶尺寸为2～2.6微米。例如，第三台阶尺寸为3～4微米。
例如，如图1至图3所示，第一台阶尺寸与第二台阶尺寸S11的比值小于第三台阶尺寸与第四台阶尺寸S21的比值。
例如，如图1至图3所示，第二台阶尺寸S11与第四台阶尺寸S21的比值为0.8～1.2。例如，第二台阶尺寸S11与第四台阶尺寸S21的比值为0.9～1.1。例如，第二台阶尺寸S11与第四台阶尺寸S21相同。例如，第二台阶尺寸S11和第四台阶尺寸S21可以为0.1～0.5微米。
本公开实施例通过将第一突出部中的第二台阶尺寸与第二突出部中的第四台阶尺寸设置为相同，且第一突出部中的第一台阶尺寸设置为小于第二突出部中的第三台阶尺寸，可以在不影响掺杂非晶硅材料与导电层的接触面积的同时，降低数据线边缘的半导体层的尺寸，以降低相对于数据线边缘突出的半导体层对产品性能的影响。
例如，如图1所示，被配置为连接数据线410与晶体管300的第一极301的连接部330也与半导体层200层叠设置，半导体层200与连接部330交叠的部分的延伸方向与连接部330的延伸方向相同，且该部分半导体层包括未被连接部330覆盖且相对于连接部330的边缘突出的突出部240，该突出部240设置在连接部330的至少一侧边缘，该突出部240远离连接部330的边缘与连接部330的边缘之间间隔的尺寸可以与第一突出部210的第一尺寸相同，以尽量降低相对于连接部边缘突出的半导体层对产品性能的影响。
例如，如图1和图3所示，晶体管300还包括栅极303，栅极303位于半导体层200与衬底基板100之间，第二突出部220在衬底基板100上的正投影位于栅极303所在膜层在衬底基板100上的正投影内。例如，栅极303可以与晶体管300的第一极301和第二极302之一交叠以形成存储电容。
例如，如图2和图3所示，显示基板还包括位于半导体层200与衬底基板100之间，且位于栅极303远离衬底基板100一侧的栅极绝缘层101。例如，栅极绝缘层101的厚度可以为2500～4000埃。
图4为根据本公开实施例的一示例提供的显示基板的局部平面结构示意图，图1为图4所示显示基板的局部C的放大图。例如，如图1至图4所示，显示基板包括多个子像素10，每个子像素10包括像素电极11，像素电极11位于导电层400远离衬底基板100的一侧。晶体管300的第二极302与像素电极11电连接。例如，像素电极11的材料可以采用氧化铟锡。例如，像素电极11的厚度可以为400～1100埃。例如，像素电极11与晶体管300的第二极302之间还可以设置钝化层，钝化层的厚度可以为1000～6000埃。
例如，显示基板还可以包括公共电极。例如，公共电极可以位于像素电极 远离衬底基板的一侧，多个子像素可以共用公共电极。例如，公共电极可以位于像素电极与衬底基板之间。例如，像素电极和公共电极之一可以为板状电极，另一个可以为狭缝电极。例如，公共电极可以与像素电极同层设置。例如，显示基板可以为阵列基板，公共电极可以设置在与显示基板相对设置的对置基板上。本公开实施例对公共电极和像素电极的位置关系以及形状不作限定，可以根据产品需求进行设置。
例如，如图1所示，半导体层200还包括与晶体管300的第二极302交叠且相对于第二极302的边缘突出的第三突出部230，第三突出部230围绕第二极302的至少部分边缘，第三突出部230远离第二极302的边缘与第二极302的边缘之间的最小间隔的尺寸为第三尺寸，第三尺寸大于第一尺寸。例如，第三尺寸可以与第二尺寸相等。当然，本公开实施例不限于第三尺寸大于第一尺寸，第三尺寸也可以与第一尺寸相等。例如，本公开实施例中，晶体管的第二极302延伸部分和栅线500之间在垂直衬底基板的方向上存在交叠，即此部分对应的半导体层也与栅线之间存在交叠，存在的交叠部分形成存储电容，有利于提高显示效果。
例如，如图1所示，晶体管300的第二极302包括延伸至晶体管300的第一极301的U形开口内的部分以及被配置为与像素电极11电连接的另一部分。例如，晶体管300的第二极302中被配置为与像素电极11电连接的另一部分与半导体层200层叠设置，这部分半导体层200的边缘相对于第二极302的边缘突出以形成第三突出部230。
例如，沿垂直于衬底基板100的方向，晶体管300的第二极302的一部分与栅极303所在膜层交叠。例如，沿垂直于衬底基板100的方向，晶体管300的第二极302的一部分与半导体层200的掺杂区图案320交叠，第二极302的另一部分与半导体层200的除沟道区310和掺杂区图案320以外的部分区域交叠。
例如，如图1和图4所示，显示基板还包括栅线500，栅线500与晶体管300的栅极303同层设置，且与栅极303电连接。例如，栅极303可以和与其电连接的栅线500一体化设置。
例如，如图1和图4所示，显示基板包括的多个子像素10沿行方向和列方向阵列排布，本公开实施例示意性的示出X方向为行方向，Y方向为列方向，但不限于此，行方向和列方向可以互换。
例如，如图4所示，相邻两列子像素列组成子像素列组010，显示基板包括沿行方向排列的多个子像素列组010，每个子像素列组010包括相邻的两列子像素列。
例如，多个子像素10可以包括多个发出不同颜色光的子像素，例如，多个子像素10可以包括多个发红色光的红色子像素、多个发绿色光的绿色子像素以及多个发蓝色光的蓝色子像素，红色子像素、绿色子像素以及蓝色子像素可以沿行方向依次重复排列，沿列方向排列的子像素可以为发相同颜色光的子像素，但不限于此，沿列方向排列的子像素也可以为依次重复排列的红色子像素、绿色子像素以及蓝色子像素。
例如，如图1和图4所示，数据线410沿列方向延伸，栅线500沿行方向延伸。上述数据线410沿列方向延伸可以指每条数据线410的整体延伸方向为沿列方向延伸，每条数据线410可以为沿列方向延伸的直线，也可以为沿列方向延伸的折线。上述栅线500沿行方向延伸可以指每条栅线500的整体延伸方向为沿行方向延伸，每条栅线500可以为沿行方向延伸的直线，也可以为沿行方向延伸的折线。
例如，如图1和图4所示，栅线500包括多条第一子栅线510和多条第二子栅线520。例如，多条第一子栅线510和多条第二子栅线520沿列方向交替排列。
例如，如图4所示，数据线410位于相邻两个子像素列组010之间，且子像素列组010中的两列子像素与同一条数据线410电连接。
例如，如图4所示，子像素列组010包括多行子像素行，且沿列方向，每个子像素行的两侧分别设置第一子栅线510和第二子栅线520，且相邻的子像素行之间包括第一子栅线510和第二子栅线520组成的栅线对。本公开实施例的一示例提供的显示基板可以采用双栅线(dual gate)技术，双栅线技术是将显示装置中的数据线的数量减少一半，栅线的数量增加一倍的驱动技术，即，将与数据线连接的源极驱动集成电路(integrated circuit，IC)的数量减半，将与栅线连接的栅极驱动集成电路的数量加倍。由于栅极驱动集成电路的单价比源极驱动集成电路的单价便宜，从而实现成本的降低。
例如，如图4所示，子像素10还包括公共电极，显示基板还包括与公共电极连接的公共电极线600，公共电极线600可以采用折线形。在液晶显示装置的对盒工艺中，液晶配向(rubbing)过程中，折线形的公共电极线可引导液 晶旋转。例如，公共电极线600上设置的宽度较大位置处可以对应设置隔垫物。
图5为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图。例如，图5所示示例中的显示基板与图1至图4所示示例中的显示基板的不同之处在于，晶体管300的第一极301与数据线410的位置关系不同，相邻子像素行之间仅设置一条栅线，且任意相邻子像素列之间均设置一条数据线，不采用双栅线技术。图5所示显示基板中半导体层200的边缘相对于数据线410的边缘突出的第一突出部210、半导体层200的边缘相对于第一极301的边缘突出的第二突出部220、数据线410、栅线500以及像素电极11等可以与图1所示显示基板中的第一突出部210、第二突出部220、数据线410、栅线500以及像素电极11等可以具有相同的特征，在此不再赘述。
例如，如图5所示，晶体管300的第一极301与数据线410可以为一体化的结构，没有采用图1所示的连接部330进行电连接。
例如，本公开实施例提供的显示基板可以为阵列基板。
例如，本公开另一实施例提供一种显示装置，该显示装置包括上述任一示例提供的显示基板。
例如，显示装置还可以包括与阵列基板对置设置的彩膜基板，以及设置在阵列基板与彩膜基板之间的液晶层。
例如，显示装置可以为液晶显示装置，或者包括该液晶显示装置的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本实施例不限于此。
本公开另一实施例提供一种形成图1至图4所示的显示基板的制作方法。图6A至图6C为制作沿图1所示的DD’线所截显示基板的局部截面结构的方法的示意图。如图1、图6A至图6C所示，显示基板的制作方法包括提供衬底基板100；在衬底基板100上形成半导体材料层20；在半导体材料层20远离衬底基板100的一侧形成导电材料层40；以及在导电材料层40远离半导体材料层20的一侧形成蚀刻掩模800。如图1、图6A至图6C所示，蚀刻掩模800包括第一掩模部810，第一掩模部810包括第一子掩模部811和第二子掩模部812，第二子掩模部812位于第一子掩模部811的至少一侧，且第二子掩模部812位于第一掩模部810的边缘，沿垂直于衬底基板100的方向，第一子掩模部811的厚度大于第二子掩模部812的厚度。形成蚀刻掩模800后，制作方法还包括：以第一掩模部810为掩模对导电材料层40和半导体材料层20进行图 案化以形成数据线410以及位于数据线410与衬底基板100之间的第一半导体图案23(如图17所示第一半导体图案23)。第一半导体图案23包括未被数据线410覆盖且相对于数据线410的边缘突出的第一突出部210，第一突出部210设置在数据线410的边缘，第一突出部210远离数据线410的边缘与数据线410的边缘之间间隔的尺寸为第一尺寸S1；第一尺寸S1大于0且小于3.0微米。本公开实施例采用具有不同厚度的第一掩模部为掩模图案化形成数据线以及与数据线交叠的第一半导体图案，有利于减小第一突出部的尺寸，进而提高产品性能，降低显示装置发生显示不良的几率。
例如，如图6A至图6C所示，第一子掩模部811和第二子掩模部812为一体化的结构。
例如，如图6A所示，可以采用半色调掩模(HTM Mask)910为掩模图案化形成蚀刻掩模800的第一掩模部810。
例如，蚀刻掩模800可以包括光刻胶，利用半色调掩模工艺直接对蚀刻掩模层进行图案化以形成具有不同厚度的第一掩模部810，即，第一掩模部810包括具有不同厚度的第一子掩模部811和第二子掩模部812。例如，第二子掩模部812位于第一子掩模部811的两侧。
例如，如图6A所示，半色调掩模910包括高透光部911、低透光部912以及遮光部913，半色调掩模910利用不同位置透光率具有差异的特性可以形成具有不同厚度的第一掩模部810。例如，在一个示例中，先形成蚀刻掩模层，然后利用半色调掩模910对蚀刻掩模层进行曝光，在需要暴露导电材料层40的蚀刻掩模层的边缘的位置形成完全曝光区域901，在需要形成第二子掩模部812的位置形成部分曝光区域902，在需要形成第一子掩模部811的区域903不进行曝光。然后，再对进行过曝光处理的蚀刻掩模层进行显影，以形成具有不同厚度的第一掩模部810。本示例以蚀刻掩模层采用包括正性光致刻蚀剂的材料为例进行描述，本示例不限于此，例如还可以是用包括负性光致刻蚀剂的材料。
例如，如图6B所示，可以采用狭缝掩模(SSM Mask)920为掩模图案化形成蚀刻掩模800的第一掩模部810。
例如，蚀刻掩模800可以包括光刻胶，利用狭缝掩模工艺直接对蚀刻掩模层进行图案化以形成具有不同厚度的第一掩模部810，即，第一掩模部810包括具有不同厚度的第一子掩模部811和第二子掩模部812。例如，第二子掩模 部812位于第一子掩模部811的两侧。
图6D包括图6B以及图7B所示狭缝掩模的平面结构图。例如，如图6B和图6D所示，狭缝掩模920包括透光部921以及遮光部922，透光部921可以包括狭缝，狭缝掩模920利用光的衍射实现一部分区域904的透光率低于另一部分区域905的透光率，区域905可以为部分曝光区域。例如，狭缝可以位于狭缝掩模920的两侧靠近边缘的位置，以在狭缝掩模920的靠近边缘的位置形成部分曝光区域。
例如，在一个示例中，先形成蚀刻掩模层，然后利用狭缝掩模920对蚀刻掩模层进行曝光，在需要暴露导电材料层40的蚀刻掩模层的边缘的位置形成完全曝光区域，在需要形成第二子掩模部812的位置形成部分曝光区域905，在需要形成第一子掩模部811的区域904不进行曝光。然后，再对进行过曝光处理的蚀刻掩模层进行显影，以形成具有不同厚度的第一掩模部810。本示例以蚀刻掩模层采用包括正性光致刻蚀剂的材料为例进行描述，本示例不限于此，例如还可以是用包括负性光致刻蚀剂的材料。
例如，如图6B和图6D所示，狭缝掩模920包括的狭缝的宽度s1可以为0.8～3微米。例如，狭缝掩模920包括的狭缝的宽度s1可以为1～2微米。例如，狭缝远离狭缝掩模920中心一侧的遮光部922的宽度w1可以为0.5～3微米。例如，狭缝远离狭缝掩模920中心一侧的遮光部922的宽度w1可以为1～2微米。
例如，图6C示意性的示出采用半色调掩模(HTM Mask)910为掩模图案化形成蚀刻掩模800的第一掩模部810的示意图，但不限于此，采用狭缝掩模(SSM Mask)920为掩模也可以图案化形成图6C所示的蚀刻掩模800的第一掩模部810。例如，采用半色调掩模(HTM Mask)910或者狭缝掩模(SSM Mask)920为掩模图案化形成的第一掩模部810中可以形成如图6A-图6B所示的坡度明显的第二子掩模部812，也可以形成如图6C所示坡度不太明显的第二子掩模部812。例如，如图6C所示，第二子掩模部812的坡度角可以为10～30度。例如，第二子掩模部812的坡度角可以为15～25度。第二子掩模部812的坡度角可以为18度。上述第二子掩模部812的坡度角可以指曲面被XZ面所截的曲线与导电材料层40接触的交点处切线与X方向之间的夹角。例如，第二子掩模部812的曲面被XZ面所截的曲线中点处切线与X方向之间的夹角可以为26～46度。例如，第二子掩模部812的曲面被XZ面所截的曲线中点处切线与 X方向之间的夹角可以为30～40度。例如，第二子掩模部812的曲面被XZ面所截的曲线中点处切线与X方向之间的夹角可以为36度。
例如，如图6A至图6C所示，第一子掩模部811的厚度H1可以为1.5～3.0微米。例如，第二子掩模部812的厚度H2可以为0.2～1.5微米。
例如，如图6A至图6C所示，半导体材料层20的材料可以包括非晶硅以及掺杂非晶硅。例如，掺杂非晶硅可以位于非晶硅面向导电材料层40的一侧。例如，半导体材料层20的厚度可以为1000～5000埃。例如，半导体材料层20的厚度可以为1000～2000埃。
例如，如图6A至图6C所示，导电材料层40可以包括至少一层膜层。例如，导电材料层40的材料可以包括钼、铝、铜等金属材料。
例如，如图6A至图6C所示，在形成半导体材料层20前，可以在衬底基板100上沉积栅极金属层，对栅极金属层进行曝光、刻蚀等工艺后可以形成图1、图3和图4所示的栅极303和栅线500。
例如，如图6A至图6C所示，在形成栅极303以及栅线500后，在栅线500远离衬底基板的一侧沉积栅极绝缘层101。
图7A至图7C为制作沿图1所示的EE’线所截显示基板的局部截面结构的方法的示意图。例如，如图1、图6A至图7C所示，蚀刻掩模800还包括第二掩模部820，第二掩模部820包括位于边缘位置的第三子掩模部821，沿垂直于衬底基板100的方向，第三子掩模部821的厚度与第一子掩模部811的厚度相同。例如，如图7A和图7B所示，第二掩模部820的两侧边缘位置处均为第三子掩模部821，第三子掩模部821远离第二掩模部820的边缘没有设置厚度小于第三子掩模部821的结构。
例如，如图7A至图7C所示，第二掩模部820还包括第四子掩模部822，第四子掩模部822的厚度小于第三子掩模部821的厚度。例如，如图7A至图7C所示，第二掩模部820包括三个第三子掩模部821和两个第四子掩模部822，第三子掩模部821和第四子掩模部822沿Y方向交替排列。
例如，如图7A至图7C所示，第三子掩模部821的厚度H3可以为1.5～3.0微米，第四子掩模部822的厚度H4可以为0.2～1.5微米。
例如，如图1、图7A至图7C所示，以第三子掩模部821为掩模可以形成晶体管300的第一极301和第二极302，以第四子掩模部822为掩模可以形成晶体管300的沟道区。
例如，如图7A所示，可以采用半色调掩模(HTM Mask)930为掩模图案化形成蚀刻掩模800的第二掩模部820。
例如，蚀刻掩模800可以包括光刻胶，利用半色调掩模工艺直接对蚀刻掩模层进行图案化以形成具有不同厚度的第二掩模部820，即，第二掩模部820包括具有不同厚度的第三子掩模部821和第四子掩模部822。
例如，如图7A所示，半色调掩模930包括高透光部931、低透光部932以及遮光部933，半色调掩模930利用不同位置透光率具有差异的特性可以形成具有不同厚度的第二掩模部820。例如，在一个示例中，先形成蚀刻掩模层，然后利用半色调掩模930对蚀刻掩模层进行曝光，在需要暴露导电材料层40的蚀刻掩模层的边缘的位置形成完全曝光区域901，在需要形成第四子掩模部822的位置形成部分曝光区域902，在需要形成第三子掩模部821的区域903不进行曝光。然后，再对进行过曝光处理的蚀刻掩模层进行显影，以形成具有不同厚度的第二掩模部820。本示例以蚀刻掩模层采用包括正性光致刻蚀剂的材料为例进行描述，本示例不限于此，例如还可以是用包括负性光致刻蚀剂的材料。
例如，如图7B所示，可以采用狭缝掩模(SSM Mask)940为掩模图案化形成蚀刻掩模800的第二掩模部820。
例如，蚀刻掩模800可以包括光刻胶，利用半色调掩模工艺直接对蚀刻掩模层进行图案化以形成具有不同厚度的第二掩模部820，即，第二掩模部820包括具有不同厚度的第三子掩模部821和第四子掩模部822。
例如，如图6D和图7B所示，狭缝掩模940包括透光部941以及遮光部942，透光部941可以包括狭缝，狭缝掩模940利用光的衍射实现一部分区域904的透光率低于另一部分区域905的透光率，区域905可以为部分曝光区域，而区域904可以为非曝光区域。例如，狭缝可以位于狭缝掩模940的非边缘位置，狭缝掩模940的中间区域以及两侧边缘区域设置有尺寸较大的遮光部942，以在狭缝掩模920的中间区域和两侧边缘区域的位置形成非曝光区，在狭缝掩模920的两个非曝光区中间的位置形成部分曝光区域，在位于边缘位置的非曝光区远离部分曝光区的一侧形成完全曝光区。
例如，在一个示例中，先形成蚀刻掩模层，然后利用狭缝掩模940对蚀刻掩模层进行曝光，在需要暴露导电材料层40的蚀刻掩模层的边缘的位置形成完全曝光区域，在需要形成第四子掩模部822的位置形成部分曝光区域905， 在需要形成第三子掩模部821的区域904不进行曝光。然后，再对进行过曝光处理的蚀刻掩模层进行显影，以形成具有不同厚度的第二掩模部820。本示例以蚀刻掩模层采用包括正性光致刻蚀剂的材料为例进行描述，本示例不限于此，例如还可以是用包括负性光致刻蚀剂的材料。
例如，如图7B和图6D所示，狭缝掩模940包括的每个狭缝的宽度s2(如狭缝沿Y方向的尺寸)可以大于3微米。例如，狭缝掩模940包括的每个狭缝的宽度s2可以为3～6微米。例如，狭缝掩模940包括的每个狭缝的宽度s2可以为4.7～5.2微米。例如，位于相邻两个狭缝之间的尺寸较大的遮光部942的宽度w2可以为1.5～3微米。例如，位于相邻两个狭缝之间的尺寸较大的遮光部942的宽度w2可以为2.1～2.3微米。
例如，图7C示意性的示出采用半色调掩模(HTM Mask)930为掩模图案化形成蚀刻掩模800的第二掩模部820的示意图，但不限于此，采用狭缝掩模(SSM Mask)940为掩模也可以图案化形成图7C所示的蚀刻掩模800的第二掩模部820。例如，采用半色调掩模(HTM Mask)930或者狭缝掩模(SSM Mask)940为掩模图案化形成的第二掩模部820中可以形成如图7A-8B所示的被YZ面所截边缘大致为直线第二掩模部820，也可以形成如图7C所示被YZ面所截边缘为曲线的第二掩模部820。例如，如图7C所示，第二掩模部820被YZ面所截曲线的坡度角可以为35～55度。例如，第二掩模部820被YZ面所截曲线的坡度角可以为40～50度。例如，第二掩模部820被YZ面所截曲线的坡度角可以为45度。上述第二掩模部820的坡度角可以指曲面被YZ面所截的曲线与导电材料层40接触的交点处切线与Y方向之间的夹角。
图8为另一种制作沿图1所示的EE’线所截显示基板的局部截面结构的方法的示意图。图8与图7A和图7C不同之处在于第二掩模部820中第三子掩模部821没有位于边缘位置，第三子掩模部821的边缘位置设置有第五子掩模部833，沿垂直于衬底基板100的方向，第三子掩模部821的厚度与第一子掩模部811的厚度相同，第五子掩模部833的厚度与第二子掩模部的厚度相同。
例如，如图8所示，第五子掩模部823的厚度H5可以为0.2～1.5微米。
例如，如图8所示，可以采用半色调掩模(HTM Mask)940为掩模图案化形成蚀刻掩模800的第二掩模部820。当然，本公开实施例不限于采用半色调掩模为掩模图案化形成图8所示的第二掩模部820，还可以采用狭缝掩模为掩模图案化形成图8所示的第二掩模部820。
例如，蚀刻掩模800可以包括光刻胶，利用半色调掩模工艺直接对蚀刻掩模层进行图案化以形成具有不同厚度的第二掩模部820，即，第二掩模部820包括具有不同厚度的第三子掩模部821、第四子掩模部822以及第五子掩模部823。
例如，如图8所示，半色调掩模950包括高透光部951、低透光部952以及遮光部953，半色调掩模950利用不同位置透光率具有差异的特性可以形成具有不同厚度的第二掩模部820。例如，在一个示例中，先形成蚀刻掩模层，然后利用半色调掩模950对蚀刻掩模层进行曝光，在需要暴露导电材料层40的蚀刻掩模层的边缘的位置形成完全曝光区域901，在需要形成第四子掩模部822和第五子掩模部823的位置形成部分曝光区域902，在需要形成第三子掩模部821的区域903不进行曝光。然后，再对进行过曝光处理的蚀刻掩模层进行显影，以形成具有不同厚度的第二掩模部820。本示例以蚀刻掩模层采用包括正性光致刻蚀剂的材料为例进行描述，本示例不限于此，例如还可以是用包括负性光致刻蚀剂的材料。
例如，与采用图7A所示第二掩模部820形成的晶体管处的半导体层不同之处在于：形成图8所示的第二掩模部820后，以图8所示第二掩模部820为掩模图案化形成的晶体管处的半导体层包括的第二突出部的第二尺寸与上述第一突出部的第一尺寸相同。采用图8所示第二掩模部图案化形成后续结构的方法步骤可以参考图10、图12、图14、图16以及图18对应方法形成的结构，在此不再赘述。
可选的，参见图8本案中晶体管对应半导体层的位置，第二突出部的长度大于数据线下对应的半导体的位置的第一突出部，即数据线层的边缘到半导体边缘之间的距离，可选的，晶体管对应半导体层的位置，和数据线下对应的半导体的位置，至少一个采用如图8所示的制备方法，即半导体层超出数据线的部分采用半色调掩模版或者SSM掩膜版，实现掩模部在半导体超出数据线层的位置有阶梯的形状。
图9为以第一掩模部为掩模图案化形成数据线图案的示意图，图10为以第二掩模部为掩模图案化形成晶体管源漏极图案的示意图。例如，如图6A、图6B以及图9所示，以第一掩模部810为掩模对导电材料层40进行图案化包括以第一掩模部810为掩模刻蚀导电材料层40形成数据线图案41。例如，以第一掩模部810为掩模对导电材料层40进行图案化包括以第一掩模部810为 掩模对导电材料层40进行湿刻以形成数据线图案41。例如，湿刻可以为各向同性刻蚀(例如在图中所示的X方向、Y方向以及Z方向均刻蚀)，导电材料层40的边缘相对于第一掩模部810的边缘缩进一定尺寸。
例如，如图7A、图7B以及图10所示，以第二掩模部820为掩模对导电材料层40进行图案化形成晶体管源漏极图案42。例如，以第二掩模部820为掩模刻蚀导电材料层40形成晶体管源漏极图案42。例如，以第二掩模部820为掩模对导电材料层40进行湿刻形成晶体管源漏极图案42。例如，湿刻可以为各向同性刻蚀，导电材料层40的边缘相对于第二掩模部820的边缘缩进一定尺寸。
例如，如图9和图10所示，数据线图案41和晶体管源漏极图案42被同步刻蚀形成。
图11为以第一掩模部为掩模对半导体材料层进行图案化形成第一半导体图案层的示意图，图12为以第二掩模部为掩模对半导体材料层进行图案化形成第二半导体图案层的示意图。例如，如图9和图11所示，形成数据线图案41后，以第一掩模部810为掩模刻蚀半导体材料层20以形成第一半导体图案层21。例如，如图9和图11所示，以第一掩模部810为掩模对半导体材料层20进行图案化包括：以第一掩模部810为掩模对半导体材料层20进行干刻以使第一掩模部810的边缘和半导体材料层20的边缘被同步刻蚀。例如，干刻可以为各向异性刻蚀(例如以在图中所示的Z方向上刻蚀为主，如X方向等其他横向方向刻蚀率较小)，且采用干刻工艺刻蚀半导体材料层20的边缘的同时，第一掩模部810的边缘也被同步刻蚀。
例如，如图9和图11所示，采用干刻工艺刻蚀半导体材料层20的同时，厚度较小的第二子掩模部812被同步刻蚀。相对于蚀刻掩模没有包括厚度不同的第一子掩模部和第二子掩模部的情况，本公开实施例采用边缘设置厚度较小的第二子掩模部的蚀刻掩模，以实现在采用干刻工艺刻蚀半导体材料层的同时，对位于蚀刻掩模边缘且厚度较小的第二子掩模部刻蚀的刻蚀量较大，使得以该第二子掩模部为掩模刻蚀掉的半导体材料层的边缘的尺寸较大，从而为后续形成具有较小第一突出部的第一半导体图案提供工艺基础。
例如，如图11所示，第一半导体图案层21的边缘位置可以大致为后续形成的第一半导体图案中的第一突出部(Act tail)的边缘位置，由此，采用边缘设置厚度较小的第二子掩模部的蚀刻掩模会影响第一突出部的尺寸。
例如，相对于先将第一掩模部灰化后，再对半导体材料层刻蚀而形成第一半导体图案层的工艺，本公开实施例采用干刻工艺同步刻蚀半导体材料层和第一掩模部的方法不仅可以为后续形成具有较小第一突出部的第一半导体图案提供工艺基础，还节省了一步灰化工艺的步骤。
例如，如图9和图11所示，采用干刻工艺刻蚀半导体材料层20的同时，厚度较大的第一子掩模部811也被同步刻蚀。
例如，如图9和图11所示，采用干刻工艺刻蚀半导体材料层20的同时对第一掩模部810进行刻蚀后得到了刻蚀后的第一掩模部810’。例如，刻蚀后的第一掩模部810’各位置处的厚度均小于第一掩模部810(图11中虚线所示)相应位置处的厚度。
例如，如图11所示，在刻蚀形成第一半导体图案层21的同时，栅极绝缘层101远离衬底基板100一侧的边缘也会被刻蚀掉部分厚度的材料。
例如，如图10和图12所示，以第二掩模部820为掩模对半导体材料层20进行图案化包括：在形成晶体管源漏极图案42后，以第二掩模部820为掩模刻蚀半导体材料层20以形成第二半导体图案层22。例如，以第二掩模部820为掩模对半导体材料层20进行图案化包括：以第二掩模部820为掩模对半导体材料层20进行干刻以使第二掩模部820的边缘和半导体材料层20的边缘被同步刻蚀。
例如，如图10和图12所示，采用干刻工艺刻蚀半导体材料层20的同时对第二掩模部820进行刻蚀得到了刻蚀后的第二掩模部820’。例如，刻蚀后的第二掩模部820’各位置处的厚度均小于第二掩模部820(图12中虚线所示)相应位置处的厚度。
例如，如图11和图12所示，第一半导体图案层21和第二半导体图案层22被同步刻蚀形成。例如，第一掩模部810和第二掩模部820同步刻蚀以分别形成刻蚀后的第一掩模部810’和刻蚀后的第二掩模部820’。
图13为对刻蚀后的第一掩模部进行灰化后的示意图，图14为对刻蚀后的第二掩模部进行灰化后的示意图。例如，如图9至图14所示，以第一掩模部810和第二掩模部820为掩模刻蚀半导体材料层20以形成第一半导体图案层21和第二半导体图案层22之后，制作方法还包括：对第一掩模部810和第二掩模部820同时进行灰化处理。例如，对第一掩模部810(如图13中虚线框所示)进行灰化处理包括对刻蚀后的第一掩模部810’进行灰化处理以形成灰化后 的第一掩模部810”。例如，对第二掩模部820(如图14中虚线框所示)进行灰化处理包括对刻蚀后的第二掩模部820’进行灰化处理以形成灰化后的第二掩模部820”。
例如，灰化后的第一掩模部810”的边缘的坡度角可以为35～55度。例如，灰化后的第一掩模部810”的边缘的坡度角可以为45度。例如，灰化后的第二掩模部820”的边缘的坡度角可以为60～80度。例如，灰化后的第二掩模部820”的边缘的坡度角可以为70度。
例如，如图9至图14所示，在垂直于衬底基板100的方向上，灰化后的第一掩膜部810”的厚度小于未灰化的第一子掩模部811的厚度。例如，灰化后的第一掩膜部810”的厚度小于刻蚀后的第一子掩模部的厚度。
例如，如图13所示，对刻蚀后的第一掩模部进行灰化处理后的得到的灰化后的第一掩膜部810”的边缘可以与数据线图案41的边缘齐平。
例如，如图14所示，对刻蚀后的第二掩模部进行灰化处理后的得到的灰化后的第一掩膜部820”的边缘可以与晶体管源漏极图案42的边缘齐平。
例如，如图9至图14所示，在垂直于衬底基板100的方向上，灰化后的第二掩膜部820”的厚度小于未灰化的第三子掩模部830的厚度。例如，灰化后的第一掩膜部810”的厚度小于刻蚀后的第三子掩模部的厚度。
例如，如图14所示，灰化后的第二掩模部820”包括间隔设置的多个子掩模部，相邻子掩模部之间的间隔被配置为暴露晶体管的沟道区，每个子掩模部被配置为遮挡晶体管的第一极和第二极之一。
图15为以灰化后的第一掩模部为掩模对数据线图案进行刻蚀后的示意图，图16为以灰化后的第二掩模部为掩模对晶体管源漏极图案进行刻蚀后的示意图。例如，如图13和图15所示，对第一掩模部和第二掩模部同时进行灰化处理后，制作方法还包括：以灰化后的第一掩模部810”为掩模刻蚀数据线图案41以形成数据线410。例如，以灰化后的第一掩模部810”为掩模刻蚀数据线图案41以形成数据线410包括：以灰化后的第一掩模部810”为掩模对数据线图案41进行湿刻以形成数据线410，数据线410的边缘相对于灰化后的第一掩模部810”的边缘内缩一定尺寸。
例如，如图13至图16所示，在刻蚀数据线图案41以形成数据线410的同时，制作方法还包括以灰化后的第二掩模部820”为掩模刻蚀晶体管源漏极图案42以形成晶体管的第一极301和第二极302。例如，可以采用湿刻法刻蚀 形成晶体管的第一极301和第二极302，第一极301和第二极302的边缘均相对于灰化后的第二掩模部820”的边缘内缩一定尺寸。
例如，如图16所示，第一极301与第二极302间隔设置。例如，第一极301和第二极302之间的间隔被配置为暴露第二半导体图案层22的部分。
图17为以灰化后的第一掩模部为掩模对第一半导体图案层进行刻蚀后的示意图，图18为以灰化后的第二掩模部为掩模对第二半导体图案层进行刻蚀后的示意图。例如，如图15和图17所示，形成数据线410后，以灰化后的第一掩模部810”为掩模刻蚀掉第一半导体图案层21边缘的远离衬底基板10的部分厚度的材料以形成第一半导体图案23。
例如，如图2和图17所示，第一半导体图案23包括第一级台阶211和第二级台阶212，第一级台阶211位于第二级台阶212与衬底基板100之间，且第一级台阶211的边缘与数据线410的边缘之间间隔的尺寸为第一台阶尺寸S1，第二级台阶212的边缘与数据线410的边缘之间间隔的尺寸为第二台阶尺寸S11；第一台阶尺寸S1与第二台阶尺寸S11比例范围为2-25。例如，第一台阶尺寸与第二台阶尺寸比例范围为3-20。例如，第一台阶尺寸与第二台阶尺寸比例范围为5-15。例如，第一台阶尺寸与第二台阶尺寸比例范围为8-12。
例如，第一级台阶211和第二级台阶212可以为一体化的结构。例如，第一级台阶211的材料包括非晶硅(a-Si)，第二级台阶212的材料包括掺杂非晶硅，例如，第二级台阶212可以为N型掺杂非晶硅(N+a-Si)，例如第二级台阶212的材料可以掺杂磷元素。
例如，第一半导体图案层21中被刻蚀掉的部分的材料至少包括掺杂非晶硅。例如，第一半导体图案层21中被刻蚀掉的部分的材料还可以包括非晶硅。
例如，如图3、图7A-图7B、图10、图12、图14、图16和图18所示，形成蚀刻掩模后，制作方法还包括：以第二掩模部820为掩模对导电材料层40和半导体材料层20进行图案化以形成晶体管300的第一极301和第二极302以及位于晶体管300的第一极301和第二极302与衬底基板100之间的第二半导体图案24。例如，第二半导体图案24包括晶体管300的沟道区310和掺杂区图案320，第二半导体图案24的边缘相对于第一极301的边缘(如第一极301远离第二极302一侧的边缘)突出的突出部分为第二突出部220，第一极301和第二极302均与掺杂区图案320电连接，第一极301与数据线410电连接，第二突出部220远离第一极301的边缘与第一极301的边缘之间的最小间 隔的尺寸为第二尺寸，第二尺寸大于第一尺寸。本公开实施例中，通过第一半导体图案的边缘相对于数据线边缘突出的第一突出部的尺寸设置为小于第二半导体图案的边缘相对于晶体管的第一极的边缘突出的第二突出部的尺寸，可以在不影响晶体管正常工作的情况下，降低数据线边缘的第一突出部的尺寸，有利于解决尺寸较长的第一突出部产生的水波纹、残像等不良问题，进而提高产品性能。
例如，如图3和图18所示，第二突出部220包括层叠设置的第三级台阶221和第四级台阶222，第三级台阶221位于第四级台阶222与衬底基板100之间，且第三级台阶221的边缘与晶体管300的第一极301的边缘之间间隔的尺寸为第三台阶尺寸，即第二尺寸S2，第四级台阶222的边缘与第一极301的边缘之间间隔的尺寸为第四台阶尺寸S21，第四台阶尺寸S21小于第三台阶尺寸。
例如，如图1和图3所示，第三级台阶221和第四级台阶222可以为一体化的结构。例如，第三级台阶221的材料包括非晶硅(a-Si)，第四级台阶222的材料包括掺杂非晶硅，例如，第四级台阶222可以为N型掺杂非晶硅(N+a-Si)，例如第四级台阶222的材料可以掺杂磷元素。
例如，第二半导体图案层22中被刻蚀掉的部分的材料至少包括掺杂非晶硅。例如，第二半导体图案层22中被刻蚀掉的部分的材料还可以包括非晶硅。
相对于直接形成没有第二子掩模部的第一掩模部，本公开实施例提供的显示基板的制作方法通过采用半色调掩模或者狭缝掩模形成具有第二子掩模部的第一掩模部，没有增加额外的掩模工艺就可以减小后续形成的第一半导体图案的第一突出部的尺寸，以节约成本。此后，在两次湿刻和两次干刻(2W2D)工艺下形成的尺寸较小的第一突出部(Act Tail)在背光源照射下，形成光生载流子较少，有利于提高产品的性能。
本公开实施例中，用于形成与数据线交叠的半导体层的蚀刻掩模边缘包括厚度较小的第二子掩模部(或者蚀刻掩模边缘坡度角较小)，用于形成晶体管位置处的半导体层的蚀刻掩模边缘不包括厚度较小的子掩模部(或者蚀刻掩模边缘坡度角较大)，从而形成的晶体管位置处的半导体层相对于导电层突出的第二突出部的尺寸大于形成的与数据线交叠的半导体层相对于数据线突出的第一突出部的尺寸。晶体管包括的半导体层被栅极覆盖，可以阻挡背光源的光线对晶体管位置的半导体层产生影响，而与数据线交叠的半导体层没有被栅极 所在膜层遮挡，容易被背光源的光线照射，造成对半导体层的电学性能产生影响。本公开实施例提供的显示基板中，将第一突出部的尺寸设置为小于第二突出部的尺寸，可以不改变晶体管中半导体层的形貌，但是减小数据线下的半导体层相对于数据线突出部分的长度，从而减小背光对半导体层产生的影响。
例如，如图16和图18所示，在形成第一半导体图案23和第二半导体图案24以后，制作方法还包括将灰化后的蚀刻掩模去除，以暴露数据线410和晶体管的第一极301和第二极302。
例如，在去除蚀刻掩模后，在数据线410所在膜层远离衬底基板100的一侧形成钝化层。例如，在形成钝化层后，制作方法还包括在钝化层远离衬底基板的一侧形成像素电极。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (21)

  1. 一种显示基板，包括：
    衬底基板；
    半导体层，位于所述衬底基板上，所述半导体层包括晶体管的沟道区和掺杂区图案；
    导电层，与所述半导体层层叠设置，且位于所述半导体层远离所述衬底基板的一侧，所述导电层包括数据线以及与所述掺杂区图案电连接的所述晶体管的第一极和第二极，所述第一极与所述数据线电连接，
    其中，所述半导体层与所述数据线交叠部分的延伸方向和所述数据线延伸方向相同，所述半导体层包括未被所述数据线覆盖且相对于所述数据线的边缘突出的第一突出部，所述第一突出部设置在所述数据线的边缘，所述第一突出部远离所述数据线的边缘与所述数据线的边缘之间间隔的尺寸为第一尺寸，所述第一尺寸大于0且小于3.0微米。
  2. 根据权利要求1所述的显示基板，其中，所述半导体层的边缘相对于所述第一极的边缘突出的部分为第二突出部，所述第二突出部设置在所述第一极的边缘，所述第二突出部远离所述第一极的边缘与所述第一极的边缘之间的间隔的尺寸为第二尺寸，所述第二尺寸大于所述第一尺寸。
  3. 根据权利要求2所述的显示基板，其中，所述第一突出部包括层叠设置的第一级台阶和第二级台阶，所述第一级台阶位于所述第二级台阶与所述衬底基板之间，且所述第一级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第一台阶尺寸，所述第二级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第二台阶尺寸；
    所述第一台阶尺寸与所述第二台阶尺寸的比例范围为2-25。
  4. 根据权利要求3所述的显示基板，其中，所述第一级台阶的材料包括非晶硅，所述第二级台阶的材料包括掺杂非晶硅。
  5. 根据权利要求3或4所述的显示基板，其中，所述数据线包括至少一层导电层，所述数据线的侧壁与所述第二级台阶远离所述衬底基板一侧表面之间的夹角范围包括30～80度。
  6. 根据权利要求3-5任一项所述的显示基板，其中，所述第二突出部包括层叠设置的第三级台阶和第四级台阶，所述第三级台阶位于所述第四级台阶 与所述衬底基板之间，且所述第三级台阶的边缘与所述第一极的边缘之间间隔的尺寸为第三台阶尺寸，所述第四级台阶的边缘与所述第一极的边缘之间间隔的尺寸为第四台阶尺寸；
    所述第一台阶尺寸小于所述第三台阶尺寸。
  7. 根据权利要求6所述的显示基板，其中，所述第三级台阶的材料包括非晶硅，所述第四级台阶的材料包括掺杂非晶硅。
  8. 根据权利要求6或7所述的显示基板，其中，所述第一台阶尺寸与所述第二台阶尺寸的比值小于所述第三台阶尺寸与所述第四台阶尺寸的比值。
  9. 根据权利要求1-8任一项所述的显示基板，其中，所述晶体管还包括栅极，所述栅极位于所述半导体层与所述衬底基板之间，所述第二突出部在所述衬底基板上的正投影位于所述栅极所在膜层在所述衬底基板上的正投影内。
  10. 根据权利要求9所述的显示基板，还包括：
    多个子像素，每个子像素包括像素电极，所述像素电极位于所述导电层远离所述衬底基板的一侧，
    其中，所述第二极与所述像素电极电连接；
    所述半导体层还包括与所述第二极交叠且相对于所述第二极边缘突出的第三突出部，所述第三突出部围绕所述第二极的至少部分边缘，所述第三突出部远离所述第二极的边缘与所述第二极的边缘之间的最小间隔的尺寸为第三尺寸，所述第三尺寸大于所述第一尺寸。
  11. 根据权利要求10所述的显示基板，还包括：
    栅线，所述栅线与所述栅极同层设置，且与所述栅极电连接，
    其中，所述多个子像素沿行方向和列方向阵列排布，相邻两列子像素列组成子像素列组；
    所述数据线沿所述列方向延伸，所述栅线沿所述行方向延伸，所述栅线包括多条第一子栅线和多条第二子栅线；
    所述数据线位于相邻两个子像素列组之间，且所述子像素列组中的两列子像素与同一条数据线电连接；
    所述子像素列组包括多行子像素行，且沿所述列方向，每个所述子像素行的两侧分别设置所述第一子栅线和所述第二子栅线，且相邻的所述子像素行之间包括所述第一子栅线和所述第二子栅线组成的栅线对。
  12. 根据权利要求6-8任一项所述的显示基板，其中，所述第二台阶尺寸 与所述第四台阶尺寸的比值为0.8～1.2。
  13. 一种显示装置，包括权利要求1-12任一项所述的显示基板。
  14. 一种显示基板的制作方法，包括：
    提供衬底基板；
    在所述衬底基板上形成半导体材料层；
    在所述半导体材料层远离所述衬底基板的一侧形成导电材料层；以及
    在所述导电材料层远离所述半导体材料层的一侧形成蚀刻掩模，
    其中，所述蚀刻掩模包括第一掩模部，所述第一掩模部包括第一子掩模部和第二子掩模部，所述第二子掩模部位于所述第一子掩模部的至少一侧，且所述第二子掩模部位于所述第一掩模部的边缘，沿垂直于所述衬底基板的方向，所述第一子掩模部的厚度大于所述第二子掩模部的厚度，
    形成所述蚀刻掩模后，所述制作方法还包括：
    以所述第一掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化以形成数据线以及位于所述数据线与所述衬底基板之间的第一半导体图案，其中，所述第一半导体图案包括未被所述数据线覆盖且相对于所述数据线的边缘突出的第一突出部，所述第一突出部设置在所述数据线的边缘，所述第一突出部远离所述数据线的边缘与所述数据线的边缘之间间隔的尺寸为第一尺寸；所述第一尺寸大于0且小于3.0微米。
  15. 根据权利要求14所述的制作方法，其中，以所述第一掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化包括：
    以所述第一掩模部为掩模刻蚀所述导电材料层形成数据线图案；
    形成所述数据线图案后，以所述第一掩模部为掩模刻蚀所述半导体材料层以形成第一半导体图案层。
  16. 根据权利要求15所述的制作方法，其中，以所述第一掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化包括：
    以所述第一掩模部为掩模对所述导电材料层进行湿刻以形成所述数据线图案，以所述第一掩模部为掩模对所述半导体材料层进行干刻以使所述第一掩模部的边缘和所述半导体材料层的边缘被同步刻蚀。
  17. 根据权利要求14-16任一项所述的制作方法，其中，所述蚀刻掩模还包括第二掩模部，所述第二掩模部包括位于边缘位置的第三子掩模部，沿垂直于所述衬底基板的方向，所述第三子掩模部的厚度与所述第一子掩模部的厚度 相同；
    形成所述蚀刻掩模后，所述制作方法还包括：
    以所述第二掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化以形成晶体管的第一极和第二极以及位于所述晶体管的第一极和第二极与所述衬底基板之间的第二半导体图案，其中，所述第二半导体图案包括所述晶体管的沟道区和掺杂区图案，所述第二半导体图案的边缘相对于所述第一极的边缘突出的突出部分为第二突出部，所述第一极和所述第二极均与所述掺杂区图案电连接，所述第一极与所述数据线电连接，所述第二突出部远离所述第一极的边缘与所述第一极的边缘之间的最小间隔的尺寸为第二尺寸，所述第二尺寸大于所述第一尺寸。
  18. 根据权利要求17所述的制作方法，其中，以所述第二掩模部为掩模对所述导电材料层和所述半导体材料层进行图案化包括：
    以所述第二掩模部为掩模刻蚀所述导电材料层形成晶体管源漏极图案；
    形成所述晶体管源漏极图案后，以所述第二掩模部为掩模刻蚀所述半导体材料层形成第二半导体图案层。
  19. 根据权利要求18所述的制作方法，其中，以所述第一掩模部和所述第二掩模部为掩模刻蚀所述半导体材料层以形成所述第一半导体图案层和所述第二半导体图案层之后，所述制作方法还包括：
    对所述第一掩模部和所述第二掩模部同时进行灰化处理，
    其中，在垂直于所述衬底基板的方向上，灰化后的所述第一掩膜部的厚度小于未灰化的所述第一子掩模部的厚度。
  20. 根据权利要求19所述的制作方法，其中，对所述第一掩模部和所述第二掩模部同时进行灰化处理后，所述制作方法还包括：
    以灰化后的所述第一掩模部为掩模刻蚀所述数据线图案以形成所述数据线；
    形成所述数据线后，以灰化后的所述第一掩模部为掩模对所述第一半导体图案层边缘进行刻蚀以形成第一级台阶和第二级台阶，
    其中，所述第一半导体图案包括所述第一级台阶和所述第二级台阶，所述第一级台阶位于所述第二级台阶与所述衬底基板之间，且所述第一级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第一台阶尺寸，所述第二级台阶的边缘与所述数据线的边缘之间间隔的尺寸为第二台阶尺寸；所述第一台阶尺寸与 所述第二台阶尺寸比例范围为2-25。
  21. 根据权利要求14-20任一项所述的制作方法，其中，采用半色调掩模或者狭缝掩模形成所述蚀刻掩模中的所述第一掩模部。
PCT/CN2021/134572 2021-11-30 2021-11-30 显示基板及其制作方法、显示装置 WO2023097496A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/134572 WO2023097496A1 (zh) 2021-11-30 2021-11-30 显示基板及其制作方法、显示装置
CN202180003730.5A CN117377903A (zh) 2021-11-30 2021-11-30 显示基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/134572 WO2023097496A1 (zh) 2021-11-30 2021-11-30 显示基板及其制作方法、显示装置

Publications (2)

Publication Number Publication Date
WO2023097496A1 true WO2023097496A1 (zh) 2023-06-08
WO2023097496A9 WO2023097496A9 (zh) 2023-08-03

Family

ID=86611438

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/134572 WO2023097496A1 (zh) 2021-11-30 2021-11-30 显示基板及其制作方法、显示装置

Country Status (2)

Country Link
CN (1) CN117377903A (zh)
WO (1) WO2023097496A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553267A (zh) * 2003-05-28 2004-12-08 友达光电股份有限公司 平面显示器及其制造方法
CN1743935A (zh) * 2004-09-03 2006-03-08 三星电子株式会社 显示器件的基板和具有其的液晶显示器件及其制造方法
US20060131581A1 (en) * 2004-12-17 2006-06-22 Samsung Electronics Co., Ltd. Thin film transistor array panel and method for manufacturing the same
CN101598876A (zh) * 2008-06-02 2009-12-09 乐金显示有限公司 用于液晶显示装置的阵列基板及其制造方法
CN109524419A (zh) * 2018-10-11 2019-03-26 深圳市华星光电技术有限公司 Tft阵列基板的制作方法
CN110648923A (zh) * 2019-03-22 2020-01-03 友达光电股份有限公司 半导体结构及其制作方法
CN110867458A (zh) * 2019-11-25 2020-03-06 昆山龙腾光电股份有限公司 金属氧化物半导体薄膜晶体管阵列基板及制作方法
CN112071867A (zh) * 2020-09-17 2020-12-11 惠科股份有限公司 主动开关阵列基板、薄膜晶体管阵列基板的制造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553267A (zh) * 2003-05-28 2004-12-08 友达光电股份有限公司 平面显示器及其制造方法
CN1743935A (zh) * 2004-09-03 2006-03-08 三星电子株式会社 显示器件的基板和具有其的液晶显示器件及其制造方法
US20060131581A1 (en) * 2004-12-17 2006-06-22 Samsung Electronics Co., Ltd. Thin film transistor array panel and method for manufacturing the same
CN101598876A (zh) * 2008-06-02 2009-12-09 乐金显示有限公司 用于液晶显示装置的阵列基板及其制造方法
CN109524419A (zh) * 2018-10-11 2019-03-26 深圳市华星光电技术有限公司 Tft阵列基板的制作方法
CN110648923A (zh) * 2019-03-22 2020-01-03 友达光电股份有限公司 半导体结构及其制作方法
CN110867458A (zh) * 2019-11-25 2020-03-06 昆山龙腾光电股份有限公司 金属氧化物半导体薄膜晶体管阵列基板及制作方法
CN112071867A (zh) * 2020-09-17 2020-12-11 惠科股份有限公司 主动开关阵列基板、薄膜晶体管阵列基板的制造方法

Also Published As

Publication number Publication date
CN117377903A (zh) 2024-01-09
WO2023097496A9 (zh) 2023-08-03

Similar Documents

Publication Publication Date Title
US9437619B2 (en) Array substrate, manufacturing method thereof and display device
US9613986B2 (en) Array substrate and its manufacturing method, display device
US8253905B2 (en) Liquid crystal display device and method of making the same
KR101942982B1 (ko) 액정표시장치용 어레이 기판 및 이의 제조방법
US9484364B2 (en) Array substrate and method for manufacturing the same, display device
KR20020091683A (ko) 프린지 필드 스위칭 액정표시장치 및 그 제조방법
WO2021203894A9 (zh) 阵列基板及其制作方法、显示装置
CN109494257B (zh) 一种薄膜晶体管及其制造方法、阵列基板、显示装置
JP2009133954A (ja) 液晶表示装置及びその製造方法
US20230178560A1 (en) Thin-film transistor and method for manufacturing same, and array substrate and display panel
KR20110061773A (ko) 액정표시장치용 어레이 기판 및 그 제조방법
WO2013143321A1 (zh) 阵列基板及其制造方法和显示装置
KR20020093351A (ko) 그레이톤 마스크 및 이를 이용한 액정디스플레이 제조방법
US10217851B2 (en) Array substrate and method of manufacturing the same, and display device
CN113687548B (zh) 阵列基板及其制作方法、以及显示面板
US8796079B2 (en) Pixel structure and fabricating method thereof
WO2015021720A1 (zh) 一种阵列基板及其制备方法及显示装置
WO2016041349A1 (zh) 阵列基板及其制备方法、显示装置
US20120169984A1 (en) Display substrate and method of manufacturing the same
WO2023097496A1 (zh) 显示基板及其制作方法、显示装置
US20180149934A1 (en) Array substrate and liquid crystal display panel
KR101897747B1 (ko) 에프에프에스 방식 액정표시장치용 어레이기판 및 그 제조방법
KR20070115235A (ko) 개구율이 향상된 표시 장치 및 그 제조 방법
KR20050117846A (ko) 액정표시장치용 어레이 기판 제조방법
KR20150062741A (ko) 프린지필드 스위칭모드 어레이기판 및 그 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180003730.5

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 18019267

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21965934

Country of ref document: EP

Kind code of ref document: A1