WO2023097445A1 - 发光基板及其制备方法、显示装置 - Google Patents

发光基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023097445A1
WO2023097445A1 PCT/CN2021/134395 CN2021134395W WO2023097445A1 WO 2023097445 A1 WO2023097445 A1 WO 2023097445A1 CN 2021134395 W CN2021134395 W CN 2021134395W WO 2023097445 A1 WO2023097445 A1 WO 2023097445A1
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Prior art keywords
light
substrate
pad
layer
electrode
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PCT/CN2021/134395
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English (en)
French (fr)
Inventor
牛亚男
曲燕
杨明
彭锦涛
秦斌
陈婉芝
Original Assignee
京东方科技集团股份有限公司
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Priority to PCT/CN2021/134395 priority Critical patent/WO2023097445A1/zh
Priority to CN202180003688.7A priority patent/CN116529885A/zh
Publication of WO2023097445A1 publication Critical patent/WO2023097445A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, and specifically relate to a light-emitting substrate, a manufacturing method thereof, and a display device.
  • Micro Light Emitting Diode With the development of chip manufacturing and packaging technology, Micro Light Emitting Diode (Micro LED) has become the first choice for next-generation display technology due to its significant advantages such as low power consumption, high color gamut, ultra-high resolution, and ultra-thin. research direction.
  • the Micro LED In the currently commonly used Micro LED transfer process, the Micro LED is usually directly transferred to the driver backplane. Under the existing process and structure, especially in the front lighting, due to the deviation between the Micro LED shape and the design, the side-emission light is obvious, and the area of the side-emission light radiation path becomes larger due to the residual sacrificial layer for transfer. , the front Micro LED is more prone to back light leakage, which seriously affects the related yield of Micro LED.
  • an embodiment of the present disclosure provides a light-emitting substrate, including a substrate, a crystal-bonding structure disposed on the substrate, a light-shielding structure, and a light-emitting chip, and the light-emitting chip is disposed on a surface far away from the substrate.
  • the light-shielding structure is located on the peripheral side of the light-emitting chip, and the light-emitting substrate further includes a flux functional layer covering the side of the die-bonding structure away from the substrate, the light-shielding structure includes a light-shielding material layer and The isolation structure, the solder flux functional layer is blocked at the isolation structure.
  • At least part of the light-shielding material layer covers the partition structure.
  • the partition structure includes a first side and a second side arranged on the base, a partition groove is formed between the first side and the second side, and the light-shielding material A layer fills at least part of the isolation slots.
  • the die-bonding structure includes a pad support, a second insulating layer disposed on a side of the pad support away from the substrate, and a second insulating layer disposed on a side of the second insulating layer away from the substrate.
  • the light-emitting chip is disposed on the pad, and the first side and/or the second side are integrally formed with the second insulating layer using the same material.
  • a surface of the isolation structure on a side away from the base is higher than a surface of the pad holder on a side away from the base.
  • the light-shielding material layer is disposed around the periphery of the light-emitting chip.
  • the orthographic projection of the light-shielding material layer on the substrate has no overlapping area with the orthographic projection of the light emitting chip on the substrate.
  • an encapsulation layer is further included, the encapsulation layer covers the light-emitting chip, and the surface of the light-shielding material layer on a side away from the base is higher than the surface of the encapsulation layer on a side away from the base.
  • the die-bonding structure includes a pad support, a second insulating layer disposed on a side of the pad support away from the substrate, and a second insulating layer disposed on a side of the second insulating layer away from the substrate.
  • the pad includes a first pad electrode and a second pad electrode disconnected from each other
  • the light-emitting substrate further includes a connection electrode, a first lead, and The first insulating layer
  • the connection electrode is located on the side of the first pad electrode close to the substrate
  • the orthographic projection of the connection electrode on the substrate is the same as the orthographic projection of the first pad electrode on the substrate
  • the first lead is connected to at least one side of the connection electrode
  • the first insulating layer is located between the connection electrode and the first pad electrode
  • the first insulating layer A first opening is provided, the first opening exposes the connection electrode, and the first pad electrode is connected to the connection electrode through the first opening.
  • the first lead and the connecting electrode are integrally formed using the same material.
  • the light-emitting substrate further includes a light-shielding layer, the light-shielding layer is located on the side of the connecting electrode close to the substrate, and at least part of the light-shielding layer has an orthographic projection on the substrate that is aligned with the connecting electrode. Orthographic projections on the bases have overlapping regions.
  • it also includes a second lead, the second lead is connected to at least one side of the second pad electrode, and the second lead is made of the same material as the second pad electrode One piece.
  • the section of the isolation structure is C-shaped in a direction parallel to the base, the second lead is located on the side of the isolation structure away from the base, and the second lead is on the side of the isolation structure.
  • the orthographic projection of the base does not overlap with the orthographic projection of the partition structure on the base.
  • the die-bonding structure includes a pad support, a second insulating layer disposed on a side of the pad support away from the substrate, and a second insulating layer disposed on a side of the second insulating layer away from the substrate.
  • the light-emitting chip is arranged on the pad, the pad includes a first pad electrode and a second pad electrode disconnected from each other, and the light-emitting substrate further includes a first connection disconnected from each other electrode, a first lead, a second connection electrode, a second lead, and a first insulating layer, the first connection electrode is located on the side of the first pad electrode close to the substrate, and the first connection electrode is on the side of the first pad electrode
  • the orthographic projection of the substrate has an overlapping area with the orthographic projection of the first pad electrode on the substrate, the first lead is connected to at least one side of the first connection electrode; the second connection electrode is located at the The second pad electrode is close to the side of the substrate, the orthographic projection of the second connection electrode on the substrate has an overlapping area with the orthographic projection of the second pad electrode on the substrate, and the second A lead wire is connected to at least one side of the second connection electrode; the first insulating layer is located between the first connection electrode and the first pad electrode, and the first insulating layer is located
  • the light-emitting substrate further includes a light-shielding layer, the light-shielding layer is located on the side of the first connection electrode close to the substrate, and the light-shielding layer is located on the side of the second connection electrode close to the substrate.
  • the orthographic projections of at least part of the light-shielding layer on the substrate have an overlapping area with the orthographic projections of the first connection electrode on the substrate and the orthographic projections of the second connection electrode on the substrate.
  • the light emitting chip includes at least one micro light emitting diode.
  • the embodiment of the present disclosure also provides a method for preparing a light-emitting substrate, including:
  • soldering flux functional layer Forming a soldering flux functional layer on the crystal-bonding structure, welding the light-emitting chip to the crystal-bonding structure; the soldering flux functional layer is blocked at the isolation groove;
  • the light-shielding material layer and the partition structure form a light-shielding structure, and the light-shielding structure is located on the peripheral side of the light-emitting chip.
  • forming the die-bonding structure and the isolation structure on the substrate includes:
  • the sacrificial layer is removed through the second opening, and the second insulating layer on the sacrificial layer is retained; the second insulating layer on the sacrificial layer forms the isolation structure.
  • the sacrificial layer and the pad support are simultaneously formed on the substrate through a half-tone masking process.
  • an embodiment of the present disclosure further provides a display device, including the aforementioned light-emitting substrate.
  • FIG. 1 is a structural schematic diagram 1 of a light-emitting substrate according to an embodiment of the present disclosure
  • FIG. 2 is a second structural schematic diagram of a light-emitting substrate according to an embodiment of the present disclosure
  • FIG. 3 is a first schematic diagram after forming a first conductive layer pattern and a light-shielding layer pattern on a light-emitting substrate according to an embodiment of the present disclosure
  • FIG. 4 is a first cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming a first conductive layer pattern and a light-shielding layer pattern;
  • FIG. 5 is a schematic diagram of a light-emitting substrate according to an embodiment of the present disclosure after forming a pad support pattern and a sacrificial layer pattern;
  • FIG. 6 is a first cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming a pad support pattern and a sacrificial layer pattern;
  • FIG. 7 is a schematic diagram of a light-emitting substrate according to an embodiment of the present disclosure after forming a pad pattern
  • FIG. 8 is a first cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming a pad pattern
  • FIG. 9 is a schematic diagram of a light-emitting substrate after transferring a light-emitting chip according to an embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view of a light-emitting substrate after transferring a light-emitting chip according to an embodiment of the present disclosure
  • FIG. 11 is a cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming an encapsulation layer pattern;
  • FIG. 12 is a cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after removing a sacrificial layer pattern;
  • FIG. 13 is a schematic diagram 2 after the first conductive layer pattern and the light-shielding layer pattern are formed on the light-emitting substrate according to the embodiment of the present disclosure
  • FIG. 14 is a second cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming a first conductive layer pattern and a light-shielding layer pattern;
  • 15 is a second cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming a pad support pattern and a sacrificial layer pattern;
  • FIG. 16 is a second cross-sectional view of a light-emitting substrate according to an embodiment of the present disclosure after forming a pad pattern.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • LED light-emitting substrates are usually miniaturized, arrayed, and thinned by using miniaturization process technology to miniaturize, array, and thin-film the LED chips, and transfer the LED chips to the drive backplane in batches through mass transfer technology.
  • the LED light-emitting substrate generally includes a driving backplane and a plurality of LED light-emitting chips arranged on the driving backplane.
  • the applicant of the present disclosure found that due to the deviation between the shape of the LED light-emitting chip and the design, it is easy to cause the side-emitting light of the LED light-emitting chip to be obvious and the area of the radiation path of the side-emitting light caused by the residue of the sacrificial layer for transfer becomes larger, making the LED light-emitting substrate Light leakage on the back is more likely to occur.
  • the LED light-emitting substrate of the related art due to the influence of the mismatch between the light-shielding area and the height of the driving backplane and the dirt on the edge of the LED, the light-shielding performance of the LED light-emitting substrate is poor.
  • the LED chip is generally soldered to the pad by using a leveling flux layer or flux.
  • the deposition range of the leveling flux layer or flux is not easy to control, and it is easy to deposit outside the solid crystal area of the LED chip, while the leveling flux layer or flux is located below it (close to the direction of the substrate) ) there is a difference in refractive index between the film layers, the light emitted by the LED chip is refracted multiple times and then exits from the side of the substrate away from the LED chip, resulting in light leakage from the side of the light-emitting chip 11, and the more the leveling flux layer or flux residue area The larger the size, the larger the light leakage range.
  • FIG. 1 is a first structural schematic diagram of a light-emitting substrate according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a light-emitting substrate, including a substrate 1, a crystal-bonding structure disposed on the substrate 1, a light-shielding structure, and a light-emitting chip 11.
  • the light-emitting chip 11 is disposed on the crystal-bonding structure away from the substrate 1- On the side, the light-shielding structure is located on the peripheral side of the light-emitting chip 11.
  • the light-emitting substrate also includes a soldering function layer covering the side of the die-bonding structure away from the substrate 1.
  • the light-shielding structure includes a light-shielding material layer 14 and a partition structure 13. The soldering function layer is in the partition structure. 13 were blocked.
  • the soldering functional layer is blocked by the partition structure 13 in the light-shielding structure, and the range of the soldering functional layer is limited by the partition structure 13, so as to prevent the soldering functional layer from flowing to areas other than the die-bonding area of the light-emitting chip 11, thereby Solve the problem of light leakage from the side of the light-emitting chip 11 caused by the flux functional layer.
  • At least part of the light-shielding material layer 14 covers the partition structure 13, that is, the orthographic projection of at least part of the light-shielding material layer 14 on the substrate 1 and the partition structure 13 on the substrate 1 have an overlapping area, thereby reducing the number of light-shielding structures.
  • the area occupied by the direction parallel to the base 1 saves space.
  • the orthographic projection of the partition structure 13 on the substrate 1 is located in the orthographic projection of the light-shielding material layer 14 on the substrate, that is, the light-shielding material layer 14 covers the entire partition structure 13, and the light-shielding material layer 14 covers the partition structure 13
  • the partition slots in are completely filled.
  • the light emitting chip 11 may be a micro LED light emitting chip or a submillimeter LED light emitting chip.
  • Each micro-LED light-emitting chip may include a plurality of micro-light-emitting diodes (Micro LEDs) connected in series, and a typical size (eg, length) of each micro-LED may be less than 50 ⁇ m, such as 10 ⁇ m to 50 ⁇ m.
  • Each submillimeter LED light-emitting chip may include a plurality of submillimeter light emitting diodes (Mini LEDs) connected in series, and a typical size (eg, length) of each submillimeter LED may be about 50 ⁇ m to 150 ⁇ m, such as 80 ⁇ m to 120 ⁇ m.
  • the shape of the light emitting chip 11 may be set as required.
  • the outline of the light-emitting chip 11 in a direction parallel to the substrate may be rectangular, which makes it easier to realize partition control of the backlight source.
  • the number and arrangement of the light-emitting chips 11 on the substrate 1 and the number and arrangement of the plurality of light-emitting diodes in the light-emitting chip 11 can be set according to actual conditions, which are not limited in this disclosure.
  • the isolation structure 13 includes a first side 131 and a second side 132 disposed on the substrate 1 , the first side 131 is located on a side of the second side 132 away from the light-emitting chip 11 .
  • a partition groove is formed between the first side 131 and the second side 132, and the light-shielding material layer fills at least part of the partition groove, so that the light-shielding material layer in the partition groove can block the light emitted from the side of the light-emitting chip 11, preventing the light-emitting chip 11 from The light emitted from the side passes through the partition structure 13 to cause light leakage.
  • the crystal bonding structure includes a pad holder 6, a second insulating layer 8 disposed on the side of the pad holder 6 away from the substrate 1, and a pad 9 disposed on the side of the second insulating layer 8 away from the substrate 1 , the light emitting chip 11 is welded on the pad 9 .
  • the pad holder 6 is used to support the pad 9 and the light emitting chip 11 .
  • the pad 9 is made of conductive material, such as metal, and the pad 9 is used to electrically connect with the light emitting chip 11 and transmit the light emitting signal to the light emitting chip 11 .
  • the second insulating layer 8 is used to isolate the pad holder 6 from the pad 9 .
  • the first side 131 and/or the second side 132 of the partition structure 13 are integrally formed with the second insulating layer 8 using the same material, that is, the first side 131 and/or the first side 131 of the partition structure 13
  • the second side 132 and the second insulating layer 8 are made of the same material through the same manufacturing process.
  • the first side 131 and the second side 132 are integrally formed with the same material as the second insulating layer 8 . The preparation process is simplified and the production cost is reduced.
  • the surface of the isolation structure 13 on the side away from the base 1 is higher than the surface of the pad holder 6 on the side away from the base 1, that is, in the thickness direction of the base 1, the height of the isolation structure 13 is greater than that of the pad holder 6. high.
  • the partition structure 13 can effectively block the overflow of the welding flux functional layer.
  • the cross-section of the pad holder 6 in a direction perpendicular to the substrate 1 can adopt various shapes.
  • the cross section of the pad support 6 in the direction perpendicular to the substrate 1 may be trapezoidal, rectangular or the like.
  • the light-shielding material layer 14 may have a ring shape, for example, a rectangular ring shape.
  • the light-shielding material layer 14 is arranged around the light-emitting chip 11 , so that the light-shielding material layer 14 can completely block the light emitted from the side of the light-emitting chip 11 to avoid light leakage from the side of the light-emitting chip 11 .
  • the orthographic projection of the light-shielding material layer 14 on the substrate 1 has no overlapping area with the orthographic projection of the light-emitting chip 11 on the substrate 1, so as to prevent the light-shielding material layer 14 from blocking the light-emitting chip 11 in a direction perpendicular to the substrate 1, affecting The luminous efficiency of the light emitting chip 11.
  • the light-emitting substrate of the present disclosure further includes an encapsulation layer 12, and the encapsulation layer 12 covers the light-emitting chip 11, that is, the encapsulation layer 12 is located on the side of the light-emitting chip 11 away from the substrate 1, and the orthographic projection of the encapsulation layer 12 on the substrate 1 is the same as Orthographic projections of the light-emitting chips 11 on the substrate 1 overlap.
  • the encapsulation layer 12 is used to protect the light emitting chip 11 .
  • the surface of the light-shielding material layer 14 away from the substrate 1 is higher than the surface of the packaging layer 12 away from the substrate 1 , so that the light-shielding material layer 14 has a better light-shielding effect.
  • the pad 9 includes a first pad electrode 901 and a second pad electrode 902 that are disconnected from each other, and the light-emitting substrate further includes a connection electrode 3, a first lead, and a first insulating Layer 5, the connection electrode 3 is located on the side of the first pad electrode 901 close to the substrate 1 , and the orthographic projection of the connection electrode 3 on the substrate 1 and the orthographic projection of the first pad electrode 901 on the substrate 1 have an overlapping area.
  • the first lead is connected to at least one side of the connection electrode 3 , for example, the first lead is connected to the side of the connection electrode 3 away from the light-emitting chip 11 , and the first lead extends away from the light-emitting chip 11 .
  • the first insulating layer 5 is located between the connecting electrode 3 and the first pad electrode 901, the first insulating layer 5 is provided with a first opening, the first opening exposes the connecting electrode 3, and the first pad electrode 901 passes through the first pad electrode 901. An opening is connected with the connecting electrode 3 .
  • the first lead and the connecting electrode 3 can be integrally formed using the same material, that is, the first lead and the connecting electrode 3 can be prepared using the same material through the same manufacturing process, which simplifies the manufacturing process and reduces Cost of production.
  • the light-emitting substrate further includes a light-shielding layer 2, which is located on the side of the connecting electrode 3 close to the substrate 1, and at least part of the orthographic projection of the light-shielding layer 2 on the substrate 1 and the orthographic projection of the connecting electrode 3 on the substrate 1 have the same overlapping areas.
  • the light-shielding layer 2 is used to shield the reflection of the connecting electrodes 3 .
  • the light shielding layer 2 may be a black matrix (BM).
  • the light-emitting substrate further includes a second lead 10, the second lead 10 is connected to at least one side of the second pad electrode 902, and the second lead 10 and the second pad electrode 902 are integrated using the same material Forming means that the second lead 10 and the second pad electrode 902 can be made of the same material through the same manufacturing process, which simplifies the manufacturing process and reduces the production cost.
  • the isolation structure 13 has a C-shaped cross section parallel to the direction of the substrate 1, the second lead 10 is located on the side of the isolation structure 13 away from the substrate 1, and the orthographic projection of the second lead 10 on the substrate 1 is consistent with the isolation structure The orthographic projections of 13 on base 1 do not overlap.
  • FIG. 2 is a second structural schematic diagram of a light-emitting substrate according to an embodiment of the disclosure.
  • the crystal bonding structure includes a pad holder 6 , a second insulating layer 8 disposed on a side of the pad holder 6 away from the base 1 , and a second insulating layer 8 disposed on a side away from the base 1 .
  • Pad 9 on one side.
  • the light emitting chip 11 is disposed on the pad 9 .
  • the pad 9 includes a first pad electrode 901 and a second pad electrode 902 disconnected from each other.
  • the light-emitting substrate further includes a first connection electrode 3a, a first lead, a second connection electrode 3b, a second lead and a first insulating layer 5 which are disconnected from each other.
  • the first connection electrode 3a is located on the side of the first pad electrode 901 close to the substrate 1, and the orthographic projection of the first connection electrode 3a on the substrate has an overlapping area with the orthographic projection of the first pad electrode 901 on the substrate;
  • At least one side of a connection electrode 3a is connected, for example, a first lead is connected to a side of the first connection electrode 3a away from the second connection electrode 3b, and the first lead extends in a direction away from the second connection electrode 3b.
  • the second connection electrode 3 b is located on the side of the second pad electrode 902 close to the substrate 1 , and the orthographic projection of the second connection electrode 3 b on the substrate and the orthographic projection of the second pad electrode 901 on the substrate have an overlapping area.
  • the second lead is connected to at least one side of the second connection electrode 3b, for example, the second lead is connected to the side of the second connection electrode 3b away from the first connection electrode 3a, and the second lead is along the direction away from the first connection electrode 3a. extend.
  • the first insulating layer 5 is located between the first connection electrode 3 a and the first pad electrode 901 , and the first insulating layer 5 is located between the second connection electrode 3 b and the second pad electrode 902 .
  • the orthographic projection of the first insulating layer 5 on the substrate 1 overlaps with the orthographic projection of the first connecting electrode 3 a on the substrate 1 and the orthographic projection of the second connecting electrode 3 b on the substrate 1 .
  • the first insulating layer 5 is provided with a first opening, the first opening exposes the first connection electrode 3a and the second connection electrode 3b, the first pad electrode 901 is connected to the first connection electrode 3a through the first opening, The second pad electrode 902 is connected to the second connection electrode 3b through the first opening.
  • the first connection electrode 3 a and the second connection electrode 3 b can be manufactured using the same material through the same manufacturing process. The preparation process is simplified and the production cost is reduced.
  • the light-emitting substrate further includes a light-shielding layer 2, the light-shielding layer 2 is located on the side of the first connection electrode close to the base, and the light-shielding layer 2 is located on the side of the second connection electrode close to the base,
  • the orthographic projections of at least part of the light-shielding layer on the substrate have an overlapping area with the orthographic projections of the first connection electrode on the substrate and the orthographic projections of the second connection electrode on the substrate.
  • An embodiment of the present disclosure also provides a display device, comprising any one of the light-emitting substrates described above.
  • the display device in the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Embodiments of the present disclosure also provide a method for preparing a light-emitting substrate, including:
  • soldering flux functional layer Forming a soldering flux functional layer on the crystal-bonding structure, welding the light-emitting chip to the crystal-bonding structure; the soldering flux functional layer is blocked at the isolation groove;
  • the light-shielding material layer and the partition structure form a light-shielding structure, and the light-shielding structure is located on the peripheral side of the light-emitting chip.
  • forming the die-bonding structure and the isolation structure on the substrate includes:
  • the sacrificial layer is removed through the second opening, and the second insulating layer on the sacrificial layer is retained; the second insulating layer on the sacrificial layer forms the isolation structure.
  • the sacrificial layer and the pad support are simultaneously formed on the substrate through a half-tone masking process.
  • the following is an exemplary description through the preparation process of the light-emitting substrate.
  • the "patterning process" mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • Thin film refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the driving backplane.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A and the orthographic projection of B Projected boundaries overlap.
  • FIG. 3 to 16 are schematic diagrams of the preparation process of the light-emitting substrate according to the embodiments of the present disclosure.
  • the preparation method of the light-emitting substrate in the embodiment of the present disclosure specifically includes:
  • Forming a first conductive layer pattern and a light shielding layer pattern may include: sequentially depositing a light-shielding film, a first conductive film, and a first insulating film on the substrate 1, sequentially depositing the light-shielding film, the first insulating film, and the light-shielding film through a patterning process.
  • the conductive film and the first insulating film are patterned to form a light shielding layer 2 disposed on the substrate 1, a first conductive layer pattern disposed on the light shielding layer 2, and a first insulating layer 5 disposed on the first conductive layer pattern .
  • the first conductive layer pattern at least includes connecting electrodes 3 and first leads 4 , and a first opening 501 is opened in the first insulating layer 5 .
  • the first opening 501 may be ring-shaped, exposing the surface of the connecting electrode 3 , as shown in FIG. 3 and FIG. 4 , and FIG. 4 is a cross-sectional view along the line A-A in FIG. 3 .
  • the orthographic projection of the light-shielding layer 2 on the substrate 1 and the orthographic projection of the connecting electrode 3 on the substrate 1 have an overlapping area, and the light-shielding layer 2 is used to shield the reflection of the connecting electrode 3 .
  • the light shielding layer 2 may be a black matrix (BM).
  • the first lead 4 is connected to at least one side of the connection electrode 3, and the end of the first lead 4 away from the connection electrode 3 can be connected to a driving circuit for transmitting the light-emitting signal to the light-emitting chip through the connection electrode 3 .
  • the first conductive film can be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr) and tungsten (W ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., can be single-layer structure, or multi-layer metal, such as Mo/Cu/ Mo, etc., can also be a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr) and tungsten (W ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc.
  • the first insulating layer 5 is an inorganic insulating layer, and any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) can be used, and can be Single layer, multilayer or composite layer, the first insulating layer is called passivation (PVX) layer.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • PVX passivation
  • the substrate may be a rigid substrate or a flexible substrate
  • the rigid substrate may be glass or the like
  • the flexible substrate may be polyimide (PI) or the like.
  • forming the pad support pattern and the sacrificial layer pattern may include: firstly depositing a first material thin film on the first insulating layer 5 on the substrate 1 on which the aforementioned pattern is formed, and through glue coating and photolithography processes, The first material film is formed into the pad holder 6 . Then a second material film is deposited on the first insulating layer 5 , and the second material film is formed into a sacrificial layer 7 by glue coating and photolithography process, and the sacrificial layer 7 is located on the edge side of the pad support 6 close to the substrate 1 .
  • the bottom of the sacrificial layer 7 extends to the surface of the connection electrode 3 through the first opening 501 .
  • a second insulating film is deposited on the first insulating layer 5 , and the second insulating film is patterned by a patterning process, so that the second insulating film forms a second insulating layer 8 covering the pad support 6 and the sacrificial layer 7 .
  • a second opening 801 and a third opening 802 are disposed in the second insulating layer 8 .
  • the orthographic projection of the second opening 801 on the substrate 1 overlaps the orthographic projection of part of the sacrificial layer 7 on the substrate 1 , that is, the second opening 801 exposes part of the surface of the sacrificial layer 7 .
  • the third opening 802 communicates with the first opening 501 , and the third opening 802 exposes the connecting electrode 3 .
  • the orthographic projections of the third opening 802 on the substrate 1 do not overlap with the orthographic projections of the pad holder 6 and the sacrificial layer 7 on the substrate 1, as shown in FIGS. 5 and 6 , and FIG. cutaway view.
  • the pad support 6 and the sacrificial layer 7 can be made of the same material and prepared simultaneously through a half-tone masking process, which simplifies the process and reduces the manufacturing cost.
  • the sacrificial layer 7 may be ring-shaped.
  • the sacrificial layer 7 is arranged around the pad support 6, that is, the sacrificial layer 7 is arranged around the first bracket 601 and the second bracket 602.
  • the sacrificial layer 7 can be made of organic materials. For example, resin.
  • the distance from the surface of the sacrificial layer 7 on the side away from the substrate 1 to the surface of the substrate 1 is greater than the distance from the surface of the pad support 6 on the side away from the substrate 1 to the surface of the substrate 1, that is, in the thickness direction of the substrate 1,
  • the height of the sacrificial layer 7 is greater than that of the pad support 6 .
  • the sacrificial layer 7 has the function of restricting the flow of the encapsulation layer material and blocking the overflow of the soldering flux functional layer.
  • the pad holder 6 includes a first socket 601 and a second socket 602 disconnected from each other.
  • the first bracket 601 and the second bracket 602 can adopt various shapes. For example, in a direction parallel to the base 1 , the cross-sections of the first bracket 601 and the second bracket 602 are both rectangular.
  • the pad support 6 is used to support the pads and the light emitting unit.
  • the pad holder 6 can be made of organic material. For example, resin.
  • the second insulating layer 8 is an inorganic insulating layer, and any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) can be used, and can be Single layer, multilayer or composite layer.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • the second opening 801 in the direction parallel to the substrate 1 , is C-shaped, a part of the ring-shaped sacrificial layer 7 is not exposed by the second opening 801 , and the second insulating layer 8 covering the sacrificial layer 7
  • a second lead wire 10 may be arranged on it for leading out the second lead wire 10 .
  • forming the pad pattern may include: depositing a second conductive film on the second insulating layer 8 on the substrate 1 forming the aforementioned pattern, and patterning the second conductive film through a patterning process, so that The second conductive film forms pads 9 and second leads 10 .
  • the pad 9 includes a first pad electrode 901 and a second pad electrode 902 that are disconnected from each other.
  • the first pad electrode 901 covers the first bracket 601 and the third opening 802.
  • the first pad electrode 901 passes through the third The opening 802 extends to the surface of the connection electrode 3 and is connected to the connection electrode 3 , so that the first lead 4 can guide the light emitting signal to the first pad electrode 901 through the connection electrode 3 .
  • the second pad electrode 902 covers the second bracket 602 , and the side of the second pad electrode 902 away from the first pad electrode 901 is connected to the second lead 10 .
  • the second lead 10 covers a part of the sacrificial layer 7, the second lead 10 extends from the second pad electrode 902 in a direction away from the first pad electrode 901, and crosses a part of the sacrificial layer 7, and the second lead 10 is on the base 1
  • the orthographic projection does not overlap with the orthographic projection of the second opening 801 on the substrate 1 .
  • One end of the second lead wire 10 away from the second pad electrode 902 can be connected to the drive circuit for guiding the luminous signal to the second pad electrode 902, as shown in Figure 7 and Figure 8, Figure 8 is the A-A direction in Figure 7 cutaway view.
  • the second conductive film can be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr) and tungsten (W ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., can be single-layer structure, or multi-layer metal, such as Mo/Cu/ Mo, etc., can also be a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), chromium (Cr) and tungsten (W ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc.
  • transferring the light-emitting chip may include: transferring the light-emitting chip 11 on the substrate 1 formed with the aforementioned pattern, and performing die bonding and welding on the light-emitting chip 11 , so that the light-emitting chip 11 is welded on the pad 9 .
  • the light-emitting chip 11 includes a first electrode and a second electrode, the first electrode of the light-emitting chip 11 is connected to the first pad electrode 901, and the second electrode of the light-emitting chip 11 is connected to the second pad electrode 902, as As shown in Fig. 9 and Fig. 10, Fig. 10 is a sectional view along the direction A-A in Fig. 9 .
  • the solder flux functional layer 12 is deposited on the pad 9 first, and then the light-emitting chip 11 is soldered to the pad 9 .
  • the soldering flux functional layer 12 can be a leveling soldering flux layer or flux.
  • the fluxing functional layer and the encapsulation layer are illustrated as the same material, so the fluxing functional layer in FIG. 10 and the encapsulation layer in FIG. 11 are both indicated by the same reference number 12, and the two materials can also be different, which is not limited.
  • Forming the encapsulation layer pattern may include: depositing an encapsulation film on the second insulating layer 8 through an inkjet printing process on the substrate 1 forming the aforementioned pattern, and patterning the encapsulation film through a patterning process , making the encapsulation film form the encapsulation layer 12 covering the light-emitting chip 11, as shown in FIG. 11 .
  • the encapsulation layer 12 completely covers the sharp part of the light-emitting chip 11 , and the refractive index of the encapsulation layer 12 matches that of the light-emitting chip 11 .
  • removing the sacrificial layer pattern may include: etching and removing the sacrificial layer through the second opening 801 on the substrate 1 on which the foregoing pattern is formed, and leaving the second insulating layer 8 on the sacrificial layer. After the sacrificial layer is removed, the second insulating layer 8 on the sacrificial layer forms an isolation structure 13 , as shown in FIG. 12 .
  • soldering flux functional layer 12 on the sacrificial layer will fall off with the sacrificial layer, so that the soldering flux functional layer 12 is blocked at the isolation structure 13, thereby solving the problem that the soldering flux functional layer 12 causes light-emitting chip 11 side The problem of light leakage.
  • the distance from the surface of the partition structure 13 on the side away from the substrate 1 to the substrate 1 is greater than the surface of the packaging layer 12 on the side away from the substrate 1 , that is, the surface of the partition structure 13 on the side away from the substrate 1 is higher than the packaging layer 12 The surface away from the side of the base 1.
  • the partition structure 13 includes a first side 131 and a second side 132 oppositely disposed, the second opening 801 is located between the top of the first side 131 and the top of the second side 132 , A partition groove is formed between the first side 131 and the second side 132 , as shown in FIG. 12 .
  • Forming a light-shielding material layer pattern may include: depositing a light-shielding material on the outside of the encapsulation layer 12 on the substrate 1 formed with the aforementioned pattern, the light-shielding material covers the partition structure 13, and at least part of the light-shielding material fills the partition structure 13 In the isolation groove, the light-shielding material is patterned through a patterning process, so that the light-shielding material forms a light-shielding material layer 14, as shown in FIG. 1 .
  • the light-shielding material layer 14 can be prepared by using a normal temperature or low temperature black matrix.
  • the light-shielding material layer 14 may be ring-shaped, and the light-shielding material layer 14 may be disposed around the light-emitting chip 11 .
  • the light-shielding material layer 14 is used to shield light emitted from the side of the light-emitting chip 11 to prevent light leakage from the side of the light-emitting chip 11 .
  • the bottom of the light-shielding material layer 14 extends into the isolation groove in the isolation structure 13, and extends to the connection electrode 3 through the first opening 501 in the first insulating layer 5.
  • the light emitted from the side of the light-emitting chip 11 is prevented from being emitted through the first insulating layer 5 , so as to avoid light leakage from the side of the light-emitting chip 11 .
  • the distance between the surface of the light-shielding material layer 14 on the side away from the substrate 1 and the surface of the substrate 1 is greater than the distance from the surface of the encapsulation layer 12 on the side away from the substrate 1 to the surface of the substrate 1, that is, In the thickness direction of the substrate 1 , the height of the light-shielding material layer 14 is greater than that of the encapsulation layer 12 , so as to improve the light-shielding efficiency of the light-shielding material layer 14 .
  • an embodiment of the present disclosure also provides a method for preparing a light-emitting substrate, and the method for preparing the light-emitting substrate includes:
  • Forming a first conductive layer pattern and a light shielding layer pattern may include: sequentially depositing a light-shielding film, a first conductive film, and a first insulating film on the substrate 1, sequentially depositing the light-shielding film, the first insulating film, and the light-shielding film through a patterning process.
  • the conductive film and the first insulating film are patterned to form a light shielding layer 2 disposed on the substrate 1, a first conductive layer pattern disposed on the light shielding layer 2, and a first insulating layer 5 disposed on the first conductive layer pattern .
  • the first conductive layer pattern at least includes a first connection electrode 3 a, a second connection electrode 3 b, a first lead 4 and a second lead 10 .
  • the first connection electrode 3a and the second connection electrode 3b are disconnected from each other.
  • the first lead wire 4 is connected to the first connection electrode 3a, and is located on the side of the first connection electrode 3a away from the second connection electrode 3b.
  • the second lead wire 10 is connected to the second connection electrode 3b, and is located on the side of the second connection electrode 3b away from the first connection electrode 3a.
  • a first opening 501 is opened in the first insulating layer 5 .
  • the first opening 501 may be ring-shaped, exposing the surfaces of the first connection electrode 3 a and the second connection electrode 3 b, as shown in FIG. 13 and FIG. 14 , and FIG. 14 is a cross-sectional view along the line A-A in FIG. 13 .
  • forming the pad support pattern and the sacrificial layer pattern may include: firstly depositing a first material thin film on the first insulating layer 5 on the substrate 1 on which the aforementioned pattern is formed, and through glue coating and photolithography processes, The first material film is formed into the pad holder 6 . Then a second material film is deposited on the first insulating layer 5 , and the second material film is formed into a sacrificial layer 7 by glue coating and photolithography process, and the sacrificial layer 7 is located on the edge side of the pad support 6 close to the substrate 1 .
  • the bottom of the sacrificial layer 7 extends to the surface of the connection electrode 3 through the first opening 501 . Then a second insulating film is deposited on the first insulating layer 5 , and the second insulating film is patterned by a patterning process, so that the second insulating film forms a second insulating layer 8 covering the pad support 6 and the sacrificial layer 7 .
  • the second insulating layer 8 is provided with a second opening 801 , a third opening a803 and a third opening b804 .
  • the orthographic projection of the second opening 801 on the substrate 1 overlaps the orthographic projection of part of the sacrificial layer 7 on the substrate 1 , that is, the second opening 801 exposes part of the surface of the sacrificial layer 7 .
  • Both the third opening a803 and the third opening b804 communicate with the first opening 501 .
  • the orthographic projections of the third opening a803 on the substrate 1 overlap with the orthographic projection of the first connection electrode 3a on the substrate 1, and the third opening a803 exposes the surface of the first connection electrode 3a; the third opening b804 is in The orthographic projections on the substrate 1 overlap with the orthographic projections of the second connection electrode 3 b on the substrate 1 , and the third opening b804 exposes the surface of the second connection electrode 3 b, as shown in FIG. 15 .
  • forming the pad pattern may include: depositing a second conductive film on the second insulating layer 8 on the substrate 1 forming the aforementioned pattern, and patterning the second conductive film through a patterning process, so that The second conductive film forms the pad 9 .
  • the pad 9 includes a first pad electrode 901 and a second pad electrode 902 disconnected from each other, the first pad electrode 901 covers the first bracket 601 and the third opening a803, the first pad electrode 901 passes through the third
  • the opening a803 extends to the surface of the first connecting electrode 3a, and is connected to the first connecting electrode 3a, so that the first lead 4 can lead the light emitting signal to the first pad electrode 901 through the first connecting electrode 3a.
  • the second pad electrode 902 covers the second bracket 602 and the third opening b804, the second pad electrode 902 extends to the surface of the second connection electrode 3b through the third opening b804, and is connected to the second connection electrode 3b, so that The second lead wire 10 can lead the light emitting signal to the second pad electrode 902 through the second connection electrode 3b, as shown in FIG. 16 .
  • the subsequent preparation process of the preparation method of the light-emitting substrate in the embodiment of the present disclosure is the same as the preparation process of the preparation method of the light-emitting substrate in the foregoing embodiment, and will not be repeated here in the embodiment of the present disclosure.

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Abstract

一种发光基板及其制备方法、显示装置。发光基板包括基底，设置于所述基底上的固晶结构、遮光结构以及发光芯片，所述发光芯片设置在所述固晶结构远离所述基底一侧，所述遮光结构位于所述发光芯片的周侧，所述发光基板还包括覆盖所述固晶结构远离所述基底一侧的的助焊功能层，所述遮光结构包括遮光材料层以及隔断结构，所述助焊功能层在所述隔断结构处被阻断。

Description

发光基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及发光基板及其制备方法、显示装置。
背景技术
随着芯片制作及封装技术的发展，微发光二极管(Micro Light Emitting Diode，Micro LED)以其低功耗、高色域、超高分辨率、超薄等显著优势已经成为下一代显示技术的首选研究方向。
在目前常用的Micro LED转移制程中，通常将Micro LED直接转印至驱动背板上。在现有工艺和结构下，特别是在前置照明时，由于Micro LED形貌与设计有偏差导致的侧出光明显、转移用的牺牲层残留导致的侧出光辐射路径发光区面积变大等原因，前置Micro LED较易出现背面漏光现象，严重影响了Micro LED的相关良率。
公开内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种发光基板，包括基底，设置于所述基底上的固晶结构、遮光结构以及发光芯片，所述发光芯片设置在所述固晶结构远离所述基底一侧，所述遮光结构位于所述发光芯片的周侧，所述发光基板还包括覆盖所述固晶结构远离所述基底一侧的的助焊功能层，所述遮光结构包括遮光材料层以及隔断结构，所述助焊功能层在所述隔断结构处被阻断。
在示例性实施例中，至少部分所述遮光材料层覆盖所述隔断结构。
在示例性实施例中，所述隔断结构包括设置在基底上的第一侧边和第二侧边，所述第一侧边与所述第二侧边之间形成隔断槽，所述遮光材料层填充至少部分所述隔断槽。
在示例性实施例中，所述固晶结构包括焊盘托、设置在所述焊盘托远离所述基底一侧 的第二绝缘层以及设置在所述第二绝缘层远离所述基底一侧的焊盘，所述发光芯片设置在所述焊盘上，所述第一侧边和/或所述第二侧边与所述第二绝缘层采用相同的材料一体成型。
在示例性实施例中，所述隔断结构远离所述基底一侧的表面高于所述焊盘托远离所述基底一侧的表面。
在示例性实施例中，所述遮光材料层围绕所述发光芯片的四周设置。
在示例性实施例中，所述遮光材料层在所述基底上的正投影与所述发光芯片在所述基底上的正投影没有重叠区域。
在示例性实施例中，还包括封装层，所述封装层覆盖所述发光芯片，所述遮光材料层远离所述基底一侧的表面高于所述封装层远离所述基底一侧的表面。
在示例性实施例中，所述固晶结构包括焊盘托、设置在所述焊盘托远离所述基底一侧的第二绝缘层以及设置在所述第二绝缘层远离所述基底一侧的焊盘，所述发光芯片设置在所述焊盘上，所述焊盘包括相互断开的第一焊盘电极和第二焊盘电极，所述发光基板还包括连接电极、第一引线以及第一绝缘层，所述连接电极位于所述第一焊盘电极靠近所述基底一侧，所述连接电极在所述基底的正投影与所述第一焊盘电极在所述基底的正投影具有交叠区域，所述第一引线与所述连接电极的至少一侧连接，所述第一绝缘层位于所述连接电极与所述第一焊盘电极之间，所述第一绝缘层中设置有第一开孔，所述第一开孔将所述连接电极暴露，所述第一焊盘电极通过所述第一开孔与所述连接电极连接。
在示例性实施例中，所述第一引线与所述连接电极采用相同的材料一体成型。
在示例性实施例中，所述发光基板还包括遮光层，所述遮光层位于所述连接电极靠近所述基底一侧，至少部分所述遮光层在所述基底的正投影与所述连接电极在所述基底的正投影具有交叠区域。
在示例性实施例中，还包括第二引线，所述第二引线与所述第二焊盘电极的至少一侧连接，且所述第二引线与所述第二焊盘电极采用相同的材料一体成型。
在示例性实施例中，所述隔断结构在平行于所述基底方向的截面呈C形，所述第二引线位于所述隔断结构远离所述基底一侧，且所述第二引线在所述基底的正投影与所述隔断结构在所述基底的正投影不交叠。
在示例性实施例中，所述固晶结构包括焊盘托、设置在所述焊盘托远离所述基底一侧的第二绝缘层以及设置在所述第二绝缘层远离所述基底一侧的焊盘，所述发光芯片设置在所述焊盘上，所述焊盘包括相互断开的第一焊盘电极和第二焊盘电极，所述发光基板还包括相互断开的第一连接电极、第一引线、第二连接电极、第二引线以及第一绝缘层，所述第一连接电极位于所述第一焊盘电极靠近所述基底一侧，所述第一连接电极在所述基底的正投影与所述第一焊盘电极在所述基底的正投影具有交叠区域，所述第一引线与所述第一连接电极的至少一侧连接；所述第二连接电极位于所述第二焊盘电极靠近所述基底一侧，所述第二连接电极在所述基底的正投影与所述第二焊盘电极在所述基底的正投影具有交叠区域，所述第二引线与所述第二连接电极的至少一侧连接；所述第一绝缘层位于所述第一连接电极与所述第一焊盘电极之间，以及所述第一绝缘层位于所述第二连接电极与所述第二焊盘电极之间，所述第一绝缘层中设置有第一开孔，所述第一开孔将所述第一连接电极和所述第二连接电极暴露，所述第一焊盘电极通过所述第一开孔与所述第一连接电极连接，所述第二焊盘电极通过所述第一开孔与所述第二连接电极连接。
在示例性实施例中，所述发光基板还包括遮光层，所述遮光层位于所述第一连接电极靠近所述基底一侧，以及所述遮光层位于所述第二连接电极靠近所述基底一侧，至少部分所述遮光层在所述基底的正投影均与所述第一连接电极在所述基底的正投影和所述第二连接电极在所述基底的正投影具有交叠区域。
在示例性实施例中，所述发光芯片包括至少一个微发光二极管。
第二方面，本公开实施例还提供了一种发光基板的制备方法，包括：
在基底上形成固晶结构以及隔断结构；
在所述固晶结构上形成助焊功能层，将发光芯片与所述固晶结构焊接；所述助焊功能层在所述隔断槽处被阻断；
在所述隔断结构上形成遮光材料层；
其中，所述遮光材料层和所述隔断结构形成遮光结构，所述遮光结构位于所述发光芯片的周侧。
在示例性实施例中，在基底上形成固晶结构以及隔断结构包括：
在基底上形成牺牲层以及焊盘托；
在基底上形成覆盖牺牲层以及焊盘托的第二绝缘层，将所述第二绝缘层中形成第二开孔，所述第二开孔将至少部分所述牺牲层暴露；
通过所述第二开孔将所述牺牲层去除，将所述牺牲层上的第二绝缘层保留；所述牺牲层上的第二绝缘层形成所述隔断结构。
在示例性实施例中，通过半色调掩膜工艺，在基底上同时形成牺牲层以及焊盘托。
第三方面，本公开实施例还提供了一种显示装置，包括前述的发光基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
图1为本公开实施例发光基板的结构示意图一；
图2为本公开实施例发光基板的结构示意图二；
图3为本公开实施例发光基板形成第一导电层图案以及遮光层图案后的示意图一；
图4为本公开实施例发光基板形成第一导电层图案以及遮光层图案后的剖视图一；
图5为本公开实施例发光基板形成焊盘托图案以及牺牲层图案后的示意图；
图6为本公开实施例发光基板形成焊盘托图案以及牺牲层图案后的剖视图一；
图7为本公开实施例发光基板形成焊盘图案后的示意图；
图8为本公开实施例发光基板形成焊盘图案后的剖视图一；
图9为本公开实施例发光基板转移发光芯片后的示意图；
图10为本公开实施例发光基板转移发光芯片后的剖视图；
图11为本公开实施例发光基板形成封装层图案后的剖视图；
图12为本公开实施例发光基板去除牺牲层图案后的剖视图；
图13为本公开实施例发光基板形成第一导电层图案以及遮光层图案后的示意图二；
图14为本公开实施例发光基板形成第一导电层图案以及遮光层图案后的剖视图二；
图15为本公开实施例发光基板形成焊盘托图案以及牺牲层图案后的剖视图二；
图16为本公开实施例发光基板形成焊盘图案后的剖视图二。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
目前，LED发光基板通常是通过将LED芯片用微缩制程技术进行微缩化、阵列化、薄膜化，通过巨量转移技术将LED芯片批量转移到驱动背板上。LED发光基板通常包括驱动背板以及设置在驱动背板上的多个LED发光芯片。经本公开申请人研究发现，由于LED发光芯片形貌与设计有偏差，容易导致LED发光芯片侧出光明显以及转移用的牺牲层残留导致的侧出光辐射路径发光区面积变大，使LED发光基板较易出现背面漏光现象。相关技术的LED发光基板中，由于受到驱动背板遮光区和高度不匹配以及LED边缘脏污等影响，LED发光基板的遮光性能较差。
经过本公开申请人发现，LED芯片一般采用流平助焊层或助焊剂与焊盘焊接。在LED芯片与焊盘焊接过程中，流平助焊层或助焊剂的沉积范围不易控制，容易沉积至LED芯片的固晶区域以外，而流平助焊层或助焊剂和位于其下方(靠近基底方向)的膜层之间存 在折射率差异，LED芯片出射的光线被多次折射后从基底背离LED芯片一侧出射，导致发光芯片11侧部漏光，该流平助焊层或助焊剂残留的面积越大，漏光范围也越大。但是，如果通过灰化方式很难将流平助焊层或助焊剂限定在小范围内，并且过度灰化会导致LED芯片脱落和损伤。
图1为本公开实施例发光基板的结构示意图一。如图1所示，本公开实施例提供了一种发光基板，包括基底1，设置于基底上1的固晶结构、遮光结构以及发光芯片11，发光芯片11设置在固晶结构远离基底1一侧，遮光结构位于发光芯片11的周侧，发光基板还包括覆盖固晶结构远离基底1一侧的助焊功能层，遮光结构包括遮光材料层14以及隔断结构13，助焊功能层在隔断结构13处被阻断。
本公开实施例通过遮光结构中的隔断结构13将助焊功能层阻断，通过隔断结构13限制助焊功能层的范围，避免助焊功能层流动至发光芯片11固晶区域以外的区域，从而解决助焊功能层导致发光芯片11侧部漏光的问题。
在示例性实施例中，至少部分遮光材料层14覆盖隔断结构13，即至少部分遮光材料层14在基底1的正投影与隔断结构13在基底1的正投影具有交叠区域，从而减少遮光结构在平行于基底1方向所占的面积，节省空间。
在示例性实施例中，隔断结构13在基底1上的正投影位于遮光材料层14在基底上的正投影中，即遮光材料层14覆盖整个隔断结构13，且遮光材料层14将隔断结构13中的隔断槽全部填充。
在示例性实施例中，发光芯片11可以为微发光二极管发光芯片或者次毫米发光二极管发光芯片。每个微发光二极管发光芯片可以包括多个串联的微发光二极管(Micro LED)，每个微发光二极管的典型尺寸(例如长度)可以小于50μm，例如10μm至50μm。每个次毫米发光二极管发光芯片可以包括多个串联的次毫米发光二极管(Mini LED)，每个次毫米发光二极管的典型尺寸(例如长度)可以约为50μm至150μm，例如80μm至120μm。
在示例性实施例中发光芯片11的形状可以根据需要设置。例如，发光芯片11在平行于基底方向的轮廓可以为矩形，这样更加容易实现背光源的分区控制。
在示例性实施例中，基底1上发光芯片11的数量和排列方式以及发光芯片11内多个发光二极管的数量和排列方式等，可以根据实际情况来设置，本公开在此不做限定。
在示例性实施例中，隔断结构13包括设置在基底1上的第一侧边131和第二侧边132， 第一侧边131位于第二侧边132远离发光芯片11一侧。第一侧边131与第二侧边132之间形成隔断槽，遮光材料层填充至少部分隔断槽，从而使隔断槽中的遮光材料层能够遮挡发光芯片11侧部发出的光线，避免发光芯片11侧部发出的光线透过隔断结构13导致漏光的情况发生。
在示例性实施例中，固晶结构包括焊盘托6、设置在焊盘托6远离基底1一侧的第二绝缘层8以及设置在第二绝缘层8远离基底1一侧的焊盘9，发光芯片11焊接在焊盘9上。焊盘托6用于支撑焊盘9以及发光芯片11。焊盘9采用导电材料，例如金属，焊盘9用于与发光芯片11电连接，将发光信号传递给发光芯片11。第二绝缘层8用于将焊盘托6与焊盘9隔离。
在示例性实施例中，隔断结构13的第一侧边131和/或第二侧边132与第二绝缘层8采用相同的材料一体成型，即隔断结构13的第一侧边131和/或第二侧边132与第二绝缘层8采用相同的材料通过同一制备工艺制备而成。例如，第一侧边131和第二侧边132均与第二绝缘层8采用相同的材料一体成型。简化了制备工艺，降低了生产成本。
在示例性实施例中，隔断结构13远离基底1一侧的表面高于焊盘托6远离基底1一侧的表面，即在基底1的厚度方向，隔断结构13的高度大于焊盘托6的高度。使隔断结构13能够有效阻断助焊功能层溢出。
在示例性实施例中，焊盘托6在垂直于基底1方向的截面可以采用多种形状。例如，焊盘托6在垂直于基底1方向的截面可以为梯形、矩形等。
在示例性实施例中，遮光材料层14可以为环状，例如，矩形环状。遮光材料层14围绕发光芯片11的四周设置，使遮光材料层14能够将发光芯片11侧部发出的光线全部遮挡，避免发光芯片11侧部漏光。
在示例性实施例中，遮光材料层14在基底1上的正投影与发光芯片11在基底1上的正投影没有重叠区域，避免遮光材料层14在垂直于基底1方向遮挡发光芯片11，影响发光芯片11的发光效率。
在示例性实施例中，本公开发光基板还包括封装层12，封装层12覆盖发光芯片11，即封装层12位于发光芯片11远离基底1一侧，且封装层12在基底1的正投影与发光芯片11在基底1的正投影交叠。封装层12用于保护发光芯片11。
在示例性实施例中，遮光材料层14远离基底1一侧的表面高于封装层12远离基底1 一侧的表面，使遮光材料层14具有更好的遮光效果。
在示例性实施例中，如图1所示，焊盘9包括相互断开的第一焊盘电极901和第二焊盘电极902，发光基板还包括连接电极3、第一引线以及第一绝缘层5，连接电极3位于第一焊盘电极901靠近基底1一侧，且连接电极3在基底1的正投影与第一焊盘电极901在基底1的正投影具有交叠区域。第一引线与连接电极3的至少一侧连接，例如，第一引线与连接电极3远离发光芯片11一侧连接，且第一引线沿着远离发光芯片11方向延伸。第一绝缘层5位于连接电极3与第一焊盘电极901之间，第一绝缘层5中设置有第一开孔，第一开孔将连接电极3暴露，第一焊盘电极901通过第一开孔与连接电极3连接。
在示例性实施例中，第一引线与连接电极3可以采用相同的材料一体成型，即第一引线可以与连接电极3采用相同的材料通过同一制备工艺制备而成，简化了制备工艺，降低了生产成本。
在示例性实施例中，发光基板还包括遮光层2，遮光层2位于连接电极3靠近基底1一侧，至少部分遮光层2在基底1的正投影与连接电极3在基底1的正投影具有交叠区域。遮光层2用于遮挡连接电极3的反光。遮光层2可以为黑矩阵(BM)。
在示例性实施例中，发光基板还包括第二引线10，第二引线10与第二焊盘电极902的至少一侧连接，且第二引线10与第二焊盘电极902采用相同的材料一体成型，即第二引线10可以与第二焊盘电极902采用相同的材料通过同一制备工艺制备而成，简化了制备工艺，降低了生产成本。
在示例性实施例中，隔断结构13在平行于基底1方向的截面呈C形，第二引线10位于隔断结构13远离基底1一侧，且第二引线10在基底1的正投影与隔断结构13在基底1的正投影不交叠。
图2为本公开实施例发光基板的结构示意图二。在示例性实施例中，如图2所示，固晶结构包括焊盘托6、设置在焊盘托6远离基底1一侧的第二绝缘层8以及设置在第二绝缘层8远离基底1一侧的焊盘9。发光芯片11设置在所述焊盘9上。焊盘9包括相互断开的第一焊盘电极901和第二焊盘电极902。发光基板还包括相互断开的第一连接电极3a、第一引线、第二连接电极3b、第二引线以及第一绝缘层5。第一连接电极3a位于第一焊盘电极901靠近基底1一侧，第一连接电极3a在基底的正投影与第一焊盘电极901在基底的正投影具有交叠区域；第一引线与第一连接电极3a的至少一侧连接，例如，第一引 线与第一连接电极3a远离第二连接电极3b一侧连接，且第一引线沿着远离第二连接电极3b方向延伸。第二连接电极3b位于第二焊盘电极902靠近基底1一侧，第二连接电极3b在基底的正投影与第二焊盘电极901在基底的正投影具有交叠区域。第二引线与第二连接电极3b的至少一侧连接，例如，第二引线与与第二连接电极3b远离第一连接电极3a一侧连接，且第二引线沿着远离第一连接电极3a方向延伸。第一绝缘层5位于第一连接电极3a和第一焊盘电极901之间，以及第一绝缘层5位于第二连接电极3b和第二焊盘电极902之间。且第一绝缘层5在基底1的正投影均与第一连接电极3a在基底1的正投影和第二连接电极3b在基底1的正投影均有交叠区域。第一绝缘层5中设置有第一开孔，第一开孔将第一连接电极3a和第二连接电极3b暴露，第一焊盘电极901通过第一开孔与第一连接电极3a连接，第二焊盘电极902通过第一开孔与第二连接电极3b连接。
在示例性实施例中，第一连接电极3a和第二连接电极3b可以采用相同的材料通过同一制备工艺制备而成。简化了制备工艺，降低了生产成本。
在示例性实施例中，如图2所示，发光基板还包括遮光层2，遮光层2位于第一连接电极靠近基底一侧，以及遮光层2位于第二连接电极靠近所述基底一侧，至少部分所述遮光层在所述基底的正投影均与所述第一连接电极在所述基底的正投影和所述第二连接电极在所述基底的正投影具有交叠区域。
本公开实施例还提供了一种显示装置，包括前面任一所述的发光基板。本公开实施例显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种发光基板的制备方法，包括：
在基底上形成固晶结构以及隔断结构；
在所述固晶结构上形成助焊功能层，将发光芯片与所述固晶结构焊接；所述助焊功能层在所述隔断槽处被阻断；
在所述隔断结构上形成遮光材料层；
其中，所述遮光材料层和所述隔断结构形成遮光结构，所述遮光结构位于所述发光芯片的周侧。
在示例性实施例中，在基底上形成固晶结构以及隔断结构包括：
在基底上形成牺牲层以及焊盘托；
在基底上形成覆盖牺牲层以及焊盘托的第二绝缘层，将所述第二绝缘层中形成第二开孔，所述第二开孔将至少部分所述牺牲层暴露；
通过所述第二开孔将所述牺牲层去除，将所述牺牲层上的第二绝缘层保留；所述牺牲层上的第二绝缘层形成所述隔断结构。
在示例性实施例中，通过半色调掩膜工艺，在基底上同时形成牺牲层以及焊盘托
下面通过发光基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于驱动背板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
图3至图16为本公开实施例发光基板制备过程的示意图。本公开实施例发光基板的制备方法，具体包括：
(1)形成第一导电层图案以及遮光层图案。在示例性实施方式中，形成第一导电层图案以及遮光层图案可以包括：在基底1上依次沉积遮光薄膜、第一导电薄膜以及第一绝缘薄膜，通过图案化工艺依次对遮光薄膜、第一导电薄膜以及第一绝缘薄膜进行图案化，形成设置在基底1上的遮光层2，设置在遮光层2上的第一导电层图案，以及设置在第一导电层图案上的第一绝缘层5。第一导电层图案至少包括连接电极3以及第一引线4，第一绝缘层5中开设有第一开孔501。第一开孔501可以为环状，将连接电极3的表面暴露，如图3和图4所示，图4为图3中A-A向的剖视图。
在示例性实施方式中，遮光层2在基底1的正投影与连接电极3在基底1的正投影具 有交叠区域，遮光层2用于遮挡连接电极3的反光。遮光层2可以为黑矩阵(BM)。
在示例性实施方式中，第一引线4与连接电极3的至少一侧连接，第一引线4远离连接电极3的一端可以与驱动电路连接，用于将发光信号通过连接电极3传递给发光芯片。
在示例性实施方式中，第一导电薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)、铬(Cr)和钨(W)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，可以是单层结构，或者是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
在示例性实施方式中，第一绝缘层5为无机绝缘层，可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，第一绝缘层称为钝化(PVX)层。
在示例性实施例中，基底可以采用硬质基底或柔性基底，硬质基底可以是玻璃等，柔性基底可以是聚酰亚胺(PI)等。
(2)形成焊盘托图案以及牺牲层图案。在示例性实施方式中，形成焊盘托图案以及牺牲层图案可以包括：在形成前述图案的基底1上，先在第一绝缘层5上沉积第一材料薄膜，通过涂胶和光刻工艺，将第一材料薄膜形成焊盘托6。然后在第一绝缘层5上沉积第二材料薄膜，通过涂胶和光刻工艺，将第二材料薄膜形成牺牲层7，牺牲层7位于焊盘托6靠近基底1边缘一侧。牺牲层7的底部通过第一开孔501延伸至连接电极3的表面。然后在第一绝缘层5上沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行图案化，使第二绝缘薄膜形成覆盖焊盘托6和牺牲层7第二绝缘层8。第二绝缘层8中设置有第二开孔801以及第三开孔802。第二开孔801在基底1上的正投影与部分牺牲层7在基底1上的正投影交叠，即第二开孔801将部分牺牲层7的表面暴露。第三开孔802与第一开孔501连通，第三开孔802将连接电极3暴露。第三开孔802在基底1上的正投影均与焊盘托6和牺牲层7在基底1上的正投影不交叠，如图5和图6所示，图6为图5中A-A向的剖视图。
在一些实施例中，焊盘托6和牺牲层7可以采用相同的材料，通过半色调掩膜工艺同时制备，简化工艺，降低制备成本。
在示例性实施例中，牺牲层7可以为环状。牺牲层7围绕焊盘托6的四周设置，即牺 牲层7围绕第一托座601和第二托座602的四周设置。其中，牺牲层7可以采用有机材料。例如，树脂。
在示例性实施例中，牺牲层7远离基底1一侧的表面到基底1表面的距离大于焊盘托6远离基底1一侧的表面到基底1表面的距离，即在基底1的厚度方向，牺牲层7的高度大于焊盘托6的高度。牺牲层7具有限制封装层材料流动作用，以及阻断助焊功能层溢出的作用。
在示例性实施例中，焊盘托6包括相互断开第一托座601和第二托座602。第一托座601和第二托座602可以采用多种形状。例如，在平行于基底1方向，第一托座601和第二托座602的截面均为矩形。焊盘托6用于支撑焊盘和发光单元。其中，焊盘托6可以采用有机材料。例如，树脂。
在示例性实施例中，第二绝缘层8为无机绝缘层，可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施例中，在平行于基底1方向，第二开孔801呈C状，环状的牺牲层7一部分没有被第二开孔801暴露，该覆盖牺牲层7的第二绝缘层8上可以设置第二引线10，用于将第二引线10引出。
(3)形成焊盘图案。在示例性实施方式中，形成焊盘图案可以包括：在形成前述图案的基底1上，在第二绝缘层8上沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，使第二导电薄膜形成焊盘9以及第二引线10。焊盘9包括相互断开的第一焊盘电极901和第二焊盘电极902，第一焊盘电极901覆盖第一托座601以及第三开孔802，第一焊盘电极901通过第三开孔802延伸至连接电极3的表面，与连接电极3连接，使第一引线4可以将发光信号通过连接电极3引导至第一焊盘电极901。第二焊盘电极902覆盖第二托座602，第二焊盘电极902远离第一焊盘电极901的一侧与第二引线10连接。第二引线10覆盖一部分牺牲层7，第二引线10由第二焊盘电极902沿着远离第一焊盘电极901的方向延伸，并越过一部分牺牲层7，且第二引线10在基底1的正投影与第二开孔801在基底1的正投影不交叠。第二引线10远离第二焊盘电极902的一端可以与驱动电路连接，用于将发光信号引导至第二焊盘电极902，如图7和图8所示，图8为图7中A-A向的剖视图。
在示例性实施例中，第二导电薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝 (Al)、钛(Ti)、钼(Mo)、铬(Cr)和钨(W)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，可以是单层结构，或者是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
(4)转移发光芯片。在示例性实施方式中，转移发光芯片可以包括：在形成前述图案的基底1上，转移发光芯片11，并对发光芯片11进行固晶、焊接，使发光芯片11焊接在焊盘9上。具体地，发光芯片11包括第一电极和第二电极，将发光芯片11的第一电极与第一焊盘电极901连接，将发光芯片11的第二电极与第二焊盘电极902连接，如图9和图10所示，图10为图9中A-A向的剖视图。
在示例性实施例中，发光芯片11与焊盘9焊接过程中，先在焊盘9上沉积助焊功能层12，再将发光芯片11与焊盘9焊接。助焊功能层12可以采用流平助焊层或助焊剂。
本实施例中以助焊功能层和封装层为同一材料进行示意，所以图10中助焊功能层和图11中的封装层均以同一标号12示意，二者材料也可以不同，不作限定。
(5)形成封装层图案。在示例性实施方式中，形成封装层图案可以包括：在形成前述图案的基底1上，通过喷墨打印工艺，在第二绝缘层8上沉积封装薄膜，通过图案化工艺对封装薄膜进行图案化，使封装薄膜形成覆盖发光芯片11的封装层12，如图11所示。其中，封装层12完全包覆发光芯片11的尖锐部分，且封装层12的折射率与发光芯片11的折射率匹配。
(6)去除牺牲层图案。在示例性实施方式中，去除牺牲层图案可以包括：在形成前述图案的基底1上，通过第二开孔801，将牺牲层刻蚀去除，将牺牲层上的第二绝缘层8保留。牺牲层去除后，牺牲层上的第二绝缘层8形成隔断结构13，如图12所示。在牺牲层刻蚀去除后，牺牲层上的助焊功能层12会跟随牺牲层脱落，使助焊功能层12在隔断结构13处被阻断，从而解决助焊功能层12导致发光芯片11侧部漏光的问题。
在示例性实施例中，隔断结构13远离基底1一侧的表面到基底1的距离大于封装层12远离基底1一侧的表面，即隔断结构13远离基底1一侧的表面高于封装层12远离基底1一侧的表面。
在示例性实施例中，隔断结构13包括相对设置的第一侧边131以及第二侧边132，第二开孔801位于第一侧边131的顶部与第二侧边132的顶部之间，第一侧边131与第二 侧边132之间形成隔断槽，如图12所示。
(7)形成遮光材料层图案。在示例性实施方式中，形成遮光材料层图案可以包括：在形成前述图案的基底1上，在封装层12的外侧沉积遮光材料，遮光材料覆盖隔断结构13，且至少部分遮光材料填充隔断结构13中的隔断槽内，通过图案化工艺对遮光材料进行图案化，使遮光材料形成遮光材料层14，如图1所示。其中，遮光材料层14可以使用常温或低温黑矩阵制备。
在示例性实施例中，遮光材料层14可以为环状，遮光材料层14可以围绕发光芯片11的四周设置。遮光材料层14用于遮挡发光芯片11侧部发出的光线，防止发光芯片11侧部漏光。
在示例性实施例中，如图1所示，遮光材料层14的底部延伸至隔断结构13中的隔断槽内，并通过第一绝缘层5中的第一开孔501延伸至连接电极3的表面，避免发光芯片11侧部发出的光线通过第一绝缘层5射出，避免发光芯片11侧部漏光。
在示例性实施例中，遮光材料层14远离基底1一侧的表面到基底1的表面之间的距离大于封装层12远离基底1一侧的表面到基底1的表面之间的距离，即在基底1的厚度方向，遮光材料层14的高度大于封装层12的高度，以提高遮光材料层14的遮光效率。
在示例性实施例中，本公开实施例还提供了一种发光基板的制备方法，该发光基板的制备方法包括：
(1)形成第一导电层图案以及遮光层图案。在示例性实施方式中，形成第一导电层图案以及遮光层图案可以包括：在基底1上依次沉积遮光薄膜、第一导电薄膜以及第一绝缘薄膜，通过图案化工艺依次对遮光薄膜、第一导电薄膜以及第一绝缘薄膜进行图案化，形成设置在基底1上的遮光层2，设置在遮光层2上的第一导电层图案，以及设置在第一导电层图案上的第一绝缘层5。第一导电层图案至少包括第一连接电极3a、第二连接电极3b、第一引线4以及第二引线10。第一连接电极3a与第二连接电极3b互相断开。第一引线4与第一连接电极3a连接，位于第一连接电极3a远离第二连接电极3b一侧。第二引线10与第二连接电极3b连接，位于第二连接电极3b远离第一连接电极3a一侧。第一绝缘层5中开设有第一开孔501。第一开孔501可以为环状，将第一连接电极3a与第二连接电极3b的表面暴露，如图13和图14所示，图14为图13中A-A向的剖视图。
(2)形成焊盘托图案以及牺牲层图案。在示例性实施方式中，形成焊盘托图案以及 牺牲层图案可以包括：在形成前述图案的基底1上，先在第一绝缘层5上沉积第一材料薄膜，通过涂胶和光刻工艺，将第一材料薄膜形成焊盘托6。然后在第一绝缘层5上沉积第二材料薄膜，通过涂胶和光刻工艺，将第二材料薄膜形成牺牲层7，牺牲层7位于焊盘托6靠近基底1边缘一侧。牺牲层7的底部通过第一开孔501延伸至连接电极3的表面。然后在第一绝缘层5上沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行图案化，使第二绝缘薄膜形成覆盖焊盘托6和牺牲层7的第二绝缘层8。第二绝缘层8中设置有第二开孔801、第三开孔a803以及第三开孔b804。第二开孔801在基底1上的正投影与部分牺牲层7在基底1上的正投影交叠，即第二开孔801将部分牺牲层7的表面暴露。第三开孔a803和第三开孔b804均与第一开孔501连通。第三开孔a803在基底1上的正投影均与第一连接电极3a在基底1上的正投影交叠，第三开孔a803将第一连接电极3a的表面暴露；第三开孔b804在基底1上的正投影均与第二连接电极3b在基底1上的正投影交叠，第三开孔b804将第二连接电极3b的表面暴露，如图15所示。
(3)形成焊盘图案。在示例性实施方式中，形成焊盘图案可以包括：在形成前述图案的基底1上，在第二绝缘层8上沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，使第二导电薄膜形成焊盘9。焊盘9包括相互断开的第一焊盘电极901和第二焊盘电极902，第一焊盘电极901覆盖第一托座601以及第三开孔a803，第一焊盘电极901通过第三开孔a803延伸至第一连接电极3a的表面，与第一连接电极3a连接，使第一引线4能过将发光信号通过第一连接电极3a引导至第一焊盘电极901。第二焊盘电极902覆盖第二托座602以及第三开孔b804，第二焊盘电极902通过第三开孔b804延伸至第二连接电极3b的表面，与第二连接电极3b连接，使第二引线10能过将发光信号通过第二连接电极3b引导至第二焊盘电极902，如图16所示。
本公开实施例发光基板的制备方法后面的制备过程与前述实施例发光基板的制备方法的制备过程相同，本公开实施例在此不再赘述。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种发光基板，包括基底，设置于所述基底上的固晶结构、遮光结构以及发光芯片，所述发光芯片设置在所述固晶结构远离所述基底一侧，所述遮光结构位于所述发光芯片的周侧，所述发光基板还包括覆盖所述固晶结构远离所述基底一侧的的助焊功能层，所述遮光结构包括遮光材料层以及隔断结构，所述助焊功能层在所述隔断结构处被阻断。
  2. 根据权利要求1所述的发光基板，其中，至少部分所述遮光材料层覆盖所述隔断结构。
  3. 根据权利要求2所述的发光基板，其中，所述隔断结构包括设置在基底上的第一侧边和第二侧边，所述第一侧边与所述第二侧边之间形成隔断槽，所述遮光材料层填充至少部分所述隔断槽。
  4. 根据权利要求3所述的发光基板，其中，所述固晶结构包括焊盘托、设置在所述焊盘托远离所述基底一侧的第二绝缘层以及设置在所述第二绝缘层远离所述基底一侧的焊盘，所述发光芯片设置在所述焊盘上，所述第一侧边和/或所述第二侧边与所述第二绝缘层采用相同的材料一体成型。
  5. 根据权利要求1至4任一所述的发光基板，其中，所述隔断结构远离所述基底一侧的表面高于所述焊盘托远离所述基底一侧的表面。
  6. 根据权利要求1至4任一所述的发光基板，其中，所述遮光材料层围绕所述发光芯片的四周设置。
  7. 根据权利要求1至4任一所述的发光基板，其中，所述遮光材料层在所述基底上的正投影与所述发光芯片在所述基底上的正投影没有重叠区域。
  8. 根据权利要求1至4任一所述的发光基板，还包括封装层，所述封装层覆盖所述发光芯片，所述遮光材料层远离所述基底一侧的表面高于所述封装层远离所述基底一侧的表面。
  9. 根据权利要求1至4任一所述的发光基板，其中，所述固晶结构包括焊盘托、设置在所述焊盘托远离所述基底一侧的第二绝缘层以及设置在所述第二绝缘层远离所述基底一侧的焊盘，所述发光芯片设置在所述焊盘上，所述焊盘包括相互断开的第一焊盘电极和第二焊盘电极，所述发光基板还包括连接电极、第一引线以及第一绝缘层，所述连接电 极位于所述第一焊盘电极靠近所述基底一侧，所述连接电极在所述基底的正投影与所述第一焊盘电极在所述基底的正投影具有交叠区域，所述第一引线与所述连接电极的至少一侧连接，所述第一绝缘层位于所述连接电极与所述第一焊盘电极之间，所述第一绝缘层中设置有第一开孔，所述第一开孔将所述连接电极暴露，所述第一焊盘电极通过所述第一开孔与所述连接电极连接。
  10. 根据权利要求9所述的发光基板，其中，所述第一引线与所述连接电极采用相同的材料一体成型。
  11. 根据权利要求9所述的发光基板，其中，所述发光基板还包括遮光层，所述遮光层位于所述连接电极靠近所述基底一侧，至少部分所述遮光层在所述基底的正投影与所述连接电极在所述基底的正投影具有交叠区域。
  12. 根据权利要求9所述的发光基板，还包括第二引线，所述第二引线与所述第二焊盘电极的至少一侧连接，且所述第二引线与所述第二焊盘电极采用相同的材料一体成型。
  13. 根据权利要求12所述的发光基板，其中，所述隔断结构在平行于所述基底方向的截面呈C形，所述第二引线位于所述隔断结构远离所述基底一侧，且所述第二引线在所述基底的正投影与所述隔断结构在所述基底的正投影不交叠。
  14. 根据权利要求1至4任一所述的发光基板，其中，所述固晶结构包括焊盘托、设置在所述焊盘托远离所述基底一侧的第二绝缘层以及设置在所述第二绝缘层远离所述基底一侧的焊盘，所述发光芯片设置在所述焊盘上，所述焊盘包括相互断开的第一焊盘电极和第二焊盘电极，所述发光基板还包括相互断开的第一连接电极、第一引线、第二连接电极、第二引线以及第一绝缘层，所述第一连接电极位于所述第一焊盘电极靠近所述基底一侧，所述第一连接电极在所述基底的正投影与所述第一焊盘电极在所述基底的正投影具有交叠区域，所述第一引线与所述第一连接电极的至少一侧连接；所述第二连接电极位于所述第二焊盘电极靠近所述基底一侧，所述第二连接电极在所述基底的正投影与所述第二焊盘电极在所述基底的正投影具有交叠区域，所述第二引线与所述第二连接电极的至少一侧连接；所述第一绝缘层位于所述第一连接电极与所述第一焊盘电极之间，以及所述第一绝缘层位于所述第二连接电极与所述第二焊盘电极之间，所述第一绝缘层中设置有第一开孔，所述第一开孔将所述第一连接电极和所述第二连接电极暴露，所述第一焊盘电极通过所述第一开孔与所述第一连接电极连接，所述第二焊盘电极通过所述第一开孔与所述第二连接 电极连接。
  15. 根据权利要求14所述的发光基板，其中，所述发光基板还包括遮光层，所述遮光层位于所述第一连接电极靠近所述基底一侧，以及所述遮光层位于所述第二连接电极靠近所述基底一侧，至少部分所述遮光层在所述基底的正投影均与所述第一连接电极在所述基底的正投影和所述第二连接电极在所述基底的正投影具有交叠区域。
  16. 根据权利要求1至4任一所述的发光基板，其中，所述发光芯片包括至少一个微发光二极管。
  17. 一种发光基板的制备方法，包括：
    在基底上形成固晶结构以及隔断结构；
    在所述固晶结构上形成助焊功能层，将发光芯片与所述固晶结构焊接；所述助焊功能层在所述隔断槽处被阻断；
    在所述隔断结构上形成遮光材料层；
    其中，所述遮光材料层和所述隔断结构形成遮光结构，所述遮光结构位于所述发光芯片的周侧。
  18. 根据权利要求17所述的发光基板的制备方法，其中，在基底上形成固晶结构以及隔断结构包括：
    在基底上形成牺牲层以及焊盘托；
    在基底上形成覆盖牺牲层以及焊盘托的第二绝缘层，将所述第二绝缘层中形成第二开孔，所述第二开孔将至少部分所述牺牲层暴露；
    通过所述第二开孔将所述牺牲层去除，将所述牺牲层上的第二绝缘层保留；所述牺牲层上的第二绝缘层形成所述隔断结构。
  19. 根据权利要求18所述的发光基板的制备方法，其中，通过半色调掩膜工艺，在基底上同时形成牺牲层以及焊盘托。
  20. 一种显示装置，包括权利要求1至16任一所述的发光基板。
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CN110176463A (zh) * 2019-05-24 2019-08-27 深圳市华星光电技术有限公司 基板及制备方法
CN209896060U (zh) * 2019-05-23 2020-01-03 弘凯光电(深圳)有限公司 一种发光二极管封装结构
CN112599552A (zh) * 2020-12-14 2021-04-02 苏州芯聚半导体有限公司 微发光二极管显示面板及制备方法
CN112687748A (zh) * 2020-12-29 2021-04-20 佛山市国星光电股份有限公司 一种背光模块及其制作方法

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CN209896060U (zh) * 2019-05-23 2020-01-03 弘凯光电(深圳)有限公司 一种发光二极管封装结构
CN110176463A (zh) * 2019-05-24 2019-08-27 深圳市华星光电技术有限公司 基板及制备方法
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