WO2023092935A1 - 显示装置、显示面板及其制造方法 - Google Patents

显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2023092935A1
WO2023092935A1 PCT/CN2022/088548 CN2022088548W WO2023092935A1 WO 2023092935 A1 WO2023092935 A1 WO 2023092935A1 CN 2022088548 W CN2022088548 W CN 2022088548W WO 2023092935 A1 WO2023092935 A1 WO 2023092935A1
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Prior art keywords
layer
electrode
display panel
cut
groove
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PCT/CN2022/088548
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English (en)
French (fr)
Inventor
杨盛际
陈小川
董学
王辉
张大成
黄冠达
卢鹏程
焦志强
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/257,593 priority Critical patent/US20240040845A1/en
Priority to CN202280000913.6A priority patent/CN116548091A/zh
Priority to PCT/CN2022/096228 priority patent/WO2023092978A1/zh
Priority to GB2318338.7A priority patent/GB2621786A/en
Priority to US18/026,365 priority patent/US20240099066A1/en
Priority to CN202280001575.8A priority patent/CN116548084A/zh
Publication of WO2023092935A1 publication Critical patent/WO2023092935A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/32—Stacked devices having two or more layers, each emitting at different wavelengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a method for manufacturing the display panel.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the disclosure provides a display device, a display panel and a manufacturing method of the display panel.
  • a display panel comprising:
  • the first electrode layer is arranged on one side of the drive backplane and includes a plurality of first electrodes distributed at intervals;
  • the pixel definition layer is arranged on the same side of the driving backplane as the first electrode layer, and exposes each of the first electrodes;
  • the pixel definition layer includes a filling layer stacked in a direction away from the driving backplane and a cut-off layer, the thickness of the filling layer is smaller than that of the first electrode layer, and is located outside the first electrode;
  • the cut-off layer is provided with a separation groove located outside the first electrode, and the side of the separation groove
  • the wall is provided with a first cut-off groove;
  • the second electrode covers the light emitting layer.
  • the cut-off layer includes a plurality of insulating layers stacked in a direction away from the driving backplane, the separation groove exposes the filling layer; the first cut-off groove opens on an insulating layer, and the insulating layer where the first cut-off groove is located is any insulating layer other than the insulating layer farthest from the driving backplane.
  • the insulating layer of the cut-off layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence along a direction away from the driving backplane, and the first insulating layer A cut-off groove is opened in the second insulating layer.
  • the sidewall of the separation groove is a slope surface expanding in a direction away from the driving backplane.
  • the bottom surface of the first cut-off groove is a slope surface whose depth decreases along a direction away from the driving backplane.
  • the slope angle of the bottom surface of the first cut-off groove is greater than the slope angle of the sidewall of the separation groove located on the first insulating layer, and greater than the slope angle of the separation groove located on the side wall of the first insulating layer.
  • the slope angle of the sidewall of the third insulating layer is greater than the slope angle of the sidewall of the third insulating layer.
  • the sum of the slope angle of the bottom surface of the first cut-off groove and the slope angle of the sidewall of the separation groove located in the first insulating layer is not greater than 90°.
  • the sum of the slope angle of the bottom surface of the first cut-off groove and the slope angle of the sidewall of the separation groove located in the third insulating layer is not greater than 90°.
  • the included angle between the extension surfaces of the two side walls of the separation groove is an acute angle.
  • the cut-off layer includes a cut-off portion and an extension portion, the cut-off portion is located outside the first electrode, and the extension portion is located at the first electrode away from the driving back.
  • the surface of the board has a pixel opening exposing the first electrode; the side wall of the pixel opening is a slope extending away from the driving backplane.
  • the sum of the slope angle of the sidewall of the pixel opening and the slope angle of the bottom surface of the first cut-off groove is not less than 90°.
  • At least a part of sidewalls of the pixel openings are provided with second cut-off grooves.
  • the maximum depth of the first cutoff groove is greater than the maximum depth of the second cutoff groove.
  • the portion of the third insulating layer used to form the sidewall of the first cut-off groove is inclined toward the driving backplane, and the inclination angle is a first inclination angle
  • the portion of the third insulating layer used to form the sidewall of the second cut-off groove is inclined toward the driving backplane, and the inclination angle is a second inclination angle;
  • the first inclination angle is greater than the second inclination angle.
  • the second electrode forms a flat portion in a region corresponding to the first electrode, and forms a depression in a region corresponding to the separation groove, and the depression and The flat portion transitions smoothly.
  • the depth of the recessed portion is smaller than the depth of the separation groove.
  • the depth of the recessed portion is greater than the thickness of the filling layer.
  • the filling layer is in contact with the sidewall of the first electrode
  • the light-emitting layer further includes multiple light-emitting sublayers connected in series, at least one light-emitting sublayer is connected in series with an adjacent light-emitting sublayer through a charge generation layer; A portion of the charge generation layer corresponding to the first electrode is disconnected from a portion corresponding to the separation groove.
  • the filling layer includes a filling insulating layer and a filling conductive layer stacked in a direction away from the driving backplane, and the filling insulating layer is connected to the sidewall of the first electrode. contact, the filled conductive layer is spaced apart from the sidewall of the first electrode.
  • the driving backplane includes a pixel area and a peripheral area outside the pixel area; the pixel area has a pixel circuit for driving the light-emitting layer to emit light, and the peripheral area has a peripheral circuit;
  • the first electrode layer further includes a transfer ring, the orthographic projection of the transfer ring on the driving backplane is located in the peripheral area and surrounds the pixel area, and the transfer ring and the The peripheral circuit is connected, and the second electrode is connected to the adapter ring; the adapter ring is provided with a gap;
  • the filled conductive layer includes a main body and a connecting portion, the main body is located in the adapter ring and spaced apart from the adapter ring; the connecting portion is connected to the main body, and is connected by the gap passing through the adapter ring and spaced apart from the adapter ring; the connecting part is used for receiving the aging voltage signal.
  • the display panel is the above-mentioned display panel
  • the manufacturing method includes:
  • first electrode layer comprising a plurality of first electrodes distributed at intervals on one side of the drive backplane
  • a pixel definition layer exposing each of the first electrodes is formed on the side of the driving backplane provided with the first electrode layer;
  • the pixel definition layer includes a filling layer stacked in a direction away from the driving backplane and a blocking layer layer, the filling layer has a thickness smaller than the first electrode layer and is located outside the first electrode;
  • a second electrode covering the light emitting layer is formed.
  • a method of manufacturing a display panel including:
  • first electrode layer comprising a plurality of first electrodes distributed at intervals on one side of the drive backplane
  • a pixel definition layer exposing each of the first electrodes is formed on the side of the driving backplane on which the first electrode layer is formed;
  • the pixel definition layer includes a filling layer and a blocking layer stacked in a direction away from the driving backplane , the thickness of the filling layer is smaller than the first electrode layer, and is located outside the first electrode;
  • the cut-off layer is provided with a separation groove located outside the first electrode, and the side wall of the separation groove is provided with first cut-off slot;
  • a second electrode covering the light emitting layer is formed.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a partial cross-sectional view of an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a partial cross-sectional view of another embodiment of the display panel of the present disclosure.
  • FIG. 3 is a partial cross-sectional view of some film layers in an embodiment of the display panel of the present disclosure.
  • FIG. 4 is a partial cross-sectional view of some film layers in another embodiment of the display panel of the present disclosure.
  • FIG. 5 is a schematic diagram of a light emitting unit in an embodiment of the display panel of the present disclosure.
  • FIG. 6 is a partial top view of an embodiment of the display panel of the present disclosure.
  • FIG. 7 is a schematic diagram of a light emitting unit in an embodiment of the display panel of the present disclosure.
  • FIG. 8 is a partial cross-sectional view of an embodiment of the display panel of the present disclosure.
  • FIG. 9 is a schematic diagram of an adapter ring and a filled conductive layer in an embodiment of the display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • any “slope” in the present application is a straight line in the section perpendicular to the driving backplane, and the slope angle (for example, ⁇ 1, ⁇ 1, ⁇ , ⁇ , ⁇ in Fig. 3 ) of the "slope” can be defined as the Among the angles between the straight line or its extended line and the surface where the slope is located, the angle close to the first electrode surrounded by the slope is included.
  • the above-mentioned straight line may not be an absolute straight line, but may be a curve extending approximately along a straight line. There may be multiple tangents to the curve, and each tangent line is in line with the position of the slope.
  • the surface has included angles, and the slope angle of the curve can be the largest included angle among the included angles, or the average value of the included angles.
  • a silicon-based OLED display panel includes a driving backplane and a light-emitting functional layer, wherein: the light-emitting functional layer is arranged on one side of the driving backplane and includes a plurality of light-emitting units, and the light-emitting unit may include one or more light-emitting devices connected in series , the light-emitting device can be an organic light-emitting diode, which can include a first electrode (anode), a light-emitting layer, and a second electrode (cathode) stacked in sequence in a direction away from the driving backplane, and by applying an electric current to the first electrode and the second electrode
  • the signal can drive the light-emitting layer to emit light, and the specific light-emitting principle of the light-emitting device will not be described in detail here.
  • each light-emitting device can be directly evaporated and formed through a fine mask (FMM), and the light-emitting layers of each light-emitting device are distributed at intervals to emit light independently to achieve color display.
  • FMM fine mask
  • PPI pixel density
  • the color film layer has multiple light-emitting units one by one
  • the corresponding filter part, a filter part and the corresponding light-emitting unit can constitute a sub-pixel, and a plurality of sub-pixels constitute a pixel, and the colors of the light that can pass through different filter parts can be different, so that different sub-pixels emit light Colors can vary.
  • the same pixel includes a plurality of sub-pixels with different colors.
  • a pixel may include three sub-pixels whose luminous colors are red, green, and blue. Thereby, color display can be realized by a plurality of pixels.
  • Each light-emitting unit may include a plurality of light-emitting devices connected in series, and each light-emitting device of the same light-emitting unit shares the first electrode and the second electrode, and there are multiple light-emitting sub-layers between the first electrode and the second electrode, and at least two adjacent The two light-emitting sublayers can be connected in series through the charge generation layer. Positive charges (holes) can be transferred between two adjacent light-emitting units through the charge generation layer.
  • the light-emitting unit corresponding to the red filter in the color filter layer emits light
  • the The light-emitting unit corresponding to the green filter part in the color filter layer also emits light, which reduces the purity of light emitted by a single pixel and reduces the color gamut of the entire display panel.
  • the display panel may include a driving backplane BP, a first electrode layer FE, a pixel definition layer PDL, a light emitting layer OL, and a second electrode CAT, wherein :
  • the first electrode layer FE is disposed on one side of the driving backplane BP, and includes a plurality of first electrodes ANO distributed at intervals.
  • the pixel definition layer PDL and the first electrode layer FE are arranged on the same side of the driving backplane BP, and each first electrode ANO is exposed;
  • the pixel definition layer PDL includes a filling layer PBR and a blocking layer PCL stacked in a direction away from the driving backplane BP , the thickness of the filling layer PBR is smaller than that of the first electrode layer FE, and it is located outside the first electrode ANO;
  • the cut-off layer PCL is provided with a separation groove SES outside the first electrode ANO, and the side wall of the separation groove SES is provided with a first cut-off groove CUS1 .
  • the light emitting layer OL covers the cutoff layer PCL and the first electrode layer FE.
  • the second electrode CAT covers the light emitting layer OL.
  • any first electrode ANO and its corresponding light-emitting layer OL and second electrode CAT can constitute a light-emitting unit SUP, and the pixel definition layer PDL can separate each light-emitting unit SUP to define each light-emitting unit The range of SUPs.
  • the sidewall of the separation groove SES is provided with the first cut-off groove CUS1, even if the light-emitting layer OL is recessed into the separation groove SES, it is difficult to be continuously formed in the first cut-off groove CUS1, that is, at least part of the film layer of the light-emitting layer OL can be The first cut-off groove CUS1 is disconnected, so that the risk of electric leakage between adjacent light-emitting units SUP can be reduced, and cross-color can be improved.
  • the filling layer PBR can be used to limit the depth of the separation groove SES, preventing the difficulty in controlling the etching depth when etching the separation groove SES, which is beneficial to improving the uniformity of different driving backplanes BP.
  • the driving backplane BP may include a pixel area and a peripheral area, and the peripheral area is located outside the pixel area and may be arranged around the pixel area.
  • the driving backplane BP is used to form a driving circuit for driving the light emitting unit SUP to emit light, and the driving circuit may include a pixel circuit and a peripheral circuit, wherein:
  • the number of pixel circuits and the light emitting unit SUP can be multiple, and at least a part of the pixel circuits are located in the pixel area.
  • the pixel circuits can be 2T1C, 4T1C and other pixel circuits, as long as they can drive the light emitting unit SUP to emit light, the structure will not be discussed here. Make a special limit.
  • the number of pixel circuits is the same as that of the first electrodes ANO, and they are connected to the first electrodes ANO in a one-to-one correspondence, so as to respectively control each light emitting unit SUP to emit light.
  • nTmC indicates that a pixel circuit includes n transistors (indicated by the letter “T") and m capacitors (indicated by the letter “C”).
  • T n transistors
  • C m capacitors
  • the same pixel circuit can also drive multiple light emitting units SUP.
  • the peripheral circuit is located in the peripheral area and connected with the pixel circuit.
  • the peripheral circuit may include a light emission control circuit, a gate drive circuit, a source drive circuit, etc., and may also include a power supply circuit connected to the second electrode CAT for inputting a power supply signal to the second electrode CAT.
  • the peripheral circuit may input signals to the first electrode ANO and the second electrode CAT through the pixel circuit, so that the light emitting unit SUP emits light.
  • the driving backplane BP may include a substrate SU, and the substrate SU may be a silicon substrate, and the above-mentioned driving circuit may be formed on the silicon substrate through a semiconductor process, for example , the pixel circuit and the peripheral circuit may include a plurality of transistors, and a well region WL may be formed in the silicon substrate through a doping process, and the well region WL has two doped regions DR distributed at intervals.
  • a well region WL as an example: there is a gate GATE on one side of the driving backplane BP, and the orthographic projection of the gate GATE on the driving backplane BP is located between the two doped regions DR.
  • the well region WL and the gate GATE can be A transistor is formed, the doped region DR of the well region WL is respectively the first pole and the second pole of the transistor, and the well region WL between the two doped regions DR is the channel region of the transistor.
  • the driving backplane BP can also include at least one wiring layer TL and a flat layer PLN, the wiring layer TL is arranged on the side of the substrate SU, the flat layer PLN covers the wiring layer TL, at least one wiring layer TL and each doped Area DR connection.
  • the number of wiring layers TL is two layers, and is located in the flat layer PLN, for example, the wiring layer TL includes the first wiring layer TL1 and the second wiring layer TL2 , the first wiring layer TL1 is disposed on one side of the substrate SU, and a part of the flat layer PLN is disposed between the substrate SU and the substrate SU.
  • the second wiring layer TL2 is arranged on the side of the first wiring layer TL1 away from the substrate SU, and is separated from the first wiring layer TL1 by a part of the flat layer PLN, and at least part of the second wiring layer TL2 The region is connected to the first wiring layer TL1.
  • Each wiring layer TL can be formed by a sputtering process.
  • the material of the planar layer PLN can be silicon oxide, silicon oxynitride or silicon nitride, which is formed layer by layer through multiple deposition and polishing processes, that is to say, the planar layer PLN can be formed by stacking multiple insulating film layers.
  • each light emitting unit SUP is disposed on the surface of the flat layer PLN away from the substrate SU.
  • Each light-emitting unit SUP may include a first electrode ANO, a second electrode CAT, and a light-emitting layer OL between the first electrode ANO and the second electrode CAT. Both the first electrode ANO and the second electrode CAT may be connected to the wiring layer TL. connected, by driving the backplane BP to apply a driving signal to the first electrode ANO, and to apply a power signal to the second electrode CAT, thereby driving the light-emitting layer OL to emit light.
  • each light-emitting unit SUP can emit light of the same color, cooperate with the color filter layer CF located on the side of the second electrode CAT away from the driving backplane BP, to realize color display.
  • the embodiments of the present disclosure use this color The scheme shown is described as an example.
  • a plurality of light emitting units SUP may be formed by the first electrode layer FE, the pixel definition layer PDL, the light emitting layer OL, and the second electrode CAT, wherein:
  • the first electrode layer FE is disposed on one side of the driving backplane BP, for example, the first electrode layer FE is disposed on the surface of the flat layer PLN away from the substrate SU.
  • the first electrode layer FE may include a plurality of first electrodes ANO distributed at intervals, the orthographic projection of each first electrode ANO on the driving backplane BP is located in the pixel area, and connected to the pixel circuit, and one first electrode ANO is connected to one pixel circuit .
  • the first electrode layer FE can be a single-layer or multi-layer structure, and its material is not particularly limited here. For example:
  • the first electrode ANO may include a first conductive layer ANO1, a second conductive layer ANO2 and a third conductive layer sequentially stacked in a direction away from the driving backplane BP.
  • Layer ANO3 wherein: both the first conductive layer ANO1 and the third conductive layer ANO3 can be made of metal or metal oxide, such as titanium, titanium nitride, etc., and the materials of the two can be the same or different.
  • the second conductive layer ANO2 can use a metal material different from the first conductive layer ANO1 and the third conductive layer ANO3, and the resistivity is lower than the first conductive layer ANO1 and the third conductive layer ANO3, for example, the material of the second conductive layer ANO2 Can be aluminum.
  • the first electrode ANO may further include a fourth conductive layer, which may be provided on the surface of the third conductive layer away from the driving backplane BP, and the fourth conductive layer may use ITO (Indium Tin Oxide ) and other transparent conductive materials.
  • ITO Indium Tin Oxide
  • the pixel definition layer PDL and the first electrode layer FE are arranged on the same surface of the driving backplane BP, that is, the flat layer PLN is away from the surface of the substrate SU, and the pixel definition layer PDL exposes each first electrode ANO.
  • the pixel definition layer PDL may be provided with a plurality of pixel openings PO exposing each first electrode ANO.
  • the orthographic projection of any pixel opening PO on the driving backplane BP can be located within the exposed first electrode ANO, that is, the pixel opening PO is not larger than the exposed first electrode ANO, for example: the pixel opening PO
  • the boundary is located inside the boundary of the exposed first electrode ANO, that is, the area of the pixel opening PO is smaller than the area of the exposed first electrode ANO.
  • the shape of the pixel opening PO can be a rectangle, a pentagon, a hexagon and other polygons, but not necessarily a regular polygon. limited.
  • the light emitting layer OL covers the pixel definition layer PDL and the first electrode ANO, and the stacked area of the light emitting layer OL and the first electrode ANO is used to form a light emitting unit SUP, that is, each light emitting unit SUP can be share the same light-emitting layer OL, and the parts of the light-emitting layer OL stacked on different first electrodes ANO belong to different light-emitting units SUP.
  • each light-emitting unit SUP shares the light-emitting layer OL, different light-emitting units SUP emit the same color of light.
  • each light-emitting device LD of the same light-emitting unit SUP can share the same first electrode ANO and the same second electrode CAT, that is, the same light-emitting unit
  • the SUP may have only one first electrode ANO and one second electrode CAT.
  • the light-emitting layer OL may include multiple light-emitting sub-layers OLP connected in series along the direction away from the driving backplane BP, at least one light-emitting sub-layer OLP is connected to the charge generation layer CGL and An adjacent light-emitting sub-layer OLP is connected in series.
  • each light emitting sublayer OLP can emit light, and different light emitting sublayers OLP can be used to emit light of different colors.
  • any light-emitting sub-layer OLP may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting material layer EML, an electron transport layer ETL, and an electron transport layer distributed along a direction away from the driving backplane BP.
  • Injection layer EIL the specific light emitting principle will not be described in detail here, where:
  • the number of the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL and the electron injection layer EIL is not particularly limited here, and the adjacent light-emitting sub-layers OLP can share the hole injection layer HIL, the hole transport layer One or more of HTL, electron transport layer ETL, and electron injection layer EIL.
  • a charge generation layer CGL may be provided between at least two adjacent light emitting sub-layers OLP, so that the two light emitting sub-layers OLP are connected in series.
  • the light-emitting layer OL may include three light-emitting sublayers OLP with different colors, that is, the first light-emitting sublayer OLPr that emits red light, the second light-emitting sublayer OLPr that emits green light, and the light-emitting sublayer OLP that emits green light.
  • the layer OLPg and the third light emitting sublayer OLPb emitting blue light
  • the first light emitting sublayer OLPr, the second light emitting sublayer OLPg and the third light emitting sublayer OLPb can simultaneously emit light
  • the light emitting layer OL emits white light.
  • the first light emitting sublayer OLPr and the second light emitting sublayer OLPg share the hole injection layer HIL, the hole transport layer HTL1, the electron transport layer ETL2 and the electron injection layer EIL, and the light emitting material layer G of the second light emitting sublayer OLPg -EML is arranged on the surface of the luminescent material layer R-EML of the first luminescent sublayer OLPr away from the driving backplane BP, so that the first luminescent sublayer OLPr and the second luminescent sublayer OLPg are directly connected in series, and differently by setting special charges Generate layers.
  • the surface of the second light-emitting sub-layer OLPg away from the driving backplane BP may be provided with a charge generation layer CGL.
  • the third luminescent sublayer OLPb shares the electron injection layer EIL with the first luminescent sublayer OLPr and the second luminescent sublayer OLPg, and the hole injection layer HIL2 of the third luminescent sublayer OLPb is disposed on the charge generation layer CGL away from the side of the driving backplane BP.
  • the side of the hole transport layer HTL2 and the hole transport layer HTL3 of the third luminescent sublayer OLPb is laminated on the side of the charge generation layer CGL away from the driving backplane BP, and the charge generation layer CGL can be combined with the third luminescent sublayer OLPb It is connected in series with the second light emitting sublayer OLPg and the first light emitting sublayer OLPr.
  • a hole filling layer HBL may be disposed between the electron transport layer HYL of the third light emitting sub-layer OLPb and the light emitting material layer BEML.
  • the structure of the above-mentioned light-emitting layer OL is only for illustration and does not constitute a limitation to its film layer. It may include only two light-emitting sub-layers OLP, or more, or only one light-emitting sub-layer OLP, as long as it can
  • the color display can be realized by cooperating with the color filter layer CF.
  • the second electrode CAT covers the light emitting layer OL, and the orthographic projection of the second electrode CAT on the driving backplane BP can cover the pixel area and extend into the peripheral area.
  • Each light emitting unit SUP may share the same second electrode CAT.
  • the light emitting layer OL may be controlled to emit light by controlling voltages of a power signal input to the second electrode CAT and a driving signal input to the first electrode ANO.
  • the display panel may further include a color filter layer CF, which may be disposed on the side of the second electrode CAT away from the driving backplane BP, and includes a plurality of filter units CFU, each of the first electrodes ANO
  • Each filter unit CFU is arranged opposite to each other in a direction perpendicular to the driving backplane BP, that is, the orthographic projection of a filter unit CFU on the driving backplane BP at least partially overlaps with a first electrode ANO.
  • Each filter CFU includes at least three color filter CFUs, for example, a filter CFU that can transmit red light, a filter CFU that can transmit green light, and a filter CFU that can transmit blue light.
  • each light-emitting unit SUP After the light emitted by each light-emitting unit SUP is filtered by the filter unit CFU, monochromatic light of different colors can be obtained, thereby realizing color display, wherein a filter unit CFU and its corresponding light-emitting unit SUP can constitute a sub-pixel , the color of light emitted by any sub-pixel is the color of the light transmitted by its filter unit CFU, a plurality of sub-pixels can constitute a pixel, and the light-emitting colors of each sub-pixel of the same pixel are different.
  • the color filter layer CF may further include a light-shielding portion separating the filter portion CFU, the light-shielding portion is opaque and shields the area between the two light-emitting units SUP.
  • the CFU of the filter unit can be directly spaced from the CFU of the filter unit by using a light-shielding material; or, as shown in FIG. 1 and FIG.
  • the area between two adjacent light-emitting units SUP is stacked, and the colors of light transmitted by the two are different, so that the stacked area is opaque.
  • the color filter layer CF may further include a transparent part.
  • a transparent part may be A light-emitting unit SUP is arranged opposite to each other, so that the color filter layer CF can also pass through white light, and the brightness can be increased through white light.
  • the light extraction layer can be covered on the side of the second electrode CAT facing away from the driving backplane BP to improve brightness. Furthermore, the light extraction layer can directly cover the surface of the second electrode CAT facing away from the driving backplane BP.
  • the first electrode layer FE further includes an adapter ring, and the orthographic projection of the adapter ring on the drive backplane BP is located in the peripheral area, and the adapter ring
  • the ring can be connected with peripheral circuits and surrounds the pixel area.
  • the second electrode CAT can be connected with the adapter ring, so that the second electrode CAT can be connected with the peripheral circuit through the adapter ring, so that the peripheral circuit can apply a driving signal to the second electrode CAT.
  • the pattern of the transfer ring may be the same as that of the first electrode ANO in the pixel area, so as to improve the uniformity of the pattern of the first electrode layer FE.
  • the display panel of the present disclosure may further include a first encapsulation layer TFE1, which may be disposed on the side of the second electrode CAT away from the driving backplane BP, and Located between the color filter layer CF and the second electrode CAT, it is used to block the erosion of external water and oxygen.
  • the first encapsulation layer TFE1 can be a single-layer or multi-layer structure.
  • the first encapsulation layer TFE1 can include a first encapsulation sublayer, a second encapsulation sublayer, and a third encapsulation sublayer stacked in sequence in a direction away from the drive backplane BP.
  • the materials of the first encapsulation sublayer and the second encapsulation sublayer can be inorganic insulating materials such as silicon nitride and silicon oxide, and the second encapsulation sublayer can be formed by ALD (Atomic layer deposition, atomic layer deposition) process ;
  • the material of the third encapsulation sublayer can be an organic material, which can be formed by MLD (Molecular Layer Deposition, molecular layer deposition) process.
  • MLD Molecular Layer Deposition, molecular layer deposition
  • the first encapsulation layer TFE1 may also adopt other structures, and the structure of the first encapsulation layer TFE1 is not specifically limited here.
  • the display panel of the present disclosure may further include a second encapsulation layer TFE2, which may cover the surface of the color filter layer CF facing away from the driving backplane BP, In order to achieve planarization, it is convenient to cover the transparent cover plate, and the packaging effect can be improved, and water and oxygen can be further blocked.
  • the second encapsulation layer may be a single-layer or multi-layer structure, and may include inorganic materials such as silicon nitride and silicon oxide, or organic materials, and the structure of the second encapsulation layer is not particularly limited here.
  • the display panel may further include a transparent cover, which may cover the side of the second encapsulation layer TFE2 facing away from the driving backplane BP.
  • the transparent cover may be a single-layer or multi-layer structure, and its material is not specifically limited here.
  • each light-emitting unit SUP shares the light-emitting layer OL, carriers (such as holes) in one light-emitting unit SUP may move to other light-emitting units SUP through layers such as the charge generation layer CGL, especially If it moves to the adjacent light-emitting unit SUP, electric leakage occurs, which affects the purity of light emission and causes cross-color.
  • the separation groove SES can be provided in the cutoff layer PCLSL, and the first cutoff groove CUS1 can be opened on the side wall of the separation groove SES, and through the restriction of the first cutoff groove CUS1, the formed
  • the light-emitting layer OL is difficult to be continuous in the first cut-off groove CUS1, it is disconnected in the separation groove SES, so as to prevent carriers from moving between the light-emitting units SUP, thereby avoiding cross-color caused by electric leakage.
  • the etching depth when forming the filling layer PBR can be limited by the filling layer PBR, namely The depth of the separation groove SES is limited by the filling layer PBR, which is beneficial to improve the uniformity of the structures of different driving backplanes BP.
  • the pixel definition layer PDL may include at least two layers, namely, a filling layer PBR and a blocking layer PCL, and the filling layer PBR may be directly stacked on the driving backplane BP.
  • the filling layer PBR and the first electrode layer FE can be arranged on the surface of the flat layer PLN facing away from the substrate, and the filling layer PBR is located outside the first electrode layer FE and separates the first electrodes ANO, that is, the filling layer PBR can be As a film layer with a plurality of through holes, each first electrode ANO can be disposed in each through hole in a one-to-one correspondence.
  • the thickness of the filling layer PBR is smaller than that of the first electrode ANO.
  • the thickness of the filling layer PBR may be greater than the thickness of the first conductive layer ANO1, but smaller than the thickness of the second conductive layer ANO1.
  • the sum of the thicknesses of the conductive layer ANO2 and the first conductive layer ANO1, that is, the surface of the filling layer PBR facing away from the driving backplane BP is located between the surface of the second conductive layer ANO2 facing away from the driving backplane BP and the first conductive layer ANO1.
  • the material of the filling layer PBR may be inorganic insulating materials such as silicon oxide and silicon nitride, and of course other insulating materials may also be used.
  • the filling layer PBR can be in contact with the sidewall of the first electrode ANO, that is, the sidewall of the through hole is attached to the sidewall of the first electrode ANO inside. Since the material of the filling layer PBR is an insulating material, it will not contact with the first electrode ANO.
  • One electrode ANO is electrically connected to avoid short circuit between adjacent first electrodes ANO.
  • the blocking layer PCL can be stacked on the surface of the filling layer PBR facing away from the driving backplane BP, and each first electrode ANO is exposed, and the sum of the thicknesses of the blocking layer PCL and the filling layer PBR can be greater than that of the first electrodes.
  • Layer FE thickness As shown in FIG. 1 and FIG. 2, the blocking layer PCL can be stacked on the surface of the filling layer PBR facing away from the driving backplane BP, and each first electrode ANO is exposed, and the sum of the thicknesses of the blocking layer PCL and the filling layer PBR can be greater than that of the first electrodes.
  • Layer FE thickness As shown in FIG. 1 and FIG. 2, the blocking layer PCL can be stacked on the surface of the filling layer PBR facing away from the driving backplane BP, and each first electrode ANO is exposed, and the sum of the thicknesses of the blocking layer PCL and the filling layer PBR can be greater than that of the first electrodes.
  • Layer FE thickness As shown in
  • a partial area of the cutoff layer PCL may extend to the surface of the first electrode ANO facing away from the driving backplane BP, but does not completely cover the first electrode ANO.
  • the cut-off layer PCL may include a cut-off portion PDLc and an extension portion PDLe, the cut-off portion PDLc may be located outside the first electrode ANO, the extension portion PDLe is located on the surface of the first electrode ANO away from the driving backplane BP, the pixel definition layer PDL and the first The orthographic projections of the electrodes ANO on the driving backplane BP have overlapping regions.
  • the pixel opening PO can be opened in the extension portion PDLe to expose the first electrode ANO. Since the thickness of the first electrode ANO is greater than that of the filling layer PBR, when the cut-off layer PCL extends from the cut-off portion PDLc to the extension portion PDLe, it needs to climb a slope, that is, the surface of the extension portion PDLe away from the first electrode ANO is located at the cut-off portion PDLc away from the driving backplane The surface of the BP faces away from the side of the driving backplane BP.
  • the sidewall of the pixel opening PO may be a slope extending in a direction away from the driving backplane BP.
  • the cut-off layer PCL may not include the extension portion PDLe, but only include the cut-off portion PDLc, and the cut-off portion PDLc can separate the first electrodes ANO, that is, the cut-off portion PDLc and the filling layer PBR are used for driving
  • the boundaries of the projections on the backplane BP may coincide.
  • the pixel opening PO may be a through hole passing through the cut-off portion PDLc and the filling layer PBR, and there is no overlapping area between the orthographic projections of the pixel definition layer PDL and the first electrode ANO on the driving backplane BP.
  • the cut-off layer PCL is provided with a separation groove SES, and the separation groove SES is located outside the first electrode ANO, which may be an annular groove surrounding the first electrode ANO, and each first electrode ANO can be surrounded by a separation slot SES.
  • the separation groove SES surrounding two adjacent first electrodes ANO can share part of the area, so that there can be only one separation groove SES between two adjacent first electrodes ANO, and the side wall of the separation groove SES surrounds an electrode, and separates Both side walls of the slot SES.
  • the separation grooves SES surrounding two adjacent first electrodes ANO can also be opened independently, and there is no shared part.
  • the side walls of the separation slot SES may be slopes that expand in the direction away from the drive backplane BP, that is, the distance between the two side walls of the separation slot SES increases gradually in the direction away from the drive backplane BP, and the separation groove
  • the slope angle of the sidewall of the SES is less than or equal to 90°.
  • the sidewall of the separation groove SES is provided with a first cut-off groove CUS1
  • the first cut-off groove CUS1 may have a side wall of the separation groove SES that is recessed toward the first electrode ANO surrounded by the separation groove SES, and the direction of the depression is That is, in its depth direction, the depth of the first cut-off groove CUS1 may be smaller than the distance between its sidewall and the first electrode ANO, that is, the first cut-off groove CUS1 does not penetrate through the cut-off layer PCL in its depth direction.
  • the first cut-off groove CUS1 may extend along the extending direction of the separation groove SES, so as to form an annular groove on the sidewall of the separation groove SES.
  • the light-emitting layer OL covers the cut-off layer PCL and the first electrode layer FE, and is recessed into the separation groove SES.
  • the charge generation layer CGL or other film layers of the light-emitting layer OL it is difficult for the charge generation layer CGL or other film layers of the light-emitting layer OL to be formed on the first cut-off groove.
  • a side wall of the separation groove SES is disconnected, for example, a portion of the charge generation layer CGL corresponding to the first electrode ANO is disconnected from a portion corresponding to the separation groove SES.
  • first cut-off grooves CUS1 can be provided on both side walls of the separation groove SES, and one or more first cut-off grooves CUS1 can be opened on the same side wall. If a plurality of first cut-off grooves CUS1 are defined on one side wall, each first cut-off groove CUS1 may be distributed at intervals along a direction away from the driving backplane BP.
  • the blocking layer PCL includes a plurality of insulating layers stacked in a direction away from the driving backplane BP, and the material of each insulating layer can be silicon oxide, nitride
  • the insulating inorganic material such as silicon is not particularly limited here, and the materials of different insulating layers are the same or different.
  • the separation groove SES can expose the filling layer PBR, that is, the separation groove SES penetrates through each insulating layer.
  • the first cut-off groove CUS1 can be opened on an insulating layer, and the insulating layer where it is located is any insulating layer except the insulating layer farthest from the driving backplane BP.
  • the number of insulating layers of the blocking layer PCL may be three, that is, the first insulating layer CL1 , the second insulating layer CL2 and the third insulating layer CL3 are sequentially stacked along the direction away from the driving backplane BP.
  • the groove CUS1 can be opened in the second insulating layer CL2.
  • the separation groove SES runs through the first insulating layer CL1 and the third insulating layer CL3 , and the sidewall of the part of the separation groove SES located in the first insulating layer CL1 can be a slope extending away from the driving backplane BP.
  • the sidewall of the part of the separation groove SES located in the third insulating layer CL3 may be a slope extending in a direction away from the drive backplane BP, the slope angles ⁇ 1 and ⁇ 2 of the two slopes are neither greater than 90°, and both can be the same.
  • the material of the insulating layer to be formed into the first cut-off groove CUS1 can be different from that of other insulating layers.
  • different materials are etched to different extents by an etching process to form the separation groove SES and the second cut-off groove.
  • other processes can also be used, as long as the separation groove SES and the first cut-off groove CUS1 can be formed.
  • the two side walls of the first cut-off groove CUS1 can be distributed along the direction away from the drive backplane BP, and there is a bottom surface between the two side walls, and the bottom surface surrounds the first electrode ANO, which can make the second
  • the depth of a truncated groove CUS1 decreases along the direction away from the driving backplane BP, that is, the bottom surface of the first truncated groove CUS1 surrounding a first electrode ANO expands along the direction away from the driving backplane BP.
  • the annular surface, that is, the slope angle ⁇ of the bottom surface of the first cut-off groove CUS1 is greater than 90°.
  • the bottom surface of the first cut-off groove CUS1 may also be perpendicular to the driving backplane BP.
  • the slope angle ⁇ of the bottom surface of the first cut-off groove CUS1 is greater than the slope angle ⁇ 1 of the side wall of the separation groove SES located in the first insulating layer CL1, and larger than the slope angle ⁇ 1 of the side wall of the separation groove SES located in the third insulation layer CL3.
  • the slope angle ⁇ 2 of the wall is not greater than 90°, for example, 50°, 60° and so on.
  • the sum of the slope angle ⁇ of the bottom surface of the first cut-off groove CUS1 and the slope angle ⁇ 2 of the sidewall of the separation groove SES located in the third insulating layer CL3 is not greater than 90°.
  • the slope angles of the two slopes may be different.
  • the sum of the slope angle ⁇ of the sidewall of the pixel opening PO and the slope angle ⁇ of the bottom surface of the first cutoff groove CUS1 may be not less than 90°.
  • one side wall of the first cut-off groove CUS1 is located on the first insulating layer CL1, and the other side wall is located on the third insulating layer CL3, so that the clamping surface of the extension surface of the two side walls of the separation slot SES
  • the angle ⁇ is an acute angle, so that the sidewall of the third insulating layer CL3 is shorter than the sidewall of the first insulating layer CL1;
  • a portion of the insulating layer CL1 corresponding to the first cut-off groove CUS1 cuts off the light-emitting layer OL while reducing the risk of the third insulating layer CL3 being broken due to the existence of the first cut-off groove CUS1.
  • a second cut-off groove CUS2 may be provided on at least a part of the sidewall of the pixel opening PO, since the pixel opening PO PO is located in the extension portion PDLe, so the second cut-off groove CUS2 is actually opened on the extension portion PDLe, and the charge generation layer CGL can be disconnected by the second cut-off groove CUS2 to further prevent cross-color.
  • the specific implementation of the second cut-off groove CUS2 can refer to the first cut-off groove CUS1, for example, the second cut-off groove CUS2 is opened in the second insulating layer CL2, and the third insulating layer CL3 is formed overhead at the second cut-off groove CUS2.
  • the range of the extension part PDLe is relatively small.
  • the depth of the second cut-off groove CUS2 it is necessary to limit the depth of the second cut-off groove CUS2, so that the first cut-off groove CUS1 and the first cut-off groove
  • the maximum depth of CUS1 is greater than the maximum depth of the second cut-off groove CUS2, while ensuring that the second cut-off groove CUS2 can cut off at least part of the film layer of the light-emitting layer OL, and at the same time prevent its depth from being too large to cut off the extension portion PDLe, which is conducive to maintaining the structure stability.
  • the second cut-off groove CUS2 may be formed on the extension portion PDLe of each first electrode ANO; the second cut-off groove CUS2 may also be formed on the extension portion PDLe of the first electrode ANO of a specific light emitting unit SUP.
  • the range of the CFU of the blue filter unit is larger than the range of the CFU of the red and green filter units, that is, the range of the orthographic projection of the CFU of the blue filter unit on the driving backplane BP
  • the area is larger than the area of the orthographic projection of the red and green filter parts CFU on the driving backplane BP.
  • the second cut-off groove CUS2 may be provided on the sidewall of the pixel opening PO of the blue sub-pixel, while the second cut-off groove CUS2 may not be provided on the pixel opening PO of the red and green sub-pixels.
  • the third insulating layer CL3 is used to form the first cut-off groove CUS1
  • the part of the sidewall of the first cut-off groove CUS1 is inclined toward the driving backplane BP, and the inclination angle is the first inclination angle ⁇ 1, that is, the two sidewalls of the first cut-off groove CUS1 may not be parallel.
  • the part of the third insulating layer CL3 used to form the sidewall of the second cut-off groove CUS2 is inclined toward the driving backplane BP, and the slope angle is the second slope angle ⁇ 2; that is, the two side walls of the second cut-off groove CUS2 can be are not parallel; wherein, the first inclination angle ⁇ 1 may be greater than the second inclination angle ⁇ 2, that is, compared with the area of the third insulating layer CL3 in the second sectional groove CUS2, the third insulating layer CL3 is inclined in the area of the first sectional groove CUS1 more.
  • the second electrode CAT can form a flat part CATp in the region corresponding to the first electrode ANO, and form a flat part CATp in the region corresponding to the separation groove SES.
  • the concave portion CATg, the concave portion CATg and the flat portion CATp can be smoothly transitioned and connected to avoid sharp edges and corners of the second electrode CAT. Due to the filling of the separation groove SES by the light emitting layer OL, the depth of the depressed part CATg of the second electrode CAT is smaller than the depth of the separation groove SES. In addition, the depth of the depressed portion CATg may be greater than the thickness of the filling layer PBR.
  • the light-emitting layer OL is subjected to aging treatment to increase the impedance of the light-emitting layer OL in the aged region, thereby reducing the ability of the light-emitting layer OL to conduct laterally, and weakening the leakage between adjacent light-emitting units SUP.
  • the filling layer PBR may include a filling insulating layer PBRi and a filling conductive layer PBRc stacked in a direction away from the driving backplane BP, wherein:
  • the material for filling the insulating layer PBR may be insulating materials such as silicon nitride and silicon oxide, and the filling insulating layer PBRi is in contact with the sidewall of the first electrode ANO.
  • the material filling the conductive layer PBRc may be metal or other conductive materials, and is spaced apart from the sidewall of the first electrode ANO so as to be insulated from the first electrode ANO.
  • the bottom of the separation groove SES may not be a plane, and it may include the area where the surface of the filled insulating layer PBR facing away from the driving backplane BP is not covered by the filled conductive layer PBRc, and also includes the area where the filled conductive layer PBRc faces away from the driving backplane BP. surface.
  • the first cut-off groove CUS1 is located on a side of the filled conductive layer PBRc away from the driving backplane BP, that is, above the filled conductive layer PBRc.
  • the cut-off layer PCL may cover the filled conductive layer PBRc, or be located outside the filled conductive layer PBRc, as long as it does not affect the formation of the first cut-off groove CUS1.
  • the first electrode layer FE may further include a transfer ring CR.
  • the orthographic projection of the transfer ring CR on the drive backplane BP is located in the peripheral area and surrounds the pixel area.
  • the transfer ring CR is connected to the peripheral circuit.
  • the second electrode CAT It is connected with the adapter ring CR, and the adapter ring CR can refer to the above implementation manners, which will not be repeated here.
  • the adapter ring CR is provided with a notch CRh for disconnecting it;
  • the filled conductive layer PBRc may include a main body PBRc1 and a connection part PBRc2, the main body PBRc is located in the adapter ring CR, and is spaced apart from the adapter ring CR, so as to be insulated from the adapter ring CR.
  • the connection part PBRc2 is connected to the main part PBRc1, and passes through the adapter ring CR through the notch CRh, and is spaced apart from the adapter ring CR, that is, the connection part PBRc2 does not contact the notch CRh, and thus is insulated from the adapter ring CR.
  • the main body part PBRc1 and the connection part PBRc2 may be integrally formed, and may be formed at the same time.
  • the connection part PBRc2 can be connected with the peripheral circuit for receiving the aging voltage signal, so as to cooperate with the second electrode CAT to apply the aging voltage to the light emitting layer OL, so that the area of the light emitting layer OL corresponding to the main part PBRc1 will age and the impedance will increase.
  • the aging voltage can depend on the material and thickness of the luminescent layer OL, for example, it can be greater than 8v, 15v, 20v, 30v, etc., and there is no special limitation here, as long as the luminescent material OL can be aged.
  • the duration of the aging voltage can also be controlled to a specified duration, that is, the duration of the aging voltage signal is a specified duration. The specified duration may not be greater than 10 seconds, and of course it may be longer, as long as the luminescent material OL can be aged.
  • Embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the display panel may be the display panel in any of the above embodiments, and its structure will not be described in detail here.
  • the manufacturing method may include step S110-step S140, wherein:
  • Step S110 forming a driving backplane
  • Step S120 forming a first electrode layer comprising a plurality of first electrodes distributed at intervals on one side of the driving backplane;
  • Step S130 forming a pixel definition layer exposing each first electrode on the side of the driving backplane on which the first electrode layer is formed;
  • the pixel definition layer includes a filling layer and a blocking layer stacked in a direction away from the driving backplane, and the thickness of the filling layer is smaller than the first electrode layer, and located outside the first electrode;
  • the cut-off layer is provided with a separation groove located outside the first electrode, and the side wall of the separation groove is provided with a first cut-off groove;
  • Step S140 forming a light-emitting layer covering the cut-off layer and the first electrode layer;
  • Step S150 forming a second electrode covering the light emitting layer.
  • the manufacturing method may include step S110-step S170, wherein:
  • Step S110 forming a driving backplane
  • Step S120 forming a first electrode layer including a plurality of first electrodes distributed at intervals on one side of the driving backplane;
  • Step S130 forming a pixel definition layer exposing each of the first electrodes on the side of the driving backplane provided with the first electrode layer;
  • the pixel definition layer includes filling layers stacked in a direction away from the driving backplane layer and a blocking layer, the filling layer has a thickness smaller than that of the first electrode layer and is located outside the first electrode;
  • Step S140 applying an aging voltage signal to the filled conductive layer for a specified period of time
  • Step S150 forming a separation groove located outside the first electrode and a first separation groove located on the sidewall of the separation groove in the separation layer;
  • Step S160 forming a light-emitting layer covering the blocking layer and the first electrode layer
  • Step S170 forming a second electrode covering the light emitting layer.
  • Embodiments of the present disclosure further provide a display device, which may include the display panel in any of the above embodiments.
  • the specific structure and beneficial effects of the display panel have been described in detail in the implementation of the display panel above, and will not be described in detail here.
  • the display device of the present disclosure can be used in electronic devices with an image display function such as watches, wristbands, mobile phones, and tablet computers, and will not be listed here.

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Abstract

一种显示装置、显示面板及其制造方法。显示面板包括驱动背板(BP)、第一电极层(FE)、像素定义层(PDL)、发光层(OL)和第二电极(CAT)，第一电极层(FE)设于驱动背板(BP)一侧面，且包括多个第一电极(ANO)；像素定义层(PDL)与第一电极层(FE)设于驱动背板(BP)的同一侧面，且露出各第一电极(ANO)；像素定义层(PDL)包括沿背离驱动背板(BP)的方向层叠的填充层(PBR)和截断层(PCL)，填充层(PBR)的厚度小于第一电极层(FE)；截断层(PCL)设有位于第一电极(ANO)以外的分隔槽(SES)，分隔槽(SES)的侧壁设有第一截断槽(CUS1)；发光层(OL)覆盖截断层(PCL)和第一电极层(FE)；第二电极(CAT)覆盖发光层(OL)。 (图2)

Description

显示装置、显示面板及其制造方法
交叉引用
本公开要求于2021年11月29日提交的申请号为PCT/CN2021/133886，名称为“显示基板”的PCT国际申请的优先权，该PCT国际申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及显示面板的制造方法。
背景技术
随着显示技术的发展，显示面板已经广泛的应用于手机等各种电子设备，用于实现图像显示和触控操作。其中，OLED(OrganicLight-Emitting Diode，有机发光二极管)显示面板是较为常见的一种。但是，现有显示面板的色域仍有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种显示装置、显示面板及显示面板的制造方法。
根据本公开的一个方面，提供一种显示面板，包括：
驱动背板；
第一电极层，设于所述驱动背板一侧面，且包括间隔分布的多个第一电极；
像素定义层，与所述第一电极层设于所述驱动背板的同一侧面，且露出各所述第一电极；所述像素定义层包括沿背离所述驱动背板的方向层叠的填充层和截断层，所述填充层的厚度小于所述第一电极层，且位于所述第一电极以外；所述截断层设有位于所述第一电极以外的分隔槽， 所述分隔槽的侧壁设有第一截断槽；
发光层，覆盖所述截断层和所述第一电极层；
第二电极，覆盖所述发光层。
在本公开的一种示例性实施方式中，所述截断层包括沿背离所述驱动背板的方向层叠的多个绝缘层，所述分隔槽露出所述填充层；所述第一截断槽开设于一绝缘层，且所述第一截断槽所处的绝缘层为距离所述驱动背板最远的绝缘层以外的任意绝缘层。
在本公开的一种示例性实施方式中，所述截断层的绝缘层包括沿背离所述驱动背板的方向依次层叠的第一绝缘层、第二绝缘层和第三绝缘层，所述第一截断槽开设于所述第二绝缘层。
在本公开的一种示例性实施方式中，所述分隔槽的侧壁为沿背离所述驱动背板的方向扩张的坡面。
在本公开的一种示例性实施方式中，所述第一截断槽的底面为使其深度沿背离所述驱动背板的方向减小的坡面。
在本公开的一种示例性实施方式中，所述第一截断槽的底面的坡度角大于所述分隔槽位于所述第一绝缘层的侧壁的坡度角，且大于所述分隔槽位于所述第三绝缘层的侧壁的坡度角。
在本公开的一种示例性实施方式中，所述第一截断槽的底面的坡度角与所述分隔槽的位于所述第一绝缘层的侧壁的坡度角之和，不大于90°。
在本公开的一种示例性实施方式中，所述第一截断槽的底面的坡度角与所述分隔槽的位于所述第三绝缘层的侧壁的坡度角之和，不大于90°。
在本公开的一种示例性实施方式中，所述分隔槽的两侧壁的延伸面的夹角为锐角。
在本公开的一种示例性实施方式中，所述截断层包括截断部和延伸部，所述截断部位于所述第一电极以外，所述延伸部位于所述第一电极背离所述驱动背板的表面，且具有露出所述第一电极的像素开口；所述像素开口的侧壁为沿背离所述驱动背板的方向扩张的坡面。
在本公开的一种示例性实施方式中，所述像素开口的侧壁的坡度角 与所述第一截断槽的底面的坡度角之和不小于90°。
在本公开的一种示例性实施方式中，至少一部分所述像素开口的侧壁设有第二截断槽。
在本公开的一种示例性实施方式中，所述第一截断槽的最大深度大于所述第二截断槽的最大深度。
在本公开的一种示例性实施方式中，所述第三绝缘层的用于形成所述第一截断槽的侧壁的部分向所述驱动背板倾斜，且倾斜角度为第一倾斜角；
所述第三绝缘层的用于形成所述第二截断槽的侧壁的部分向所述驱动背板倾斜，且倾斜角度为第二倾斜角；
所述第一倾斜角大于所述第二倾斜角。
在本公开的一种示例性实施方式中，所述第二电极在对应于所述第一电极的区域形成平坦部，且在对应于所述分隔槽的区域形成凹陷部，所述凹陷部与所述平坦部平滑过渡。
在本公开的一种示例性实施方式中，所述凹陷部的深度小于所述分隔槽的深度。
在本公开的一种示例性实施方式中，所述凹陷部的深度大于所述填充层的厚度。
在本公开的一种示例性实施方式中，所述填充层与所述第一电极的侧壁接触
在本公开的一种示例性实施方式中，所述发光层还包括多层串联的发光子层，至少一所述发光子层通过电荷生成层与相邻的一所述发光子层串联；所述电荷生成层对应于所述第一电极的部分和对应于所述分隔槽的部分断开。
在本公开的一种示例性实施方式中，所述填充层包括沿背离所述驱动背板的方向层叠的填充绝缘层和填充导电层，所述填充绝缘层与所述第一电极的侧壁接触，所述填充导电层与所述第一电极的侧壁间隔设置。
在本公开的一种示例性实施方式中，所述驱动背板包括像素区和位于所述像素区外的外围区；所述像素区具有驱动发光层发光的像素电路，所述外围区具有外围电路；
所述第一电极层还包括转接环，所述转接环在所述驱动背板上的正投影位于所述外围区，且围绕于所述像素区外，所述转接环与所述外围电路连接，所述第二电极与所述转接环连接；所述转接环设有缺口；
所述填充导电层包括主体部和连接部，所述主体部位于所述转接环内，且与所述转接环间隔设置；所述连接部与所述主体部连接，并由所述缺口穿出所述转接环，且与所述转接环间隔设置；所述连接部用于接收老化电压信号。
根据本公开的一个方面，所述显示面板为上述的显示面板，所述制造方法包括：
形成驱动背板；
在所述驱动背板一侧面形成包括间隔分布的多个第一电极的第一电极层；
在所述驱动背板设有所述第一电极层的侧面形成露出各所述第一电极的像素定义层；所述像素定义层包括沿背离所述驱动背板的方向层叠的填充层和截断层，所述填充层的厚度小于所述第一电极层，且位于所述第一电极以外；
对所述填充导电层施加老化电压信号，并持续指定时长；
在所述截断层形成位于所述第一电极以外的分隔槽以及位于所述分隔槽的侧壁的第一截断槽；
形成覆盖所述截断层和所述第一电极层的发光层；
形成覆盖所述发光层的第二电极。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
形成驱动背板；
在所述驱动背板一侧面形成包括间隔分布的多个第一电极的第一电极层；
在形成有所述第一电极层的驱动背板的侧面形成露出各所述第一电极的像素定义层；所述像素定义层包括沿背离所述驱动背板的方向层叠的填充层和截断层，所述填充层的厚度小于所述第一电极层，且位于所述第一电极以外；所述截断层设有位于所述第一电极以外的分隔槽，所述分隔槽的侧壁设有第一截断槽；
形成覆盖所述截断层和所述第一电极层的发光层；
形成覆盖所述发光层的第二电极。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板的一实施方式的局部截面图。
图2为本公开显示面板的另一实施方式的局部截面图。
图3为本公开显示面板的一实施方式中部分膜层的局部截面图。
图4为本公开显示面板的另一实施方式中部分膜层的局部截面图。
图5为本公开显示面板一实施方式中发光单元的示意图。
图6为本公开显示面板的一实施方式的局部俯视图。
图7为本公开显示面板一实施方式中发光单元的示意图。
图8为本公开显示面板的一实施方式的局部截面图。
图9为本公开显示面板的一实施方式中转接环和填充导电层的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性 图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本申请中的任意“坡面”在垂直于驱动背板的截面中为直线，该“坡面”的坡度角(例如，图3中的α1、α1、β、γ、δ)可定义为该直线或其延伸线与坡面所处的表面的夹角中靠近该坡面围绕的第一电极的夹角。需要说明的是，考虑到工艺误差的影响，上述的直线可以不是绝对的直线，而可以是大致沿直线延伸的曲线，该曲线可以存在多个相切的切线，各个切线均与坡面所处表面具有夹角，该曲线的坡度角可以是各夹角中的最大夹角，也可以是各夹角的平均值。
相关技术中，硅基OLED显示面板包括驱动背板和发光功能层，其中：发光功能层设于驱动背板一侧，且包括多个发光单元，发光单元可包括一个或多个串联的发光器件，发光器件可采用有机发光二极管，其可包括向背离驱动背板的方向依次层叠的第一电极(阳极)、发光层和第二电极(阴极)，通过向第一电极和第二电极施加电信号，可驱动发光层发光，发光器件的具体发光原理在此不再详述。
此外，各个发光器件的发光层可以通过精细掩膜版(FMM)直接蒸镀形成，且各发光器件的发光层间隔分布，独立发光，实现彩色显示。但是由于精细掩膜版制造工艺的限制，难以实现高PPI(像素密度)。因此，还可通过单色光或白光配合彩膜实现彩色显示，即各发光器件共用同一连续的发光层，发光层可发白光或其它单色光，彩膜层具有多个与发光单元一一对应的滤光部，一滤光部和对应的发光单元可构成一子像素，多个子像素构成一像素，不同的滤光部可透过的光线的颜色可以不同，使得不同的子像素的发光颜色可以不同。同一像素包括多个颜色不同的子像素，例如，一像素可包括发光颜色分别为红、绿、蓝的三种子像素。由此，可通过多个像素实现彩色显示。
但是，若发光层为连续的整层结构，使得一发光单元与周边的发光单元之间容易出现漏电，导致串色。每个发光单元可包括多个串联的发光器件，同一发光单元的各发光器件共用第一电极和第二电极，第一电极和第二电极之间具有多层发光子层，至少两个相邻两发光子层可通过电荷生成层串联。正电荷(空穴)可通过电荷生成层在相邻两个发光单元之间转移，举例而言，在对应彩膜层中的红色滤光部的发光单元发光时，由于漏电的影响，会使对应彩膜层中的绿色滤光部的发光单元也发光，导致单个像素发光纯度降低，整个显示面板的色域降低。
本公开实施方式提供了一种显示面板，如图1和图2所示，显示面板可包括驱动背板BP、第一电极层FE、像素定义层PDL、发光层OL和第二电极CAT，其中：
第一电极层FE设于驱动背板BP一侧面，且包括间隔分布的多个第一电极ANO。像素定义层PDL与第一电极层FE设于驱动背板BP的同一侧面，且露出各第一电极ANO；像素定义层PDL包括沿背离驱动背板BP的方向层叠的填充层PBR和截断层PCL，填充层PBR的厚度小于第一电极层FE，且位于第一电极ANO以外；截断层PCL设有位于第一电极ANO以外的分隔槽SES，分隔槽SES的侧壁设有第一截断槽CUS1。发光层OL覆盖截断层PCL和第一电极层FE。第二电极CAT覆盖发光层OL。
本公开实施方式的显示面板，任一第一电极ANO与其对应的发光层OL和第二电极CAT可构成一发光单元SUP，像素定义层PDL可对各发光单元SUP进行分隔，限定出各发光单元SUP的范围。由于分隔槽SES的侧壁设有第一截断槽CUS1，使得发光层OL即便凹陷至分隔槽SES内，也难以连续的形成在第一截断槽CUS1内，即发光层OL的至少部分膜层可在第一截断槽CUS1断开，从而可降低相邻的发光单元SUP之间相互漏电的风险，改善串色。此外，填充层PBR可用于限制分隔槽SES的深度，防止在刻蚀分隔槽SES时刻蚀深度难以控制，有利于提高不同驱动背板BP的均一性。
下面对本公开显示面板实现显示功能的结构进行详细说明：
如图1和图2所示，驱动背板BP可包括像素区和外围区，外围区位于像素区外，并可围绕像素区设置。驱动背板BP用于形成驱动发光单元SUP发光的驱动电路，驱动电路可包括像素电路和外围电路，其中：
像素电路和发光单元SUP的数量均可以是多个，且至少一部分像素电路位于像素区内，像素电路可以是2T1C、4T1C等像素电路，只要能驱动发光单元SUP发光即可，在此不对其结构做特殊限定。像素电路的数量与第一电极ANO的数量相同，且一一对应地与第一电极ANO连接，以便分别控制各个发光单元SUP发光。其中，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。当然，同一像素电路也可驱动多个发光单元SUP。
外围电路位于外围区且与像素电路连接。外围电路可包括发光控制电路、栅极驱动电路和源极驱动电路等，此外，还可包括与第二电极CAT连接的电源电路，用于向第二电极CAT输入电源信号。外围电路可通过像素电路向第一电极ANO和第二电极CAT输入信号，从而使发光单元SUP发光。
在本公开的一些实施方式中，如图1和图2所示，驱动背板BP可包括衬底SU，衬底SU可为硅基底，上述的驱动电路可通过半导体工艺形成于硅基底，例如，像素电路和外围电路均可包括多个晶体管，可通过掺杂工艺在硅基底中形成阱区WL，阱区WL具有间隔分布的两个掺杂区DR。以一个阱区WL为例：驱动背板BP一侧设有栅极GATE，栅极GATE在驱动背板BP上的正投影位于两掺杂区DR之间，该阱区WL和栅极GATE可形成一晶体管，阱区WL的掺杂区DR分别为该晶体管的第一极和第二极，两掺杂区DR之间的阱区WL为该晶体管的沟道区。
驱动背板BP还可包括至少一层走线层TL和平坦层PLN，走线层TL设于衬底SU一侧，平坦层PLN覆盖走线层TL，至少一走线层TL与各掺杂区DR连接。
举例而言：如图1和图2所示，走线层TL的数量为两层，且位于平坦层PLN内，例如，走线层TL包括第一走线层TL1和第二走线层TL2，第一走线层TL1设于衬底SU一侧，且与衬底SU之间设有平坦层PLN的一部分。第二走线层TL2设于第一走线层TL1背离衬底SU的一 侧，其与第一走线层TL1之间被平坦层PLN的一部分分隔，且第二走线层TL2的至少部分区域与第一走线层TL1连接。
各走线层TL可通过溅射工艺形成。平坦层PLN的材料可采用氧化硅、氮氧化硅或氮化硅，通过多次沉积和抛光工艺逐层形成，也就是说，平坦层PLN可由多个绝缘膜层层叠而成。
如图1和图2所示，显示面板的各发光单元SUP阵列分布于驱动背板BP一侧，例如，各发光单元SUP设于平坦层PLN背离衬底SU的表面。每个发光单元SUP可包括第一电极ANO、第二电极CAT以及位于第一电极ANO和第二电极CAT之间的发光层OL，第一电极ANO和第二电极CAT均可与走线层TL连接，通过驱动背板BP向第一电极ANO施加驱动信号，向第二电极CAT施加电源信号，从而驱动发光层OL发光。
为了实现彩色显示，可以使各发光单元SUP均发出相同颜色的光线，配合位于第二电极CAT背离驱动背板BP一侧的彩膜层CF，实现彩色显示，本公开的实施方式以此种彩色显示的方案为例进行说明。
在本公开的一些实施方式中，如图1和图2所示，可通过第一电极层FE、像素定义层PDL、发光层OL和第二电极CAT形成多个发光单元SUP，其中：
第一电极层FE设于驱动背板BP一侧面，例如，第一电极层FE设于平坦层PLN背离衬底SU的表面。第一电极层FE可包括多个间隔分布的第一电极ANO，各第一电极ANO在驱动背板BP上的正投影位于像素区，且与像素电路连接，一个第一电极ANO连接一个像素电路。
第一电极层FE可为单层或多层结构，其材料在此不做特殊限定。举例而言：
如图1和图2所示，在本公开的一些实施方式中，第一电极ANO可包括向背离驱动背板BP的方向依次层叠的第一导电层ANO1、第二导电层ANO2和第三导电层ANO3，其中：第一导电层ANO1和第三导电层ANO3可均采用金属或金属氧化物等，例如，钛、氮化钛等，二者的材料可以相同，也可以不同。第二导电层ANO2可采用与第一导电层ANO1和第三导电层ANO3不同的金属材料，且电阻率低于第一导电层 ANO1和第三导电层ANO3，例如，第二导电层ANO2的材料可为铝。
在本公开的另一些实施方式中，第一电极ANO还可以包括第四导电层，其可设于第三导电层背离驱动背板BP的表面，且第四导电层可采用ITO(氧化铟锡)等透明导电材料。
如图3和图4所示，像素定义层PDL与第一电极层FE设于驱动背板BP的同一表面，即平坦层PLN背离衬底SU的表面，且像素定义层PDL露出各第一电极ANO。具体而言，像素定义层PDL可设有露出各第一电极ANO的多个像素开口PO。
任一像素开口PO在驱动背板BP上的正投影可位于其露出的第一电极ANO以内，也就是说，像素开口PO不大于其露出的第一电极ANO，举例而言：像素开口PO的边界位于其露出的第一电极ANO的边界的内侧，即像素开口PO的面积小于其露出的第一电极ANO的面积。
如图6所示，像素开口PO的形状可以是矩形、五边形、六边形等多边形，但不一定是正多边形，像素开口PO的形状还可以是椭圆形等其它形状，在此不做特殊限定。
如图1和图2所示，发光层OL覆盖像素定义层PDL和第一电极ANO，发光层OL与第一电极ANO层叠的区域用于形成发光单元SUP，也就是说，各个发光单元SUP可共用同一发光层OL，发光层OL位于层叠于不同的第一电极ANO的部分属于不同的发光单元SUP。此外，由于各发光单元SUP共用发光层OL，使得不同的发光单元SUP的发光颜色相同。
在本公开的一些实施方式中，如图1、图2和图7所示，发光单元SUP可包括多个串联的发光器件LD，每个发光单元SUP均包括第一电极ANO、第二电极CAT以及第一电极ANO和第二电极CAT之间的多个发光子层OLP，同一发光单元SUP的各发光器件LD可共用同一第一电极ANO和同一第二电极CAT，也就是说，同一发光单元SUP可以只有一个第一电极ANO和一个第二电极CAT。
举例而言：如图1、图2和图7所示，发光层OL可包括沿背离驱动背板BP的方向串联的多层发光子层OLP，至少一发光子层OLP通过电荷生成层CGL与相邻的一发光子层OLP串联。在向第一电极ANO和第 二电极CAT施加电信号时，各发光子层OLP均可发光，且不同的发光子层OLP可用于发出不同颜色的光线。
进一步的，如图7所示，任一发光子层OLP可包括沿背离驱动背板BP的方向分布的空穴注入层HIL、空穴传输层HTL、发光材料层EML、电子传输层ETL和电子注入层EIL，具体发光原理在此不再详述，其中：
空穴注入层HIL、空穴传输层HTL、电子传输层ETL和电子注入层EIL的数量在此不做特殊限定，且相邻的发光子层OLP可共用空穴注入层HIL、空穴传输层HTL、电子传输层ETL和电子注入层EIL中的一个或多个。同时，至少有两个相邻的发光子层OLP之间可设有电荷生成层CGL，从而将两发光子层OLP串联。
在本公开的一些实施方式中，如图7所示，发光层OL可包括三个颜色不同的发光子层OLP，即发红光的第一发光子层OLPr、发绿光的第二发光子层OLPg和发蓝光的第三发光子层OLPb，第一发光子层OLPr、第二发光子层OLPg和第三发光子层OLPb可同时发光时，使得发光层OL发白光。其中，第一发光子层OLPr和第二发光子层OLPg共用空穴注入层HIL、空穴传输层HTL1、电子传输层ETL2和电子注入层EIL，且第二发光子层OLPg的发光材料层G-EML设于第一发光子层OLPr的发光材料层R-EML背离驱动背板BP的表面，从而使第一发光子层OLPr和第二发光子层OLPg直接串联，而不同通过设置专门的电荷生成层。第二发光子层OLPg背离驱动背板BP的表面可设有电荷生成层CGL。第三发光子层OLPb与第一发光子层OLPr和第二发光子层OLPg共用电子注入层EIL，第三发光子层OLPb的空穴注入层HIL2设于电荷生成层CGL背离驱动背板BP的表面，第三发光子层OLPb的空穴传输层HTL2和空穴传输层HTL3一侧层叠于电荷生成层CGL背离驱动背板BP的一侧，可将电荷生成层CGL将第三发光子层OLPb与第二发光子层OLPg和第一发光子层OLPr串联。此外，第三发光子层OLPb的电子传输层HYL和发光材料层BEML之间可设置空穴填充层HBL。
上述的发光层OL结构仅为示例性说明，并不构成对其膜层的限制，其可以是仅包括两个发光子层OLP，也可以更多，或者仅包括一个发光子层OLP，只要能配合彩膜层CF实现彩色显示即可。
如图1、图2和图7所示，第二电极CAT覆盖发光层OL，且第二电极CAT在驱动背板BP上的正投影可覆盖像素区，并延伸至外围区内。各个发光单元SUP可共用同一第二电极CAT。可通过控制输入至第二电极CAT的电源信号和输入至第一电极ANO的驱动信号的电压来控制发光层OL发光。
如图1和图2所示，显示面板还可包括彩膜层CF，其可设于第二电极CAT背离驱动背板BP的一侧，且包括多个滤光部CFU，各第一电极ANO与各滤光部CFU在垂直于驱动背板BP的方向上一一相对设置，即一滤光部CFU在驱动背板BP上的正投影与一第一电极ANO至少部分重合。各个滤光部CFU中至少包括三种颜色的滤光部CFU，例如，可透红光的滤光部CFU、可透过绿光的滤光部CFU和可透过蓝光的滤光部CFU。各发光单元SUP发出的光线经过滤光部CFU的滤光作用后，可得到不同颜色的单色光，从而实现彩色显示，其中，一滤光部CFU与其对应的发光单元SUP可构成一子像素，任一子像素发光的颜色即为其滤光部CFU透过的光线的颜色，多个子像素可构成一像素，同一像素的各子像素的发光颜色不同。
彩膜层CF还可包括分隔滤光部CFU的遮光部，遮光部不透光，并遮挡两发光单元SUP之间的区域。滤光部CFU可直接采用遮光材料与滤光部CFU间隔设置；或者，如图1和图2所示，在本公开的一些实施方式中，可以使相邻的滤光部CFU在对应于相邻两发光单元SUP之间的区域层叠设置，且二者透光的光线的颜色不同，从而使得层叠区域不透光。
此外，在本公开的一些实施方式中，在发光层OL发出白光的基础上，为了提高画面亮度，彩膜层CF还可包括透明部，在垂直于衬底的方向上，一透明部可与一发光单元SUP相对设置，使得彩膜层CF还可透过白光，可通过白光增加亮度。
为了提高出光效率，可在第二电极CAT背离驱动背板BP的一侧覆盖光提取层，以提高亮度，进一步的，光提取层可直接覆盖第二电极CAT背离驱动背板BP的表面。
为了便于将第二电极CAT与驱动电路连接，在本公开的一些实施方 式中，第一电极层FE还包括转接环，转接环在驱动背板BP上的正投影位于外围区，转接环可与外围电路连接，且围绕于像素区外。第二电极CAT可与转接环连接，从而可通过转接环将第二电极CAT与外围电路连接起来，以便由外围电路向第二电极CAT施加驱动信号。转接环的图案可与像素区内的第一电极ANO的图案相同，以便提高第一电极层FE的图案的均一性。
在本公开的一些实施方式中，如图1和图2所示，本公开的显示面板还可包括第一封装层TFE1，其可设于第二电极CAT背离驱动背板BP的一侧，且位于彩膜层CF和第二电极CAT之间，用于阻隔外界水、氧的侵蚀。第一封装层TFE1可为单层或多层结构，例如，第一封装层TFE1可包括向背离驱动背板BP的方向依次层叠的第一封装子层、第二封装子层和第三封装子层，其中，第一封装子层和第二封装子层的材料可以是氮化硅、氧化硅等无机绝缘材料，且第二封装子层可采用ALD(Atomic layer deposition，原子层沉积)工艺形成；第三封装子层的材料可为有机材料，其可采用MLD(Molecular Layer Deposition，分子层沉积)工艺形成。当然，第一封装层TFE1还可以采用其它结构，在此不对第一封装层TFE1的结构做特殊限定。
此外，在本公开的一些实施方式中，如图1和图2所示，本公开的显示面板还可包括第二封装层TFE2，其可覆盖于彩膜层CF背离驱动背板BP的表面，以便实现平坦化，便于覆盖透明盖板，且可以提高封装效果，进一步阻隔水、氧。第二封装层可以是单层或多层结构，且可以包括氮化硅、氧化硅等无机材料，也可以包括有机材料，在此不对第二封装层的结构做特殊限定。
此外，显示面板还可包括透明盖板，其可覆盖于第二封装层TFE2背离驱动背板BP的一侧，透明盖板可以是单层或多层结构，其材料在此不做特殊限定。
基于上文中对相关技术的分析，由于各个发光单元SUP共用发光层OL，一发光单元SUP的载流子(例如空穴)可能会通过电荷生成层CGL等膜层向其它发光单元SUP移动，特别是向相邻的发光单元SUP移动， 即发生漏电，影响发光的纯度，造成串色。为此，如图1和图2所示，可通过在截断层PCLSL设置分隔槽SES，并在分隔槽SES的侧壁开设第一截断槽CUS1，通过第一截断槽CUS1的限制，使得在形成发光层OL时，其难以在第一截断槽CUS1内连续，从而在分隔槽SES内断开，达到防止载流子在发光单元SUP之间移动的目的，进而避免因漏电而导致的串色。进一步的，为了限制分隔槽SES的深度，避免其延伸至驱动背板BP内，且不同显示面板的深度差异过大，可通过填充层PBR对形成填充层PBR时的刻蚀深度进行限制，即分隔槽SES的深度以填充层PBR为限，有利于提高不同驱动背板BP的结构的均一性。
下面对本公开的显示面板解决串色问题的方案进行详细说明：
如图1和图2所示，为了实现上述目的，像素定义层PDL可至少包括两层，即填充层PBR和截断层PCL，填充层PBR可直接层叠于驱动背板BP上。填充层PBR可与第一电极层FE同设于平坦层PLN背离衬底的表面，且填充层PBR位于第一电极层FE以外，且分隔各第一电极ANO，也就是说，填充层PBR可视作一具有多个通孔的膜层，各第一电极ANO可一一对应的设于各通孔内。同时，为了给截断层PCL上的分隔槽SES提供足够的凹陷空间，填充层PBR的厚度小于第一电极ANO。举例而言，针对包括第一导电层ANO1、第二导电层ANO2和第三导电层ANO3的第一电极ANO而言，填充层PBR的厚度可大于第一导电层ANO1的厚度，但小于第二导电层ANO2和第一导电层ANO1的厚度之和，也就是说，填充层PBR背离驱动背板BP的表面位于第二导电层ANO2背离驱动背板BP的表面和第一导电层ANO1之间。此外，填充层PBR的材料可以是氧化硅、氮化硅等无机绝缘材料，当然也可以是其它绝缘材料。此外，填充层PBR可与第一电极ANO的侧壁接触，即通孔的侧壁与其内的第一电极ANO的侧壁贴合，由于填充层PBR的材料为绝缘材料，因而不会与第一电极ANO电连接，避免相邻的第一电极ANO之间出现短路。
如图1和图2所示，截断层PCL可层叠于填充层PBR背离驱动背板BP的表面，且露出各第一电极ANO，截断层PCL与填充层PBR的厚度之和可大于第一电极层FE厚度。
在本公开的一些实施方式中，如图3所示，截断层PCL的部分区域可延伸至第一电极ANO背离驱动背板BP的表面上，但不完全遮盖第一电极ANO。相应的，截断层PCL可包括截断部PDLc和延伸部PDLe，截断部PDLc可位于第一电极ANO以外，延伸部PDLe位于第一电极ANO背离驱动背板BP的表面，像素定义层PDL与第一电极ANO在驱动背板BP上的正投影存在交叠区域。像素开口PO可开设于延伸部PDLe，以露出第一电极ANO。由于第一电极ANO的厚度大于填充层PBR，使得截断层PCL从截断部PDLc向延伸部PDLe延伸时，需要爬坡，即延伸部PDLe背离第一电极ANO的表面位于截断部PDLc背离驱动背板BP的表面背离驱动背板BP的一侧。此外，在本实施方式中，像素开口PO的侧壁可为沿背离驱动背板BP的方向扩张的坡面。
在本公开的其它实施方式中，截断层PCL可以不包括延伸部PDLe，而只包括截断部PDLc，截断部PDLc可分隔各第一电极ANO，也就是说，截断部PDLc和填充层PBR在驱动背板BP上的投影的边界可以重合。像素开口PO可以是贯穿截断部PDLc和填充层PBR的通孔，像素定义层PDL与第一电极ANO在驱动背板BP上的正投影不存在交叠区域。
如图1和图2所示，截断层PCL开设有分隔槽SES，且分隔槽SES位于第一电极ANO以外，其可以是围绕于第一电极ANO外的环形槽，且每个第一电极ANO外均可围绕一分隔槽SES。相邻两第一电极ANO外围绕的分隔槽SES可以共用部分区域，使得相邻两第一电极ANO之间可以只有一个分隔槽SES，分隔槽SES的一侧壁围绕于一电极外，且分隔槽SES的两侧壁。当然，相邻两第一电极ANO外围绕的分隔槽SES也可以分别独立开设，而不存在共用的部分。此外，分隔槽SES的侧壁可为沿背离驱动背板BP的方向扩张的坡面，也就是说，分隔槽SES的两侧壁的距离沿背离驱动背板BP的方向逐渐增大，分隔槽SES的侧壁的坡度角为小于或等于90°。
如图1和图2所示，分隔槽SES的侧壁设有第一截断槽CUS1，第一截断槽CUS1可有分隔槽SES的侧壁向分隔槽SES围绕的第一电极ANO凹陷，凹陷方向即为其深度方向，第一截断槽CUS1的深度可以小 于其所在的侧壁与第一电极ANO之间的距离，也就是说，第一截断槽CUS1在其深度方向上不贯穿截断层PCL。
如图1和图2所示，第一截断槽CUS1可沿分隔槽SES的延伸方向延伸，从而在分隔槽SES的侧壁上形成环形的凹槽。发光层OL覆盖截断层PCL和第一电极层FE，且凹陷至分隔槽SES内，但是由于第一截断槽CUS1的存在，发光层OL的电荷生成层CGL或其它膜层难以形成在第一截断槽CUS1内，在分隔槽SES的侧壁上断开，例如，电荷生成层CGL对应于第一电极ANO的部分和对应于分隔槽SES的部分断开。从而可以防止相邻发光单元SUP之间的串色。
为了确保阻断效果，可在分隔槽SES的两侧壁均设置第一截断槽CUS1，且同一侧壁上可开设一个或多个第一截断槽CUS1。若一侧壁上开设多个第一截断槽CUS1，则各第一截断槽CUS1可沿背离驱动背板BP的方向间隔分布。
下面对形成第一截断槽CUS1的具体方式进行详细说明：
如图1和图2所示，在本公开的一些实施方式中，截断层PCL包括沿背离驱动背板BP的方向层叠的多个绝缘层，各绝缘层的材料均可以是氧化硅、氮化硅等绝缘的无机材料，在此不做特殊限定，不同的绝缘层的材料相同或不同。分隔槽SES可露出填充层PBR，即分隔槽SES贯穿各绝缘层。第一截断槽CUS1可开设于一绝缘层，且其所处的绝缘层为距离驱动背板BP最远的绝缘层以外的任意绝缘层。举例而言，截断层PCL的绝缘层的数量可为三个，即沿背离驱动背板BP的方向依次层叠的第一绝缘层CL1、第二绝缘层CL2和第三绝缘层CL3，第一截断槽CUS1可开设于第二绝缘层CL2。如图3所示，分隔槽SES贯穿第一绝缘层CL1和第三绝缘层CL3，分隔槽SES位于第一绝缘层CL1的部分的侧壁可为沿背离驱动背板BP的方向扩张的坡面，分隔槽SES位于第三绝缘层CL3的部分的侧壁可为沿背离驱动背板BP的方向扩张的坡面，该两个坡面的坡度角α1、α2都不大于90°，且二者可以是相同的。
可使待形成第一截断槽CUS1的绝缘层的材料可与其它绝缘层的材料不同，在形成第一截断槽CUS1时，通过刻蚀工艺对不同材料的刻蚀程度不同形成分隔槽SES和第一截断槽CUS1。当然，也可以采用其它 工艺，只要能形成分隔槽SES和第一截断槽CUS1即可。
如图3所示，第一截断槽CUS1的两侧壁可沿背离驱动背板BP的方向分布，两侧壁之间具有一底面，该底面围绕于第一电极ANO外，其可以是使第一截断槽CUS1的深度沿背离驱动背板BP的方向减小的坡面，也就是说，围绕于一第一电极ANO外的第一截断槽CUS1的底面为沿背离驱动背板BP的方向扩张的环形面，即第一截断槽CUS1的底面的坡度角β大于90°。当然，第一截断槽CUS1的底面也可以垂直于驱动背板BP。
如图3所示，第一截断槽CUS1的底面的坡度角β大于分隔槽SES的位于第一绝缘层CL1的侧壁的坡度角α1，且大于分隔槽SES的位于第三绝缘层CL3的侧壁的坡度角α2。此外，第一截断槽CUS1的底面的坡度角β与分隔槽SES的位于第一绝缘层CL1的侧壁的坡度角α1之和不大于90°，例如，50°、60°等。同时，第一截断槽CUS1的底面的坡度角β与分隔槽SES的位于第三绝缘层CL3的侧壁的坡度角α2之和，不大于90°。在本公开的其它实施方式中，该两个坡面的坡度角可以不同。此外，如图3所示，可使像素开口PO的侧壁的坡度角δ与第一截断槽CUS1的底面的坡度角β之和不小于90°。
在本公开的一些实施方式中，第一截断槽CUS1的一侧壁位于第一绝缘层CL1，另一侧壁位于第三绝缘层CL3，可使分隔槽SES的两侧壁的延伸面的夹角γ为锐角，使得位于第三绝缘层CL3的侧壁短于位于第一绝缘层CL1的侧壁；也就是说，第三绝缘层CL3对应于第一截断槽CUS1的悬空的部分短于第一绝缘层CL1对应于第一截断槽CUS1的部分，在截断发光层OL的同时，可降低第三绝缘层CL3因第一截断槽CUS1的存在而断裂的风险。
在本公开的一些实施方式中，如图2和图3所示，对于具有延伸部PDLe的像素定义层PDL，可在至少一部分像素开口PO的侧壁设有第二截断槽CUS2，由于像素开口PO位于延伸部PDLe，所以第二截断槽CUS2实际上开设于延伸部PDLe上，通过第二截断槽CUS2可使电荷生成层CGL断开，进一步防止串色。第二截断槽CUS2的具体实现方式可参考第一截断槽CUS1，例如，第二截断槽CUS2开设于第二绝缘层CL2， 第三绝缘层CL3在第二截断槽CUS2处形成架空。同时，为了避免延伸部PDLe对第一电极ANO造成较大遮挡，延伸部PDLe的范围较小，相应的，需要限制第二截断槽CUS2的深度，因而可使第一截断槽CUS1第一截断槽CUS1的最大深度大于第二截断槽CUS2的最大深度，在保证第二截断槽CUS2能截断发光层OL的至少部分膜层的同时，避免其深度过大而截断延伸部PDLe，有利于保持结构的稳定性。
进一步的，可以在每个第一电极ANO上的延伸部PDLe均开设第二截断槽CUS2；也可以在特定的发光单元SUP的第一电极ANO的延伸部PDLe开设第二截断槽CUS2。举例而言，在彩膜层CF中，蓝色滤光部CFU的范围大于红色和绿色滤光部CFU的范围，也就是说，蓝色滤光部CFU在驱动背板BP上的正投影的面积大于红色和绿色滤光部CFU在驱动背板BP上的正投影的面积。可在蓝色子像素的像素开口PO的侧壁开设第二截断槽CUS2，而在红色和绿色子像素的像素开口PO则可以不开设第二截断槽CUS2。
在本公开的一些实施方式中，如图4所示，针对形成于第二绝缘层CL2的第一截断槽CUS1和第二截断槽CUS2，第三绝缘层CL3的用于形成第一截断槽CUS1的侧壁的部分向驱动背板BP倾斜，且倾斜角度为第一倾斜角θ1，也就是说，第一截断槽CUS1的两侧壁可以不平行。第三绝缘层CL3的用于形成第二截断槽CUS2的侧壁的部分向驱动背板BP倾斜，且倾斜角度为第二倾斜角θ2；也就是说，第二截断槽CUS2的两侧壁可以不平行；其中，第一倾斜角θ1可以大于第二倾斜角θ2，即相较于第三绝缘层CL3在第二截断槽CUS2的区域，第三绝缘层CL3在第一截断槽CUS1的区域倾斜的更多。
如图5所示，基于上述的像素定义层PDL和发光层OL的形貌，第二电极CAT在对应于第一电极ANO的区域可形成平坦部CATp，且在对应于分隔槽SES的区域形成凹陷部CATg，凹陷部CATg与平坦部CATp可以平滑过渡连接，避免第二电极CAT出现尖锐的棱角。由于发光层OL对分隔槽SES的填充，使得第二电极CAT的凹陷部CATg的深度小于分隔槽SES的深度。此外，凹陷部CATg的深度可以大于填充层PBR的厚度。
此外，在本公开的一些实施方式中，如图8和图9所示，针对整层设置的发光层OL，即各个发光单元SUP共用发光层OL的情况，还可通过对发光单元SUP之间的发光层OL进行老化处理，增大老化区域的发光层OL的阻抗，从而减少发光层OL横向导通的能力，减弱相邻发光单元SUP之间的漏电。
举例而言，可使填充层PBR包括沿背离驱动背板BP的方向层叠的填充绝缘层PBRi和填充导电层PBRc，其中：
填充绝缘层PBR的材料可以是氮化硅、氧化硅等绝缘材料，且填充绝缘层PBRi与第一电极ANO的侧壁接触。填充导电层PBRc的材料可以是金属或其它导电材料，且与第一电极ANO的侧壁间隔设置，从而与第一电极ANO绝缘。在此情况下，分隔槽SES的底部可以不是平面，其可以包括填充绝缘层PBR背离驱动背板BP的表面未被填充导电层PBRc覆盖的区域，也包括填充导电层PBRc背离驱动背板BP的表面。第一截断槽CUS1位于填充导电层PBRc背离驱动背板BP的一侧，即位于填充导电层PBRc的上方。截断层PCL可以覆盖填充导电层PBRc，也可以位于填充导电层PBRc以外，只要不影响第一截断槽CUS1的形成即可。
第一电极层FE还可包括转接环CR，转接环CR在驱动背板BP上的正投影位于外围区，且围绕于像素区外，转接环CR与外围电路连接，第二电极CAT与转接环CR连接，转接环CR可以参考上文的实施方式，在此不再赘述。转接环CR设有使其断开的缺口CRh；
填充导电层PBRc可包括主体部PBRc1和连接部PBRc2，主体部PBRc位于转接环CR内，且与转接环CR间隔设置，从而与转接环CR绝缘。连接部PBRc2与主体部PBRc1连接，并由缺口CRh穿出转接环CR，且与转接环CR间隔设置，即连接部PBRc2与缺口CRh不接触，从而与转接环CR绝缘。主体部PBRc1和连接部PBRc2可为一体结构，可同时形成。
连接部PBRc2可与外围电路连接，用于用于接收老化电压信号，从而可与第二电极CAT配合向发光层OL施加老化电压，使发光层OL对应于主体部PBRc1的区域老化，阻抗增加。老化电压可视发光层OL的 材料和厚度而定，例如，其可以大于8v，15v、20v，30v等，在此不做特殊限定，只要能使发光材料OL老化即可。此外，还可控制老化电压的持续时间为指定时长，即老化电压信号的持续时长为指定时长，该指定时长可以不大于10秒，当然也可以更长，只要能使发光材料OL老化即可。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述任意实施方式的显示面板，其结构在此不再详述，该制造方法可包括步骤S110-步骤S140，其中：
步骤S110、形成驱动背板；
步骤S120、在驱动背板一侧面形成，包括间隔分布的多个第一电极的第一电极层；
步骤S130、在形成有第一电极层的驱动背板的侧面形成露出各第一电极的像素定义层；像素定义层包括沿背离驱动背板的方向层叠的填充层和截断层，填充层的厚度小于第一电极层，且位于第一电极以外；截断层设有位于第一电极以外的分隔槽，分隔槽的侧壁设有第一截断槽；
步骤S140、形成覆盖截断层和第一电极层的发光层；
步骤S150、形成覆盖发光层的第二电极。
基于上述的具有填充绝缘层PBRi和填充导电层PBRc显示面板，在本公开的一些实施方式中，制造方法可包括步骤S110-步骤S170，其中：
步骤S110、形成驱动背板；
步骤S120、在所述驱动背板一侧面形成包括间隔分布的多个第一电极的第一电极层；
步骤S130、在所述驱动背板设有所述第一电极层的侧面形成露出各所述第一电极的像素定义层；所述像素定义层包括沿背离所述驱动背板的方向层叠的填充层和截断层，所述填充层的厚度小于所述第一电极层，且位于所述第一电极以外；
步骤S140、对所述填充导电层施加老化电压信号，并持续指定时长；
步骤S150、在所述截断层形成位于所述第一电极以外的分隔槽以及位于所述分隔槽的侧壁的第一截断槽；
步骤S160、形成覆盖所述截断层和所述第一电极层的发光层；
步骤S170、形成覆盖所述发光层的第二电极。
由于上述制造方法的各步骤中涉及的结构的细节已在上文显示面板的实施方式中进行了详细说明，在此不再对其细节和有益效果进行详细说明。
需要说明的是，尽管在附图中以特定顺序描述了本公开中制造方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种显示装置，该显示装置可包括上述任意实施方式的显示面板。该显示面板的具体结构及有益效果已在上文显示面板的实施方式中进行了详细说明，在此不再详述。本公开的显示装置可以用于手表、手环、手机、平板电脑等具有图像显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (23)

  1. 一种显示面板，其中，包括：
    驱动背板；
    第一电极层，设于所述驱动背板一侧面，且包括间隔分布的多个第一电极；
    像素定义层，与所述第一电极层设于所述驱动背板的同一侧面，且露出各所述第一电极；所述像素定义层包括沿背离所述驱动背板的方向层叠的填充层和截断层，所述填充层的厚度小于所述第一电极层，且位于所述第一电极以外；所述截断层设有位于所述第一电极以外的分隔槽，所述分隔槽的侧壁设有第一截断槽；
    发光层，覆盖所述截断层和所述第一电极层；
    第二电极，覆盖所述发光层。
  2. 根据权利要求1所述的显示面板，其中，所述截断层包括沿背离所述驱动背板的方向层叠的多个绝缘层，所述分隔槽露出所述填充层；所述第一截断槽开设于一绝缘层，且所述第一截断槽所处的绝缘层为距离所述驱动背板最远的绝缘层以外的任意绝缘层。
  3. 根据权利要求1所述的显示面板，其中，所述截断层的绝缘层包括沿背离所述驱动背板的方向依次层叠的第一绝缘层、第二绝缘层和第三绝缘层，所述第一截断槽开设于所述第二绝缘层。
  4. 根据权利要求3所述的显示面板，其中，所述分隔槽的侧壁为沿背离所述驱动背板的方向扩张的坡面。
  5. 根据权利要求4所述的显示面板，其中，所述第一截断槽的底面为使其深度沿背离所述驱动背板的方向减小的坡面。
  6. 根据权利要求5所述的显示面板，其中，所述第一截断槽的底面的坡度角大于所述分隔槽位于所述第一绝缘层的侧壁的坡度角，且大于所述分隔槽位于所述第三绝缘层的侧壁的坡度角。
  7. 根据权利要求5所述的显示面板，其中，所述第一截断槽的底面的坡度角与所述分隔槽的位于所述第一绝缘层的侧壁的坡度角之和，不大于90°。
  8. 根据权利要求5所述的显示面板，其中，所述第一截断槽的底面 的坡度角与所述分隔槽的位于所述第三绝缘层的侧壁的坡度角之和，不大于90°。
  9. 根据权利要求4所述的显示面板，其中，所述分隔槽的两侧壁的延伸面的夹角为锐角。
  10. 根据权利要求5所述的显示面板，其中，所述截断层包括截断部和延伸部，所述截断部位于所述第一电极以外，所述延伸部位于所述第一电极背离所述驱动背板的表面，且具有露出所述第一电极的像素开口；所述像素开口的侧壁为沿背离所述驱动背板的方向扩张的坡面。
  11. 根据权利要求10所述的显示面板，其中，所述像素开口的侧壁的坡度角与所述第一截断槽的底面的坡度角之和不小于90°。
  12. 根据权利要求10所述的显示面板，其中，至少一部分所述像素开口的侧壁设有第二截断槽。
  13. 根据权利要求12所述的显示面板，其中，所述第一截断槽的最大深度大于所述第二截断槽的最大深度。
  14. 根据权利要求13所述的显示面板，其中，所述第三绝缘层的用于形成所述第一截断槽的侧壁的部分向所述驱动背板倾斜，且倾斜角度为第一倾斜角；
    所述第三绝缘层的用于形成所述第二截断槽的侧壁的部分向所述驱动背板倾斜，且倾斜角度为第二倾斜角；
    所述第一倾斜角大于所述第二倾斜角。
  15. 根据权利要求1-14任一项所述的显示面板，其中，所述第二电极在对应于所述第一电极的区域形成平坦部，且在对应于所述分隔槽的区域形成凹陷部，所述凹陷部与所述平坦部平滑过渡。
  16. 根据权利要求15所述的显示面板，其中，所述凹陷部的深度小于所述分隔槽的深度。
  17. 根据权利要求15所述的显示面板，其中，所述凹陷部的深度大于所述填充层的厚度。
  18. 根据权利要求1-14任一项所述的显示面板，其中，所述填充层与所述第一电极的侧壁接触。
  19. 根据权利要求15所述的显示面板，其中，所述发光层还包括多 层串联的发光子层，至少一所述发光子层通过电荷生成层与相邻的一所述发光子层串联；所述电荷生成层对应于所述第一电极的部分和对应于所述分隔槽的部分断开。
  20. 根据权利要求1-14任一项所述的显示面板，其中，所述填充层包括沿背离所述驱动背板的方向层叠的填充绝缘层和填充导电层，所述填充绝缘层与所述第一电极的侧壁接触，所述填充导电层与所述第一电极的侧壁间隔设置。
  21. 根据权利要求20所述的显示面板，其中，所述驱动背板包括像素区和位于所述像素区外的外围区；所述像素区具有驱动发光层发光的像素电路，所述外围区具有外围电路；
    所述第一电极层还包括转接环，所述转接环在所述驱动背板上的正投影位于所述外围区，且围绕于所述像素区外，所述转接环与所述外围电路连接，所述第二电极与所述转接环连接；所述转接环设有缺口；
    所述填充导电层包括主体部和连接部，所述主体部位于所述转接环内，且与所述转接环间隔设置；所述连接部与所述主体部连接，并由所述缺口穿出所述转接环，且与所述转接环间隔设置；所述连接部用于接收老化电压信号。
  22. 一种显示面板的制造方法，所述显示面板为权利要求20或21所述的显示面板，所述制造方法包括：
    形成驱动背板；
    在所述驱动背板一侧面形成包括间隔分布的多个第一电极的第一电极层；
    在所述驱动背板设有所述第一电极层的侧面形成露出各所述第一电极的像素定义层；所述像素定义层包括沿背离所述驱动背板的方向层叠的填充层和截断层，所述填充层的厚度小于所述第一电极层，且位于所述第一电极以外；
    对所述填充导电层施加老化电压信号，并持续指定时长；
    在所述截断层形成位于所述第一电极以外的分隔槽以及位于所述分隔槽的侧壁的第一截断槽；
    形成覆盖所述截断层和所述第一电极层的发光层；
    形成覆盖所述发光层的第二电极。
  23. 一种显示装置，其中，包括权利要求1-21任一项所述的显示面板。
PCT/CN2022/088548 2021-11-29 2022-04-22 显示装置、显示面板及其制造方法 WO2023092935A1 (zh)

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