WO2023089916A1 - Power conversion device and control method for power conversion device - Google Patents

Abstract

This power conversion device 101 comprises: a switching circuit RSC comprising switching elements Q1, Q2, a resonant capacitor Cr, and a transformer Tr that comprises a primary winding Tr1 connected in series to the resonant capacitor Cr; a gate driver circuit 2 that outputs a gate drive current to a gate terminal of each of the switching elements Q1, Q2 and controls the turning on and off of the switching elements Q1, Q2; a detection circuit 5 that detects a current I1 flowing through the switching circuit RSC; and a determination circuit 6 that determines a reversal of the polarity of the current detected by the detection circuit 5. The gate driver circuit 2 comprises a gate adjustment circuit that adjusts the gate drive current on the basis of determination results from the determination circuit 6.

Description

POWER CONVERSION DEVICE AND CONTROL METHOD OF POWER CONVERSION DEVICE

The present invention relates to a power conversion device and its control method, and for example, to a resonance type power conversion device including a plurality of switching elements, a capacitor, and a transformer, and its control method.

Resonance type power converters are described in Patent Documents 1 and 2, for example. Patent Literatures 1 and 2 describe resonance-type power converters capable of detecting or determining variations in resonance frequency.

JP 2017-184599 A Japanese Patent Application Laid-Open No. 2019-201455

A resonant power converter includes a plurality of switching elements, a capacitor, and a transformer having a primary winding connected in series with the capacitor. As a result of investigation by the present inventor, when the load of the resonance type power conversion device suddenly changes to, for example, a high load, the resonance frequency of the series resonance circuit configured by the capacitor and the primary winding changes to the frequency at which the multiple switching elements turn on and off. It was found that there was a problem that the current flowed through the switching element due to a deviation from the resonance (resonance deviation), resulting in an increase in surge voltage and noise. The study by the inventor will be described later with reference to the drawings.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power conversion device and a control method for the power conversion device that can suppress an increase in surge voltage and noise when an out-of-resonance occurs.
Other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

A brief outline of representative embodiments among the embodiments disclosed in the present application is as follows.

That is, the power conversion device includes a switching circuit including a plurality of switching elements, a capacitor, and a transformer having a primary winding connected in series with the capacitor, and outputs a gate drive current to the gate of the switching element. and a gate drive circuit for controlling on/off of the switching element, a detection circuit for detecting current flowing through the switching circuit, and a determination circuit for determining reversal of the polarity of the current detected by the detection circuit. Here, the gate drive circuit includes a gate adjustment circuit that adjusts the gate drive current based on the determination result of the determination circuit.

Among the inventions disclosed in the present application, to briefly explain the effects obtained by the representative embodiments, there is provided a power conversion device capable of suppressing an increase in surge voltage and noise when out-of-resonance occurs. can do.

1 is a circuit diagram showing a configuration of a power converter according to Embodiment 1; FIG. 2 is a block diagram showing the configuration of a gate drive circuit according to Embodiment 1; FIG. 2 is a circuit diagram showing a configuration of a gate output circuit according to Embodiment 1; FIG. 4 is a flowchart for explaining a control method according to Embodiment 1; 4 is a waveform diagram for explaining the operation of the power converter according to Embodiment 1. FIG. 4 is a waveform diagram for explaining the operation of the power converter according to Embodiment 1. FIG. 2 is a cross-sectional view showing the structure of a GaN-HEMT used in the power converter according to Embodiment 1; FIG. 8 is a circuit diagram showing the configuration of a gate output circuit according to Embodiment 2; FIG. FIG. 10 is a circuit diagram showing the configuration of a power conversion device according to Embodiment 3; FIG. 11 is a circuit diagram showing the configuration of a power conversion device according to Embodiment 4; FIG. 11 is a plan view showing a portion of a semiconductor chip according to a fourth embodiment; It is a circuit diagram of a power conversion device for explaining the study of the present inventor.

Embodiments will be described with reference to the drawings. It should be noted that the embodiments described below do not limit the invention according to the scope of claims, and all of the various elements and their combinations described in the embodiments are essential to the solution of the invention. Not necessarily.
Before describing the embodiments of the present invention, the problem of the power conversion device studied by the inventor will be described with reference to FIG. 12 .

FIG. 12 is a circuit diagram of a power conversion device for explaining the inventor's study. Hereinafter, in this specification, a high-efficiency LLC resonance type resonant power converter using a leakage inductor and an exciting inductor of a transformer and a capacitor coupled to the transformer will be described as an example of the power converter.

In FIG. 12, 100 denotes a power converter (hereinafter also referred to as a DC/DC converter). The DC/DC converter 100 includes a gate drive circuit 2 and a primary side circuit and a secondary side circuit to be described below, and converts the voltage of the DC power supply Vi supplied to the primary side circuit to the secondary side circuit. The coupled load 4 is fed with the converted DC voltage. The primary side circuit includes a half bridge circuit 1 composed of switching elements Q1 and Q2, a resonance capacitor (current resonance capacitor) Cr, and a transformer Tr. Further, the secondary side circuit includes diodes D1 and D2 and a rectifier circuit 3 configured by a smoothing capacitor Co.

The two switching elements Q1 and Q2 that make up the half bridge circuit 1 are driven by the gate drive circuit 2. That is, the gate drive circuit 2 alternately switches the switching elements Q1 and Q2 at a predetermined cycle while providing a dead time (a time during which both switching elements are in an OFF state). By alternately switching the switching elements Q1 and Q2 at a predetermined cycle, the value of the voltage output from the secondary side circuit is adjusted. In this case, the predetermined period for alternately switching the switching elements Q1 and Q2 is the operation period of the DC/DC converter 100 (in other words, the operation frequency of the DC/DC converter).

LLC resonance type DC/DC converter 100 utilizes a series resonance circuit composed of a resonance capacitor Cr, a leakage inductance (not shown) included in transformer Tr, and an exciting inductance, and voltages of switching elements Q1 and Q2 are controlled. Alternatively, when at least one of the currents is zero (“0”), zero voltage (current) switching is performed to turn on/off the switching elements Q1 and Q2. By performing zero-voltage switching, it is possible to reduce the power loss and the occurrence of switching noise during switching of the switching element.

However, if the voltage value of the DC power supply Vi on the input side or the load 4 on the output side fluctuates from the designed value, the resonance frequency of the series resonance circuit will fluctuate, and the operating frequency of the DC/DC converter 100 will deviate from the resonance frequency. may be lost. In this case, zero voltage switching cannot be achieved, resulting in an increase in power loss, generation of switching noise, destruction of switching elements, and the like. In the following description, the deviation of the operating frequency of the DC/DC converter from the resonance frequency of the series resonance circuit is also referred to as out-of-resonance.

Patent Documents 1 and 2 describe techniques for coping with fluctuations in the resonance frequency of a series resonance circuit. For example, in Patent Document 1, a current detection circuit is provided to detect the value of current flowing through a switching element. is determined to have changed and an abnormality has occurred. Further, in Patent Document 2, in the same resonance period, current values are detected at two or more points in time that are symmetrical about a half period of the resonance period, and if the current values differ by a predetermined value or more, the resonance frequency is detected. is determined to have changed and an abnormality has occurred.

With the techniques described in Patent Documents 1 and 2, the occurrence of an abnormality is detected, and when the occurrence of an abnormality is detected, for example, the switching element is forcibly turned off, and the operating frequency of the DC/DC converter is increased. can be avoided.

However, in this case, the switching element is forced to continue to be turned off during the period in which the resonance out-of-resonance occurs, that is, the period in which the voltage of the DC power supply Vi and the load 4 on the output side continue to be high. During this period, the DC/DC converter cannot perform power conversion properly.

If a configuration that forcibly turns off the switching element is not adopted in order to avoid out-of-resonance, an increase in power loss will occur. That is, in the DC/DC converter, when out of resonance occurs, the current flowing through one switching element (for example, Q1) that is on is reversed from positive to negative, and after the reversal, the switching element (Q1) is turned off, the switching element (Q1) is in a reverse conducting state, and when the other switching element (Q2) is turned on after the dead time has elapsed, a recovery current flows through the switching elements Q1 and Q2, resulting in a large Power loss occurs and switching element destruction may occur.

By using an element with a small recovery current in the event of reverse conduction as the switching element, it is possible to suppress the increase in power loss in the event of out-of-resonance and prevent the destruction of the switching element. As an example of a switching element with a small recovery current during reverse conduction, a high-speed recovery metal-oxide-semiconductor field effect transistor (MOSFET) or a gallium nitride (GaN)-based material is used. There is a high electron mobility transistor (High Electron Mobility Transistor: HEMT) and the like. A HEMT using a GaN-based material is hereinafter referred to as a GaN-HEMT.

In particular, since the GaN-HEMT does not include a body diode inside the element, the recovery current is theoretically zero. Therefore, in a DC/DC converter using a GaN-HEMT as a switching element, loss due to recovery current does not occur even if a resonance out-of-resonance occurs, and the occurrence of destruction of the switching element can be reduced. It is possible to operate the DC/DC converter even when the voltage value of Vi or the load on the output side is high.

By using a GaN-HEMT as a switching element, it is possible to eliminate the above-described effects of the body diode. Impact exists. That is, when out-of-resonance occurs, when one switching element (for example, Q1) becomes reverse conductive, the output capacitance of the switching element (Q1) is discharged, and when the other switching element (Q2) is turned on, switching The output capacitance of device (Q1) will be recharged. At this time, a current is generated that flows through the switching element (Q2) and the switching element (Q1) in order to recharge the output capacitance.

　The output capacity of GaN-HEMT is small, and the amount of stored charge is small compared to the recovery current, so there is little risk of increased power loss or destruction of switching elements. However, since power converters using GaN-HEMTs as switching elements are often operated at high frequencies, the amount of time change in current due to recharging of the output capacity (dI/dt: I is the output capacity current flowing through ) increases. This large amount of current change over time (dI/dr) causes a surge voltage and an increase in noise, and interferes with normal operation of the power converter.

Patent Documents 1 and 2 do not describe or recognize the surge voltage or noise increase caused by the time change of the current that recharges the output capacitance of the switching element when the resonance out occurs.

In order to solve the problems described above, the present inventors have made intensive studies and have come up with the configuration of the present embodiment. Hereinafter, this embodiment will be described with reference to the drawings.
(Embodiment 1)
<Overall Configuration of Power Converter>

FIG. 1 is a circuit diagram showing the configuration of the power converter according to Embodiment 1. FIG. In FIG. 1, 101 indicates a power converter. The power conversion device 101 is an LLC resonance type DC/DC converter including a half bridge circuit 1 using two switching elements.

The power conversion device 101 includes a half bridge circuit 1, a gate drive circuit 2, a current detection circuit (hereinafter also referred to as a detection circuit) 5, a current polarity reversal determination circuit (hereinafter also referred to as a determination circuit) 6, a resonance capacitor Cr, a primary It includes a transformer Tr composed of a winding Tr1 and secondary windings Tr2-1 and Tr2-2, and a rectifier circuit 3 composed of diodes D1 and D2 and a smoothing capacitor Co. In FIG. 1, T1 and T2 indicate input terminals of the power conversion device 101, and T3 and T4 indicate output terminals of the power conversion device 101. FIG. Input terminals T1 and T2 of the power converter 101 are connected to an external DC power supply Vi as shown in FIG. 1, and a load 4 is connected to output terminals T3 and T4 as shown in FIG. . The DC power supply Vi is, for example, a battery, an AC/DC (alternating current/direct current) converter, or the like.

The half bridge circuit 1 is connected between both terminals of the DC power source Vi, as shown in FIG. The half bridge circuit 1 includes switching elements Q1 and Q2 connected in series between both terminals (between input terminals T1 and T2) of a DC power supply Vi. The switching elements Q1 and Q2 are composed of GaN-HEMTs formed on a silicon substrate of one semiconductor chip (the same semiconductor chip), although not particularly limited.

In FIG. 1, Cp1 and Cp2 indicated by broken lines indicate parasitic capacitors of switching elements Q1 and Q2. One terminal of the parasitic capacitor Cp1 is connected to the source terminal of the switching element Q1, and the other terminal is connected to the drain terminal of the switching element Q1. This parasitic capacitor Cp1 corresponds to the output capacitance of the switching element Q1. Similarly, the parasitic capacitor Cp2 is connected between the source terminal and the drain terminal of the switching element Q2, and the parasitic capacitor Cp2 corresponds to the output capacitance of the switching element Q2. The parasitic capacitors Cp1 and Cp2 are hereinafter also referred to as output capacitors Cp1 and Cp2.

In the half bridge circuit 1, the drain terminal of the switching element Q1 is connected to the DC power supply Vi through the input terminal T1. A source terminal of the switching element Q1 and a drain terminal of the switching element Q2 are connected. A source terminal of the switching element Q2 is connected to the DC power supply Vi through an input terminal T2. Gate terminals of the switching elements Q1 and Q2 are connected to the gate drive circuit 2 . Between the source terminal of the switching element Q2 and the node where the source terminal of the switching element Q1 and the drain terminal of the switching element Q2 are connected, the detection circuit 5, the resonance capacitor Cr and the primary of the transformer Tr are connected. The winding Tr1 is connected in series. The secondary side of the transformer Tr is composed of secondary windings Tr2-1 and Tr2-2. Although not particularly limited, the secondary windings Tr2-1 and Tr2-2 have the same number of turns and are connected in series so as to have the same winding direction. Note that the ● mark in FIG. 1 indicates the polarity of the transformer Tr.

The rectifier circuit 3 is composed of diodes D1 and D2 and a smoothing capacitor Co, and the cathode terminals of the diodes D1 and D2 and one terminal of the smoothing capacitor Co are connected. The other terminal of smoothing capacitor Co is connected to a node at which one terminals of secondary windings Tr2-1 and Tr2-2 of transformer Tr are connected to each other. The other terminals of secondary windings Tr1 and Tr2-2 of transformer Tr are connected to anode terminals of diodes D1 and D2, respectively. The terminals of smoothing capacitor Co are connected to load 4 via output terminals T3 and T4.

The detection circuit 5 is composed of a current sensor. The current sensor is composed of, for example, a shunt resistor, a Hall element, or a Rogowski coil. The detection circuit 5 detects the current value of the current I1 flowing through the resonance switching circuit RSC (hereinafter simply referred to as the switching circuit) including the switching elements Q1 and Q2, the resonance capacitor Cr, and the primary winding Tr1 of the transformer Tr. do. The current value detected by the detection circuit 5 is output to the determination circuit 6 as an analog value. Note that in the first embodiment, the detection circuit 5 is also provided in the resonant switching circuit RSC in order to detect the current value of the current I1.

The determination circuit 6 is composed of a comparator and an edge detector (not shown), although not particularly limited. The comparator is configured by, for example, a comparator, and the edge detector is configured by, for example, an edge detection circuit configured by combining logic circuits or an edge detector using a microprocessor. The comparator is supplied with the input (analog current value) from the detection circuit 5 and the reference value corresponding to the current value "0 (zero)", and the comparator compares the analog current value and the reference value. A comparison result is output to the edge detector as a digital value. The edge detector captures changes in the input digital value as falling and rising signals, and outputs them as determination signals indicating the polarity (current polarity) of the current I1 of the resonant switching circuit flowing through the detection circuit 5 to the gate drive circuit. Output to 2.

For example, when the analog current value from the detection circuit 5 drops from a high current value to a reference value or less, the comparator in the determination circuit 6 changes the digital value from "1" to "0". The edge detector in the determination circuit 6 captures a change from a digital value of "1" to "0" as a signal falling, indicating that the current polarity of the current I1 of the resonant switching circuit RSC has been reversed from positive to negative. Outputs a judgment signal. On the other hand, when the analog current value from the detection circuit 5 exceeds the reference value from a value lower than the reference value, the comparator in the determination circuit 6 changes the digital value from "0" to "1". Let The edge detector in the determination circuit 6 captures the change of the digital value from "0" to "1" as the rise of the signal, and determines that the current polarity of the current I1 of the resonant switching circuit RSC has been reversed from negative to positive. Output a signal.

A Schmitt trigger or a low-pass filter may be provided on the input side to the comparator in the determination circuit 6. Noise contained in the output from the detection circuit 5 can be removed by this Schmitt trigger or low-pass filter.

The gate drive circuit 2 drives the switching elements Q1 and Q2 so as to alternately turn on and off at an operation cycle determined by the operation frequency of the power converter 101 . When driving the switching elements Q1 and Q2, the gate drive circuit 2 adjusts the drive capability based on the determination signal from the determination circuit 6. FIG. The gate drive circuit 2 will now be described in detail with reference to the drawings.
<<Configuration of Gate Drive Circuit>>

FIG. 2 is a block diagram showing the configuration of the gate drive circuit according to the first embodiment. As shown in FIG. 2, the gate drive circuit 2 includes a control circuit 21 and two gate output circuits 22 corresponding to the switching elements Q1 and Q2.

The control circuit 21 is composed of, for example, a microprocessor, a programmable gate array (for example, a so-called FPGA), or the like, and includes gates necessary for alternately turning on and off the switching elements Q1 and Q2 at the operating frequency of the power converter 101. Generate a signal. Further, the control circuit 21 inputs the determination signal (current reversal positive/negative and current reversal negative/positive) output from the determination circuit 6 via the input terminals T21 and T22, and switches the gate drive currents of the switching elements Q1 and Q2. to generate an output switching signal for Since the gate drive currents of the switching elements Q1 and Q2 are adjusted by switching the gate drive currents, the control circuit 21 that generates the output switching signal can be regarded as a gate adjustment circuit.

The gate output circuit 22 is provided for each of the switching elements Q1 and Q2 and outputs a gate output signal according to the gate signal and the output switching signal input from the control circuit 21 . A gate output signal output from the gate output circuit 22 is supplied to the gate terminals of the switching elements Q1 and Q2 via the output terminals T23 and T24. In FIG. 2, reference numeral 22-1 indicates a gate output circuit that supplies gate output signal 1 to the gate terminal of switching element Q1, and reference numeral 22-2 indicates gate output signal 2 to the gate terminal of switching element Q2. Fig. 3 shows a gate output circuit for supplying;
<<<Configuration of Gate Output Circuit>>>

Next, the configuration of the gate output circuit will be described with reference to the drawings. Since the gate output circuit 22-1 corresponding to the switching element Q1 and the gate output circuit 22-2 corresponding to the switching element Q2 have the same configuration, they will be described as the gate output circuit 22 below.
3 is a circuit diagram showing a configuration of a gate output circuit according to Embodiment 1. FIG.

The gate output circuit 22 includes P-channel field effect (hereinafter also referred to as PMOS) transistors PTr1 and PTr2, N-channel field effect (hereinafter also referred to as NMOS) transistors NTr, resistance elements Rgon1, Rgon2 and Rgoff, and an inverter. It comprises gates inv1 and inv2 and OR gates or1 and or2. Here, the electrical resistance value of the resistive element Rgon2 is set to be greater than the electrical resistance value of the resistive element Rgon1.

The source terminals of the PMOS transistors PTr1 and PTr2 are connected to the voltage line Vgon. The voltage (Vg,on) applied to the voltage line Vgon is a predetermined voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn on the switching elements Q1 and Q2. A source terminal of the NMOS transistor NTr is connected to the voltage line Vgoff. The voltage (Vg, off) applied to the voltage line Vgoff is the voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn off the switching elements Q1 and Q2. The voltages (Vg, on) and (Vg, off) are generated from the DC power supply Vi shown in FIG. 1, although not particularly limited.

The drain terminals of the PMOS transistors PTr1 and PTr2 are connected to one terminals of the resistance elements Rgon1 and Rgon2, respectively, and the other terminals of the resistance elements Rgon1 and Rgon2 are connected to the output terminal T223. A drain terminal of the NMOS transistor NTr is connected to one terminal of the resistance element Rgoff, and the other terminal of the resistance element Rgoff is connected to the output terminal T223.

The gate signal output from the control circuit 21 is supplied to the input of the inverter gate inv2 via the input terminal T222. The output of the inverter gate inv2 is connected to one input of the OR gates or1 and or2, and also connected to the gate terminal of the NMOS transistor NTr. The output switching signal output from the control circuit 21 is connected to the other input of the OR gate or1 via the input terminal T221 and to the other input of the OR gate or2 via the inverter gate inv1. Outputs of OR gates or1 and or2 are connected to gate terminals of PMOS transistors PTr1 and PTr2, respectively.

Therefore, the PMOS transistors PTr1 and PTr2 are turned off while the gate signal is at the low level ("0"). On the other hand, during this period, the NMOS transistor NTr is turned on. In this case, the resistance element Rgoff is connected between the voltage line Vgoff and the gate terminal of the switching element Q1 or Q2 via the NMOS transistor NTr and the output terminal T223. That is, the resistance element Rgoff corresponds to the gate resistance of the switching element, and the voltage (Vg,off) through the gate resistance (resistance element Rgoff) is applied to the switching element Q1 or Q2 as the gate-off voltage. The switching element Q1 or Q2 is turned off.

On the other hand, the NMOS transistor NTr is turned off while the gate signal is at high level ("1"). During this period, when the output switching signal is low level (“0”), the PMOS transistor PTr1 is turned on, and when the output switching signal is high level (“1”), the PMOS transistor PTr2 is turned on. Therefore, in the period when the gate signal is high level, when the output switching signal is low level, the resistance element Rgon1 corresponds to the gate resistance of the switching element, and the switching element Q1 or Q2 is connected through the gate resistance (resistance element Rgon1). The resulting voltage (Vg,on) is applied to the switching element Q1 or Q2 as a gate-on voltage, and the switching element Q1 or Q2 is turned on. At this time, in the switching element Q1 or Q2 that is in the ON state, the current of the gate output signal (high level gate current) supplied to the gate terminal of the switching element Q1 or Q2 through the gate resistance (resistive element Rgon1). drive current) flows.

Further, when the output switching signal is at a high level (“1”) while the gate signal is at a high level (“1”), the resistance element Rgon2 corresponds to the gate resistance of the switching element. The voltage (Vg,on) through (resistive element Rgon2) is applied to switching element Q1 or Q2 as a gate-on voltage.In this case also, switching element Q1 or Q2 is turned on.However, at this time, switching The gate output signal current (gate drive current) supplied to the gate terminal of the element Q1 or Q2 is the gate output signal current (low level gate drive current) determined by the resistor element Rgon2 because the resistor element Rgon2 functions as a gate resistor. Therefore, at this time, in the switching element Q1 or Q2 that is turned on, a drain current corresponding to the gate drive current determined by the resistance element Rgon2 flows.

In the gate output circuit 22 according to Embodiment 1, the gate resistances of the switching elements Q1 and Q2 that are turned on can be switched by the output switching signal. By switching the gate resistance, a gate drive current determined by the switched gate resistance is supplied to the gate terminals of the switching elements Q1 and Q2. drain current flows. That is, a gate drive current having a level corresponding to the resistance element Rgon1 or Rgon2 corresponding to the gate resistance is supplied to the gate terminal of the switching element, and a drain current corresponding to the gate drive current is output from the switching element. As described above, the electrical resistance value of the resistance element Rgon2 is greater than the electrical resistance value of the resistance element Rgon1. Therefore, when the output switching signal is at a high level, the gate output circuit 22 outputs a low level gate drive current to the switching element Q1. , Q2 to switch the drain currents of the switching elements Q1 and Q2 to a low level.

During the period in which the gate signal is at high level, the inverter gate inv1, the OR gates or1 and or2, and the PMOS transistors PTr1 and PTr2 form a switching circuit that selects a resistance element from the resistance elements Rgon1 and Rgon2 according to the output signal. can be considered to be In this case, the selected resistive element will be connected between the predetermined voltage (Vg,on) and the gate terminal of the switching element.
<Operation of power converter>

First, the control method executed in the power converter according to Embodiment 1 will be described using the drawings. FIG. 4 is a flowchart for explaining a control method according to Embodiment 1. FIG.

In step S1, the control circuit 21 shown in FIG. 2 outputs the gate output signal 1 and the gate output signal 2 to turn on/off the switching elements Q1 and Q2 shown in FIG. Next, steps S2, S3 and S4 are sequentially executed, and these steps S2 to S4 are executed while switching element Q1 or Q2 is on.
Step S2 is a current detection step in which the detection circuit 5 of FIG. 1 detects the current I1 flowing through the resonant switching circuit RSC.

In step S3, the determination circuit 6 determines the polarity of the current I1 based on the current I1 detected in step S2, and supplies the determination result to the control circuit 21 as a determination signal. That is, step S3 is a polarity determination step.

When it is determined in step S3 that the polarity is reversed (Y), the control circuit 21 generates an output switching signal and switches the gate drive current of the switching element. Since the gate drive current is adjusted by switching the gate drive current, step S4 is a step of adjusting the drive current.

When it is determined in step S3 that the polarity is not reversed (N) and when step S4 ends, step S1 is executed again. That is, steps S1 to S3 are repeated.

In the power conversion device according to Embodiment 1, when it is determined in step S3 that the polarity is reversed, processing is performed assuming that out-of-resonance has occurred. On the other hand, when it is determined in step S3 that the polarity is not reversed, the processing is performed assuming that no resonance has occurred.

Although not particularly limited, step S4 (adjustment step) according to Embodiment 1 includes two steps. That is, in step S4, when it is determined that the polarity is reversed, a step of adjusting (switching) the gate drive current to a low level is performed. and adjusting (switching) the gate drive current to a level higher than the low level after a predetermined period (output switching period) after switching the gate drive current to the low level.
Next, the case where the resonance has not occurred and the case where the resonance has occurred will be described.
<<When no out-of-resonance occurs>>

First, the case where the load of the power conversion device 101 is not high and no out-of-resonance has occurred will be described. FIG. 5 is a waveform diagram for explaining the operation of the power converter according to Embodiment 1. FIG. Description will be made below with reference to FIGS. 1 to 3 and 5. FIG.

FIG. 5 shows the waveforms of the gate output signal 1 and the gate output signal 2 output by the gate drive circuit 2 and the primary winding Tr1 of the transformer Tr detected by the detection circuit 5 in order to control the half bridge circuit 1. The waveform of the current I1 flowing through the resonant switching circuit RSC containing is shown. Further, FIG. 5 shows waveforms of voltages Vds1 and Vds2 applied between the drain terminals and the source terminals of the switching elements Q1 and Q2, and a current (drain current) flowing from the drain terminal to the source terminal of the switching elements Q1 and Q2. Current) Id1 and Id2 waveforms are shown. Voltage Vds1 and current Id1 are the voltage and current of switching element Q1, and voltage Vds2 and current Id2 are the voltage and current of switching element Q2.

The detection circuit 5 detects a current with positive (+) polarity in the direction of flow from the left side to the right side, as indicated by the arrow in FIG. A gate output signal 1 output from the gate drive circuit 2 is an output signal for controlling on/off of the switching element Q1, and a gate output signal 2 is an output signal for controlling on/off of the switching element Q2. Control circuit 21 forming gate drive circuit 2 generates gate signals to complementarily drive switching elements Q1 and Q2 including dead times td1 and td2. Dead times td1 and td2 are periods during which both switching elements Q1 and Q2 are in the off state.

First, at time t1, when the switching element Q2 is turned off and the switching element Q1 is turned on by the gate output signal, the DC power supply Vi, the switching element Q1, the detection circuit 5, the resonance capacitor Cr, and the primary winding Tr1 of the transformer Tr are turned on. A current I1 of positive (+) polarity flows through a resonant switching circuit RSC that includes .

At subsequent time t2, when the switching element Q1 is turned off and dead time td1 is entered, the switching element Q2 is reversely conducted, and the current flowing through the primary winding Tr1 of the transformer Tr is commutated to the switching element Q2. After that, by turning on the switching element Q2 in a reverse conducting state, so-called zero voltage switching is performed in which the voltage applied between the source terminal and the drain terminal of the switching element Q2 is substantially zero. After that, due to LC resonance due to the inductance included in the transformer Tr and the capacitance of the resonance capacitor Cr, the polarity of the current I1 flowing through the resonance switching circuit RSC including the primary winding Tr1 of the transformer Tr changes from positive (+) to negative (-). and reverse.

Next, at time t3, when the switching element Q2 is turned off to enter the dead time td2, the switching element Q1 reversely conducts, and the current flowing through the primary winding Tr1 of the transformer Tr is commutated to the switching element Q1. Zero-voltage switching is performed by turning on the switching element Q1 in a reverse conduction state, and thereafter, due to LC resonance, the current I1 flowing through the resonant switching circuit RSC including the primary winding Tr1 of the transformer Tr changes from negative (-) to positive. Reverse to (+).

Since the gate output signal described above is generated periodically with a period determined by the operating frequency of the power conversion device 101, the operations from times t1 to t3 described above are repeated. A current is generated in the secondary winding Tr2-1 or Tr2-2 according to a change in the current I1 flowing through the primary winding Tr1 of the transformer Tr, converted to a direct current by the rectifying circuit 3, and supplied to the load 4. .
<<When out of resonance occurs>>

FIG. 6 is a waveform diagram for explaining the operation of the power converter according to Embodiment 1. FIG. FIG. 6 is similar to FIG. 5, and similarly to FIG. 5, FIG. Voltages Vds1 and Vds2 between the drain and source terminals and drain currents Id1 and Id2 of the switching elements Q1 and Q2 are shown. FIG. 6 is different from FIG. 5 in that it shows a case where the load 4 suddenly changes to a high load and out-of-resonance occurs while the power converter 101 is operating. be.

At high load, during the period (time t1 to t2) in which the switching element Q1 is in the ON state, at a certain time (for example, time t12), LC resonance due to the inductance included in the transformer Tr and the capacitance of the resonance capacitor Cr causes The polarity of the current flowing through the resonant switching circuit RSC including the primary winding Tr1 of the transformer Tr is reversed from positive to negative as shown in FIG. 6, and the switching element Q1 is reversely conducting. After that, when the switching element Q1 is turned off and the dead time td1 is entered, the switching element Q2 is turned off, so that no current flows, and the switching element Q1 continues the reverse conduction state to conduct current. At this time, the output capacitance Cp1 (FIG. 1) of the switching element Q1 is discharged.

At subsequent time t2, when the switching element Q2 is turned on (transitioned), the current flowing through the switching element Q1 is commutated to the switching element Q2. charging occurs. Since the output capacitance Cp1 is a capacitor connected between the source terminal and the drain terminal of the switching element Q1, during the recharging period during which the output capacitance Cp1 is recharged, the drain terminal of the switching element Q1 and the A current (current for recharging the output capacitor Cp1) flows between the source terminals. At this time, since the switching element Q2 transitions to the ON state, a through current is generated that flows through the switching elements Q1 and Q2.

Since this through current is a current that flows through the switching elements Q1 and Q2, the time change in the current value of the through current is determined by the speed at which the switching element Q2 is turned on.

Next, the operation of turning off the switching element Q2 and turning on the switching element Q1 after the dead time td2 has elapsed is a complementary operation to the above. That is, at the time (t23) before the switching element Q2 transitions to the OFF state, the LC resonance causes the polarity of the current I1 flowing through the resonant switching circuit RSC including the primary winding Tr1 of the transformer Tr to change from negative to positive. and reverse. In this case, the switching element Q2 is in a reverse conducting state, the output capacitance Cp2 of the switching element Q2 is discharged, and the output capacitance Cp2 is recharged by the transition of the switching element Q1 to the ON state. Therefore, when switching element Q1 transitions to the ON state, a through current is generated that flows through switching elements Q1 and Q2. The time change of the current value of the through current at this time is also determined by the speed at which the switching element Q1 is turned on.

In Embodiment 1, the control circuit 21 forming the gate drive circuit 2 executes steps S2 to S4 shown in FIG. 4 during the ON period of the switching element Q1. That is, the control circuit 21 is connected to the switching element Q2 to be turned on when a determination signal indicating that the polarity of the current I1 is inverted (in this case, from positive to negative) is input from the determination circuit 6. output switching signal to the gate output circuit 22-2. When the output switching signal is input, the gate output circuit 22-2 switches the gate resistance when driving the switching element Q2 to the ON state from the resistance element Rgon1 to the resistance element Rgon2 to increase the value of the gate resistance. As a result, the gate driving current for the switching element Q2 decreases, the drain current of the switching element Q2 also decreases, and the driving current of the switching element Q2 is adjusted to decrease.

This adjustment lowers the drain current, thereby lowering the speed at which the switching element Q2 is turned on. Therefore, even when the load 4 becomes a high load during the period when the switching element Q1 is in the ON state, the amount of time change in the through current generated when the switching element Q2 is turned on can be reduced, and the surge can be prevented. It is possible to suppress the generation of voltage and noise.

The control circuit 21 also executes steps S2 to S4 shown in FIG. 4 during the ON period of the switching element Q2. That is, when the control circuit 21 receives a determination signal indicating that the polarity of the current I1 is inverted (in this case, the polarity is inverted from negative to positive), the control circuit 21 controls the gate output circuit 22-1 connected to the switching element Q1. Outputs the output switching signal. When the output switching signal is input, the gate output circuit 22-1 switches the gate resistance when driving the switching element Q1 to the ON state from the resistance element Rgon1 to the resistance element Rgon2 to increase the value of the gate resistance. As a result, the gate driving current for the switching element Q1 decreases, the drain current of the switching element Q1 also decreases, and the driving current of the switching element Q1 is adjusted to decrease.

As the drain current decreases due to the adjustment, the speed at which the switching element Q1 transitions to the ON state decreases. Therefore, even when the load 4 becomes a high load during the period when the switching element Q2 is in the ON state, the amount of time change in the through current generated when the switching element Q1 is turned on can be reduced and the surge can be prevented. It is possible to suppress the generation of voltage and noise.

In FIG. 6, the drain current change Id_1 indicated by the dashed line indicates the change in the drain current when the resistive element Rgon1 is used as the gate resistance without switching the resistive element, and the drain current change Id_2 indicated by the solid line is 4 shows changes in drain current when the gate resistance is switched to the resistance element Rgon2 according to the first embodiment. A voltage change Vsg_1 indicated by a dashed line indicates changes in the voltages Vds1 and Vds2 when the resistive element Rgon1 is used as the gate resistance without switching the resistive elements. 1 shows changes in voltages Vds1 and Vds2 when the gate resistance is switched to the resistance element Rgon2 according to the first form of FIG. These voltage changes Vsg_1 and Vsg_2 become surge voltage and noise.

According to Embodiment 1, the time during which the drain current change occurs becomes longer, but the peak value can be reduced. As a result, as shown in FIG. 6, the voltage change Vsg_2 becomes smaller than the voltage change Vsg_1, and the generated surge voltage and noise can be suppressed.

In the control circuit 21 according to the first embodiment, a period (output switching period) during which the output switching signal is output to the gate output circuits 22 (22-1, 22-2) is set in advance. During this set output switching period, the gate output circuit 22 uses the resistance element Rgon as the gate resistance and outputs a low gate drive current. In the first embodiment, the output switching period is longer than the period from when it is determined that the polarity of the current I1 is reversed to when the switching elements Q1 and Q2 are turned on and off, and is the period during which the switching elements Q1 and Q2 are turned on and off. It is set shorter than half (half cycle).

Taking FIG. 6 as an example, the output switching period is set longer than the time from time t12 to time t2 and shorter than the time from time t1 to time t2. By setting the output switching period, the gate output from the output circuit when transitioning the switching element to the ON state is performed in the cycle in which the high load of the load 4 is detected as the polarity reversal of the current I1. When the drive current is suppressed to a low value (low level) and the switching element is next turned on and off, the resistance element Rgon1 is used as the gate resistor to raise the gate drive current to a high level, enabling high-speed switching. Become.
<<Structure of Switching Element>>

In Embodiment 1, GaN-HEMTs are used as the switching elements Q1 and Q2 as described above. Here, an example of GaN-HEMT will be explained. FIG. 7 is a cross-sectional view showing the structure of the GaN-HEMT used in the power converter according to the first embodiment.

In FIG. 7, 500 indicates the GaN-HEMT. The GaN-HEMT includes a substrate 501, a buffer layer 502 formed on the substrate 501, a gallium nitride (GaN) layer 503 formed on the buffer layer 502, and an aluminum gallium nitride layer 503 formed on the gallium nitride layer 503. (AlGaN) layer 504, a gate electrode 507 formed at a predetermined position on the aluminum gallium nitride layer 504 via a P-type gallium nitride (P-GaN) layer 505, and on the aluminum gallium nitride layer 504, It has a gate electrode 507 and a source electrode 506 and a drain electrode 508 formed at separated positions.

The gate electrode 507 corresponds to the gate terminals of the switching elements Q1 and Q2, and the source electrode 506 and drain electrode 508 correspond to the source terminals and drain terminals of the switching elements Q1 and Q2. Also, the output capacitance (Cp1) of the switching element (for example, Q1) is a parasitic capacitor with the source electrode 506 as one terminal and the drain electrode 508 as the other terminal. That is, the output capacitor (Cp1) is connected between the source terminal and the drain terminal of the switching element (Q1).

As shown in FIG. 7, since no body diode is formed in the GaN-HEMT, it is possible to prevent loss due to recovery current flowing through the body diode. Therefore, according to Embodiment 1, even if the load 4 becomes a high load and out of resonance occurs, loss due to recovery current does not occur, so the possibility of breaking down the element (GaN-HEMT) is reduced. can do.

According to the first embodiment, even if the load 4 is in a high load state and out of resonance occurs, the time change dI/dt of the current flowing through the switching elements Q1 and Q2 forming the half bridge circuit 1 is It is possible to suppress surge voltage and increase noise. Therefore, stable operation of the power converter 101 is possible.

In the first embodiment, the configuration using field effect transistors as shown in FIG. 3 has been described as the gate output circuit 22, but instead of the field effect transistors, GaN-HEMTs are used similarly to the switching elements. You may do so.
Also, the GaN-HEMTs forming the switching elements Q1 and Q2 and the detection circuit 5 may be formed on the semiconductor substrate of the same semiconductor chip.
(Embodiment 2)

In the second embodiment, gate output circuit 22 shown in FIG. 2 is modified. FIG. 8 is a circuit diagram showing the configuration of the gate output circuit according to the second embodiment. The power converter according to the second embodiment differs from the power converter according to the first embodiment in that the configuration of the gate output circuit is changed from that shown in FIG. 3 to that shown in FIG. This is the point. Therefore, only the gate output circuit will be described below unless necessary for the description.
Unlike the first embodiment, the gate output circuit according to the second embodiment uses a current mirror circuit to switch the gate driving current.

In FIG. 8, 22a indicates a gate output circuit. The gate output circuit 22a includes a PMOS transistor PTr1, a current mirror circuit CM configured by PMOS transistors PTr-CM1 and PTr-CM2, a voltage generation circuit Vref that outputs a voltage value corresponding to an input, an operational amplifier OPref, and an NMOS transistor. It includes transistors NTr and NTr-ref, resistance elements Rref and Rgoff, and an inverter gate inv.

The source terminals of the PMOS transistors PTr-CM1 and PTr-CM2 forming the current mirror circuit CM are connected to the voltage line Vgon. The voltage applied to the voltage line Vgon is the voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn on the switching elements Q1 and Q2 (FIG. 1). Gate terminals of the PMOS transistors PTr-CM1 and PTr-CM2 are connected to each other and to the drain terminal of the PMOS transistor PTr-CM1. The drain terminal of the PMOS transistor PTr-CM1 is connected to the drain terminal of the NOMS transistor NTr-ref. A drain terminal of the PMOS transistor PTr-CM2 is connected to the output terminal T223.

The source terminal of the PMOS transistor PTr1 is connected to the voltage line Vgon, and its drain terminal is connected to the drain terminal of the NMOS transistor NTr-ref. A source terminal of the NMOS transistor NTr is connected to the voltage line Vgoff. The voltage applied to the voltage line Vgoff is the voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn off the switching elements Q1 and Q2. A drain terminal of the NMOS transistor NTr is connected to one terminal of the resistance element Rgoff, and the other terminal of the resistance element Rgoff is connected to the output terminal T223.

The output of the voltage generating circuit Vref is connected to the non-inverting input terminal (+) of the operational amplifier OPref. The inverting input terminal (-) of the operational amplifier OPref is connected to the source terminal of the NMOS transistor NTr-ref, and its output terminal is connected to the gate terminal of the NMOS transistor NT-ref. A source terminal of the NMOS transistor NTr-ref is connected to one terminal of the resistance element Rref, and the other terminal of the resistance element Rref is connected to the voltage line Vgoff. Therefore, the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref is equal to the ratio (output voltage/Rref) of the output voltage of the voltage generation circuit Vref and the resistance value of the resistance element Rref. Since the resistance value of the resistance element Rref is fixed, the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref has a value proportional to the output voltage of the voltage generation circuit Vref.

A gate signal output from the control circuit 21 (FIG. 2) is supplied to the gate terminal of the PMOS transistor PTr1 via the input terminal T222 and to the input of the inverter gate inv. The output of the inverter gate inv is connected to the gate terminal of the NMOS transistor NTr. The output switching signal output from the control circuit 21 is supplied as an input to the voltage generation circuit Vref via the input terminal T221. Since the output switching signal is supplied as an input, the voltage generation circuit Vref generates a lower voltage when the output switching signal is at high level (“1”) than when the output switching signal is at low level (“0”). It works to output.

When the gate signal output from the control circuit 21 (FIG. 2) is at the low level (“0”), the PMOS transistor PTr1 is turned on, so the voltage between the drain terminal and the source terminal of the PMOS transistor PTr-CM1 is almost zero. becomes zero. Since the drain terminal and gate terminal of the PMOS transistor PTr-CM1 are connected to each other, the PMOS transistor PTr-CM1 is turned off, and a current flows between the source terminal and the drain terminal of the PMOS transistor PTr-CM2 that constitutes the current mirror circuit CM. does not flow. At this time, the output of the inverter gate inv becomes high level (“1”), so the NMOS transistor NTr is turned on. Therefore, the resistance element Rgoff functions as a gate resistance, and a gate-off voltage is output to the switching element Q1 or Q2 to turn it off.

On the other hand, while the gate signal output from the control circuit 21 is at high level ("1"), the output of the inverter gate inv is at low level ("0"), so the NMOS transistor NTr is turned off. At this time, the high-level gate signal turns off the PMOS transistor PTr, so that the current mirror circuit CM operates, and a current proportional to the current flowing from the source terminal to the drain terminal of the PMOS transistor PTr-CM1 flows to the PMOS transistor PTr-CM1. It flows from the source terminal of PTr-CM2 to the drain terminal. Since the PMOS transistor PTr-CM1 and the NMOS transistor NTr-ref are connected in series, the current flowing from the source terminal to the drain terminal of the PMOS transistor PTr-CM1 flows from the drain terminal to the source terminal of the NMOS transistor NTr-ref. equal to the current. Therefore, a current proportional to the output voltage of the voltage generation circuit Vref is output to the gate terminal of the switching element Q1 or Q2 via the output terminal T223. When the output switching signal is at a high level (“1”), the output voltage of the voltage generation circuit Vref is lower than when the output switching signal is at a low level (“0”). The gate drive current output from the gate drive circuit 2 (FIG. 2) including the circuit 22a is switched to a low level.

In FIG. 8, a current circuit that outputs a current according to the level of the output switching signal supplied to the input terminal T221 is formed by the voltage generation circuit Vref, the operational amplifier OPref, the NMOS transistor NTr-ref, and the resistance element Rref. can be considered configured. In this case, a current proportional to the current output from the current circuit is output from the current mirror circuit CM as a gate drive current to the gate terminal of the switching element Q1 or Q2.

According to the second embodiment, the level of the gate driving current output from the gate output circuit 22a can be switched according to the output switching signal. As in the first embodiment, when out-of-resonance occurs in the power converter, the control circuit 21 of the gate drive circuit 2 generates an output switching signal according to the output of the determination circuit 6 (FIG. 1). , it is possible to suppress the amount of change in the through current with time, suppressing the occurrence of surge voltage and noise. Furthermore, according to the second embodiment, resistance elements corresponding to resistance elements Rgon1 and Rgon2 shown in FIG. 3 are not required, and power loss in these resistance elements can be reduced.

When the level of the gate drive current output from the gate output circuit is increased more than two levels, the gate output circuit 22 shown in FIG. It is necessary to increase PMOS transistors (corresponding to PTr1 and PTr2 in FIG. 3), resistance elements (corresponding to Rgon1 and Rgon2), and OR gates (corresponding to or1 and or2) controlling the gates of the PMOS transistors. In contrast, according to the second embodiment, the output voltage of the voltage generating circuit Vref can be multi-staged (three or more stages), so that it can be realized with a simple configuration. In addition, it becomes possible to quickly switch the output of the gate drive current according to the output switching signal, and it becomes possible to operate the power converter at a high operating frequency. Also in the second embodiment, the transistors forming the gate output circuit 22a are not limited to field effect transistors, and may be GaN-HEMTs, for example.
(Embodiment 3)

FIG. 9 is a circuit diagram showing the configuration of the power converter according to Embodiment 3. FIG. Since FIG. 9 is similar to FIG. 1, differences will be mainly described. The main difference is that the power converter shown in FIG. 9 uses a full bridge circuit instead of a half bridge circuit.

In FIG. 9, 101a indicates the power converter according to the third embodiment. The power converter 101a includes a full bridge circuit 7 instead of the half bridge circuit 1 (FIG. 1). That is, the power conversion device 101a includes a full bridge circuit 7, a gate drive circuit 2, a detection circuit 5, a determination circuit 6, a resonance capacitor Cr, a primary winding Tr1 and secondary windings Tr2-1 and Tr2-2. A rectifier circuit 3 including a transformer Tr, diodes D1 and D2, and a smoothing capacitor Co is provided. An external DC power supply Vi is connected to input terminals T1 and T2, and a load 4 is connected to output terminals T3 and T4. Also in Embodiment 3, the DC power source Vi is a device that supplies a DC power source, such as a battery or an AC/DC converter.

A full bridge circuit 7 is connected between both terminals of the DC power supply Vi via input terminals T1 and T2. In the full bridge circuit 7, the switching elements Q1 and Q2 are connected in series, and the switching elements Q3 and Q4 are connected in series. The switching elements Q1 to Q4 are composed of, for example, GaN-HEMTs formed on a silicon substrate of a semiconductor chip. In the full bridge circuit 7, the drain terminals of the switching elements Q1 and Q3 are connected to the DC power source Vi through the input terminal T1. A source terminal of the switching element Q1 and a drain terminal of the switching element Q2 are connected, and a source terminal of the switching element Q3 and a drain terminal of the switching element Q4 are connected. Source terminals of the switching elements Q2 and Q4 are connected to the DC power supply Vi through the input terminal T2.

The gate terminals of the switching elements Q1 and Q4 are connected to one gate output of the gate drive circuit 2, eg, T23 in FIG. Gate terminals of switching elements Q2 and Q3 are connected to the other gate output of gate drive circuit 2 (T24 in FIG. 2). Between a node where the source terminal of the switching element Q1 and the drain terminal of the switching element Q2 are connected and a node where the source terminal of the switching element Q3 and the drain terminal of the switching element Q4 are connected, A detection circuit 5, a resonance capacitor Cr, and a primary winding Tr1 of a transformer Tr are connected in series. Therefore, in the full bridge circuit 7, the diagonally positioned switching elements (switching element pair) Q1 and Q4 are simultaneously turned on and off, and similarly the diagonally positioned switching elements (switching element pair) Q2 and Q3 are simultaneously turned on and off. do.

Since the voltage between the drain terminal and the source terminal of the switching element Q4 is almost zero, the operation during the ON period of the switching elements Q1 and Q4 is the same as the circuit using the half bridge circuit 1 of the first embodiment. As a result, the same operation as in the first embodiment is performed. That is, the current I1 flows through the resonance switching circuit including the DC power source Vi, the switching elements Q1 and Q4, the detection circuit 5, the resonance capacitor Cr, and the primary winding Tr1 of the transformer Tr.

On the other hand, unlike the first embodiment, the operation during the ON period of the switching elements Q2 and Q3 is such that the DC power source Vi is included in the path of the current I2 flowing through the resonant switching circuit including the primary winding Tr1 of the transformer Tr. Become. Therefore, according to the third embodiment using the full bridge circuit 7, the current is supplied from the DC power supply Vi not only during the ON period of the switching elements Q1 and Q4 but also during the ON period of the switching elements Q2 and Q3. Since it operates, the current that can be output from the power conversion device 101a can be increased compared to the case where the same amount of current as the switching element of the first embodiment flows through the switching elements Q1 to Q4. Therefore, an operation suitable for a power conversion device that outputs a large current becomes possible.

In the third embodiment as well, when the load 4 becomes, for example, a high load, the through current flowing between the switching elements Q1 and Q4 and between the switching elements Q3 and Q2 is reduced as in the first embodiment. It is possible to suppress the amount of change over time and suppress the occurrence of surge voltage and noise.
Also in the third embodiment, the configuration described in the second embodiment may be adopted for the gate output circuit.
(Embodiment 4)

FIG. 10 is a circuit diagram showing the configuration of the power converter according to Embodiment 4. FIG. Since FIG. 10 is similar to FIG. 1, differences will be mainly described below. The main difference is that in FIG. 10, two sense elements are added, two detection circuits corresponding to the sense elements are provided as detection circuits, and the outputs of the two detection circuits are supplied to the determination circuit. is.

In FIG. 10, 101b indicates the power converter according to the fourth embodiment. The power converter 101b includes a half bridge circuit 1a, a gate drive circuit 2, two detection circuits 5-1 and 5-2, a determination circuit 6a, a resonance capacitor Cr, a primary winding Tr1, a secondary winding Tr2-1 and Tr2-2, a transformer Tr, and a rectifier circuit 3, which is composed of diodes D1 and D2 and a smoothing capacitor Co. An external DC power supply Vi is connected to input terminals T1 and T2, and a load 4 is connected to output terminals T3 and T4.

The half bridge circuit 1a includes switching elements Q1a and Q2a connected in series with each other. The switching elements Q1a and Q2a are composed of, for example, GaN-HEMTs formed on a silicon substrate of a semiconductor chip. The switching elements Q1a and Q2a include switching elements (main switching elements) Q1a-f and Q2a-f through which the main current flows, and a switching element (switching element for sensing) Q1a through which the current flowing through the switching elements Q1a and Q2a is split. -s and Q2a-s.

The drain terminals of the switching elements Q1a-f and Q1a-s are connected to each other, and the gate terminals of the switching elements Q1a-f and Q1a-s are also connected to each other. Similarly, respective drain terminals of switching elements Q2a-f and Q2a-s are connected together, and respective gate terminals of switching elements Q2a-f and Q2a-s are also connected together.

The main switching element and the sensing switching element used in Embodiment 4 are formed on the semiconductor substrate (silicon substrate) of the same semiconductor chip. FIG. 11 is a plan view showing part of a semiconductor chip according to the fourth embodiment. FIG. 11 shows a portion of the switching element Q1a formed on the semiconductor substrate (silicon substrate) of the semiconductor chip.

The switching elements Q1a-f and Q1a-s included in the switching element Q1a are integrated on the same substrate. In FIG. 11, symbols Q1a-Td indicate common drain terminals of switching elements Q1a-f and Q1a-s. References Q1a-Tg indicate common gate terminals of switching elements Q1a-f and Q1a-s. Reference characters Q1a-Ts-f indicate source terminals of the switching elements Q1a-f, and reference characters Q1a-Ts-s indicate source terminals of the switching elements Q1a-s. The respective drain terminals and gate terminals of switching elements Q1a-f and Q1a-s are connected to each other, switching elements Q1a-f and Q1a-s are connected in parallel, and switching elements Q1a-f and Q1a-s are connected in parallel. The switching element Q1a-s is used as a sense element by shunting part of the current flowing through the switching element Q1a to the switching element Q1a-s.

As shown in FIG. 11, the device area of the switching elements Q1a-s is made smaller than the device area of the switching elements Q1a-f. Although only the switching element Q1a is shown in FIG. 11, the switching element Q2a is configured similarly to the switching element Q1a. Further, in the fourth embodiment, switching elements Q1a and Q2a are formed on the same semiconductor substrate.

Returning to Fig. 10, explanation will be given. The source terminals of the switching elements Q1a-f and the drain terminal of the switching element Q2a are connected. The source terminals of the switching elements Q2a-f are connected to the DC power source Vi through the input terminal T2. Gate terminals of the switching elements Q1a and Q2a are connected to the gate drive circuit 2 . A resonance capacitor Cr and a primary winding Tr1 of a transformer Tr are connected between the node where the source terminals of the switching elements Q1a-f and the drain terminals of the switching elements Q2a are connected and the source terminals of the switching elements Q2a-f. connected in series.

A detection circuit 5-1 is connected between the source terminals of the switching elements Q1a-f and Q1a-s, and a detection circuit 5-2 is connected between the source terminals of the switching elements Q2a-f and Q2a-s. It is The detection circuits 5-1 and 5-2 are current sensors using, for example, shunt resistors, Hall elements, Rogowski coils, or the like. Detecting circuits 5-1 and 5-2 detect current values of currents flowing through switching elements Q1a-s and Q2a-s, respectively. The current values detected by the detection circuits 5-1 and 5-2 are output as analog values to the determination circuit 6a.

The determination circuit 6a is composed of a comparator such as a comparator and an edge detector using an edge detection circuit or a microprocessor, for example. The comparator compares the magnitude of the input from the current detection circuits 5-1 and 5-2 with the detected value when the current value is zero, and outputs the result as a digital value. The signal output from the comparator is input to the edge detector, and the edge detector outputs to the gate drive circuit 2 a signal corresponding to the falling edge of the signal from the comparator.

Since the switching elements Q1 and Q2 described in the first embodiment correspond to the switching elements Q1a and Q2a in the fourth embodiment, the currents output from the detection circuits 5-1 and 5-2 are shown in FIGS. 6 correspond to the currents Id1 and Id2 shown in FIG. Therefore, the current output from the detection circuit 5-1 is used as the determination signal when the polarity of the current I1 flowing through the primary winding Tr1 of the transformer Tr is reversed from positive to negative. That is, when the current output from the detection circuit 5-1 is inverted from positive to negative, the judgment circuit 6a outputs a judgment signal indicating that the polarity of the current I1 is inverted from positive to negative.

On the other hand, the current output from the detection circuit 5-2 is used as the determination signal when the polarity of the current I1 flowing through the primary winding Tr1 of the transformer Tr is reversed from negative to positive. That is, when the current output from the detection circuit 5-2 is inverted from positive to negative, the judgment circuit 6a outputs a judgment signal indicating that the polarity of the current I1 is inverted from negative to positive. The gate drive circuit 2 performs the same operation as in the first embodiment based on the determination signal from the determination circuit 6a.

According to the fourth embodiment, the detection circuits 5-1 and 5-2 detect the currents obtained by shunting the currents flowing through the switching elements Q1a and Q2a. It is smaller than the absolute value of the current I1 flowing through the primary winding Tr1 of Tr. Therefore, it is possible to downsize the detection circuits 5-1 and 5-2.

Further, according to the fourth embodiment, since the detection circuits 5-1 and 5-2 are provided at locations other than the resonance switching circuit including the primary winding Tr1 of the transformer Tr, which is a path through which a large current flows, the resonance It becomes possible to reduce the parasitic inductance of the switching circuit.

Also, in general, when using a switching element in which sensing elements are integrated, the current sensing ratio fluctuates due to the influence of the temperature distribution inside the element. However, according to the fourth embodiment, the sense element is only used to determine the reversal of the polarity (positive, negative) of the current. ) can be used with integrated sense elements without affecting the operation of the power converter.

The detection circuit 5-1 shown in FIG. 10 may be formed on the same semiconductor substrate as the switching element Q1a, and the detection circuit 5-2 may also be formed on the same semiconductor substrate as the switching element Q2a. good.

In addition, in Embodiment 4, an example based on the power converter described in Embodiment 1 has been described, but it is not limited to this. That is, it may be based on the power converters described in the second and third embodiments.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

1 half bridge circuit 2 gate drive circuit 3 rectifier circuit 4 load 5, 5-1, 5-2 detection circuit 6 determination circuit 7 full bridge circuit 100, 101, 101a, 101b power conversion device Cp1, Cp2 output capacitance Q1, Q2, Q3, Q4, Q1a, Q2a switching element RSC switching circuit

Claims (12)

1. a switching circuit comprising a plurality of switching elements, a capacitor, and a transformer comprising a primary winding connected in series with the capacitor;
   a gate drive circuit that outputs a gate drive current to the gate of the switching element to control on/off of the switching element;
   a detection circuit that detects current flowing through the switching circuit;
   a determination circuit that determines polarity reversal of the current detected by the detection circuit;
   with
   The gate drive circuit includes a gate adjustment circuit that adjusts the gate drive current based on the determination result of the determination circuit.
   Power converter.
2. In the power converter according to claim 1,
   the gate adjustment circuit outputs an output switching signal that switches the gate drive current between at least two levels;
   the gate adjustment circuit outputs the output switching signal for switching the gate drive current output by the gate drive circuit to a low level when the determination circuit determines that the polarity is inverted;
   The gate adjustment circuit outputs the output switching signal for switching the gate drive power to a high level after a predetermined period of time after switching the gate drive current to a low level.
   Power converter.
3. In the power converter according to claim 2,
   The gate drive circuit selects a gate resistor corresponding to the output switching signal from a plurality of gate resistors having different resistance values and the plurality of gate resistors. comprising a switch circuit connected between the gate terminal of
   Power converter.
4. In the power converter according to claim 2,
   The gate drive circuit includes a current circuit whose current value changes according to the output switching signal, and a current mirror circuit that outputs a current proportional to the current flowing through the current circuit.
   Power converter.
5. In the power converter according to any one of claims 1 to 4,
   The plurality of switching elements comprises two switching elements,
   When one switching element of the two switching elements is in an ON state, the gate adjustment circuit adjusts the gate drive current of the other switching element to a low level.
   Power converter.
6. In the power converter according to any one of claims 1 to 4,
   The plurality of switching elements comprise two pairs of switching elements positioned diagonally,
   The gate adjustment circuit adjusts the gate drive current of the other switching element to a low level when one switching element of the switching element pair is in an ON state.
   Power converter.
7. In the power converter according to any one of claims 1 to 6,
   at least one switching element among the plurality of switching elements, when in an ON state, supplies a current to the capacitor and a primary winding connected in series with the capacitor; a sense element that shunts a portion of the current flowing through the switching element,
   the detection circuit detects a current flowing through the sense element;
   The main switching element and the sense element are formed on the same semiconductor chip,
   Power converter.
8. In the power conversion device according to claim 7,
   The detection circuit is formed on the same semiconductor chip as at least one switching element among the plurality of switching elements,
   Power converter.
9. In the power converter according to any one of claims 1 to 8,
   At least one switching element among the plurality of switching elements uses a gallium nitride-based material,
   Power converter.
10. a switching circuit comprising a plurality of switching elements, a capacitor, and a transformer comprising a primary winding connected in series with the capacitor;
    a gate drive circuit that outputs a gate drive current to a gate terminal of the switching element to control on/off of the switching element;
    A control method for a power conversion device comprising
    detecting the current flowing through the switching circuit;
    determining whether the polarity of the detected current is reversed;
    adjusting the gate drive current if the polarity is determined to be reversed;
    A control method for a power converter.
11. In the control method of the power converter according to claim 10,
    if the polarity is determined to be reversed, switching the gate drive current to a lower level;
    switching the gate drive current to a high level after a predetermined period of time after switching the gate drive current to a low level;
    A control method for a power converter.
12. In the control method of the power converter according to claim 11,
    The predetermined period is longer than the time from when it is determined that the polarity has been reversed to when the on/off state of the switching element is switched, and is shorter than half the cycle in which the switching element turns on and off.
    A control method for a power converter.

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