JP2014187787A - Ldmosfet surge current protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable stable operation of a control circuit for on/off controlling a LDMOSFET of a lateral structure, by the prevention of the malfunction of a parasitic transistor and the suppression of an increased ASO loss.SOLUTION: A control circuit IC1 of a switching power supply device 1, including a surge current protection circuit 10 having an overcurrent detection circuit, has a function to extend or reduce an ON time of switching by the width of an on-pulse signal ON_PULS for driving a LDMOSFET Q1 and a surge current Ids at the time of turn-on.

Description

  The present invention relates to a switching power supply device, and more particularly to protection for preventing a malfunction caused by a parasitic transistor due to a surge current when a switching element having an LDMOS structure is turned on.

In the switching power supply device, an overcurrent circuit is incorporated in order to limit the current flowing to the switching element on the primary side when receiving and starting the AC power supply, or due to a sudden change in load current or a load short circuit.
In Patent Document 1, a sense MOS is used in combination with the switching element, and the overcurrent of the drain current flowing through the primary side switching element is compared with the current flowing through the sense MOS. The main current flowing through the switching element and the current flowing through the sense MOS are converted into a voltage through a resistor and set as a reference voltage, and the drain voltage when the switching element is on and the drain voltage of the sense MOS are compared, thereby causing an abnormal excess. The transistor is prevented from being destroyed by detecting the current and lowering the gate voltage of the switching element when abnormal.
As the switching element, for example, an FET (Field Effect Transistor) having an LDMOSFET (Laterally Diffused MOSFET) structure disclosed in Patent Document 2 may be used.

JP-A-6-244663 JP 2001-135719 A

However, Patent Document 1 does not mention the phenomenon in which the drain current is sustained by the parasitic transistor operation peculiar to the lateral type LDMOSFET (Laterally Diffused MOSFET) when the surge current at the turn-on time is increased due to a load short circuit or the like.
As shown in FIG. 4, the equivalent circuit of the LDMOSFET having a lateral structure is such that the collector and emitter of the transistor Tr1 are connected in parallel with the drain and source terminals of the MOSFET M1, and the base and emitter terminals of the transistor Tr1 are connected between the back gate and source terminals. The resistor r1 and the capacitor c1 are connected in parallel.
In the conventional switching power supply device 1a shown in FIG. 7, when the load is short-circuited, an overcurrent flows through the secondary side rectifier diode D3, the chip temperature of the diode D3 rises, and the recovery current increases. As a result, a surge current that is a recovery current of the diode D3 flows through the transformer T when the switching element Q1 is turned on. Here, when a large surge current flows for about 100 to 200 nanoseconds at turn-on, the capacitor c1 is charged and the parasitic transistor Tr1 is turned on. When the gate signal of the LDMOSFET is turned off immediately after the parasitic transistor Tr1 is turned on, the MOSFET M1 is turned off. However, the ON operation of the parasitic transistor Tr1 is continued for the time constant time of the capacitor c1 and the resistor r1. The on-state of the parasitic transistor Tr1 may last up to the order of 10 microseconds, and the on-state that is longer than the switching period is sustained, leading to transformer saturation and damage.

Also, in a switching power supply device, in order to prevent a malfunction that prevents the overcurrent protection circuit from malfunctioning due to a surge current generated at the time of turn-on, limiting the duty of the on-pulse signal of the switching element to near zero and not supplying power to the output. In addition, as shown in FIG. 7, there is provided a blanking circuit Blanking that does not operate the overcurrent protection circuit for a time having a little margin than the period in which the surge current flows. However, as shown in FIG. 8, when a load short circuit occurs at time t1, the duty of the gate signal Vg of the switching element at time t2 decreases to near zero, but the drain current increases. This is because the drain current cannot be limited because the overcurrent protection circuit does not operate for the blanking time during turn-on by the blanking circuit. In addition, the drain current during the blanking time is significantly increased from the current during the steady operation, so that the drain voltage in the on state increases, thereby increasing the ASO loss. FIG. 6 shows the relationship between the ASO of the LDMOSFET and the allowable time. When the gate signal Vg shown in FIG. 6 changes from the time tg3 to the time tasx, the ASO loss increases as the drain voltage Vds rises, and the channel temperature of the switching element may be exceeded, resulting in damage.
Further, Patent Document 2 discloses a semiconductor element structure for suppressing the operation of a parasitic transistor, but does not disclose a circuit that reliably protects against malfunction.

  It is an object of the present invention to avoid the drain current sustaining phenomenon caused by the parasitic transistor operation and to suppress the ASO loss when the load is short-circuited when an LDMOSFET switching element is used in the switching power supply device.

In order to solve the above-mentioned problems, a surge current protection circuit for an LDMOSFET according to the present invention has a lateral LDMOSFET connected between output terminals of a DC power supply via a load, and an on-pulse signal is input to the gate terminal of the LDMOSFET. In a control circuit that supplies a constant power to the load by performing a switching operation,
The control circuit includes a current detection unit that detects a switching current flowing through the LDMOSFET, converts the current into a voltage signal, and outputs the voltage signal. The current detection unit includes a reference voltage, and compares the voltage signal with the reference voltage. The LDMOSFET is turned on when the voltage signal is large, the voltage signal is large by comparing the voltage signal with the reference voltage, and the time width during which the voltage signal is output exceeds a predetermined first time. Off means for turning off, and when the pulse width of the on-pulse signal is less than a predetermined second time, it comprises means for turning on the LDMOSFET for at least a predetermined time. To do.
Further, the current detection means of the surge current protection circuit of the LDMOSFET according to the present invention has a first reference voltage and a second reference voltage, and the second reference voltage is higher than the first reference voltage. Set,
A current signal at turn-on flowing through the LDMOSFET and the first reference voltage are compared, and when the current signal is large, a first overcurrent signal is output;
Compared with the second reference voltage, a second overcurrent signal is output when the current signal is large,
When the first overcurrent signal exceeds a predetermined first time, the LDMOSFET is turned off,
When the pulse width of the on-pulse signal is less than a predetermined second time, the on-state of the LDMOSFET is turned on for at least a predetermined time.
In addition, the current detection means of the surge current protection circuit of the LDMOSFET according to the present invention includes a third reference voltage set lower than the first and second reference voltages, and the LDMOSFET is turned on when the LDMOSFET is turned on. A period in which the current signal flowing in the first period is not detected for a third time period, the third time period being set longer than the first time period and the second time period, and the current signal flowing in the LDMOSFET. When the voltage exceeds the third reference voltage, the on-state of the LDMOSFET is turned off.

According to the LDMOSFET surge current protection circuit of the present invention, even if the turn-on surge current flows for less than a predetermined time and more than a predetermined current, the period during which the LDMOSFET gate drive signal is applied is longer than the time when the turn-on surge current flows. Therefore, the operation of the parasitic transistor can be prevented and the reliability can be improved.
Further, when the load current is short-circuited and the drain current is in an overcurrent state for a predetermined period or longer, the drive signal of the LDMOSFET is turned off within a predetermined time until the ASO breakdown, thereby preventing an increase in ASO loss and improving the reliability. .

It is a block diagram of the switching power supply device provided with the surge current protection circuit of LDMOSFET which concerns on Example 1 of this invention. FIG. 2 is a detailed circuit diagram illustrating an example of a surge current protection circuit of the LDMOSFET according to FIG. 1. It is a sequence diagram which shows the surge current protection circuit operation | movement of LDMOSFET which concerns on FIG. It is an equivalent circuit diagram of LDMOSFET. It is a figure which shows the relationship between the surge current of LDMOSFET, parasitic transistor operation | movement, and a gate pulse width. It is a figure which shows the relationship between ASO of LDMOSFET, and permissible time. It is a block diagram which shows the switching power supply device which concerns on a prior art. It is a sequence diagram at the time of the load short circuit in the block diagram which concerns on a prior art.

  Hereinafter, a surge current protection circuit of an LDMOSFET according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a diagram showing the relationship between the surge current of the LDMOSFET, the parasitic transistor operation, and the gate pulse width. Here, FIG. 5A shows a waveform when the gate pulse signal Vg is sufficiently longer than the period tsg in which the surge current flowing through the LDMOSFET flows, and is a normal operation waveform. FIG. 5B shows a waveform in the case where the gate pulse signal Vg is equal to or less than the period tsg in which the surge current flowing in the LDMOSFET flows, and the gate pulse signal Vg becomes low despite being low. The parasitic transistor is turned on and the on state is maintained for several tens of microseconds.
As apparent from FIGS. 5A and 5B, paradoxically, the parasitic transistor may not turn on if the pulse width of the gate pulse signal Vg is sufficiently longer than the pulse width tsg of the surge current Isg. I understand.
In the embodiment described below, the pulse width tsg of the surge current Isg is assumed to be 100 to 200 nS as an example, and the time during which a malfunction of the parasitic transistor can be avoided is set to 400 nS.

  FIG. 6 is a diagram showing the relationship between the ASO of the LDMOSFET and the allowable time. Here, when the load of the switching power supply device is short-circuited, the drain current increases during the blanking period tas when the blanking circuit is turned on because the overcurrent protection circuit does not operate, and the drain voltage increases as the drain current increases. Loss increases. It can be seen that although the channel temperature does not exceed the channel temperature due to the ASO loss of the LDMOSFET in the blanking period tas, the breakdown does not occur, but in the case of the tasx period indicated by the dotted line in FIG.

  From the above, a protection circuit for the LDMOSFET can be configured by taking the logical product of the relationship between the surge current of the LDMOSFET, the parasitic transistor operation and the gate pulse width, and the condition of the limit of the ASO loss of the LDMOSFET.

FIG. 1 is a configuration diagram of a switching power supply device 1 including a surge current protection circuit for an LDMOSFET according to a first embodiment of the present invention.
The configuration of the LDMOSFET surge current protection circuit according to this embodiment will be described with reference to FIG.
The configuration diagram of the switching power supply device shown in FIG. 1 is different from the conventional configuration diagram in that a surge current protection circuit 10 of an LDMOSFET Q1 is added.
The surge current protection circuit 10 is connected between the control point CONT from the connection point between the source of the sense MOS and the current detection resistor Rs, and the gate pulse signal of the control unit CONT is sent to the gate drive unit BF via the surge current protection circuit 10. It is output.
Here, the surge current protection circuit 10 includes a surge current protection unit and an ASO protection unit, detects a drain current flowing through the LDMOSFET Q1, compares whether the detected drain current is equal to or higher than a predetermined reference value, and is a flowing period From surge current protection or ASO protection.
FIG. 2 is a detailed circuit diagram showing an example of the surge current protection circuit 10 of the LDMOSFET according to FIG.
The surge current protection circuit includes comparators CP1, CP2, reference voltages Vr1, Vr2, AND circuits AND1 to 4, OR circuits OR1, OR2, S-R flip-flop circuits FF1, FF2, timer TM1, delay circuits DL1, DL2, It consists of a one-shot circuit SH1.
The breakdown is that the surge current protection unit is composed of the comparator CP2, the reference voltage Vr2, the AND circuits AND1 to 4, the SR flip-flop circuit FF2, the timer TM1, the delay circuit DL2, and the one-shot circuit SH1, and the ASO protection unit The comparator CP1, the reference voltage Vr1, the OR circuit OR2, the SR flip-flop circuit FF1, and the delay circuit DL1. Here, the reference voltages Vr1 and Vr2 are described below assuming that Vr1 <Vr2. However, the set voltages of the reference voltages Vr1 and Vr2 may be the same depending on the characteristics of the LDMOSFET. The reference voltage Vr1 is a value set to a value less than a current that does not cause ASO damage. The reference voltage Vr2 is a parasitic transistor due to a surge current. Is the current setting value at which malfunction starts.

FIG. 3 is a sequence diagram showing a surge current protection circuit operation of the LDMOSFET according to FIG.
Next, details of the surge current protection circuit operation of the LDMOSFET will be described with reference to FIGS.
FIG. 3 (1) shows the waveform of each part during steady operation.
When the on-pulse signal ON_PULS is input from the time t10 to the time t12, the gate voltage Vg of the LDMOSFET Q1 is applied to be turned on. Here, since the drain current Id of the LDMOSFET Q1, that is, the resistance Rs voltage VRs has not reached the reference voltages Vr1 and Vr2, the outputs of the comparators CP1 and CP2 remain L. Therefore, during steady operation, neither surge current protection nor ASO protection is activated, and the same gate voltage Vg as the on-pulse signal ON_PULS is applied.
When the on-pulse signal ON_PULS is input, the timer circuit TM1 starts a timer counting operation, and after 200 nS, outputs a one pulse (200 nS) and self-resets.

FIG. 3 (2) shows the waveform of each part during the surge current protection operation when the load is short-circuited.
The pulse widths (a) to (c) of the on-pulse signal ON_PULS shown in FIG. 3 (2) are (a) tg1 = 500 nS, (b) tg2 = 200 nS, and (c) tg3 = 100 nS.
First, (a) when an on-pulse signal ON_PULS of tg1 = 500 nS is input, the SR flip-flop circuit FF1 is set, an H level is input to the OR circuit OR1, and the gate voltage Vg of the LDMOSFET Q1 is applied and turned on. become. Here, the drain current Id of the LDMOSFET Q1, that is, the resistor Rs voltage VRs, overcurrent flows due to a short circuit of the load, reaches the reference voltages Vr1 and Vr2, and the outputs of the comparators CP1 and CP2 output H level. When the comparator CP2 becomes H level, the SR flip-flop circuit FF2 is set and the Q output outputs H level. The AND circuit AND4 performs an OR operation on the H level because the inverting input terminal to which the output of the timer circuit TM1 is connected is at the L level when the Q output of the SR flip-flop circuit FF2 becomes the H level. Output to circuit OR1.
At the same time when the on-pulse signal ON_PULS of tg1 = 500 nS is input, the timer circuit TM1 starts counting, and outputs the H level to the AND circuits AND1, AND2, and AND4 after 200 nS of time setting. The AND circuit AND3 outputs an H level to the one-shot circuit ST1 via the AND circuit AND1 by the H level output of the timer circuit TM1, and outputs a one-shot pulse 200nS to the OR circuit OR1, so that at least the LDMOSFET Q1 is 400 nS. Perform the operation to turn it on. However, if the on-pulse signal ON_PULS of tg1 = 500 nS in (a), the above gate signal is 400 nS, so that the effect of the protection circuit does not appear. Note that if the ON state is 400 nS or more, the malfunction due to the parasitic transistor can be sufficiently avoided even if a surge current flows.
Next, when an on-pulse signal ON_PULS of (b) tg2 = 200 nS is input, the timer circuit TM1 starts counting at the same time, and outputs an H level to the AND circuits AND1, AND2, AND4 after 200 nS of time setting. In response to the H level output of the timer circuit TM1, the AND circuit AND3 outputs an H level to the one-shot circuit ST1 via the AND circuit AND1, and outputs a one-shot pulse 200nS to the OR circuit OR1.
As a result, a pulse signal of at least 400 nS is output from the OR circuit OR1 to the gate voltage Vg of the LDMOSFET via the buffer circuit BF. Therefore, even if the parasitic transistor is operated by a surge current having a width of 200 nS, the gate signal Vg of at least 400 nS is output, so that the capacitance c1 between the base and the emitter of the parasitic transistor is discharged and the drain current of the LDMOSFET continues. It is possible to prevent the phenomenon of flowing.
Further, (c) when an on-pulse signal ON_PULS of tg3 = 100 nS is input, the timer circuit TM1 starts counting at the same time, and outputs an H level to the AND circuits AND1, AND2, AND4 after 200 nS of time setting. Here, an L level is input from the timer circuit output to the inverting input terminal of the AND circuit AND4, and an H level signal is input from the Q output of the SR flip-flop circuit FF2 to the non-inverting terminal. The signal is output to OR1, and the H level output is maintained until the timer circuit TM1 output becomes H level. Thereby, even if the ON pulse signal ON_PULS signal is as short as tg3 = 100 nS, the gate signal can be output without interruption until the H level output of the timer circuit TM1 is made. Similarly to the above, the AND circuit AND3 outputs an H level to the one-shot circuit ST1 via the AND circuit AND1 by the H level output of the timer circuit TM1, and outputs the one-shot pulse 200nS to the OR circuit OR1. Thus, a total of 400 nS of gate signals Vg can be output.
That is, even if the on-pulse signal ON_PULS signal is as short as tg3 = 100 nS and the parasitic transistor operates due to the surge current, the gate signal Vg of 400 nS is output, so the capacitance c1 between the base and emitter of the parasitic transistor is discharged, and the LDMOSFET It is possible to prevent a phenomenon in which the drain current continuously flows.
Note that the output of the comparator CP1 after the ON pulse signal ON_PULS signal of (a) to (c) is input becomes H level, and then changes to L level when the resistance Rs voltage VRs becomes less than the reference potential Vr1 voltage. Protection circuit operation is not performed.

FIG. 3 (3) shows the waveforms of each part during the ASO protection operation when the load is short-circuited.
Here, as a premise of the load short-circuit state in FIG. 3 (3), it is assumed that the overcurrent protection circuit including the blanking circuit of the control circuit IC1 in FIG. 1 is operating and the blanking time is 250 nS.
First, when an on-pulse signal ON_PULS of tg4 = 250 nS is input at time t30, the SR flip-flop circuit FF1 is set, the H level is input to the OR circuit OR1, and the gate voltage Vg of the LDMOSFET is applied and turned on. become. Here, the drain current Id of the LDMOSFET, that is, the resistor Rs voltage VRs, overcurrent flows due to a load short circuit, reaches the reference voltages Vr1 and Vr2, and the outputs of the comparators CP1 and CP2 output H level. When the comparator CP2 becomes H level, the SR flip-flop circuit FF2 is set and the Q output outputs H level. The AND circuit AND4 performs an OR operation on the H level because the inverting input terminal to which the output of the timer circuit TM1 is connected is at the L level when the Q output of the SR flip-flop circuit FF2 becomes the H level. Output to the circuit OR1 and hold the output state until the output of the timer circuit TM1 changes to H level.
Here, since the output of the comparator CP1 holds the H level until time t31, when the delay time 200nS of the delay circuit DL1 is reached, the H level is input to the non-inverting input terminal of the OR circuit OR2, and the SR flip-flop circuit FF1. To reset. As a result, the output of the OR circuit OR1 becomes L level, the gate signal Vg becomes L level at time t31, and the increase of the ASO loss of the LDMOSFET can be suppressed by turning off the drain current Id.
At time t31, the output of the timer circuit TM1 becomes H level, but since the H level of the output of the comparator CP1 is input to the inverting input terminal of the AND circuit AND1, the AND circuit AND3 does not output the H level. A one-shot pulse of 200 nS is not generated from the one-shot circuit ST1. That is, the surge current protection unit does not operate.

  As described above, during the steady operation, neither the surge current protection unit nor the ASO protection unit operates, and when the surge current flows when the load is short-circuited, the surge current protection unit operates and the ASO protection unit does not operate. When overcurrent flows when the load is short-circuited, the ASO protection unit operates and the surge current protection unit does not operate, so that a stable protection function can be obtained.

As mentioned above, although an example of the embodiment of the present invention has been described, the present invention is not limited to the specific embodiment, and various modifications are possible within the scope of the gist of the present invention described in the claims. Can be changed.
For example, although the switching power supply device has been described using the flyback method, it can be changed to a motor drive device or the like by either the forward method or the resonance method.

DESCRIPTION OF SYMBOLS 1, 1a Switching power supply device 10 Surge current protection circuit AND1-4 AND circuit BF buffer circuit C1-C6, c1 Capacitor CP1, CP2 Comparator D1-D3 Diode DB1 Bridge diode DL1, Delay circuit FF1, FF2 S-R flip-flop Circuit IC1 Control circuit IC2 Shunt regulator OR1, 2 OR circuit PC1 Photocoupler Q1 LDMOSFET
R1 to R5, Rs resistance SH1 one shot circuit TM1 timer circuit

Claims (3)

In a control circuit in which a lateral LDMOSFET is connected between output terminals of a DC power supply via a load, and a constant power is supplied to the load by inputting an on-pulse signal to the gate terminal of the LDMOSFET to perform a switching operation.
The control circuit includes a current detection unit that detects a switching current flowing through the LDMOSFET, converts the current into a voltage signal, and outputs the voltage signal.
The current detecting means includes a reference voltage, the voltage signal is compared with the reference voltage, the voltage signal is large, the voltage signal is compared with the reference voltage, the voltage signal is large, and the voltage signal is output. An off means for turning off the on-state of the LDMOSFET when the time width to be exceeded exceeds a predetermined first time,
A control circuit comprising means for turning on the LDMOSFET for at least a predetermined time when the pulse width of the on-pulse signal is less than a predetermined second time. The current detection means has a first reference voltage and a second reference voltage, and the second reference voltage is set higher than the first reference voltage,
A current signal at turn-on flowing through the LDMOSFET and the first reference voltage are compared, and when the current signal is large, a first overcurrent signal is output;
Compared with the second reference voltage, a second overcurrent signal is output when the current signal is large,
When the first overcurrent signal exceeds a predetermined first time, the LDMOSFET is turned off,
2. The control circuit according to claim 1, wherein when the pulse width of the on-pulse signal is less than a predetermined second time, the on-state of the LDMOSFET is turned on for at least a predetermined time. The current detection means includes a third reference voltage set lower than the first and second reference voltages,
At the time of turn-on flowing through the LDMOSFET, a period during which the current signal flowing through the LDMOSFET is not detected during a third time is provided,
The third time is set longer than the first time and the second time, and turns off the LDMOSFET when the current signal flowing through the LDMOSFET exceeds the third reference voltage. 3. The control circuit according to claim 1, wherein

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