JP2005198457A - Resonant circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel resonant circuit in which breakdown in di/dt mode is prevented by lowering the oscillation frequency of a power supply upon occurrence of off-resonance. <P>SOLUTION: A series circuit of a high side switch 2 and a low side switch 3 is connected across a DC power supply 1, a control circuit 10 is connected with the gate terminals of these switches 2 and 3, a series circuit of the primary winding 5 of a transformer 4 insulated between primary and secondary and a resonant capacitor 7 is connected in parallel with the low side switch 3 and the switches 2 and 3 are turned on/off alternately. In such a resonant circuit, inversion of the gate signal of the switches 2 and 3 is forbidden during a period when a current flowing through the switches 2 and 3 is flowing through the body diode of any one of these switches 2 and 3 so that the switch conducting the current is sustained in on state. After the current flowing through the switches 2 and 3 flows completely through the body diodes of the switches 2 and 3, the gate signal of the switches 2 and 3 is inverted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a resonance circuit in which both ends of a DC power supply are connected to a series circuit of a high side switch and a low side switch, and the high side switch and the low side switch are alternately turned on and off.

  The resonance circuit is shown in FIG. In the resonance circuit, both ends of the DC power source 1 are connected to a series circuit of a high-side switch 2 and a low-side switch 3, and a control circuit 10 is connected to the gate terminals of these switches 2 and 3. Further, in parallel with the low-side switch 3, a series circuit of the primary winding 5 of the transformer 4 and the resonance capacitor 7 which are insulated between the primary and secondary is connected, and the high-side switch 2 and the low-side switch 3 are alternately turned on.・ It is configured to turn off. A current detection resistor 8 is connected in series with the resonance capacitor 7, and a control circuit 10 is connected to one end of the current detection resistor 8.

  A control circuit 10 according to a conventional example is shown in FIG. The control circuit 10 detects a first level detection circuit that detects whether or not the current flowing through the resonance circuit detected by the current detection resistor 8 is less than or equal to a positive detection level, and detects whether or not the current is greater than or equal to a negative detection level. A phase control circuit 11 having a second level detection circuit for performing the control, an oscillator 12 that oscillates a control triangular wave, and a high-side switch 2 and a low-side switch 3 that are turned on and off by the triangular wave oscillated from the oscillator 12 And a pulse forming circuit 13 for generating the control pulse. The first and second level detection circuits constituting the phase control circuit 11 include comparators 61 and 62, NOT circuits 63 and 64, flip-flop circuits 65 and 66, AND circuits 67 and 68, an OR circuit 69, and a switch 70, respectively. It is.

  The current detection resistor 8 is connected to the detection terminal of the comparator 61 constituting the first level detection circuit, and the output terminal of the comparator 61 is connected to the set terminal of the flip-flop circuit 65. The input terminal of the NOT circuit 63 is connected to the output on the high side of the pulse control circuit 13, and the output terminal of the NOT circuit 63 is connected to the reset side of the flip-flop circuit 65. The input terminal of the AND circuit 67 is connected to the output terminal of the comparator 61 on the one hand and to the output terminal of the flip-flop circuit 65 on the other hand.

  On the other hand, the current detection resistor 8 is connected to the detection terminal of the comparator 62 constituting the second level detection circuit, and the output terminal of the comparator 62 is connected to the set terminal of the flip-flop circuit 66. The input terminal of the NOT circuit 64 is connected to the output on the low side of the pulse control circuit 13, and the output terminal of the NOT circuit 64 is connected to the reset side of the flip-flop circuit 66. The AND circuit 68 is connected to the output terminal of the comparator 62 on the one hand and to the output terminal of the flip-flop circuit 66 on the other hand.

The output terminals of the two AND circuits 67 and 68 are connected to respective input terminals of the OR circuit 69. The output terminal of the OR circuit 69 is connected to the control terminal of the switch 70 to control the oscillation timing of the oscillator 12 (see, for example, Patent Document 1).
JP-A-9-308243

  As shown in the timing chart of FIG. 7, the function is to detect that the current flowing through the current detection resistor 8 becomes a negative current or near zero during the period when the gate signal of the high side switch 2 is on. The gate of the side switch 2 is inverted, and when the gate signal of the low side switch 3 is on, it is detected that the current flowing through the current detection resistor 8 becomes a positive current or near zero, and the low side switch 3 Invert the gate.

  The resonance circuit ideally operates as close as possible to the resonance frequency determined by the inductance of the transformer and the capacitance of the capacitor. In other words, the detection level of the current flowing through the resonance circuit is ideally as close to zero as possible. However, in the conventional detection method, if the detection level is brought close to zero, malfunction due to noise occurs, resonance deviation due to response delay of the control circuit cannot be avoided, and it is difficult to operate at a frequency close to the resonance frequency, Further, when the resonance is lost, the high-side switch and the low-side switch may be destroyed due to excessive stress such as di / dt mode.

  The di / dt mode is a mode in which, in a half-bridge resonant circuit, the other switch is turned on while a current is flowing through the body diode of one switch. At this time, when a current is suddenly drawn from the body diode of the switch, an excessive stress may be applied to the switch or the diode to cause destruction.

  In order to prevent breakdown in the di / dt mode, a method is required in which the other switch is not turned on (that is, resonance does not shift) while a current flows through the body diode on one side of the switch.

  The present invention has been made in view of the above problems, and provides a novel resonance circuit that prevents destruction in the di / dt mode by lowering the oscillation frequency of a power source when resonance is lost.

  In order to solve the above problems, the resonance circuit of the present invention connects both ends of a DC power source to a series circuit of a high-side switch and a low-side switch constituted by MOSFETs, and connects a control circuit to the gate terminals of these switches. In parallel with the low-side switch, a series circuit of a transformer primary winding and a resonance capacitor, which are insulated between primary and secondary, is connected, and the high-side switch and the low-side switch are turned on and off alternately. A signal transmitted from the control circuit so as to maintain the ON state of the switch through which the current flows while the current flowing through the switch is flowing through the body diode of one of the switches. Switching is prohibited, and inversion of the gate signal of the switch is prohibited, and the current flowing through the switch is Switching the signals transmitted finish flows Dee diode from said control circuit, and are configured to reverse the gate signal of the switch.

  The control circuit detects whether or not the current flowing through the resonance circuit detected by the current detection means is higher than a detection level, and pulse forming means for forming a control pulse for turning on and off the high-side switch and the low-side switch And a signal transmitted from the pulse forming means so as to maintain the ON state of the switch through which the current flows while the current flowing through the switch flows through the body diode of one of the switches. And a phase control means for switching the signal transmitted from the pulse forming means and inverting the gate signal of the switch when the current flowing through the switch finishes flowing through the body diode of the switch.

  The phase control unit compares a current flowing through the resonance circuit detected by the current detection unit with a detection level of zero or more, and detects whether or not the detection current exceeds a detection level; A first AND circuit having input terminals connected to an output terminal of the first comparator and a terminal for outputting a high-side clock signal of the pulse forming means; and the resonance circuit detected by the current detecting means. A second comparator for comparing whether the detected current exceeds the detection level, an output terminal of the second comparator, and the pulse forming means And a second AND circuit to which each input terminal is connected to a terminal for outputting the low side clock signal, and the output terminals of the first AND circuit and the second AND circuit are respectively connected to the OR circuit. Connected to the input terminal is coupled to the output terminal of the OR circuit to the pulse forming means.

  The phase control means compares the current flowing through the resonance circuit detected by the current detection means with a detection level, detects whether the detection current exceeds the detection level, and an output of the comparator A first AND circuit whose respective input terminals are connected to a terminal and a terminal for outputting a high-side clock signal of the pulse forming means, a NOT circuit for inverting the signal output from the comparator, and a And an output terminal and a second AND circuit connected to each input terminal to a terminal for outputting the low-side clock signal of the pulse forming means, and the output terminals of the first AND circuit and the second AND circuit are ORed The circuit is connected to each input terminal, and the output terminal of the OR circuit is connected to the pulse forming means.

  According to the present invention, even if the resonance is off, inversion of the gate signal of the switch is prohibited while the drain current of the switch flows through the body diode of the switch, and conversely, the drain current of the switch When the body diode is finished flowing, the gate signal of the switch is inverted so that the other switch does not turn on while it flows through the body diode, preventing the switch from being damaged by di / dt. There is an effect that can be done.

  A circuit diagram of the best mode for carrying out the invention is shown in FIG. In the resonance circuit shown in FIG. 1, both ends of the DC power source 1 are connected to a series circuit of a high-side switch 2 and a low-side switch 3, and a control circuit 10 is connected to the gate terminals of these switches 2 and 3. Further, in parallel with the low-side switch 3, a series circuit of the primary winding 5 of the transformer 4 and the resonance capacitor 7 which are insulated between the primary and secondary is connected, and the high-side switch 2 and the low-side switch 3 are alternately turned on.・ It is configured to turn off. A current detection resistor 8 is connected in series with the resonance capacitor 7, and a control circuit 10 is connected to one end of the current detection resistor 8.

  In the present invention, during the period when the current flowing through the high-side switch 2 or the low-side switch 3 is flowing through the body diode of either one of the switches 2 and 3, the on-state of the switch 2 or 3 through which this current flows is determined. In order to hold, the switching of the signal transmitted from the control circuit 10 is prohibited, the inversion of the gate signals of the switches 2 and 3 is prohibited, and the current flowing through the switches 2 and 3 flows through the body diodes of the switches 2 and 3 At the end, the signal transmitted from the control circuit 10 is switched to invert the gate signals of the switches 2 and 3. In order to reproduce this feature, the control circuit 10 is configured as follows.

  The control circuit 10 is provided with a pulse forming circuit 13 that forms control pulses for turning on and off the high-side switch 2 and the low-side switch 3. A phase control circuit 11 is provided for detecting the magnitude relationship between the current flowing through the resonance circuit detected by the current detection resistor 8 and the detection level.

  The phase control circuit 11 maintains the ON state of the switch 2 or 3 through which the current flows while the current flowing through the switch 2 or 3 is flowing through the body diode of one of the switches 2 or 3. As described above, the switching of the signal transmitted from the pulse forming circuit 13 is prohibited. When the current flowing through the switches 2 and 3 finishes flowing through the body diodes of the switches 2 and 3, the signal transmitted from the pulse forming circuit 13 is switched to invert the gate signals of the switches 2 and 3. .

  By configuring as described above, the following operations are performed. First, the body diode of the high side switch 2 is turned on while the high side switch 2 is turned on. In this case, if the gate signal of the high side switch 2 is inverted and the low side switch 3 is turned on, the high side switch 2 may be destroyed due to di / dt. In the present invention, such a state is detected by the phase control circuit 11 and switching of the signal transmitted from the pulse forming circuit 13 is prohibited so that the high-side switch 2 is kept on. As a result, the low-side switch 3 can be kept off, and the high-side switch 2 can be prevented from being destroyed by di / dt.

  Conversely, when the phase control circuit 11 detects that the current flowing through the high-side switch 2 has finished flowing through the body diode of the high-side switch 2, the signal transmitted from the pulse forming means is switched, and the switches 2 and 3 The gate signal is inverted, the high side switch 2 is turned off, and the low side switch 3 is turned on.

  Subsequently, the body diode of the low-side switch 3 is turned on while the low-side switch 3 is turned on. In this case, if the gate signal of the low side switch 3 is inverted and the high side switch 2 is turned on, the low side switch 3 may be destroyed due to di / dt. In the present invention, such a state is detected by the phase control circuit 11 and switching of the signal transmitted from the pulse forming means is prohibited so that the low-side switch 3 is kept on. As a result, the high side switch 2 can be kept off, and the low side switch 3 can be prevented from being destroyed by di / dt.

  Conversely, when the phase control circuit 11 detects that the current flowing through the low-side switch 3 has finished flowing through the body diode of the low-side switch 3, the signal transmitted from the pulse forming means is immediately switched, and the gate signals of the switches 2 and 3 are switched. , The low-side switch 3 is turned off, and the high-side switch 2 is turned on.

  As described above, even when the resonance is off, if the drain current of the switches 2 and 3 starts to flow through the body diodes of the switches 2 and 3, the inversion of the gate signals of the switches 2 and 3 is prohibited, and conversely the switch 2 When the drain current of the switches 2 and 3 finishes flowing through the body diodes of the switches 2 and 3, the gate signals of the switches 2 and 3 are inverted. Since the switches 2 and 3 are not turned on, it is possible to prevent the switches 2 and 3 from being destroyed by di / dt.

  FIG. 2 shows a circuit diagram of a first embodiment of the control circuit 10 according to the resonance circuit of the present invention. The control circuit 10 includes a phase control circuit 11, an oscillator 12, and a pulse forming circuit 13. The phase control circuit 11 includes first level detection means and second level detection means. The first level detection means is means for controlling the ON period of the high side switch 2. Further, the second level detection means is means for controlling the ON period of the low side switch 3. The pulse forming circuit 13 is a circuit that forms control pulses for turning on and off the high-side switch 2 and the low-side switch 3 from the triangular wave oscillated by the oscillator 12.

  The first level detection means related to the phase control circuit 11 is means for controlling the ON period of the high side switch 2. This first level detection means includes a comparator 21 and an AND circuit 24. The comparator 21 compares the current detected by the current detection resistor 8 with a positive detection level, detects whether or not the detection current is larger than the detection level, and turns on when the detection current is smaller than the detection level. is there. The input terminal of the AND circuit 24 is connected to the output on the high side of the pulse forming circuit 13 and the output terminal of the comparator 21 and is output when both the clock signal on the high side and the output signal of the comparator 21 are turned on. Circuit. The output terminal of the AND circuit 24 is connected to the input terminal of the OR circuit 26.

  The second level detection means related to the phase control circuit 11 is means for controlling the ON period of the low side switch 3. This second level detection means includes a comparator 22 and an AND circuit 25. The comparator 22 compares the current detected by the current detection resistor 8 with a negative detection level, detects whether or not the detection current is greater than the detection level, and turns on when the detection current is greater than the detection level. is there. The input terminal of the AND circuit 25 is connected to the output on the low side of the pulse forming circuit 13 and the output terminal of the comparator 22 and is output when both the low side clock signal and the output signal of the comparator 22 are turned on. is there. The output terminal of the AND circuit 25 is connected to the input terminal of the OR circuit 26.

  The output terminal of the OR circuit 26 is connected to the pulse forming circuit 13, and a signal is transmitted to the pulse forming circuit 13 when any of the output signals of the AND circuits 24 and 25 connected to the OR circuit 26 is on. It is.

  The oscillator 12 includes a phototransistor 31, and the phototransistor 31 is connected via a transistor 33 between a DC power supply terminal and the ground. In addition to the transistor 33, a transistor 34 is provided. The emitter of the transistor 34 is connected to a power supply terminal, and the collector is connected to the ground via a capacitor 35 for generating a triangular wave. A resistor 32 is connected in parallel with the phototransistor 31.

  The pulse forming circuit 13 includes a comparator 41, an OR circuit 42, a flip-flop circuit 44, AND circuits 45 and 46, a NOT circuit 48, and a switch 49, and connects the detection terminal of the comparator 41 to the oscillator 12. It is. A switch 43 is connected to the detection terminal of the comparator 41, and the switch 43 is connected to reference voltage portions V1 and V2 having different potential differences. The input terminal of the OR circuit 42 is connected to the output terminal of the comparator 41. The other input terminal of the OR circuit 42 is connected to the output terminal of the OR circuit 26 provided in the phase control circuit 11.

  The output terminal of the OR circuit 42 is connected to the input terminal of the NOT circuit 48, the trigger terminal of the flop flip circuit 44, and the control terminal of the switch 43. The output terminal of the NOT circuit 48 is connected to the base of the switch 49. The collector of the switch 49 is connected to the reference terminal of the comparator 41 via the current source 40. The output terminal of the OR circuit 42 is connected to one input terminal of the AND circuits 45 and 46. The other terminal of the first AND circuit 45 is connected to the output terminal of the flip-flop circuit 44, and the other terminal of the second AND circuit 46 is connected to the phase inversion output terminal of the flip-flop circuit 44. The high-side switch 2 is connected to the output terminal of the first AND circuit 45 via the level shift circuit 9, and the low-side switch 3 is connected to the output terminal of the second AND circuit 46.

  The resonant circuit configured as described above operates as follows. A timing chart of this resonance circuit is shown in FIG. First, when the high-side switch 2 is turned on and a current equal to or less than E1 flows through the current detection resistor 8, the comparator 21 is turned on, this signal is transmitted to the AND circuit 24, and the AND circuit 24 is turned on. As a result, during the period in which the body diode of the high-side switch 2 is flowing, the switching of the clock signal is prohibited, the inversion of the gate signals of the switches 2 and 3 is prohibited, and the high-side switch 2 is kept on. Therefore, since the switch of the low-side switch 3 is not turned on while flowing through the body diode of the high-side switch 2, it is possible to prevent the high-side switch 2 from being damaged due to di / dt.

  On the other hand, when the low-side switch 3 is turned on, a current opposite to that when the high-side switch 2 is turned on flows through the current detection resistor 8. First, when the low-side switch 3 is turned on and a current equal to or greater than E2 flows through the current detection resistor 8, the comparator 22 is turned on, this signal is transmitted to the AND circuit 25, and the AND circuit 25 is turned on. As a result, during the period when the body diode of the low side switch 3 is flowing, the switching of the clock signal is prohibited, the inversion of the gate signals of the switches 2 and 3 is prohibited, and the on state of the low side switch 3 is held. Therefore, since the switch of the high side switch 2 is not turned on while the body diode of the low side switch 3 is flowing, the breakdown of the low side switch 3 due to di / dt can be prevented.

  Note that the control circuit 10 shown in this embodiment can be integrated as an integrated circuit.

  FIG. 4 shows a circuit diagram of a second embodiment of the control circuit 10 according to the resonance circuit of the present invention. The control circuit 10 includes a phase control circuit 11, an oscillator 12, and a pulse forming circuit 13. First, in this embodiment, the configuration of the phase control circuit 11 is different from that in the above embodiment, and the two detection levels are made equal (for example, the detection level is set to zero), and the current flowing through the resonance circuit by the comparator 21 is simply set. Detect the direction of. Since the direction of the current is reversed between when the high-side switch 2 is on and when the low-side switch 3 is on, the output of the comparator 21 is directly connected to the input of the AND circuit 24. The output of the comparator 21 is connected to the input of the AND circuit 25 via the NOT circuit 23. The specific configuration is as follows.

  The phase control circuit 11 includes a comparator 21, a NOT circuit 23, and AND circuits 24 and 25. The comparator 21 detects whether or not the current detected by the current detection resistor 8 flows through the body diode of the high-side switch 2 and whether or not the current flows through the body diode of the low-side switch 3. The output terminal of the comparator 21 is connected to the input terminal of the AND circuit 24. When a current flows through the body diode of the high side switch 2, a signal is transmitted from the comparator 21 to the AND circuit 24. The input terminal of the AND circuit 24 is connected to the high-side output terminal of the pulse forming circuit 13, and the AND circuit 24 outputs when both the high-side clock signal and the output signal of the comparator 21 are turned on. Circuit. The output terminal of the AND circuit 24 is connected to the input terminal of the OR circuit 26.

  The output terminal of the comparator 21 is connected to the NOT circuit 23 and inverts the signal. That is, the NOT circuit 23 transmits a signal when a current flows through the body diode of the low-side switch 3. The output terminal of the NOT circuit 23 is connected to the input terminal of the AND circuit 25. The input terminal of the AND circuit 25 is connected to the output terminal on the low side of the pulse forming circuit 13, and the AND circuit 25 outputs when both the low side clock signal and the output signal from the NOT circuit 23 are turned on. It is. The output terminal of the AND circuit 25 is connected to the input terminal of the OR circuit 26.

  The output terminal of the OR circuit 26 is connected to the pulse forming circuit 13, and a signal is transmitted to the pulse forming circuit 13 when any of the output signals of the AND circuits 24 and 25 connected to the OR circuit 26 is on. It is.

  The oscillator 12 includes a phototransistor 31, and the phototransistor 31 is connected via a transistor 33 between a DC power supply terminal and the ground. In addition to the transistor 33, a transistor 34 is provided. The emitter of the transistor 34 is connected to a power supply terminal, and the collector is connected to the ground via a capacitor 35 for generating a triangular wave. A resistor 32 is connected in parallel with the phototransistor 31.

  The pulse forming circuit 13 includes a comparator 41, an OR circuit 42, a flip-flop circuit 44, AND circuits 45 and 46, a NOT circuit 48, and a switch 49, and connects the detection terminal of the comparator 41 to the oscillator 12. It is. A switch 43 is connected to the detection terminal of the comparator 41, and the switch 43 is connected to reference voltage portions V1 and V2 having different potential differences. The input terminal of the OR circuit 42 is connected to the output terminal of the comparator 41. The other input terminal of the OR circuit 42 is connected to the output terminal of the OR circuit 26 provided in the phase control circuit 11.

  The output terminal of the OR circuit 42 is connected to the input terminal of the NOT circuit 48, the trigger terminal of the flop flip circuit 44, and the control terminal of the switch 43. The output terminal of the NOT circuit 48 is connected to the base of the switch 49. The collector of the switch 49 is connected to the reference terminal of the comparator 41 via the current source 40. The output terminal of the OR circuit 42 is connected to one terminal of the AND circuits 45 and 46. The other terminal of the first AND circuit 45 is connected to the output terminal of the flip-flop circuit 44, and the other terminal of the second AND circuit 46 is connected to the phase inversion output terminal of the flip-flop circuit 44. The high-side switch 2 is connected to the output terminal of the first AND circuit 45 via the level shift circuit 9, and the low-side switch 3 is connected to the output terminal of the second AND circuit 46.

  The resonant circuit configured as described above operates as follows. A timing chart of this resonance circuit is shown in FIG. First, when the high-side switch 2 is turned on and a current flows through the body diode of the high-side switch 2 through the current detection resistor 8, the signal of the comparator 21 is transmitted to the AND circuit 24, and the AND circuit 24 is turned on. As a result, during the period in which the body diode of the high-side switch 2 is flowing, the switching of the clock signal is prohibited, the inversion of the gate signals of the switches 2 and 3 is prohibited, and the ON state of the high-side switch 2 is maintained. Therefore, since the switch of the low-side switch 3 is not turned on while flowing through the body diode of the high-side switch 2, it is possible to prevent the high-side switch 2 from being damaged due to di / dt.

  On the other hand, when the low-side switch 3 is turned on, a current opposite to that when the high-side switch 2 is turned on flows through the current detection resistor 8. First, when the low side switch 3 is turned on and a current flows through the body diode of the low side switch 3, the comparator 22 is turned off and the NOT circuit 23 is turned on. As a result, the signal of the NOT circuit 23 is transmitted to the AND circuit 25, and the AND circuit 25 is turned on. As a result, during the period when the body diode of the low side switch 3 is flowing, the switching of the clock signal is prohibited, the inversion of the gate signals of the switches 2 and 3 is prohibited, and the on state of the low side switch 3 is held. Therefore, since the switch of the high side switch 2 is not turned on while the body diode of the low side switch 3 is flowing, the breakdown of the low side switch 3 due to di / dt can be prevented.

  Note that the control circuit 10 shown in this embodiment can be integrated as an integrated circuit.

  The resonant circuit of the present invention prohibits inversion of the gate signal of the switch when the drain current of the switch starts to flow through the body diode of the switch even when the resonance is off, and conversely, the drain current of the switch When the body diode is finished flowing, the gate signal of the switch is inverted so that the other switch does not turn on while it flows through the body diode, preventing the switch from being damaged by di / dt. can do.

It is a circuit diagram of the resonant circuit which concerns on this invention. It is the circuit diagram which showed the principal part of 1st Example which concerns on this invention resonant circuit. 2 is a timing chart in the embodiment shown in FIG. It is the circuit diagram which showed the principal part of 1st Example which concerns on this invention resonant circuit. 4 is a timing chart in the embodiment shown in FIG. It is the circuit diagram which showed the principal part of the prior art example in this invention resonant circuit. 7 is a timing chart of the conventional example shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 High side switch 3 Low side switch 4 Transformer 5 Primary winding 6 of transformer 4 Secondary winding 7 of transformer 4 Resonant capacitor 8 Current detection resistor 9 Level shift circuit 10 Control circuit 11 Phase control circuit 12 Oscillator 13 Pulse formation Circuits 21, 22 Comparator 23 NOT circuit 24, 25 AND circuit 26 OR circuit 31 Phototransistor 32 Resistor 33, 34 Transistor 35 Triangle wave generating capacitor 40 Current source 41 Comparator 42 OR circuit 43 Switch 44 Flip-flop circuit 45, 46 AND Circuit 48 NOT circuit 49 switch 61, 62 comparator 63, 64 NOT circuit 65, 66 flip-flop circuit 67, 68 AND circuit 69 OR circuit 70 switch

Claims (4)

Both ends of the DC power supply are connected to a series circuit of a high-side switch and a low-side switch composed of MOSFETs, a control circuit is connected to the gate terminals of these switches, and the primary and secondary are insulated in parallel with the low-side switch. A resonant circuit in which a high-side switch and a low-side switch are alternately turned on / off by connecting a series circuit of a primary winding of the transformer and a resonant capacitor, and the current flowing through the switch is one of these switches Inversion of the gate signal of the switch is prohibited while switching the signal transmitted from the control circuit so as to maintain the ON state of the switch through which the current flows while the body diode is flowing. The control circuit when the current flowing through the switch finishes flowing through the body diode of the switch. Switching the signals et outgoing resonant circuit, characterized in that are configured to invert the gate signal of the switch. The control circuit detects whether or not the current flowing through the resonance circuit detected by the current detection means is higher than a detection level, and pulse forming means for forming a control pulse for turning on and off the high-side switch and the low-side switch And a signal transmitted from the pulse forming means so as to maintain the ON state of the switch through which the current flows while the current flowing through the switch flows through the body diode of one of the switches. Phase control means for switching the signal transmitted from the pulse forming means when the current flowing through the switch finishes flowing through the body diode of the switch and inverting the gate signal of the switch is provided. The resonance circuit according to claim 1. The phase control unit compares a current flowing through the resonance circuit detected by the current detection unit with a detection level of zero or more, and detects whether or not the detection current exceeds a detection level; An output terminal of the first comparator, a terminal for outputting a high-side clock signal of the pulse forming means, and a first AND circuit connected to each input terminal, and the resonance detected by the current detecting means A second comparator for comparing a current flowing through the circuit with a detection level of zero or less and detecting whether the detection current exceeds a detection level; an output terminal of the second comparator; and the pulse formation And a second AND circuit to which each input terminal is connected to a terminal for outputting a low-side clock signal of the means, and the output terminals of the first AND circuit and the second AND circuit are those of the OR circuit. Resonance circuit according to claim 2, wherein connected to the input terminal, characterized in that the output terminal of the OR circuit is connected to said pulse forming means les. The phase control means compares the current flowing through the resonance circuit detected by the current detection means with a detection level, detects whether the detection current exceeds the detection level, and an output of the comparator A first AND circuit whose respective input terminals are connected to a terminal and a terminal for outputting a high-side clock signal of the pulse forming means, a NOT circuit for inverting the signal output from the comparator, and a And an output terminal and a second AND circuit connected to each input terminal to a terminal for outputting the low-side clock signal of the pulse forming means, and the output terminals of the first AND circuit and the second AND circuit are ORed 3. The resonance circuit according to claim 2, wherein the circuit is connected to each input terminal of the circuit, and an output terminal of the OR circuit is connected to the pulse forming means.

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