KR101832986B1 - Switch controller and converter comprising the same - Google Patents

Abstract

The switch control device for controlling the main switch and the sub switch in the converter using the transformer extends the turn-on time of the sub switch when the voltage of the signal corresponding to the current flowing in the primary coil of the transformer is higher than the reference voltage during the set period .

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a switch control apparatus,

 The present invention relates to a switch control apparatus and a converter including the switch control apparatus.

Soft switching converters use capacitors that are connected in series or in parallel to the main transformer that converts the primary side power and delivers it to the secondary side. The soft switching converter controls the switching operation of the power switches according to the resonance between the inductor of the main transformer and the capacitor. Then, zero voltage switching or zero current switching is performed to enable soft switching.

In general, in the start-up or burst mode operation of the converter, the switching operation of the power switches may fail in zero voltage switching, or a shoot-through current may occur in response to the switching operation of the power switches. This is because the magnetization current of the main transformer becomes unstable by the capacitor. The shoot-through current is generated in both the main switch and the auxiliary switch by turning on both the main switch supplying power to the primary side of the converter and the auxiliary switch delivering the supplied power to the secondary side.

Failure of zero voltage switching, or shoot-through current, causes a sudden current rise and noise. The sudden rise in current causes damage to the components of the converter, such as metal-oxide semiconductor field-effect transistors (MOSFETs), power switches.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a switch control apparatus and a converter including the switch control apparatus, which can prevent damage to the converter due to failure of shoot-through or zero voltage switching.

According to an embodiment of the present invention, there is provided an apparatus for controlling the main switch and the sub-switch in a converter including a main switch and a sub-switch and generating an output voltage using a transformer. The switch control device includes an oscillator, a duty controller, and a gate driver. The oscillator generates an oscillator signal. The duty control unit outputs a signal corresponding to the oscillator signal, a signal corresponding to the primary current flowing through the primary coil of the transformer and a predetermined reference voltage, and a feedback voltage corresponding to the output voltage and a signal corresponding to the primary current A duty signal for controlling the switching operation of each of the main switch and the sub-switch is generated. The gate driver generates first and second control signals for controlling the switching operation of the main switch and the sub switch by using the duty signal.

According to another embodiment of the present invention, there is provided a converter including a main switch, a sub-switch, a transformer, and a switch control device. The main switch operates in response to the first control signal. The sub switch is operated in response to a second control signal having a phase different from the first control signal and is connected between the main switch and the ground terminal. The transformer includes a primary coil and a secondary coil connected to an output terminal, and converts the input voltage to an output voltage by a switching operation of the main switch and the sub switch. The switch control device generates the first control signal and the second control signal using the feedback voltage corresponding to the output voltage and the voltage of the signal corresponding to the current flowing in the primary coil, The turn-on time of the sub-switch is extended when the voltage of the signal corresponding to the flowing current is higher than the reference voltage.

According to embodiments of the present invention, shoot-through or zero voltage switching failures can be predicted and shoot-through or zero voltage switching failures can be prevented. Thus, damage to the converter due to shoot-through or zero voltage switching failure is also prevented.

1 is a view of a converter according to an embodiment of the present invention.
2 is a signal timing diagram of the converter shown in Fig.
3A to 3D are diagrams showing current paths according to the signal timing charts shown in FIG. 2, respectively.
4 is a schematic block diagram of the switch control apparatus shown in FIG.
5 is a block diagram of the duty controller shown in FIG.
6 is a diagram showing an oscillator signal of an oscillator, a sense voltage, a reference voltage, an operation waveform of an up-down counter, and two control signals.
7 is a diagram showing an operation waveform of the duty control unit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention in the drawings, parts not related to the description are omitted. Like numbers refer to like parts throughout the specification.

Throughout the specification and claims, when a section is referred to as "including " an element, it is understood that it does not exclude other elements, but may include other elements, unless specifically stated otherwise. Also, when a part is connected to another part, it includes not only a direct connection but also a case where the other part is connected to the other part in between.

Now, a switch control apparatus and a converter including the same according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a view of a converter according to an embodiment of the present invention.

Referring to FIG. 1, the converter 10 includes a main switch M1, an auxiliary switch M2, a switch control device 100, a feedback loop 200, a transformer 300, A capacitor Cb, output diodes D1 and D2, an inductor Lo and a capacitor Co.

Here, the transistors M1 and M2 are switches each having a control terminal, an input terminal and an output terminal. In FIG. 1, the transistors M1 and M2 are illustrated as an n-channel field effect transistor (FET), in which the control terminal, the input terminal and the output terminal correspond to the gate, the drain, and the source, respectively. Each of the transistors M1 and M2 may have a body diode (not shown). In addition, other transistors having a similar function may be used instead of the n-channel FET as these transistors M1 and M2. For example, the transistors M1 and M2 may use an IGBT.

The drain of the main switch M1 is connected to the power supply for supplying the input voltage Vin and the source of the main switch M1 is connected to the drain of the sub switch M2 and the source of the sub switch M2 is connected to the ground terminal Respectively. The gates of the main switch M1 and the sub switch M2 are connected to the switch control device 100. The main switch M1 and the sub switch M2 are controlled by a control signal S1, and S2. The switch control apparatus 100 alternately turns on / off the main switch M1 and the sub-switch M2.

The transformer 300 includes a primary coil Co1 and a secondary coil Co21 and Co22. One end of the primary coil Co1 is connected between the source of the main switch M1 and the drain of the secondary switch M2 and the other end of the primary coil Co1 is connected to one end of the blocking capacitor Cb . One end of the secondary coil Co21 is connected to the anode of the output diode D1 and the other end of the secondary coil Co21 is connected to one end and the output end (-) of the secondary coil Co22. The other end of the secondary coil Co22 is connected to the anode of the output diode D2.

The other end of the blocking capacitor Cb is connected to one end of the resistor Rse and the switch control device 100 and the other end of the resistor Rse is connected to the ground terminal.

The cathode of the output diode D1 and the cathode of the output diode D2 are connected to one end of the inductor Lo and the other end of the inductor Lo is connected to the output end. The capacitor Co is connected between the two outputs (+, -). At this time, the inductor Lo and the capacitor Co remove the ripple component of the output voltage Vout as an LC filter.

The feedback loop 200 transfers the feedback voltage Vfb corresponding to the output voltage Vout to the switch control apparatus 100. [

The switch control apparatus 100 controls the control signals S1 and S2 using the feedback voltage Vfb and the voltage Vse of the sense signal corresponding to the current flowing in the primary coil Co1 And outputs the control signals S1 and S2 to the gates of the main switch M1 and the sub-switch M2.

The operation of the converter 10 will be described with reference to FIG. 2 and FIGS. 3A to 3D.

FIG. 2 is a signal timing diagram of the converter shown in FIG. 1, and FIGS. 3A to 3D are diagrams showing current paths according to signal timing charts shown in FIG. 2, respectively.

2 shows the voltages of the control signals S1 and S2 applied to the gates of the main switch M1 and the sub-switch M2. The main switch M1 and the sub switch M2 are turned on by the high level control signals S1 and S2 and the main switch M1 and the sub switch M2 ) Is turned off.

Referring to FIG. 2, the control signal S1 becomes high level after a predetermined dead time from when the control signal S2 becomes low level.

At the time Ta when the control signal becomes the high level S1, the main switch M1 is turned on. At this time, the sub-switch M2 is turned off. Then, as shown in Fig. 3A, the primary side current I1 flows through the main switch M1, the primary coil Co1, the blocking capacitor Cb, the resistor Rse, and the ground terminal. The voltage of the primary coil Co1 is transferred to the secondary coil Co21 and the secondary coil Co22 according to the turns ratio of the primary coil Co1 and the secondary coils Co21 and Co22. The output diode D1 is conducted by the voltage of the secondary coil Co21 and the current of the secondary coil Co21 generated by the primary side current I1 is transmitted to the capacitor Co through the output diode D1 . At this time, the voltage charged in the capacitor Co becomes the output voltage Vout.

Next, the main switch M1 is turned off at a time point Tb when the control signal S1 becomes a low level. That is, in the period Tb-Tc, both the main switch Ml and the sub-switch M2 are turned off. All the voltages of the parasitic capacitors (not shown) of the secondary switch M2 are discharged, and the voltage across the secondary switch M2 becomes 0V, as shown in Fig. 3B. The current I1 decreases during the period Tb-Tc while the primary side current I1 begins to flow through the body diode of the secondary switch M2. Then, the secondary switch M2 may be a zero voltage switching.

The control signal S2 becomes high level after a predetermined dead time from the time point Tb at which the control signal S1 becomes low level.

The sub-switch M2 is turned on at the time point Tc at which the control signal S2 becomes the high level. Then, as shown in Fig. 3C, the primary side current I1 flows through the secondary switch, the resistor Rse, the blocking capacitor Cb and the primary coil Co1. The voltage of the primary coil Co1 is transferred to the secondary coil Co21 and the secondary coil Co22 according to the turns ratio of the primary coil Co1 and the secondary coils Co21 and Co22. The output diode D2 is conducted by the voltage of the secondary coil Co22 and the current of the secondary coil Co22 generated by the primary side current I1 is transmitted to the capacitor Co through the output diode D2 . At this time, the voltage charged in the capacitor Co becomes the output voltage Vout.

Next, the sub-switch M2 is turned off at the time point Td when the control signal S2 becomes low level. That is, in the period Tc-Td, both the main switch Ml and the sub-switch M2 are turned off. As shown in Fig. 3D, the voltage of the parasitic capacitor (not shown) of the main switch M1 is all discharged, and the voltage across the sub-switch M1 becomes zero voltage. The current Id also decreases during the period Tc-Td as the primary current I1 starts to flow through the body diode of the main switch M2. Then, the sub-switch Ml can be switched to zero voltage.

In this manner, the converter 10 generates the output voltage Vout supplied to the load by using the primary side current I1 generated in accordance with the switching operation of the main switch M1 and the sub-switch M2.

In this converter 10, the current flowing in the main switch M1 and the sub-switch M2 does not change even after the sub-switch M2 is turned on by the primary current I1 flowing during the period Ta, - Shoot-through current can occur. Further, the secondary switch M2 may fail to switch the zero voltage due to the large primary side current I1.

Hereinafter, an embodiment capable of preventing such zero voltage switching failure or generation of shoot-through current will be described in detail with reference to FIG. 4 to FIG.

FIG. 4 is a schematic block diagram of the switch control apparatus shown in FIG. 1, and FIG. 5 is a block diagram of the duty control unit shown in FIG.

Referring to FIG. 4, the switch control apparatus 100 includes an oscillator 110, a duty controller 120, and a gate driver 130.

The oscillator 110 generates an oscillator signal OSC and outputs the oscillator signal OSC to the duty controller 120.

The duty controller 120 generates the duty signal Sduty by using the sense voltage Vse and the feedback voltage Vfb corresponding to the oscillator signal OSC and the primary current I1.

Specifically, the duty controller 120 turns off the main switch M1 and turns on the sub-switch M2 at a time point when the sensing voltage Vse becomes equal to the feedback voltage. At this time, the main switch M1 is turned off and the sub-switch M2 is turned on after a predetermined dead time.

If the sense voltage Vse is lower than the reference voltage (for example, OV) at the rising edge or the falling edge of the oscillator signal OSC, the duty controller 120 sets the sub- Turns the main switch M1 on. At this time, the sub-switch M2 is turned off and the main switch M1 is turned on after a predetermined dead time.

The duty controller 120 sets the maximum turn-on time of the sub-switch M2 and turns on the sub-switch M2 for the maximum turn-on time if the sense voltage Vse is still higher than the reference voltage, ). That is, when the sense voltage Vse is higher than the reference voltage, the duty controller 120 extends the turn-on time of the sub-switch M2 so that a shoot-through current is not generated.

The gate driver 130 generates control signals S1 and S2 for controlling on / off of the main switch M1 and the sub switch M2 in accordance with the duty signal Sduty. For example, the gate driver 130 turns on the main switch M1 in synchronization with the falling edge of the duty signal Sduty and turns off the main switch M1 in synchronization with the rising edge of the duty signal Sduty The control signal S1 can be generated. In this case, the gate driver 130 turns on the sub-switch M2 in synchronism with the rising edge of the duty signal Sduty and outputs the control signal S2, which turns off the sub-switch M2 in synchronization with the falling edge of the duty signal Sduty. (S2).

5, the duty controller 120 includes comparators COM1 and COM2, an up-down counter 122, AND gates AND1 and AND2, a delay unit 124, SR latches SR1, SR2, and SR3, OR devices OR1 and OR2, and inverter devices INV1 and INV2.

The inverter INV1 inverts the oscillator signal OSC and outputs the inverted oscillator signal / OSC to the SR latch SR1, the up / down counter 122 and the AND gate AND2.

The comparator COM1 receives the sense voltage Vse at the inverting terminal (-) and receives the reference voltage Vref at the non-inverting terminal (+). When the sense voltage Vse is lower than the reference voltage Vref, And outputs a pulse signal Scom1 having a low level when the sense voltage Vse is higher than the reference voltage Vref. At this time, the reference voltage Vref may be set to 0V.

The comparator COM2 receives the sense voltage Vse as the non-inverting terminal (+) and receives the feedback voltage Vfb as the inverting terminal (-). When the sense voltage Vse is higher than the feedback voltage Vfb And outputs a pulse signal Scom2 having a high level and having a low level when the sense voltage Vse is a negative of the feedback voltage Vfb. The turn-off time of the main switch M1 can be determined in accordance with the pulse signal Scom2.

The AND element AND1 receives the oscillator signal OSC and the pulse signal Scom1 which is the output signal of the comparator Com1 and performs an AND operation on the two signals Sref and Scom1 to output it to the SR latch SR1 do. The AND gate AND1 outputs a pulse signal Sand1 having a high level only when both the oscillator signal OSC and the pulse signal Sp1 are at the high level. The delay section 124 receives the inverted oscillator signal / OSC To the reset terminal R of the SR latch SR1.

The SR latch SR1 includes a reset terminal R to which a delay inversion oscillator signal / OSC 'is inputted, a set terminal S to which a pulse signal Sand1 as an output signal of the AND gate AND1 is input, And an output terminal Q connected to the element ADN2. This SR latch SR1 outputs a high level in synchronization with the rising edge of the pulse signal Sand1 input to the set terminal S and outputs the high level of the delay inverted oscillator signal / And outputs a low level in synchronization with the rising edge. That is, the SR latch SR1 latches the high-level pulse signal Sand1 to generate the high-level pulse signal Ssr1, and generates the pulse signal Sand1 (in synchronization with the rising edge of the delayed inverted oscillator signal / ) To a low level.

The AND gate AND2 receives the inverted oscillator signal / OSC and the pulse signal Ssr1 which is the output signal of the SR latch SR1 and performs an AND operation on the two signals / OSC and Ssr1, OR1). The AND gate AND2 outputs a pulse signal Ssr1 having a high level only when both the inverted oscillator signal / OSC and the pulse signal Ssr1 are at a high level.

The OR gate OR1 receives the pulse signal Scou of the up-down counter 122 and the pulse signal Sand2 which is the output signal of the AND gate AND2 and performs an OR operation on the two signals Scou and Sand2, do. The OR gate OR1 outputs the pulse signal Sor1 having the low level only when both the pulse signal Scou and the pulse signal Sand2 of the up / down counter 122 are low level.

The up-down counter 122 outputs a pulse signal Scou for resetting the count in synchronization with the inverted oscillator signal / OSC and increasing the count when the count value becomes larger than the set value, And resets the value of the count in response to the pulse signal Sand2. At this time, the sub-switch M2 is turned off in response to the pulse signal Scou. For example, when the set value is set to 4, the up-down counter 122 outputs a high-level pulse signal Scou when the count value is larger than 4, and outputs the high-level pulse signal Scou in response to the high- The count value is reset in response to the pulse signal Sand2 of the high-level OR element OR1.

The up-down counter 122 is for setting the maximum turn-on time of the sub-switch M2. The maximum turn-on time of the sub-switch M2 is the time from when the count value is reset until the pulse signal Scou is output Lt; / RTI >

The SR latch SR2 includes a reset terminal R to which an oscillator signal OSC is input, a set terminal S to which a pulse signal Sor1 as an output signal of the OR gate OR1 is input and an inverter element INV2 And a set terminal S of the SR latch SR3 and an output terminal Q connected to the OR gate OR2. The SR latch SR2 outputs a high level in synchronism with the rising edge of the pulse signal Sor1 input to the set terminal S and outputs a high level signal synchronized with the rising edge of the oscillator signal OSC input to the reset terminal R And outputs a low level. That is, the SR latch SR2 latches the high-level pulse signal Sor1 to generate the high-level pulse signal Ssr2, and synchronizes the pulse signal Ssr2 with the rising edge of the oscillator signal OSC to the low level Lt; / RTI >

The inverter element INV2 inverts the pulse signal Ssr2 which is the output signal of the SR latch SR2 and outputs the inverted pulse signal / Ssr2 to the set terminal S of the SR latch SR3.

The SR latch SR3 includes a reset terminal R to which the pulse signal Scom2 as the output signal of the comparator COMP2 is inputted and a set terminal R to which the inverted pulse signal / Ssr2, which is the output signal of the inverter element INV2, S and an inverted output terminal / Q connected to the OR gate OR2. The SR latch SR3 has a low level in synchronization with the rising edge of the inverted pulse signal / Ssr2 input to the set terminal S and is synchronized with the rising edge of the pulse signal Scom2 input to the reset terminal R And outputs the pulse signal Ssr3 having the high level to the inverted output terminal / Q.

The OR gate OR2 receives an inverted pulse signal / Ssr2 and a pulse signal Ssr3 as an output signal of the SR latch SR3 and performs a logical sum operation on the two signals / Ssr2 and Ssr3 to generate a duty signal Sduty. And outputs it to the gate driver 130.

The operation of the duty controller 120 will be described in detail with reference to FIGS. 6 and 7. FIG.

FIG. 6 is a view showing a reference pulse signal of the oscillator, a sense voltage, a reference voltage, an operation waveform of the up-down counter, and two control signals, and FIG. 7 is a diagram showing an operation waveform of the duty controller.

6 and 7, the detection voltage Vse is higher than the reference voltage Vref and is lower than the feedback voltage Vfb during a period (before T1) before the count value of the up-down counter 122 becomes the set value. . Therefore, the pulse signal Scom1 becomes low level, and accordingly, the low level pulse signal Sand is outputted. The pulse signal Scom1 maintains the low level until the time point T6 when the sensing voltage Vse becomes lower than the reference voltage Vref so that the pulse signal Sand1 also maintains the low level until the time point T6.

The low-level pulse signal Sand1 is input to the set terminal S of the SR latch SR1 until the time point T6 and the delayed inverted oscillator signal / OSC 'is input to the reset terminal R of the SR latch SR1. Is input, the pulse signal Ssr1 is held at the low level until the time point T6. That is, before the count value of the up-down counter 122 becomes larger than the set value, the low-level pulse signal Scou and the low-level pulse signal Ssr1 are input to the OR gate OR1, Sor1) are input to the set terminal S of the SR latch SR2. Therefore, in the period (before T1), the pulse signal Ssr2 becomes low level, so that the high-level inverted pulse signal / Ssr2 is input to the set terminal S of the SR latch SR3 and the OR gate OR2 . Since the low-level pulse signal Scom2 is input to the reset terminal R of the SR latch SR3, the duty signal Sduty maintains the high level. Therefore, both the main switch Ml and the sub-switch M2 remain off.

Thereafter, at the time T1 when the value of the count becomes larger than the set value, the high-level pulse signal Scou is input to the set terminal S of the SR latch SR2, so that the pulse signal Ssr2 becomes high level. The pulse signal Ssr2 maintains a high level until a time point T5 when the oscillator signal OSC becomes a high level.

When the pulse signal Ssr2 becomes a high level, the set terminal S of the SR latch SR3 and the low-level pulse signal / Ssr2 are input to the OR gate OR2. Since the low-level pulse signal Scom2 is input to the reset terminal R of the SR latch SR3, the duty signal Sduty becomes low level. The main switch M1 is turned on at a time point T2 after a predetermined dead time in response to the low level of the duty signal Sduty.

When the main switch M1 is turned on, the sense voltage Vse begins to increase as described above.

At the time T3 when the sense voltage Vse becomes equal to the feedback voltage Vfb, the high-level pulse signal Scom2 is input to the reset terminal R of the SR latch SR3, and the pulse signal Ssr2 is high Level, the set terminal S of the SR latch SR3 and the low-level pulse signal / Ssr2 are input to the OR gate OR2. Then, the pulse signal Ssr3 becomes high level, so that the duty signal Sduty becomes high level. Therefore, the sub-switch M2 is turned on at a time point T4 after a predetermined dead time in response to the high level of the duty signal Sduty. Accordingly, the sense voltage Vse is lowered.

At the time T5 when the oscillator signal OSC becomes high level, the pulse signal Ssr2 becomes low level, so that the high level inverted pulse signal / Ssr2 is output to the set terminal S of the SR latch SR3 And an OR gate OR2. At this time, since the sense voltage Vse is lower than the feedback voltage Vfb, the low level pulse signal Scom2 is input to the reset terminal R of the SR latch SR3. Then, the low-level pulse signal Ssr3 is input to the OR gate OR2, so that the duty signal Sduty maintains the high level. That is, the sub-switch M2 maintains the on-state even when the oscillator signal OSC goes low.

Thereafter, at the time point T6 when the detection voltage Vse becomes equal to the reference voltage Vref, the pulse signal Scom1 is at the high level and the oscillator signal OSC is at the high level, . That is, the high-level pulse signal Sand1 is input to the set terminal S of the SR latch SR1 and the low-level inverted oscillator signal / OSC is input to the reset terminal R of the SR latch SR1 The delayed inverted oscillator signal / OSC 'is at the low level and the pulse signal Ssr1 is at the high level at the time T6 when the sensing voltage Vse becomes equal to the reference voltage Vref.

The pulse signal Sand2 maintains the low level since the low level inverted oscillator signal / OSC and the high level pulse signal Ssr1 are input to the AND gate AND2. Then, since the low-level pulse signal Sand2 and the low-level pulse signal Scou are input to the OR gate OR1, the pulse signal Sor1 also maintains a low level. At this time, since the oscillator signal OSC has a high level, the pulse signal Ssr2 becomes a high level. Therefore, since the low level inverted pulse signal / Ssr2 is input to the set terminal S of the SR latch SR3 and the OR gate OR2, the duty signal Sduty maintains the high level of the previous state.

Next, at the time point T7 when the oscillator signal OSC goes low, the sense voltage Vse is lower than the reference voltage Vref so that the pulse signal Scom1 goes high and the oscillator signal OSC goes low Level, the pulse signal Sand1 becomes low level. That is, when the low-level pulse signal Sand1 is input to the set terminal S of the SR latch SR1, the delayed inverted oscillator signal / OSC ' Level.

Therefore, the low-level delay inversion oscillator signal / OSC 'is input to the reset terminal R of the SR latch SR1, so that the pulse signal Ssr1 maintains the high level. As a result, the AND gate AND2 outputs the high-level pulse signal Sand2. As a result, the count value of the up-down counter 122 is reset while the pulse signal Sor1 is at the high level. The delayed inverted oscillator signal / OSC 'becomes high level after the delay time Td1 of the delay unit 224 from the time point T7 when it is input to the set terminal S of the SR latch SR1 , The pulse signal Ssr1 becomes low level at a time point after the delay time Td1 from the time point T7.

Level pulse signal Sor1 is input to the set terminal S of the SR latch SR2 and the low level oscillator signal OSC is input to the reset terminal R of the SR latch SR2 at the time T7, The pulse signal Ssr2 becomes high level and the low level inverted pulse signal / Ssr2 is input to the set terminal S of the SR latch SR3 and the OR gate OR2. Since the low level pulse signal Scom2 is input to the reset terminal R of the SR latch SR3, the SR latch SR3 maintains the previous state. That is, since the low-level pulse signal Ssr3 and the low-level pulse signal / Ssr2 are input to the OR gate OR2, the duty signal Sduty becomes low level. Then, in response to the low level of the duty signal Sduty, the sub switch M2 is turned off and the main switch M1 is turned on at a time point T8 after a predetermined dead time.

Since the duty signal Sduty becomes low level at the time points T9, T10 and T11 when the oscillator signal OSC becomes low level, the sub-switch M2 is turned on And the main switch M1 is turned on after a predetermined dead time (Dead Time).

That is, according to the embodiment of the present invention, when the sensing voltage Vse becomes equal to the feedback voltage Vfb and the oscillator signal OSC is at the low level and the sensing voltage Vse becomes lower than the reference voltage Vref The sub-switch M2 is turned on. Then, shoot-through current may not be generated.

The embodiments of the present invention are not limited to the above-described apparatuses and / or methods, but may be implemented through a program for realizing functions corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, Such an embodiment can be readily implemented by those skilled in the art from the description of the embodiments described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (21)

An apparatus for controlling a main switch and a sub-switch in a converter including a main switch and a sub-switch and generating an output voltage using a transformer,
An oscillator for generating an oscillator signal,
And comparing a signal corresponding to the oscillator signal, a signal corresponding to the primary current flowing through the primary coil of the transformer with a predetermined reference voltage, and a signal corresponding to the feedback voltage corresponding to the output voltage and a signal corresponding to the primary current A duty controller for generating a duty signal for controlling a switching operation of each of the main switch and the sub-switch using the result,
And a gate driver for generating first and second control signals for controlling the switching operation of the main switch and the sub switch by using the duty signal,
The duty control unit includes:
On period of the sub-switch based on a result of comparison between a maximum turn-on time of the sub-switch and a signal corresponding to the primary current and the predetermined reference voltage. The method according to claim 1,
The duty control unit includes:
Determining a turn-on time of the main switch and a turn-off time of the sub-switch using a result of comparing the oscillator signal, the signal corresponding to the primary current, and the reference voltage, And determining a turn-off time of the main switch and a turning-on time of the sub switch by using a result of comparing the voltage and the feedback voltage. 3. The method of claim 2,
The duty control unit includes:
And a control unit that sets a maximum turn-on time of the sub-switch when the voltage of the signal corresponding to the primary current is higher than the reference voltage within the maximum turn-on time, Off time of the sub-switch. The method of claim 3,
The duty control unit includes:
And an up-down counter for setting a maximum turn-on time of the sub-switch. 5. The method of claim 4,
The up-
The count value is increased in response to the oscillator signal and the first pulse signal is outputted to reset the count value when the count value is larger than the set value,
The sub-switch is turned off according to the first pulse signal,
And the maximum turn-on time includes a time from when the count value is reset until when the first pulse signal is output. 6. The method of claim 5,
Wherein the oscillator signal alternates between a first level and a second level,
The duty control unit includes:
And turns off the sub-switch when the oscillator signal in the maximum turn-on time is lower than the reference voltage in the signal corresponding to the primary current at the first level. The method according to claim 6,
The duty control unit includes:
A comparator for comparing the reference voltage with a voltage of a signal corresponding to the primary current to output a second pulse signal,
An inverter for inverting the oscillator signal to output an inverted oscillator signal, and
Further comprising a first AND gate for ANDing a third pulse signal corresponding to the second pulse signal and the inverted oscillator signal to output a fourth pulse signal,
And the sub-switch is turned off in response to the fourth pulse signal. 8. The method of claim 7,
The duty control unit includes:
A second AND gate for ANDing the second pulse signal and the oscillator signal to output a fifth pulse signal,
A delay unit for delaying the inverting oscillator signal, and
And a reset terminal to which the delayed inverted oscillator signal is input and which generates the third pulse signal using the fifth pulse signal and the inverted oscillator signal, Further comprising a latch. 8. The method of claim 7,
The duty control unit includes:
And determines when the voltage of the signal corresponding to the primary current becomes equal to the feedback voltage as the turn-off time of the main switch. 10. The method of claim 9,
The duty control unit includes:
And a second comparator for comparing the voltage of the signal corresponding to the primary current with the feedback voltage to output a fifth pulse signal,
And the main switch is turned off in response to the fifth pulse signal. 11. The method of claim 10,
The duty control unit includes:
A first OR gate for generating a sixth pulse signal by ORing the first pulse signal and the fifth pulse signal,
A second SR latch having a set terminal receiving the sixth pulse signal and a reset terminal receiving the oscillator signal and generating a seventh pulse signal using the sixth pulse signal and the oscillator signal,
And a logic element for generating the duty signal by using the seventh pulse signal and the fifth pulse signal. 12. The method of claim 11,
The logic element comprises:
An inverter element for inverting the seventh pulse signal to generate an eighth pulse signal,
A reset terminal to which the fifth pulse signal is inputted and a set terminal to which the eighth pulse signal is inputted and generates a ninth pulse signal by using the fifth pulse signal and the eighth pulse signal A third SR latch for outputting the ninth pulse signal to the inverted output terminal,
Further comprising an OR gate for performing an OR operation on the ninth pulse signal and the eighth pulse signal to generate the duty signal. A main switch for performing a switching operation in response to a first control signal,
A sub switch connected between the main switch and the ground terminal in response to a second control signal having a phase different from the first control signal,
A transformer for converting an input voltage into an output voltage by switching operations of the main switch and the sub-switch, the transformer including a primary coil and a secondary coil connected to an output terminal,
Generating a first control signal and a second control signal by using a feedback voltage corresponding to the output voltage and a voltage of a signal corresponding to a current flowing in the primary coil, and determining whether the maximum turn-on time of the sub- And a controller for controlling a turn-on period of the sub-switch based on a result of comparing a signal corresponding to a current flowing through the primary coil with a predetermined reference voltage, and controlling a voltage of a signal corresponding to the current flowing in the primary coil, And a switch control device for extending the turn-on time of the sub-switch when the voltage is higher than a predetermined voltage. 14. The method of claim 13,
The switch control device includes:
Turns off the main switch and turns on the sub-switch corresponding to a time point when a voltage of a signal corresponding to a current flowing in the primary coil becomes equal to the feedback voltage,
The converter turns off the sub-switch and turns on the main switch at a time when the voltage of the signal corresponding to the current flowing in the primary coil at the first level of the oscillator signal becomes lower than the reference voltage. 15. The method of claim 14,
The switch control device includes:
A converter that sets the maximum turn-on time of the sub-switch and turns off the sub-switch in response to the maximum turn-on time when the voltage of the signal corresponding to the current flowing in the primary coil during the set period is higher than the reference voltage . 16. The method of claim 15,
The switch control device includes:
And an up-down counter for increasing a count value in response to the oscillator signal and resetting the count value by outputting a first pulse signal when the count value is greater than a set value,
And the sub-switch is turned off in response to the first pulse signal. 17. The method of claim 16,
And the maximum turn-on time includes a period from the reset of the count value to the output of the first pulse signal. 17. The method of claim 16,
The switch control device includes:
An oscillator for generating the oscillator signal,
A first comparator that compares a voltage of a signal corresponding to a current flowing through the primary coil with the reference voltage to generate a second pulse signal;
And a logic element for outputting a third pulse signal using the oscillator signal and the second pulse signal,
And turns off the sub-switch and turns on the sub-switch in response to the third pulse signal. 19. The method of claim 18,
The logic element comprises:
A first AND gate that performs an AND operation of the second pulse signal and the oscillator signal to generate a fourth pulse signal;
And a second AND gate for performing an AND operation on the fourth pulse signal and a signal for inverting the oscillator signal to generate the third pulse signal. 19. The method of claim 18,
The switch control device includes:
A second comparator that compares a voltage of a signal corresponding to a current flowing through the primary coil with the feedback voltage to generate a fourth pulse signal;
≪ / RTI > 21. The method of claim 20,
The switch control device includes:
An output terminal, a set terminal to which the first pulse signal or the second pulse signal is input, and a reset terminal to which the oscillator signal is input, latches the first pulse signal or the second pulse signal, A first SR latch for generating an output signal,
An inverter element for inverting the fifth pulse signal to generate a sixth pulse signal,
A delay unit for delaying the sixth pulse signal, and
And a reset terminal to which the fourth pulse signal is inputted and latches the sixth pulse signal to generate a seventh pulse signal to be inverted to an inverted output terminal A second SR latch for outputting
And an AND circuit for generating an eighth pulse signal by performing an OR operation on the sixth pulse signal and the seventh pulse signal,
Further comprising:
And the eighth pulse signal is used to turn off the main switch and turn on the sub switch.

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