JP4352299B2 - Magnetic demagnetization reduction circuit in power converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
According to the present invention, in a power converter such as a DC-DC converter having a semiconductor switching element connected in a full bridge on the primary side of the transformer, the magnetic elements of the transformer are reduced to protect the circuit elements . The present invention relates to a demagnetization reduction circuit.
[0002]
[Prior art]
FIG. 5 shows the prior art of a DC-DC converter having a full bridge circuit with a semiconductor switching element on the primary side of the transformer.
5, P ₁ and N ₁ are DC input terminals, P ₂ and N ₂ are DC output terminals, C ₁ is an input side smoothing capacitor, C ₂ is an output side smoothing capacitor, Q ₁ , Q ₂ , Q ₃ , Q ₄ is a semiconductor switching element such as a MOSFET connected in a full bridge, C _S1 , C _S2 , C _S3 , and C _S4 are snubber capacitors connected in parallel to the switching elements Q ₁ , Q ₂ , Q ₃ , and Q ₄ , Tr Is a transformer in which a primary winding is connected between the series connection point of the switching elements Q ₁ and Q _{2 and} the series connection point of the switching elements Q ₃ and Q ₄ , and D ₁ , D ₂ , D ₃ , and D ₄ are diode constituting a connected to full-wave rectifier circuit on the secondary winding of the transformer Tr, L ₁ is a smoothing reactor. Note that C _S1 , C _S2 , C _S3 , and C _S4 may be substituted by parasitic capacitances of the switching elements Q ₁ , Q ₂ , Q ₃ , and Q ₄ .
[0003]
Next, FIG. 6 is a block diagram of a control circuit for controlling the DC-DC converter of FIG. 5, and FIG. 7 is an operation waveform diagram thereof.
In this control circuit, a sawtooth carrier waveform from the oscillation circuit and the bias value A are compared by the carrier comparison circuit 21 to generate a clock pulse A ′, and the clock pulse A ′ is divided by the frequency dividing circuit 22. together to create a gate signal to the semiconductor switching element Q ₁ Te, are creating a gate signal to the semiconductor switching element Q ₂ and inverts the gate signal.
[0004]
Further, the carrier comparison circuit 21 compares the carrier waveform with the command value B to generate a signal B ′, and the signal B ′ is divided by the frequency dividing circuit 22 to generate a gate signal for the semiconductor switching element Q _3. while, as the by the gate signal inverted are creating a gate signal to the semiconductor switching element Q ₄ (in the following, the use of code Q ₁ to Q ₄ of the device also gate signals as required To do).
By creating each gate signal in this way, the phase of the gate signals of the semiconductor switching elements Q ₃ and Q ₄ can be shifted with respect to the gate signals of the semiconductor switching elements Q ₁ and Q ₂ by the command value B.
[0005]
As shown in FIG. 7, a positive voltage is applied to the primary side of the transformer Tr while the gate signals of the semiconductor switching elements Q ₁ and Q ₄ are on, and the gate signals of the semiconductor switching elements Q ₂ and Q ₃ A negative voltage is applied to the primary side of the transformer Tr during the period when is on.
As a result, the positive / negative period of the primary voltage V _tr1 of the transformer Tr can be changed depending on the value of the command value B, so that the magnitude of the DC voltage output from the DC output terminals P ₂ and N ₂ is controlled. It becomes possible.
[0006]
[Problems to be solved by the invention]
In the prior art described above, the positive side and the negative side of the primary voltage V _tr1 of the transformer Tr due to variations in the delay of the gate signal for each of the switching elements Q ₁ , Q ₂ , Q ₃ , Q ₄ , variations in the ON voltage, and the like. There are cases in which the periods of are not equal. As a result, an error occurs between the positive side voltage and the negative side voltage, causing the transformer Tr to become demagnetized, and an excessive current flows through the conversion circuit, possibly destroying the circuit element.
[0007]
The present invention has been to prevent the destruction of the circuit elements to reliably reduce magnetic deflection of the transformer, it is intended to provide a polarization磁低down circuit that put the power converter.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, a magnetic field reduction circuit according to claim 1 is a power conversion device having a semiconductor switching element connected to a primary side of a transformer in a full bridge connection, and includes a switching element of one upper and lower arm. In the power conversion device that performs switching control by shifting the phase of the on / off signal of the switching elements of the other upper and lower arms with respect to the on / off signal,
Means for detecting the amount of magnetization of the transformer ;
When the detected amount of demagnetization is positive, the signal obtained by comparing the carrier waveform and the amount of demagnetization used to create the on / off signal of each switching element with respect to the switching element of one upper arm Means for outputting a signal obtained by a logical product with the original on signal as a final on signal for the switching element;
When the detected amount of demagnetization is negative, a signal obtained by ANDing the signal obtained by comparing the carrier waveform with the amount of demagnetization and the original ON signal for the switching element of one lower arm, Means for creating a final on signal for the switching element;
It is equipped with .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiment, the present invention is applied to the DC-DC converter of FIG. 5 described above.
[0011]
FIG. 1 is a block diagram of the present embodiment, and FIG. 2 shows a part related to the gate signals of the semiconductor switching elements Q ₁ and Q ₂ in the carrier comparison circuit 24 and the bias control circuit 30 in FIG. 2 is the main part of the carrier comparison circuit 24 and the bias control circuit 30).
FIG. 3 is an operation waveform diagram when the amount of demagnetization of the transformer Tr is positive, and FIG. 4 is an operation waveform diagram when the amount of demagnetization is negative.
Here, the connection configuration and operation of the carrier comparison circuit 21 and the frequency dividing circuit 22 in FIG. 1 are the same as those in FIGS. 6 and 7, and the following description will focus on the different parts.
[0012]
In FIG. 1, reference numeral 23 denotes a demagnetization amount detection circuit. The current or voltage of the transformer Tr in FIG. 5 is applied to the detection circuit 23, and the demagnetization amount is detected by obtaining an average value thereof. Is configured to do.
The positive or negative bias amount detected by the bias amount detection circuit 23 is input to the carrier comparison circuit 24, and this bias amount is compared with the same carrier waveform as that input to the carrier comparison circuit 21. The
[0013]
In the carrier comparison circuit 24, the signal D or D ′ obtained as a result of the comparison with the positive or negative bias amount is input to the bias control circuit 30. Gate signals Q ₁ ′ (Q ₁ ), Q ₂ (Q ₂ ′), Q ₃ , Q ₄ are created using the input gate signals Q _{1 to} Q ₄ and the signal D or D ′.
Here, the gate signals Q ₁ ′ and Q ₂ ′ are signals for the switching elements Q ₁ and Q _{2 in} FIG. 5, and the gate signals Q ₃ and Q ₄ are signals for the switching elements Q ₃ and Q ₄ , as will be described later. Gate signals Q ₁ ′, Q ₂ , Q ₃ , Q ₄ are output when the amount of magnetic bias is positive, and gate signals Q ₁ , Q ₂ ′, Q ₃ , Q ₄ are output when the amount of magnetic bias is negative. Shall.
[0014]
Hereinafter, the operation when the amount of magnetic bias is positive will be described with reference to FIGS. 2 and 3. Note that the carrier comparison circuit 21 and the frequency dividing circuit 22 operate in the same manner as in the prior art. As a result, the frequency dividing circuit 22 can obtain gate signals Q _{1 to} Q ₄ as shown in FIG.
[0015]
As shown in FIG. 3, when the amount of bias is positive (H> 0), the carrier comparison circuit 24 compares the amount of bias with the carrier waveform and outputs a signal D. This signal D is output from the first comparator 31 in FIG. When the amount of magnetic bias is negative, the signal D is always at the high level, so that the gate signal Q ₁ is output as it is as Q ₁ ′.
[0016]
The first AND circuit 33 of FIG. 2, since the signal D and the original gate signal Q ₁ is being input, when polarized磁量is positive, the output signal Q _{1 'is} as shown in FIG. 3 based on amount corresponding on-pulse width proportional to the polarization磁量to the gate signal to Q ₁ is short signals.
As a result of the above-described operation, the on-pulse width of the signal Q ₁ ′ becomes shorter as the amount of demagnetization increases to the positive side, and the positive side of the transformer Tr becomes positive during the period in which the signal Q ₁ ′ and the signal Q ₄ are on. Since the period during which the voltage is applied is also shortened, as a result, the operation is performed so as to reduce the positive bias.
[0017]
That is, by changing the duty ratio of the ON-OFF signal for the switching element Q _1, Q ₂ by shortening the pulse width of the gate signal of the switching element Q _1, it is possible to reduce the positive magnetic bias.
[0018]
Next, the operation when the amount of magnetic bias is negative will be described with reference to FIGS. In this case, it is assumed that gate signals Q _{1 to} Q ₄ as shown in FIG.
[0019]
As shown in FIG. 4, when the amount of bias is negative (H <0), the carrier comparison circuit 24 compares the amount of bias with the carrier waveform and outputs a signal D ′. This signal D ′ is output from the second comparator 32 in FIG. When the amount of bias is positive, the signal D ′ is always at the high level, so that the gate signal Q ₂ is output as it is as Q ₂ ′.
[0020]
Since the signal D ′ and the original gate signal Q ₂ (inverted signal of the signal Q ₁ ) are input to the second AND circuit 34 in FIG. 2, the output signal Q Q when the amount of bias is negative. _As shown in FIG. 4, ₂ ′ is a signal having an on-pulse width that is shorter than the original gate signal Q ₂ by an amount proportional to the amount of magnetization.
As a result of the above-described operation, the on-pulse width of the signal Q ₂ ′ becomes shorter as the amount of demagnetization increases on the negative side, and the negative side of the transformer Tr becomes negative during the period in which the signal Q ₂ ′ and the signal Q ₃ are on. Since the period during which the voltage is applied is also shortened, as a result, the operation is performed so as to reduce the negative bias.
[0021]
In other words, by changing the duty ratio of the ON-OFF signal for the switching element Q _1, Q ₂ by shortening the pulse width of the gate signal of the switching element Q _2, it is possible to reduce the negative side of the magnetic bias.
[0022]
In the above embodiment, the on-pulse width of the gate signal for the switching elements Q ₁ and Q ₂ of one of the upper and lower arms is shortened to change the duty ratio, but the switching ratio of the other upper and lower arms to the switching elements Q ₃ and Q _{4 is changed} . Even if the on-pulse width of the gate signal is shortened, the same operation can be performed.
The present invention can also be applied to a DC-AC converter that obtains an AC output as it is from the secondary side of the transformer Tr.
[0023]
【The invention's effect】
As described above, according to the present invention, the on-pulse width of the switching element of the upper arm or the lower arm is controlled according to the amount of magnetic bias of the transformer, and the duty ratio of the on / off signal for each switching element is changed. Since the amount of bias is reduced, the circuit elements of the power converter can be reliably protected from excessive current due to bias.
[Brief description of the drawings]
FIG. 1 is a block diagram of a demagnetization reduction circuit showing an embodiment of the present invention.
FIG. 2 is a configuration diagram of a main part of FIG. 1;
FIG. 3 is an operation waveform diagram when the amount of bias is positive.
FIG. 4 is an operation waveform diagram when the amount of bias is negative.
FIG. 5 is a configuration diagram of a DC-DC converter.
6 is a block diagram of the control circuit of FIG. 5. FIG.
7 is an operation waveform diagram of FIG. 6. FIG.
[Explanation of symbols]
P ₁ , N ₁ DC input terminal P ₂ , N ₂ DC output terminal C ₁ input side smoothing capacitor C ₂ output side smoothing capacitor Q ₁ , Q ₂ , Q ₃ , Q ₄ semiconductor switching elements C _S1 , C _S2 , C _S3 , C _S4 snubber capacitor Tr Transformer D ₁ , D ₂ , D ₃ , D ₄ diode L ₁ Smoothing reactor 21, 24 Carrier comparison circuit 22 Divider circuit 23 Demagnetization amount detection circuit 30 Demagnetization control circuit 31, 32 Comparison 33, 34 AND circuit 35 Main parts of carrier comparison circuit 24 and bias control circuit 30

Claims (1)

A power conversion device having a semiconductor switching element connected to a primary side of a transformer in a full bridge, wherein an on / off signal of a switching element of another upper and lower arm is compared with an on / off signal of the switching element of one upper and lower arm. In the power conversion device that performs switching control by shifting the phase,
Means for detecting the amount of magnetization of the transformer ;
When the detected amount of demagnetization is positive, the signal obtained by comparing the carrier waveform and the amount of demagnetization used to create the on / off signal of each switching element with respect to the switching element of one upper arm Means for outputting a signal obtained by a logical product with the original on signal as a final on signal for the switching element;
When the detected amount of demagnetization is negative, a signal obtained by ANDing the signal obtained by comparing the carrier waveform with the amount of demagnetization and the original ON signal for the switching element of one lower arm, Means for creating a final on signal for the switching element;
A demagnetization reduction circuit in a power conversion device, comprising:

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