JP2003037973A - Biased magnet reducing method and biased magnet reducing circuit in power conversion equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect circuit elements by reducing biased magnet of a transformer within power conversion equipment. SOLUTION: A biased magnet reducing method and biased magnet reducing equipment are provided that are applied for power conversion equipment, which comprises semi-conductor switching elements Q1 -Q4 connected full-bridge to the primary side of a transformer Tr, wherein switching is controlled, in response to On-Off signals of switching elements Q1 , Q2 of an upper and lower arm, by shifting the phases of On-Off signals of switching elements Q3 , Q4 of another upper and lower arm, the method and equipment causing detection of the amount of biased magnet of the transformer Tr, and change in the duty ratio of On-Off signals of the switching elements Q1 , Q2 of an upper and lower arm in response to the amount of the biased magnet, thereby reducing the amount of biased magnet.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter such as a DC-DC converter having a semiconductor switching element that is full-bridge connected to the primary side of the transformer, and reduces the magnetic bias of the transformer to reduce the circuit. The present invention relates to a bias magnetic reduction method and a bias magnetic reduction circuit for protecting an element.

[0002]

2. Description of the Related Art FIG. 5 shows a semiconductor switch on the primary side of a transformer.
DC-DC with a full-bridge circuit with a ching element
1 shows the prior art of a converter. In FIG.
P₁, N₁Is a DC input terminal, P_Two, N_TwoIs the DC output end
Child, C₁Is the input side smoothing capacitor, C_TwoIs the output smoothing
Indexer, Q₁, Q_Two, Q_Three, Q _FourFull bridge connection
Switching device such as MOSFET, C
_S1, C_S2, C_S3, C_S4Is each switching element Q
₁, Q_Two, Q_Three, Q_FourSnubbers connected in parallel to
Capacitor and Tr are switching elements Q₁, Q_TwoIn series
Connection point and switching element Q_Three, Q_FourWith the series connection point of
Transformer with primary winding connected between them, D₁, D_Two, D_Three，
D_FourIs connected to the secondary winding of the transformer Tr and is a full-wave rectifier circuit
, The diode that makes up L₁Is a smoothing reactor
It Note that C_S1, C_S2, C_S3, C_S4Is each
Touching element Q₁, Q_Two, Q_Three, Q_FourDepending on the parasitic capacitance of
You may substitute it.

Next, FIG. 6 is a block diagram of a control circuit for controlling the DC-DC converter of FIG. 5, and FIG. 7 is an operation waveform diagram thereof. In this control circuit, the carrier waveform of the sawtooth waveform from the oscillation circuit and the bias value A are compared by the carrier comparison circuit 21 to create a clock pulse A ′, and this clock pulse A ′ is divided by the frequency dividing circuit 22. The gate signal for the semiconductor switching element Q ₁ is generated, and the gate signal is inverted to generate the gate signal for the semiconductor switching element Q ₂ .

In addition, the carrier comparison circuit 21
The signal B'is created by comparing the waveform and the command value B, and this signal
The number B'is divided by the frequency dividing circuit 22 and the semiconductor switch
Element Q_ThreeCreate a gate signal for
Semiconductor switching element Q by inverting the gate signal_FourAgainst
I am creating a gate signal to
Depending on the₁~ Q_FourTo
Shall be used). Create each gate signal in this way
By switching the command value B to semiconductor switching
Element Q₁, Q_TwoThe semiconductor switch for the gate signal of
Element Q_Three, Q _FourThe phase of the gate signal of
You can

As shown in FIG. 7, a positive voltage is applied to the primary side of the transformer Tr while the gate signals of the semiconductor switching elements Q ₁ and Q ₄ are on, and the semiconductor switching elements Q ₂ and Q ₃ are turned on. A negative voltage is applied to the primary side of the transformer Tr during the period when the gate signal of is on. As a result, the primary side voltage V of the transformer Tr depends on the value of the command value B.
_Since the positive / negative period of _tr1 can be changed, it becomes possible to control the magnitude of the DC voltage output from the DC output terminals P ₂ and N ₂ .

[0006]

In the above-mentioned prior art, the primary side of the transformer Tr is affected by variations in the delay of the gate signal with respect to the switching elements Q ₁ , Q ₂ , Q ₃ , Q ₄ and variations in the ON voltage. There may be a case where the positive and negative periods of the voltage _Vtr1 are not equal. As a result, an error occurs between the positive side voltage and the negative side voltage, and the transformer Tr
Could become a magnetically demagnetized state, and an excessive current would flow through the conversion circuit, possibly destroying the circuit element.

[0007] Therefore, the present invention is intended to provide a bias magnetic reduction method and a bias magnetic reduction circuit in a power conversion device that surely reduces the bias magnetic polarization of a transformer to prevent the destruction of circuit elements. is there.

[0008]

In order to solve the above-mentioned problems, the method of reducing magnetic bias described in claim 1 is a power conversion device having a semiconductor switching element which is full-bridge connected to the primary side of a transformer. In a power converter in which the ON / OFF signals of the switching elements of one upper and lower arms are shifted to control the switching by switching the phases of the ON / OFF signals of the switching elements of the other upper and lower arms, the magnetic polarization of the transformer The amount of eccentricity is reduced by detecting the amount and changing the duty ratio of the on / off signal of the switching element of one upper and lower arm according to the amount of eccentricity.

According to another aspect of the present invention, there is provided an eccentricity reducing circuit, which is a power conversion device having a semiconductor switching element connected in a full bridge on the primary side of a transformer, wherein one switching element of the upper and lower arms is turned on. In a power converter in which switching control is performed by shifting the phases of on / off signals of other switching elements of the upper and lower arms with respect to an off signal, a means for detecting the amount of bias of the transformer and the detected bias When the amount is positive, a signal obtained by comparing the amount of magnetic bias with the carrier waveform used to create the on / off signal of each switching element and the original on signal for the switching element of one upper arm And a means for outputting the signal obtained by the logical product of and as a final ON signal for the switching element, and when the detected bias amount is negative, A means for creating a signal obtained by a logical product of a signal obtained by comparing the carrier waveform and the amount of magnetic bias and the original ON signal for the switching element of the lower arm as a final ON signal for the switching element. And ,.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In addition, the following embodiment is based on FIG.
This is a case where the present invention is applied to the DC-DC converter of.

FIG. 1 is a block diagram of this embodiment, and FIG. 2 shows a part of the carrier comparison circuit 24 and the bias magnetic control circuit 30 in FIG. 1 related to the gate signals of the semiconductor switching elements Q ₁ and Q _2. (Reference numeral 3 in FIG. 2)
5 is a main part of the carrier comparison circuit 24 and the bias magnetic control circuit 30). Further, FIG. 3 is an operation waveform diagram when the bias magnetic amount of the transformer Tr is positive, and FIG. 4 is an operation waveform diagram when the bias magnetic amount is negative. Here, the carrier comparison circuit 21 of FIG.
The connection configuration and operation of the frequency divider circuit 22 and the frequency divider circuit 22 are similar to those in FIGS. 6 and 7, and different points will be mainly described below.

In FIG. 1, reference numeral 23 is a bias magnetic amount detection circuit. The detection circuit 23 is applied with the current or voltage of the transformer Tr shown in FIG. 5, and the bias value is obtained by obtaining the average value thereof. It is configured to detect a quantity. The positive or negative bias amount detected by the bias amount detection circuit 23 is input to the carrier comparison circuit 24, and this bias amount is compared with the same carrier waveform as that input to the carrier comparison circuit 21. It

In the carrier comparison circuit 24, the signal D or D'obtained as a result of comparison with the positive or negative magnetic bias amount is input to the magnetic bias control circuit 30, which divides the frequency. Gate signal Q ₁ input from the circuit 22
~ Q ₄ and the signal D or D ′ are used to generate gate signals Q ₁ ′ (Q ₁ ), Q ₂ (Q ₂ ′), Q ₃ and Q ₄ . Here, the gate signal _{Q 1} ', _{Q 2'} is the signal for the switching element _Q 1, _{Q 2} in FIG. 5, the gate signal _Q 3,
Q ₄ is a signal for the switching elements Q ₃ and Q ₄ , and as will be described later, when the bias amount is positive, the gate signals Q ₁ ′, Q ₂ , Q ₃ and Q ₄ are output, and the bias amount is negative. Occasionally, the gate signals Q ₁ , Q ₂ ′, Q ₃ , Q ₄ are output.

The operation when the amount of bias is positive will be described below with reference to FIGS. It is assumed that the carrier comparison circuit 21 and the frequency dividing circuit 22 operate in the same manner as the conventional technique, and as a result, the frequency dividing circuit 22 obtains the gate signals Q _{1 to} Q ₄ as shown in FIG.

As shown in FIG. 3, when the amount of magnetic bias is positive (H>
0), the carrier comparison circuit 24 compares the amount of eccentricity with the carrier waveform and outputs the signal D. This signal D is output from the first comparator 31 in FIG. When the amount of magnetic bias is negative, the signal D is always at the high level, so the gate signal Q ₁ is output as it is as Q ₁ ′.

The first AND circuit 33 shown in FIG.
Since the original gate signal Q ₁ and the original gate signal Q ₁ are input, the output signal Q ₁ ′ is proportional to the original gate signal Q _{1 as} shown in FIG. Only the ON pulse width is short. With the above-described operation, the on-pulse width of the signal Q ₁ ′ becomes shorter as the amount of bias magnetism increases to the positive side, and the positive side of the transformer Tr becomes positive when the signal Q ₁ ′ and the signal Q ₄ are on. The period in which the voltage is applied is also shortened, and as a result, the positive-side bias magnetism is reduced.

[0017] That is, the switching elements _Q 1 to shorten the pulse width of the gate signal of the switching element _{Q 1,}
By changing the duty ratio of the ON / OFF signal with respect to Q _2, it is possible to reduce the magnetic bias on the positive side.

Next, referring to FIGS. 2 and 4, the operation when the amount of bias is negative will be described. In this case, the frequency divider 2
It is assumed that the gate signals Q _{1 to} Q ₄ as shown in FIG.

As shown in FIG. 4, when the amount of bias is negative (H <
0), the carrier comparison circuit 24 compares the amount of eccentricity with the carrier waveform and outputs a signal D ′. This signal D ′ is shown in FIG.
Is output from the second comparator 32. When the amount of magnetic bias is positive, the signal D ′ is always at the high level, so the gate signal Q ₂ is output as it is as Q ₂ ′.

Since the signal D'and the original gate signal Q ₂ (inverted signal of the signal Q ₁ ) are input to the second AND circuit 34 of FIG. 2, when the amount of bias is negative, Output signal Q
_As shown in FIG. 4, 2'is a signal whose ON pulse width is shorter than that of the original gate signal Q ₂ by an amount proportional to the amount of magnetic bias.
According to the above-described operation, the on-pulse width of the signal Q ₂ ′ becomes shorter as the amount of eccentricity increases to the negative side, and a negative voltage is applied to the primary side of the transformer Tr while the signal Q ₂ ′ and the signal Q ₃ are on. The period in which the voltage is applied is shortened, and as a result, the negative-side bias magnetism is reduced.

That is, the ON pulse width of the gate signal of the switching element Q ₂ is shortened to make the switching elements Q ₁ , Q
By changing the duty ratio of the ON / OFF signal with respect to _2, it is possible to reduce the negative magnetic bias.

In the above embodiment, the duty ratio is changed by shortening the ON pulse width of the gate signal for the switching elements Q ₁ and Q ₂ of one upper and lower arms, but the switching element Q ₃ of the other upper and lower arms is changed. Even if the ON pulse width of the gate signal with respect to Q ₄ is shortened, the same operation can be performed. In addition, the present invention is a transformer T
It can also be applied to a DC-AC converter that directly obtains an AC output from the secondary side of r.

[0023]

As described above, according to the present invention, the on-pulse width of the switching element of the upper arm or the lower arm is controlled according to the amount of magnetic bias of the transformer, and the duty of the on / off signal for each switching element is controlled. Since the ratio is changed to reduce the amount of bias magnetization, the circuit element of the power conversion device can be reliably protected from excessive current due to bias magnetization.

[Brief description of drawings]

FIG. 1 is a block diagram of a bias magnetic reduction circuit showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a main part of FIG.

FIG. 3 is an operation waveform diagram when the amount of magnetic bias is positive.

FIG. 4 is an operation waveform diagram when the amount of magnetic bias is negative.

FIG. 5 is a configuration diagram of a DC-DC converter.

6 is a block diagram of the control circuit of FIG.

FIG. 7 is an operation waveform diagram of FIG.

[Explanation of symbols]

P ₁ , N ₁ DC input terminal P ₂ , N ₂ DC output terminal C ₁ Input side smoothing capacitor C ₂ Output side smoothing capacitor Q ₁ , Q ₂ , Q ₃ , Q ₄ Semiconductor switching elements C _S1 , C _S2 , C _S3 , C _S4 snubber capacitor Tr transformer D ₁ , D ₂ , D ₃ , D ₄ diode L ₁ smoothing reactor 21, 24 carrier comparison circuit 22 frequency dividing circuit 23 bias magnetic amount detection circuit 30 bias magnetic control circuit 31, 32 comparison 33, 34 AND circuit 35 Main part of carrier comparison circuit 24 and bias magnetic control circuit 30

Claims (2)

[Claims] 1. A power converter having a semiconductor switching element connected in a full bridge on the primary side of a transformer, wherein the ON / OFF signals of the switching elements of one upper and lower arms are compared with the switching elements of the other upper and lower arms. In a power conversion device configured to perform switching control by shifting a phase of an on / off signal, a bias magnetic amount of the transformer is detected, and a switching element of one upper and lower arm is turned on / off according to the bias magnetic amount. A method for reducing magnetic bias in a power conversion device, characterized in that the amount of magnetic bias is reduced by changing the duty ratio of a signal. 2. A power conversion device having a semiconductor switching element, which is full-bridge connected to the primary side of a transformer, wherein an ON / OFF signal of a switching element of one upper / lower arm is compared with a switching element of another upper / lower arm. In a power conversion device configured to perform switching control by shifting the phase of an on / off signal, a means for detecting the amount of magnetic bias of the transformer, and the switching elements when the detected amount of magnetic bias is positive. The signal obtained by comparing the carrier waveform used to create the ON / OFF signal of the above and the amount of magnetic bias and the original ON signal for the switching element of one upper arm Obtained by comparing the carrier waveform and the amount of bias when the detected amount of bias is negative and the means for outputting the final ON signal to the element. Means for creating a signal obtained by a logical product of the signal and the original ON signal for the switching element of the lower arm as a final ON signal for the switching element, Demagnetization circuit in equipment.