WO2023087347A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2023087347A1
WO2023087347A1 PCT/CN2021/132883 CN2021132883W WO2023087347A1 WO 2023087347 A1 WO2023087347 A1 WO 2023087347A1 CN 2021132883 W CN2021132883 W CN 2021132883W WO 2023087347 A1 WO2023087347 A1 WO 2023087347A1
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Prior art keywords
active layer
sub
layer
substrate
gate
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PCT/CN2021/132883
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English (en)
French (fr)
Inventor
胡凯
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惠州华星光电显示有限公司
深圳市华星光电半导体显示技术有限公司
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Priority to US17/621,250 priority Critical patent/US20240040833A1/en
Publication of WO2023087347A1 publication Critical patent/WO2023087347A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • the active layer is generally adopted as a single film layer of indium gallium zinc oxide. Due to the large oxygen flow rate during the film formation process, the oxygen content in the film layer of indium gallium zinc oxide is high, resulting in device failure. Poor electrical conductivity and low mobility. If the flow rate of oxygen is small during deposition, the oxygen content in the indium gallium zinc oxide film layer is small, and the oxygen vacancies are many, which will cause the interface between the first gate insulating layer and the indium gallium zinc oxide film layer and the interface between the second gate insulating layer and the indium gallium oxide film to be damaged. There are many defects at the interface of the zinc oxide film layer, which leads to poor stability of the device.
  • Embodiments of the present application provide a display panel and a manufacturing method thereof, which are used to improve the stability of the display panel.
  • An embodiment of the present application provides a display panel, and the display panel includes:
  • the first gate is disposed on the substrate
  • first gate insulating layer is disposed on the substrate
  • the active layer is disposed on the substrate, the active layer and the first gate are disposed in different layers, and the active layer at least includes a stacked first sub-active layer, A second sub-active layer, the first sub-active layer is disposed on the substrate, and the second sub-active layer is disposed on a side of the first sub-active layer away from the substrate, so The number of atoms of gallium in the first sub-active layer is greater than the number of atoms of gallium in the second sub-active layer;
  • the interlayer dielectric layer is disposed on the substrate;
  • the first via hole at least penetrates through the interlayer dielectric layer
  • the second via hole at least penetrates through the interlayer dielectric layer
  • the source electrode is disposed on the interlayer layer and is electrically connected to the active layer through the first via hole;
  • drain electrode is disposed on the interlayer dielectric layer and is electrically connected to the active layer through the second via hole.
  • the active layer further includes:
  • the third sub-active layer, the third sub-active layer is arranged on the second sub-active layer, the number of gallium atoms in the third sub-active layer is greater than that in the second sub-active layer Atomic number of gallium.
  • the material of the first sub-active layer includes indium gallium zinc oxide, wherein the number of indium atoms, gallium atoms and zinc atoms in the first sub-active layer
  • the first sub-active layer includes a nitrogen-doped indium gallium zinc oxide active layer
  • the third sub-active layer includes a nitrogen-doped indium gallium Zinc oxide active layer
  • the first gate is disposed on the substrate, the first gate insulating layer covers the first gate, and the active layer is disposed on the first gate.
  • a gate insulating layer is away from the side of the substrate, and the interlayer dielectric layer covers the active layer and the first gate insulating layer.
  • the first gate is disposed on the substrate, the first gate insulating layer covers the first gate, and the active layer is disposed on the first gate.
  • a gate insulating layer is away from the side of the substrate, and the interlayer dielectric layer covers the active layer and the first gate insulating layer.
  • the display panel further includes:
  • the second gate insulating layer is disposed on a side of the active layer away from the first gate insulating layer;
  • the second gate is disposed on a side of the second gate insulating layer away from the active layer;
  • connection electrode is disposed in the third via hole and the fourth via hole, and is used for connecting the first gate and the second gate.
  • the active layer is arranged on the substrate, the first gate insulating layer covers the substrate and the active layer, and the first gate is arranged On a side of the first gate insulating layer away from the substrate, the interlayer dielectric layer covers the first gate and the first gate insulating layer.
  • the active layer is arranged on the substrate, the first gate insulating layer covers the substrate and the active layer, and the first gate is arranged On a side of the first gate insulating layer away from the substrate, the interlayer dielectric layer covers the first gate and the first gate insulating layer.
  • the thickness of the first sub-active layer and the thickness of the third sub-active layer are less than or equal to 15 nanometers, and the thickness of the second sub-active layer is between 10nm to 90nm.
  • the number of gallium atoms in the third sub-active layer is equal to the number of gallium atoms in the first sub-active layer.
  • the display panel further includes:
  • the passivation layer is disposed on the interlayer dielectric layer
  • the contact electrode is arranged on the passivation layer, and one end of the contact electrode is connected to the drain;
  • planarization layer disposed on the passivation layer
  • an anode disposed on the planarization layer, and the other end of the contact electrode is connected to the anode;
  • the pixel definition layer is disposed on the planarization layer and covers the anode;
  • a light emitting layer disposed within the opening of the pixel definition layer
  • the cathode is disposed on the light-emitting layer.
  • the embodiment of the present application also provides a method for manufacturing a display panel, and the method for manufacturing a display panel includes the following steps:
  • An active layer is formed on the substrate, the active layer and the first gate are arranged in different layers, and the active layer at least includes a first sub-active layer and a second sub-active layer that are stacked. , the second sub-active layer is disposed on the side of the first sub-active layer away from the substrate, and the number of gallium atoms in the first sub-active layer is greater than that in the second sub-active layer atomic number of gallium;
  • a source and a drain are formed on the substrate, wherein the source is electrically connected to the active layer through the first via hole, and the drain is electrically connected to the active layer through the second via hole.
  • the active layer is electrically connected;
  • the step of forming an active layer on the substrate includes:
  • InGaZn oxide is formed on the first sub-active layer to form the second sub-active layer.
  • step of forming indium gallium zinc oxide on the first sub-active layer to form the second sub-active layer further includes:
  • An oxide material is formed on the second sub-active layer, and the oxide material is doped with nitrogen to form the third sub-active layer.
  • a second gate is formed on the second gate insulating layer.
  • the step of forming the first via hole and the second via hole on the interlayer dielectric layer further includes:
  • a third via hole and a fourth via hole are formed on the interlayer dielectric layer.
  • the step of forming the source electrode and the drain electrode on the substrate further includes: forming a connection electrode on the substrate, and the connection electrode is arranged on the The third via hole and the fourth via hole are used to connect the first gate and the second gate.
  • the embodiment of the present application also provides a method for manufacturing a display panel, and the method for manufacturing a display panel includes the following steps:
  • An active layer is formed on the substrate, the active layer and the first gate are arranged in different layers, and the active layer at least includes a first sub-active layer and a second sub-active layer that are stacked. , the second sub-active layer is disposed on the side of the first sub-active layer away from the substrate, and the number of gallium atoms in the first sub-active layer is greater than that in the second sub-active layer atomic number of gallium;
  • a source and a drain are formed on the substrate, wherein the source is electrically connected to the active layer through the first via hole, and the drain is electrically connected to the active layer through the second via hole.
  • the active layer is electrically connected;
  • the step of forming an active layer on the substrate includes:
  • InGaZn oxide is formed on the first sub-active layer to form the second sub-active layer.
  • step of forming indium gallium zinc oxide on the first sub-active layer to form the second sub-active layer further includes:
  • An oxide material is formed on the second sub-active layer, and the oxide material is doped with nitrogen to form the third sub-active layer.
  • Embodiments of the present application provide a display panel and a manufacturing method thereof.
  • the active layer is configured as a structure of at least two layers, that is, the first sub-active layer and the second sub-active layer, wherein the atoms of gallium in the first sub-active layer The number is greater than the number of atoms of gallium in the second sub-active layer. Due to the strong binding ability between gallium and oxygen atoms, the generation of deep-level defects can be effectively suppressed, thereby improving the stability of the device.
  • FIG. 1 is a schematic structural diagram of a display panel provided in a first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a display panel provided in a second embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a display panel provided by a third embodiment of the present application.
  • FIG. 4 is a schematic plan view of the structure of the display panel provided by the third embodiment of the present application.
  • FIG. 5 is a circuit diagram corresponding to a thin film transistor of a display panel provided in the third embodiment of the present application.
  • FIG. 6 is a flow chart of the steps of the method for manufacturing a display panel provided in the first embodiment of the present application
  • FIG. 7 is a flow chart of the steps of the manufacturing method of the display panel provided by the third embodiment of the present application.
  • FIG. 8 to FIG. 13 are schematic diagrams of the manufacturing method of the display panel provided by the embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • Embodiments of the present application provide a display panel and a manufacturing method thereof. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • An embodiment of the present application provides a display panel.
  • the display panel includes a substrate, a first gate, a first gate insulating layer, an active layer, an interlayer dielectric layer, a first via hole, a second via hole, a source electrode and a drain electrode. pole.
  • the first gate is disposed on the substrate.
  • the first gate insulating layer is disposed on the substrate.
  • the active layer is arranged on the substrate, the active layer and the first gate are arranged in different layers, the active layer at least includes a first sub-active layer and a second sub-active layer that are stacked, and the first sub-active layer is arranged On the substrate, the second sub-active layer is disposed on the side of the first sub-active layer away from the substrate, and the number of gallium atoms in the first sub-active layer is greater than that of gallium in the second sub-active layer. atomic number.
  • the interlayer dielectric layer is disposed on the substrate.
  • the first via hole at least penetrates through the interlayer dielectric layer.
  • the second via hole at least penetrates through the interlayer dielectric layer.
  • the source electrode is arranged on the interlayer layer and is electrically connected with the active layer through the first via hole.
  • the drain is arranged on the interlayer dielectric layer and is electrically connected with the active layer through the second via hole.
  • the active layer is configured as a structure of at least two layers, that is, the first sub-active layer and the second sub-active layer, wherein the atoms of gallium in the first sub-active layer The number is greater than the number of atoms of gallium in the second sub-active layer. Due to the strong binding ability between gallium and oxygen atoms, the generation of deep-level defects can be effectively suppressed, thereby improving the stability of the device.
  • FIG. 1 is a schematic structural diagram of a display panel provided by a first embodiment of the present application.
  • the embodiment of the present application provides a display panel 100, the display panel 100 includes a substrate 101, a first gate 102a, an active layer 104, a source 106 and a drain 107, a first gate insulating layer 103a, an interlayer dielectric layer 105 , passivation layer 108 , contact electrode 202 , planarization layer 201 , pixel definition layer 203 , anode 204 , light emitting layer 205 and cathode 206 .
  • the active layer 104 is disposed on the substrate 101 .
  • the first gate insulating layer 103 a covers the substrate 101 and the active layer 104 .
  • the active layer 104 includes at least a first sub-active layer 104a and a second active layer 104b that are stacked.
  • the first sub-active layer 104a is disposed on the substrate 101, and the second sub-active layer 104b is disposed on the first sub-active layer.
  • the first gate 102 a is disposed on a side of the first gate insulating layer 103 a away from the substrate 101 .
  • the interlayer dielectric layer 105 covers the first gate 102a and the first gate insulating layer 103a.
  • the first via hole h1 and the second via hole h2 penetrate the interlayer dielectric layer 105 and the first gate insulating layer 103a, the source electrode 106 is electrically connected to the active layer 104 through the first via hole h1, and the drain electrode 107 is electrically connected through the second via hole h1.
  • the hole h2 is electrically connected to the active layer 104 .
  • the passivation layer 108 is disposed on the interlayer dielectric layer 105 and covers the source 106 and the drain 107 .
  • the contact electrode 202 is disposed on the passivation layer 108 . One end of the contact electrode 202 is connected to the drain 107 .
  • a planarization layer 201 is disposed on the passivation layer 108 .
  • the anode 204 is disposed on the planarization layer 201 , and the other end of the contact electrode 202 is connected to the anode 204 .
  • the pixel definition layer 203 is disposed on the planarization layer 201 and covers the anode 204 .
  • the light emitting layer 205 is disposed in the opening of the pixel definition layer 203 .
  • the cathode 206 is provided on the light emitting layer 205 .
  • the active layer 104 is configured as a structure of at least two layers, that is, the first sub-active layer 104a and the second sub-active layer 104b, wherein the first sub-active layer
  • the number of atoms of gallium in 104a is greater than the number of atoms of gallium in the second sub-active layer 104b. Due to the strong binding ability of gallium and oxygen atoms, the generation of deep level defects at the interface between the first gate insulating layer 103a and the active layer 104 can be effectively suppressed, thereby improving the stability of the device.
  • the active layer 104 may further include a third sub-active layer 104c, the third sub-active layer 104c is disposed on the second sub-active layer 104b, and in the third sub-active layer 104c The atomic number of gallium is greater than that of gallium in the second sub-active layer 104b.
  • the number of gallium atoms in the first sub-active layer 104a in the implementation of the present application may be greater than the number of gallium atoms in the third sub-active layer 104a. In another embodiment, the number of gallium atoms in the first sub-active layer 104a may be less than or equal to the number of gallium atoms in the third sub-active layer 104a.
  • the active layer 104 is set as a three-layer stacked structure, that is, the first sub-active layer 104a, the second sub-active layer 104b and the third sub-active layer 104c, Wherein, the number of gallium atoms in the first sub-active layer 104a and the third sub-active layer 104c is greater than the number of gallium atoms in the second sub-active layer 104b. Due to the strong binding ability of gallium and oxygen atoms, the generation of deep level defects at the interface between the substrate 101 and the active layer 104 and the interface between the active layer 104 and the interlayer dielectric layer 105 can be effectively suppressed, thereby improving the stability of the device .
  • FIG. 2 is a schematic structural diagram of a display panel provided in a second embodiment of the present application.
  • the difference between the display panel 100 provided in the second embodiment of the present application and the display panel 100 provided in the first embodiment lies in that the first grid 102 a is disposed on the substrate 101 .
  • the first gate insulating layer 103a covers the first gate 102a.
  • the active layer 104 is disposed on a side of the first gate insulating layer 103 a away from the substrate 101 .
  • the interlayer dielectric layer 105 covers the active layer 104 and the first gate insulating layer 103a.
  • the active layer 104 is set as a three-layer stacked structure, that is, the first sub-active layer 104a, the second sub-active layer 104b and the third sub-active layer 104c, Wherein, the number of gallium atoms in the first sub-active layer 104a and the third sub-active layer 104c is greater than the number of gallium atoms in the second sub-active layer 104b. Due to the strong binding ability of gallium and oxygen atoms, the generation of deep level defects at the interface between the first gate insulating layer and the active layer 104 and the interface between the active layer 104 and the interlayer dielectric layer 105 can be effectively suppressed, thereby improving the performance of the device. stability.
  • FIG. 3 is a schematic structural diagram of a display panel provided in a third embodiment of the present application.
  • FIG. 4 is a schematic plan view of the structure of the display panel provided by the third embodiment of the present application.
  • the display panel 100 may further include a second gate insulating layer 103b, a second gate 102b, a third via hole h3,
  • the fourth via hole h4 is connected to the electrode 109 .
  • the second gate insulating layer 103b is disposed on a side of the active layer 104 away from the first gate insulating layer 103a.
  • the second gate 104 is disposed on a side of the second gate insulating layer 103b away from the active layer 104 .
  • the third via hole h3 penetrates through the interlayer dielectric layer 105 .
  • the fourth via hole h4 penetrates through the interlayer dielectric layer 105 and the first gate insulating layer 103a.
  • the connecting electrode 109 is disposed in the third via hole h3 and the fourth via hole h4 for connecting the first gate 102a and the second gate 102b.
  • the structure of the display panel 100 is designed as a double-gate structure, that is, it includes a first gate 102a and a second gate 102b, and the first gate 102a and the second gate 102b are connected through a connecting electrode 109 , the mobility of the display panel 100 is improved through the double gate structure.
  • the active layer 104 is set as a three-layer laminated structure, that is, the first sub-active layer 104a, the second sub-active layer 104b and the third sub-active layer 104c, wherein the first sub-active layer 104a And the number of atoms of gallium in the third sub-active layer 104c is greater than the number of atoms of gallium in the second sub-active layer 104b.
  • the generation of deep energy level defects at the interface between the first gate insulating layer and the active layer 104 and the interface between the active layer 104 and the second gate insulating layer 103b can be effectively suppressed, thereby improving the performance of the device. stability.
  • the substrate 101 may be a glass substrate or a flexible substrate.
  • the substrate 101 may also include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer, and a buffer layer that are sequentially stacked.
  • the material of the second flexible substrate layer is the same as that of the first flexible substrate, which may include PI (polyimide), PET (polyethylene dicarboxylate), PEN (polyethylene naphthalate) , PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin).
  • the buffer layer is composed of one of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride, or a stack structure of two or more of them.
  • the material of the first gate 102a can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., and a gate metal layer composed of multiple metal layers can also meet the requirements.
  • the material of the first gate insulating layer 103a may be one of silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide, or any combination thereof.
  • the number of gallium atoms in the first sub-active layer 104a and the third sub-active layer 104c may be the same or different.
  • oxygen bonding propensities or “bonding energies" of indium, gallium, and zinc are different from each other, there are some oxygen vacancies in which some of the indium, gallium, and zinc are not bonded to oxygen.
  • the oxygen vacancies may appear as "deep energy levels" formed near the valence band in the energy levels.
  • the energy difference ⁇ EDC between the deep level and the conduction band is about 2.4 eV.
  • the deep level of IGZO has a slightly higher energy level than the valence band. Therefore, electrons at the energy level of the valence band can easily jump to deep energy levels. Then, with lower energies, electrons are able to jump to the conduction band. As a result, the carrier mobility of IGZO is very high.
  • the embodiment of the present application sets the active layer 104 into three layers, that is, the first sub-active layer 104a, the second sub-active layer 104b, and the third sub-active layer 104c, wherein the first sub-active layer 104a And the number of atoms of gallium in the third sub-active layer 104c is greater than the number of atoms of gallium in the second sub-active layer 104b. Due to the strong binding ability between gallium and oxygen atoms, the generation of deep level defects can be effectively suppressed, thereby improving the stability of the device, thereby improving the reliability of the display panel.
  • the first sub-active layer 104a includes a nitrogen-doped InGaZnO active layer
  • the third sub-active layer 104c includes a nitrogen-doped InGaZnO active layer. Due to the strong binding ability of nitrogen atoms and oxygen vacancies, the introduction of nitrogen elements can occupy oxygen vacancies, which effectively regulates the carrier concentration and defect concentration in the active layer, thereby improving the mobility of the display panel and improving the performance of the display panel. reliability.
  • At least one of phosphorus, fluorine, selenium or tellurium may also be doped into the first sub-active layer 104a and/or the third sub-active layer 104c.
  • the thicknesses of the first sub-active layer 104a and the third sub-active layer 104c are less than or equal to 15 nm, and the thickness of the second sub-active layer 104b is between 10 nm and 90 nm.
  • the thickness of the first sub-active layer 104a may be any one of 0.5 nm, 3 nm, 5 nm, 8 nm or 12 nm.
  • the thickness of the third sub-active layer 104c may be any one of 0.5 nm, 3 nm, 5 nm, 8 nm or 12 nm.
  • the thickness of the second sub-active layer 104b may be any one of 15 nm, 23 nm, 35 nm, 58 nm or 70 nm.
  • the conductivity of the layer 104b is the best, and the thicknesses of the first sub-active layer 104a and the third sub-active layer 104c are smaller than the thickness of the second sub-active layer 104b, that is, the conductivity of the active layer is guaranteed, and there is energy Improve display panel stability.
  • the interlayer dielectric layer 105 can be selected from oxide or oxynitride compound.
  • the source electrode 106 and the drain electrode 107 can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., and a gate metal layer composed of multiple layers of metal can also meet the requirements.
  • the material of the second gate insulating layer 103b may be one of silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide or any combination thereof.
  • the material of the second gate 102b can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., and a gate metal layer composed of multiple metal layers can also meet the requirements.
  • the connecting electrode 109 can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., and a gate metal layer composed of multiple layers of metal can also meet the requirements.
  • the connection electrode 109 can be made of the same material as that of the first gate 102a and the second gate 102b.
  • the material of the passivation layer 108 can be SiOx, SiOx/SiNx stacked or SiOx/SiNx/Al2O3 stacked inorganic non-metal film layer material.
  • FIG. 5 is a circuit diagram corresponding to the display panel provided by the embodiment of the present application.
  • the first gate 102 a is connected to the first node Q
  • the second gate 102 b is connected to the second node P
  • the first gate 102 a and the second gate 102 b are electrically connected through the connection electrode 109 .
  • the bottom gate of the dual-gate thin film transistor is used as the main gate, so that the voltage of the top gate and source is used to adjust the threshold voltage of the driving transistor to complete the extraction and compensation of the threshold voltage, thereby reducing the cost of the pixel circuit. complexity, and achieve better display uniformity.
  • the threshold voltage variation is smaller than that of single-gate transistors under long-term electrical stress. Therefore, after a threshold voltage extraction is completed, the next one can be performed after a long period of time. Threshold voltage extraction, which undoubtedly makes the timing of the pixel circuit simpler and the driving speed faster.
  • FIG. 6 is a flow chart of the steps of the manufacturing method of the display panel provided by the first embodiment of the present application.
  • the manufacturing method of the display panel includes the following steps:
  • Step B001 providing a substrate 101 .
  • the substrate 101 may be a glass substrate or a flexible substrate.
  • the substrate 101 may further include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer, and a buffer layer that are sequentially stacked.
  • the material of the second flexible substrate layer is the same as that of the first flexible substrate, which may include PI (polyimide), PET (polyethylene dicarboxylate), PEN (polyethylene naphthalate) , PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin).
  • the buffer layer is composed of one of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride, or a stack structure of two or more of them.
  • Step B002 Forming the active layer 104 on the substrate 101, the active layer 104 and the first gate 102a are arranged in different layers, and the active layer 104 includes at least a first sub-active layer 104a, a second sub-active Layer 104b, the second sub-active layer 104b is arranged on the side of the first sub-active layer 104a away from the substrate 101, the number of atoms of gallium in the first sub-active layer 104a is greater than the number of atoms of gallium in the second sub-active layer 104b number.
  • the step of forming the active layer 104 on the substrate 101 includes:
  • InGaZn oxide is formed on the substrate 101, and the InGaZn oxide is doped with nitrogen to form the first sub-active layer 104a.
  • the first sub-active layer 104a is formed on the substrate 101 by magnetron sputtering, reactive sputtering, atomic layer deposition, or spin coating.
  • InGaZnO is formed on the first sub-active layer 104a to form the second sub-active layer 104b.
  • the second sub-active layer 104b is formed on the sub-active layer 104a by magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating.
  • step B002 may also include: forming an oxide material on the second sub-active layer 104b by magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, and performing nitrogen gas on the oxide material. doping to form the third sub-active layer 104c.
  • Step B003 forming a first gate insulating layer 103 a on the active layer 104 .
  • the material of the first gate insulating layer 103a can be one or more combinations of silicon oxide, silicon nitride, high dielectric constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric materials, and the second
  • the thickness of a gate insulating layer 103a may be 500nm ⁇ 1000nm, especially 600nm.
  • the first gate insulating layer 103 a can be formed by plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology, and the like.
  • Step B004 forming a first gate 102a on the first gate insulating layer 103a.
  • the first gate 102a may use molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) and chromium (Cr) as single substance or alloy to form a single metal layer or multiple metal layers.
  • Mo molybdenum
  • Cu copper
  • Al aluminum
  • Ti titanium
  • Cr chromium
  • the first gate 102a can also be made of non-reflective material, such as conductive metal oxide (such as ITO) or one or more combinations of other conductive materials.
  • the thickness of the first gate 102a may be 10nm-800nm as required, especially 200nm.
  • Step B005 forming an interlayer dielectric layer 105 on the first gate 102a.
  • An interlayer dielectric layer 105 is deposited on the substrate 101 by using a plasma chemical vapor deposition method.
  • the material of the interlayer dielectric layer 105 can be one or more combinations of silicon oxide, silicon nitride, high dielectric constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric materials, and the interlayer
  • the thickness of the dielectric layer 105 may be 100 nm ⁇ 1200 nm, especially 400 nm.
  • Step B006 forming a first via hole h1 and a second via hole h2 on the interlayer dielectric layer 105 .
  • the first via hole h1 , the second via hole h2 , the third via hole h3 and the fourth via hole h4 are formed through a yellow light process.
  • the first via hole h1 may be a source contact hole
  • the second via hole h2 may be a drain contact hole.
  • Step B007 forming a source 106 and a drain 107 on the substrate 101, wherein the source 106 is electrically connected to the active layer 104 through the first via hole h1, and the drain 107 is electrically connected to the active layer through the second via h2 104 is electrically connected.
  • magnetron sputtering, reactive sputtering, thermal evaporation, electronic evaporation, etc. are used to deposit the electrode conductive layer on the interlayer dielectric layer 105 and the first via hole h1 and the second via hole h2.
  • the electrode conductive layer One or more combinations of metals (such as molybdenum, copper, aluminum, titanium, chromium, etc.), conductive metal oxides (such as ITO) or other conductive materials can be used for the material.
  • the source electrode 106 and the drain electrode 107 are formed by etching.
  • FIG. 7 is a flow chart of the steps of the method for manufacturing a display panel provided by the third embodiment of the present application.
  • the manufacturing method of the display panel includes the following steps:
  • Step B01 providing a substrate 101, please refer to FIG. 8 .
  • the substrate 101 may be a glass substrate or a flexible substrate.
  • the substrate 101 may further include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer, and a buffer layer that are sequentially stacked.
  • the material of the second flexible substrate layer is the same as that of the first flexible substrate, which may include PI (polyimide), PET (polyethylene dicarboxylate), PEN (polyethylene naphthalate) , PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin).
  • the buffer layer is composed of one of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride, or a stack structure of two or more of them.
  • Step B02 forming a first gate 102a on the substrate 101, please continue to refer to FIG. 8 .
  • a first gate conductive layer 1021 is deposited on the substrate 101 .
  • the first gate conductive layer 1021 can be a single metal layer or a multi-layer metal layer using molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) and chromium (Cr) as a single substance or an alloy.
  • the first gate conductive layer 1021 can also be made of non-reflective material, such as conductive metal oxide (such as ITO) or one or more combinations of other conductive materials.
  • the thickness of the first gate conductive layer 1021 may be 10 nm to 800 nm as required, especially 200 nm.
  • the first gate conductive layer 1021 can be formed on the substrate 101 by magnetron sputtering, reactive sputtering, thermal evaporation, electron evaporation and other techniques.
  • the light reflection mentioned here means that the transmittance is at least lower than 20%.
  • the first gate conductive layer 1021 can be patterned to form the first gate 102a. Specifically, a photoresist is spin-coated on the first gate conductive layer 1021, and then operations such as photolithography, glue removal, and cleaning are performed to finally obtain a patterned first gate 102a.
  • Step B03 forming a first gate insulating layer 103a on the substrate 101, please refer to FIG. 9 .
  • a first gate insulating layer 103a is deposited on the substrate 101 and the first gate 102a.
  • the material of the first gate insulating layer 103a can be one or more combinations of silicon oxide, silicon nitride, high dielectric constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric materials, and the second
  • the thickness of a gate insulating layer 103a may be 500nm ⁇ 1000nm, especially 600nm.
  • the first gate insulating layer 103 a can be formed by plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology, and the like.
  • Step B04 Form the active layer 104 on the substrate 101, the active layer 104 and the first gate 102a are arranged in different layers, and the active layer 104 includes at least a first sub-active layer 104a, a second sub-active Layer 104b, the number of gallium atoms in the first sub-active layer 104a is greater than the number of gallium atoms in the second sub-active layer, please refer to FIG. 10 .
  • the step of forming the active layer 104 on the substrate 101 includes:
  • InGaZn oxide is formed on the substrate 101, and the InGaZn oxide is doped with nitrogen to form the first sub-active layer 104a.
  • the first oxide material layer 1041 is formed on the first gate insulating layer 103a by magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, and the first oxide material layer 1041 is formed by magnetron sputtering.
  • the oxide material layer 1041 is doped with nitrogen, and the thickness of the first oxide material layer 1041 is less than or equal to 15 nanometers.
  • InGaZnO is formed on the first sub-active layer 104a to form the second sub-active layer 104b.
  • the second oxide material layer 1042 is formed on the first oxide material layer 1041 by magnetron sputtering, reactive sputtering, atomic layer deposition, or spin coating.
  • the thickness of the second oxide material layer 1042 ranges from 10 nm to 90 nm.
  • step B04 may also include: forming a third oxide material layer 1043 on the second oxide material layer 1042 by magnetron sputtering, reactive sputtering, atomic layer deposition or spin coating, and using magnetic
  • the third oxide material layer 1043 is doped with nitrogen gas by a controlled sputtering method, and the thickness of the third oxide material layer 1043 is less than or equal to 15 nanometers.
  • the first oxide material layer 1041 , the second oxide material layer 1042 and the third oxide material layer 1043 are patterned to form the active layer 104 .
  • a photoresist may be spin-coated on the third oxide material layer 1043 , followed by photolithography and etching, followed by stripping and cleaning to obtain the active layer 104 .
  • the active layer 104 includes a doped region and a channel region, and the channel region is located on both sides of the active region.
  • step B04 the following steps may also be included:
  • the material of the second gate insulating layer 103b can be silicon oxide, silicon nitride, high dielectric constant dielectric material (such as aluminum oxide, hafnium oxide, zirconium oxide etc.) and one or more combinations of organic dielectric materials, and the thickness of the first gate insulating layer 103b may be 50nm-500nm, especially 300nm.
  • the second gate insulating layer 103b can be formed by plasma chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technology, etc. Please refer to FIG. 11 .
  • the step of forming the second gate insulating layer 103b on the active layer 104 may further include:
  • a second gate conductive layer 1022 is deposited on the second gate insulating layer 103b.
  • the second gate conductive layer 1022 can be a single metal layer or a multi-layer metal layer by using single substance or alloy of molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) and chromium (Cr).
  • Mo molybdenum
  • Cu copper
  • Al aluminum
  • Ti titanium
  • Cr chromium
  • the second gate conductive layer 1022 can also be made of non-reflective material, such as conductive metal oxide (such as ITO) or one or more combinations of other conductive materials.
  • the thickness of the second gate conductive layer 1022 may be 100 nm to 800 nm as required, especially 200 nm.
  • the second gate conductive layer 1022 can be formed on the substrate 101 by magnetron sputtering, reactive sputtering, thermal evaporation, electron evaporation and other techniques.
  • the light reflection mentioned here means that the transmittance is at least lower than 20%.
  • the second gate conductive layer 1022 can be patterned to form the second gate 102b. Specifically, photoresist is spin-coated on the second gate conductive layer 1022, and then photolithography, glue removal, cleaning and other operations are performed to finally obtain a patterned second gate 102b, please refer to FIG. 11 .
  • Step B05 forming an interlayer dielectric layer 105 on the substrate 101 , please refer to FIG. 12 .
  • a plasma chemical vapor deposition method is used to deposit an interlayer dielectric layer 105 on the substrate 101 .
  • the material of the interlayer dielectric layer 105 can be one or more combinations of silicon oxide, silicon nitride, high dielectric constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric materials, and the interlayer
  • the thickness of the dielectric layer 105 may be 100 nm ⁇ 1200 nm, especially 400 nm.
  • Step B06 forming a first via hole h1 and a second via hole h2 on the interlayer dielectric layer 105 , please refer to FIG. 12 .
  • Step B06 further includes forming a third via hole h3 and a fourth via hole h4 .
  • the first via hole h1 , the second via hole h2 , the third via hole h3 and the fourth via hole h4 are formed through a yellow light process.
  • the first via hole h1 , the second via hole h2 and the third via hole h3 penetrate through the interlayer dielectric layer 105
  • the fourth via hole h4 penetrates through the interlayer dielectric layer 105 and the first gate insulating layer 103 a.
  • the first via hole h1 may be a source contact hole
  • the second via hole h2 may be a drain contact hole
  • the third via hole h3 and the fourth via hole h4 may serve as contact holes for connecting electrodes.
  • Step B07 forming a source 106 and a drain 107 on the substrate 101, wherein the source 106 is electrically connected to the active layer 104 through the first via hole h1, and the drain 107 is electrically connected to the active layer through the second via h2 104 is electrically connected, please refer to FIG. 13 .
  • step B07 further includes: forming connection electrodes 109 .
  • the connection electrode 109 , the source electrode 106 and the drain electrode 107 can be formed through the same yellow light process. Specifically, magnetron sputtering, reactive sputtering, thermal evaporation, electron evaporation, etc. are used on the interlayer dielectric layer 105 and the first via hole h1, the second via hole h2, the third via hole h3 and the fourth
  • the electrode conductive layer is deposited on the via hole h4, and the material of the electrode conductive layer can be one or more of metal (such as molybdenum, copper, aluminum, titanium, chromium, etc.), conductive metal oxide (such as ITO) or other conductive materials combination.
  • the source electrode 106, the drain electrode 107, and the connection electrode 109 are formed by etching.
  • step B07 it further includes: forming a passivation layer 108 on the substrate 101 , please refer to FIG. 3 .
  • a passivation layer 108 is deposited on the substrate 101 by using a plasma chemical vapor deposition method.
  • the material of the passivation layer 108 can be one or more combinations of silicon oxide, silicon nitride, high dielectric constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.) and organic dielectric materials, and the passivation layer
  • the thickness of 108 may be 50nm-800nm, especially 400nm.
  • Embodiments of the present application provide a display panel and a manufacturing method thereof.
  • the active layer is set to three layers, that is, the first sub-active layer, the second sub-active layer, and the third sub-active layer, wherein the first sub-active layer and the number of atoms of gallium in the third sub-active layer is greater than the number of atoms of gallium in the second sub-active layer. Due to the strong binding ability of gallium and oxygen atoms, the generation of deep level defects can be effectively suppressed, thereby improving the stability of the device, thereby improving the reliability of the display panel.

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Abstract

一种显示面板(100)及其制作方法，显示面板(100)包括衬底(101)、第一栅极(102a)、第一栅绝缘层(103a)、有源层(104)、层间介质层(105)、第一过孔(h1)、第二过孔(h2)、源极(106)和漏极(107)，有源层(104)设置在衬底(101)上，有源层(104)至少包括层叠设置的第一子有源层(104a)、第二子有源层(104b)，第二子有源层(104b)设置在第一子有源层(104a)远离衬底(101)的一面，第一子有源层(104a)中镓的原子数大于第二子有源层中镓的原子数。

Description

显示面板及其制作方法 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制作方法。
 背景技术
目前，普遍采用的是有源层为铟镓锌氧化物的单一膜层的设置，由于成膜过程中氧气流量较大，导致铟镓锌氧化物膜层中的氧含量多，从而导致器件的导电性差，迁移率低的问题。如果沉积时氧气的流量较小，铟镓锌氧化物膜层中氧含量少，氧空位多会造成第一栅绝缘层和铟镓锌氧化物膜层的界面以及第二栅绝缘层和铟镓锌氧化物膜层的界面处缺陷多，导致器件的稳定性差。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本申请实施例提供一种显示面板及其制作方法，用于提高显示面板的稳定性。
 技术解决方案
本申请实施例提供一种显示面板，所述显示面板包括：
衬底；
第一栅极，所述第一栅极设置在所述衬底上；
第一栅绝缘层，所述第一栅绝缘层设置在所述衬底上；
有源层，所述有源层设置在所述衬底上，所述有源层和所述第一栅极异层设置，所述有源层至少包括层叠设置的第一子有源层、第二子有源层，所述第一子有源层设置在所述衬底上，所述第二子有源层设置在所述第一子有源层远离所述衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数；
层间介质层，所述层间介质层设置在所述衬底上；
第一过孔，所述第一过孔至少贯穿所述层间介质层；
第二过孔，所述第二过孔至少贯穿所述层间介质层；
源极，所述源极设置在所述层间质层上，并通过所述第一过孔与所述有源层电性连接；
漏极，所述漏极设置在所述层间介质层上，并通过所述第二过孔与所述有源层电性连接。
在本申请实施例提供的显示面板中，所述有源层还包括：
第三子有源层，所述第三子有源层设置在所述第二子有源层上，所述第三子有源层中镓的原子数大于所述第二子有源层中镓的原子数。
在本申请实施例提供的显示面板中，所述第一子有源层的材料包括铟镓锌氧化物，其中，所述第一子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=M:1:N，其中，0＜M＜1，0＜N＜1，所述第三子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=X:1:Y，0＜X＜1，0＜Y＜1。
在本申请实施例提供的显示面板中，所述第一子有源层包括氮元素掺杂的铟镓锌氧化物有源层，所述第三子有源层包括氮元素掺杂的铟镓锌氧化物有源层。
在本申请实施例提供的显示面板中，所述第二子有源层的材料包括铟镓锌氧化物，其中，所述第二子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1。
在本申请实施例提供的显示面板中，所述第一栅极设置在所述衬底上，所述第一栅绝缘层覆盖所述第一栅极，所述有源层设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述有源层和所述第一栅绝缘层。
在本申请实施例提供的显示面板中，所述第一栅极设置在所述衬底上，所述第一栅绝缘层覆盖所述第一栅极，所述有源层设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述有源层和所述第一栅绝缘层。
在本申请实施例提供的显示面板中，所述显示面板还包括：
第二栅绝缘层，所述第二栅绝缘层设置在所述有源层远离所述第一栅绝缘层的一面；
第二栅极，所述第二栅极设置在所述第二栅绝缘层远离所述有源层的一面；
第三过孔，所述第三过孔贯穿所述层间介质层；
第四过孔，所述第四过孔贯穿所述层间介质层和所述第一栅绝缘层；
连接电极，所述连接电极设置在所述第三过孔和所述第四过孔内，用于连接所述第一栅极和所述第二栅极。
在本申请实施例提供的显示面板中，所述有源层设置在所述衬底上，所述第一栅绝缘层覆盖所述衬底和所述有源层，所述第一栅极设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述第一栅极和所述第一栅绝缘层。
在本申请实施例提供的显示面板中，所述有源层设置在所述衬底上，所述第一栅绝缘层覆盖所述衬底和所述有源层，所述第一栅极设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述第一栅极和所述第一栅绝缘层。
在本申请实施例提供的显示面板中，所述第一子有源层的厚度和所述第三子有源层的厚度小于或等于15纳米，所述第二子有源层的厚度介于10纳米至90纳米。
在本申请实施例提供的显示面板中，所述第三子有源层中镓的原子数等于所述第一子有源层中镓的原子数。
在本申请实施例提供的显示面板中，所述显示面板还包括：
钝化层，所述钝化层设置在所述层间介质层上；
接触电极，所述接触电极设置在所述钝化层上，所接触电极的一端连接所述漏极；
平坦化层，所述平坦化层设置在所述钝化层上；
阳极，设置在所述平坦化层上，所述接触电极的另一端连接所述阳极；
像素定义层，所述像素定义层设置在所述平坦化层上，并覆盖所述阳极；
发光层，所述发光层设置在所述像素定义层的开口内；
阴极，所述阴极设置在所述发光层上。
本申请实施例还提供一种显示面板的制作方法，所述显示面板的制作方法包括以下步骤：
提供一衬底；
在所述衬底上形成第一栅极；
在所述衬底上形成第一栅绝缘层；
在所述衬底上形成有源层，所述有源层和所述第一栅极异层设置，所述有源层至少包括层叠设置的第一子有源层、第二子有源层，所述第二子有源层设置在所述第一子有源层远离所述衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数；
在所述衬底上形成层间介质层；
在所述层间介质层上形成第一过孔和第二过孔；
在所述衬底上形成源极和漏极，其中，所述源极通过所述第一过孔与所述有源层电性连接，所述漏极通过所述第二过孔与所述有源层电性连接；其中，
所述在所述衬底上形成有源层的步骤包括：
在所述衬底上形成铟镓锌氧化物，并对铟镓锌氧化物进行氮气掺杂，以形成所述第一子有源层；
在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层。
在本申请实施例提供的显示面板的制作方法中，所述在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层的步骤之后，还包括：
在所述第二子有源层上形成氧化物材料，并对氧化物材料进行氮气掺杂，以形成所述第三子有源层。
在本申请实施例提供的显示面板的制作方法中，所述在所述衬底上形成有源层的步骤之后，还包括：
在所述有源层上形成第二栅绝缘层；
在所述第二栅绝缘层上形成第二栅极。
在本申请实施例提供的显示面板的制作方法中，所述在所述层间介质层上形成第一过孔和第二过孔的步骤还包括：
在所述层间介质层上形成第三过孔和第四过孔。
在本申请实施例提供的显示面板的制作方法中，所述在所述衬底上形成源极和漏极的步骤还包括：在所述衬底上形成连接电极，所述连接电极设置在所述第三过孔和所述第四过孔内，用于连接所述第一栅极和所述第二栅极。
本申请实施例还提供一种显示面板的制作方法，所述显示面板的制作方法包括以下步骤：
提供一衬底；
在所述衬底上形成有源层，所述有源层和所述第一栅极异层设置，所述有源层至少包括层叠设置的第一子有源层、第二子有源层，所述第二子有源层设置在所述第一子有源层远离所述衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数；
在所述有源层上形成第一栅绝缘层；
在所述第一栅绝缘层上形成第一栅极；
在所述第一栅极上形成层间介质层；
在所述层间介质层上形成第一过孔和第二过孔；
在所述衬底上形成源极和漏极，其中，所述源极通过所述第一过孔与所述有源层电性连接，所述漏极通过所述第二过孔与所述有源层电性连接；其中，
所述在所述衬底上形成有源层的步骤包括：
在所述衬底上形成铟镓锌氧化物，并对铟镓锌氧化物进行氮气掺杂，以形成所述第一子有源层；
在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层。
在本申请实施例提供的显示面板的制作方法中，所述在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层的步骤之后，还包括：
在所述第二子有源层上形成氧化物材料，并对氧化物材料进行氮气掺杂，以形成所述第三子有源层。
为让本申请的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
 有益效果
本申请实施例提供一种显示面板及其制作方法。在本申请实施例提供的显示面板中，将有源层设置为至少两层的结构，即第一子有源层和第二子有源层，其中，第一子有源层中镓的原子数大于第二子有源层中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制深能级缺陷的产生，从而提高器件的稳定性。
 附图说明
图1为本申请第一实施例提供的显示面板的结构示意图；
图2为本申请第二实施例提供的显示面板的结构示意图；
图3为本申请第三实施例提供的显示面板的结构示意图；
图4为本申请第三实施例提供的显示面板的平面结构示意图；
图5为本申请第三实施例提供显示面板的薄膜晶体管对应的电路图；
图6为本申请第一实施例提供的显示面板的制作方法的步骤流程图
图7为本申请第三实施例提供的显示面板的制作方法的步骤流程图；
图8至图13为本申请实施例提供显示面板的制作方法的示意图。
 本发明的实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，请参照附图中的图式，其中相同的组件符号代表相同的组件，以下的说明是基于所示的本申请具体实施例，其不应被视为限制本申请未在此详述的其他具体实施例。本说明书所使用的词语“实施例”意指实例、示例或例证。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
本申请实施例提供一种显示面板及其制作方法。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请实施例提供一种显示面板，显示面板包括衬底、第一栅极、第一栅绝缘层、有源层、层间介质层、第一过孔、第二过孔、源极和漏极。第一栅极设置在衬底上。第一栅绝缘层设置在衬底上。有源层设置在衬底上，有源层和第一栅极异层设置，有源层至少包括层叠设置的第一子有源层、第二子有源层，第一子有源层设置在衬底上，第二子有源层设置在第一子有源层远离衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数。层间介质层设置在衬底上。第一过孔至少贯穿层间介质层。第二过孔至少贯穿层间介质层。源极设置在层间质层上，并通过第一过孔与有源层电性连接。漏极设置在层间介质层上，并通过第二过孔与有源层电性连接。
在本申请实施例提供的显示面板中，将有源层设置为至少两层的结构，即第一子有源层和第二子有源层，其中，第一子有源层中镓的原子数大于第二子有源层中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制深能级缺陷的产生，从而提高器件的稳定性。
下面通过具体实施例对本申请提供的显示面板进行详细的阐述。
请参考图1，图1为本申请第一实施例提供的显示面板的结构示意图。本申请实施例提供一种显示面板100，所述显示面板100包括衬底101，第一栅极102a，有源层104，源极106和漏极107、第一栅绝缘层103a、层间介质层105、钝化层108、接触电极202、平坦化层201、像素定义层203、阳极204、发光层205和阴极206。具体的，有源层104设置在衬底101上。第一栅绝缘层103a覆盖衬底101和有源层104。有源层104至少包括层叠设置的第一子有源层104a和第二有源层104b，第一子有源层104a设置在衬底101上，第二子有源层104b设置在第一子有源层104a远离衬底101的一面，其中，第一子有源层104a中镓的原子数大于第二子有源层104b中镓的原子数。第一栅极102a设置在第一栅绝缘层103a远离衬底101的一面。层间介质层105覆盖第一栅极102a和第一栅绝缘层103a。第一过孔h1和第二过孔h2贯穿层间介质层105和第一栅绝缘层103a，源极106通过第一过孔h1和有源层104电性连接，漏极107通过第二过孔h2与有源层104电性连接。钝化层108设置在层间介质层105上，并覆盖源极106和漏极107接触电极202设置在钝化层108上，接触电极202的一端连接漏极107。平坦化层201设置在钝化层108上。阳极204设置在平坦化层201上，接触电极202的另一端连接阳极204。像素定义层203设置在平坦化层201上，并覆盖阳极204。发光层205设置在像素定义层203的开口内。阴极206设置在发光层205上。
在本申请实施例提供的显示面板100中，将有源层104设置为至少两层的结构，即第一子有源层104a和第二子有源层104b，其中，第一子有源层104a中镓的原子数大于第二子有源层104b中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制第一栅绝缘层103a和有源层104的界面的深能级缺陷的产生，从而提高器件的稳定性。
进一步的，请继续参考图1，有源层104还可以包括第三子有源层104c，第三子有源层104c设置在第二子有源层104b上，第三子有源层104c中镓的原子数大于第二子有源层104b中镓的原子数。
需要说明的是，本申请实施中的第一子有源层104a中镓的原子数可以大于第三子有源层104a中镓的原子数。在另一实施例中，第一子有源层104a中镓的原子数可以小于或等于第三子有源层104a中镓的原子数。
在本申请实施例提供的显示面板100中，将有源层104设置为三层的层叠结构，即第一子有源层104a、第二子有源层104b和第三子有源层104c，其中，第一子有源层104a和第三子有源层104c中镓的原子数大于第二子有源层104b中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制衬底101和有源层104的界面以及有源层104与层间介质层105的界面的深能级缺陷的产生，从而提高器件的稳定性。
请参考图2，图2为本申请第二实施提供的显示面板的结构示意图。本申请第二实施例提供的显示面板100与第一实施例提供的显示面板100的区别在于：第一栅极102a设置在衬底101上。第一栅绝缘层103a覆盖第一栅极102a。有源层104设置在第一栅绝缘层103a远离衬底101的一面。层间介质层105覆盖有源层104和第一栅绝缘层103a。
在本申请实施例提供的显示面板100中，将有源层104设置为三层的层叠结构，即第一子有源层104a、第二子有源层104b和第三子有源层104c，其中，第一子有源层104a和第三子有源层104c中镓的原子数大于第二子有源层104b中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制第一栅绝缘层和有源层104的界面以及有源层104与层间介质层105的界面的深能级缺陷的产生，从而提高器件的稳定性。
请结合图3和图4，图3为本申请第三实施提供的显示面板的结构示意图。图4为本申请第三实施例提供的显示面板的平面结构示意图。本申请第三实施例提供的显示面板100与第二实施例提供的显示面板100的区别在于：显示面板100还可以包括第二栅绝缘层103b、第二栅极102b、第三过孔h3、第四过孔h4和连接电极109。第二栅绝缘层103b设置在有源层104远离第一栅绝缘层103a的一面。第二栅极104设置在第二栅绝缘层103b远离有源层104的一面。第三过孔h3贯穿层间介质层105。第四过孔h4贯穿层间介质层105和第一栅绝缘层103a。连接电极109设置在第三过孔h3和第四过孔h4内，用于连接第一栅极102a和第二栅极102b。
在本申请实施例中，将显示面板100的结构设计为双栅结构，即包括第一栅极102a和第二栅极102b，并通过连接电极109连接第一栅极102a和第二栅极102b，通过双栅结构提高显示面板100的迁移率。进一步的，将有源层104设置为三层的层叠结构，即第一子有源层104a、第二子有源层104b和第三子有源层104c，其中，第一子有源层104a和第三子有源层104c中镓的原子数大于第二子有源层104b中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制第一栅绝缘层和有源层104的界面以及有源层104与第二栅绝缘层103b的界面的深能级缺陷的产生，从而提高器件的稳定性。
在一些实施例中，衬底101可以是玻璃衬底或者柔性衬底。衬底101上还可以包括依次层叠设置的第一柔性衬底层、二氧化硅层、第二柔性衬底层、缓冲层。其中，第二柔性衬底层和第一柔性衬底的材料相同，其可以包括PI（聚酰亚胺）、PET（聚二甲酸乙二醇酯）、PEN（聚萘二甲酸乙二醇脂）、PC（聚碳酸酯）、PES（聚醚砜）、PAR（含有聚芳酯的芳族氟甲苯）或PCO（多环烯烃）中的至少一种。缓冲层由含硅的氮化物、含硅的氧化物或含硅的氮氧化物中的一种或两种及以上的堆栈结构组成。第一栅极102a的材料可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金，由多层金属组成的栅金属层也能满足需要。
第一栅绝缘层103a的材料可以是氮化硅、氧化硅、氮氧化硅或三氧化二铝中的一种或其任意组合。
在一些实施例中，第一子有源层104a的材料包括铟镓锌氧化物，其中，第一子有源层104a中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=M:1:N，其中，0＜M＜1，0＜N＜1。例如，在一实施方式中，第一子有源层104a中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=0.1:1:0.2、0.4:1:0.2、0.3:1:0.3或0.1:1:0.8中的任意一种。
第三子有源层104c的材料包括铟镓锌氧化物，第三子有源层104c中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=X:1:Y，0＜X＜1，0＜Y＜1。例如，在一实施方式中，第一子有源层104a中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=0.3:1:0.2、0.4:1:0.2、0.3:1:0.3或0.6:1:0.8中的任意一种。
需要说明的是，第一子有源层104a中和第三子有源层104c中镓的原子数可以相同也可以不同。
第二子有源层的材料包括铟镓锌氧化物，其中，第二子有源层104b中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1。
由于铟、镓和锌的氧键合倾向(或“键合能”)彼此不同，所以存在其中铟、镓和锌中的一些未与氧键合的一些氧空位。该氧空位在能级中可表现为形成在价带附近的“深能级”。深能级与导带之间的能量差ΔEDC为大约2.4eV。IGZO的深能级具有比价带稍高的能级。因此，价带能级处的电子能够很容易跃迁至深能级。然后，通过较低的能量，电子能够跃迁至导带。结果，IGZO的载流子迁移率非常高。
然而，当用于沟道元件的包括IGZO的薄膜晶体管被长时间使用或者暴露于非常强的光时，IGZO的迁移率特性可能劣化。注意到主要原因之一是，引起“深能级”的氧空位(或缺陷状态)将增加，然后从价带跃迁至“深能级”的电子可能被俘获到“深能级”中，因而这些被俘获的电子可能妨碍到导带的跃迁。换句话说，如果形成“深能级”的缺陷数量太大，所以使得从价带跃迁的电子并未跃迁至导带，而是仍保留在“深能级”中。这称为“深能级陷阱”。氧空位多会导致第一栅绝缘层103a和有源层104以及有源层104与第二栅绝缘层103b的界面缺陷多，产生显示面板的稳定性差和迁移率低的问题。
因此，本申请实施例将有源层104设置为三层，即第一子有源层104a、第二子有源层104b和第三子有源层104c，其中，第一子有源层104a和第三子有源层104c中镓的原子数大于第二子有源层104b中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制深能级缺陷的产生，从而提高器件的稳定性，从而改善显示面板的可靠度。第二子有源层104b中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1，保证了显示面板的导电性和迁移率。
在一些实施例中，第一子有源层104a包括氮元素掺杂的铟镓锌氧化物有源层，第三子有源层104c包括氮元素掺杂的铟镓锌氧化物有源层。由于氮原子与氧空位具有较强的结合能力，引入氮元素可以占据氧空位，有效调控了有源层中载流子浓度与缺陷浓度，从而提高了显示面板的迁移率以及改善了显示面板的可靠度。
在一些实施例中，还可以将磷、氟、硒或碲中的至少一者掺杂至第一子有源层104a和/或第三子有源层104c中。
在一些实施例中，第一子有源层104a的厚度和第三子有源层104c的厚度小于或等于15纳米，第二子有源层104b的厚度介于10纳米至90纳米。可选的，第一子有源层104a的厚度可以是0.5纳米、3纳米、5纳米、8纳米或者12纳米中的任意一者。第三子有源层104c的厚度可以是0.5纳米、3纳米、5纳米、8纳米或者12纳米中的任意一者。第二子有源层104b的厚度可以是15纳米、23纳米、35纳米、58纳米或者70纳米中的任意一者。在本申请实施例中，因为第二子有源层104b中的铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1，因此，第二子有源层104b的导电性最好，而第一子有源层104a和第三子有源层104c的厚度均小于第二子有源层104b的厚度，即保证了有源层的导电性，有能提高显示面板的稳定性。
层间介质层105可以选用氧化物或者氧氮化合物。
源极106和漏极107可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金，由多层金属组成的栅金属层也能满足需要。
第二栅绝缘层103b的材料可以是氮化硅、氧化硅、氮氧化硅或三氧化二铝中的一种或其任意组合。
第二栅极102b的材料可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金，由多层金属组成的栅金属层也能满足需要。
连接电极109可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金，由多层金属组成的栅金属层也能满足需要。在一些实施例中，连接电极109可以采用与第一栅极102a和第二栅极102b相同的材料制成。
钝化层108的材质可以为SiOx、SiOx/SiNx叠层或SiOx/SiNx/Al2O3叠层的无机非金属膜层材料。
请参考图5，图5为本申请实施例提供的显示面板对应的电路图。其中，第一栅极102a连接于第一节点Q，第二栅极102b连接于第二节点P，且第一栅极102a和第二栅极102b通过连接电极109电性连接。在本申请实施例中，将实现双栅薄膜晶体管的底栅作为主栅使用，从而使用顶栅源的电压来调节驱动晶体管的阈值电压，以完成阈值电压的提取和补偿，从而降低了像素电路的复杂度，并且达到更好的显示均匀度。由于双栅晶体管的稳定性更好，在长时间电应力作用下其阈值电压的变量化较单栅晶体管小，因此，在完成一次阈值电压提取后，可以隔很长一段时间再进行下一次的阈值电压提取，这样无疑使得像素电路的时序更简单，驱动速度加快。
请结合图1和图6，图6为本申请第一实施例提供的显示面板的制作方法的步骤流程图。显示面板的制作方法包括以下步骤：
步骤B001：提供一衬底101。
具体的，衬底101可以是玻璃衬底或者柔性衬底。在一些实施例中，衬底101上还可以包括依次层叠设置的第一柔性衬底层、二氧化硅层、第二柔性衬底层、缓冲层。其中，第二柔性衬底层和第一柔性衬底的材料相同，其可以包括PI（聚酰亚胺）、PET（聚二甲酸乙二醇酯）、PEN（聚萘二甲酸乙二醇脂）、PC（聚碳酸酯）、PES（聚醚砜）、PAR（含有聚芳酯的芳族氟甲苯）或PCO（多环烯烃）中的至少一种。缓冲层由含硅的氮化物、含硅的氧化物或含硅的氮氧化物中的一种或两种及以上的堆栈结构组成。
步骤B002：在衬底101上形成有源层104，有源层104和第一栅极102a异层设置，有源层104至少包括层叠设置的第一子有源层104a、第二子有源层104b，第二子有源层104b设置在第一子有源层104a远离衬底101的一面，第一子有源层104a中镓的原子数大于第二子有源层104b中镓的原子数。其中，在衬底101上形成有源层104的步骤包括：
在衬底101上形成铟镓锌氧化物，并对铟镓锌氧化物进行氮气掺杂，以形成第一子有源层104a。
具体的，采用磁控溅射、反应溅射、原子层淀积或旋涂等方法在衬底101上形成第一子有源层104a。
接下来，在第一子有源层104a上形成铟镓锌氧化物，以形成第二子有源层104b。
具体的，采用磁控溅射、反应溅射、原子层淀积或旋涂等方法在一子有源层104a上形成第二子有源层104b。
可选的，步骤B002还可以包括：采用磁控溅射、反应溅射、原子层淀积或旋涂等方法在第二子有源层104b上形成氧化物材料，并对氧化物材料进行氮气掺杂，形成第三子有源层104c。
步骤B003：在有源层104上形成第一栅绝缘层103a。
第一栅绝缘层103a的材料可采用氧化硅、氮化硅、高介电常数介质材料(如氧化铝、氧化铪、氧化锆等)以及有机介质材料中的一种或者多种组合，并且第一栅绝缘层103a的厚度可以是500nm～1000nm，特别是600nm。可以采用等离子体化学气相淀积、磁控溅射或反应溅射、原子层淀积或旋涂技术等形成第一栅绝缘层103a。
步骤B004：在第一栅绝缘层103a上形成第一栅极102a。
第一栅极102a可以采用钼(Mo)、铜(Cu)、铝(Al)、钛(Ti)和铬(Cr)中的单质或合金构成单一金属层或多层金属层。第一栅极102a也可以采用非反光材料，如导电金属氧化物(如ITO)或其他导电材料中的一种或多种组合。第一栅极102a的厚度根据需要可以是10nm～800nm，特别的可以是200nm。
步骤B005：在第一栅极102a上形成层间介质层105。
采用等离子体化学气相沉积方法在衬底101上沉积一层层间介质层105。层间介质层105的材料可采用氧化硅、氮化硅、高介电常数介质材料(如氧化铝、氧化铪、氧化锆等)以及有机介质材料中的一种或者多种组合，并且层间介质层105的厚度可以为100nm～1200nm，特别的可以是400nm。
步骤B006：在层间介质层105上形成第一过孔h1和第二过孔h2。
通过一道黄光制程形成第一过孔h1、第二过孔h2、第三过孔h3和第四过孔h4。具体的，第一过孔h1可以是源极接触孔，第二过孔h2可以是漏极接触孔。
步骤B007：在衬底101上形成源极106和漏极107，其中，源极106通过第一过孔h1与有源层104电性连接，漏极107通过第二过孔h2与有源层104电性连接。
具体的，采用磁控溅射、反应溅射、热蒸镀、电子术蒸镀等在层间介质层105上以及第一过孔h1、第二过孔h2上沉积电极导电层，电极导电层的材料可采用金属(如钼、铜、铝、钛、铬等)、导电金属氧化物(如ITO)或其他导电材料中的一种或多种组合。然后，通过刻蚀形成源极106、漏极107。
请参阅图7，图7为本申请第三实施例提供的显示面板的制作方法的步骤流程图。显示面板的制作方法包括以下步骤：
步骤B01：提供一衬底101，请参阅图8。
具体的，衬底101可以是玻璃衬底或者柔性衬底。在一些实施例中，衬底101上还可以包括依次层叠设置的第一柔性衬底层、二氧化硅层、第二柔性衬底层、缓冲层。其中，第二柔性衬底层和第一柔性衬底的材料相同，其可以包括PI（聚酰亚胺）、PET（聚二甲酸乙二醇酯）、PEN（聚萘二甲酸乙二醇脂）、PC（聚碳酸酯）、PES（聚醚砜）、PAR（含有聚芳酯的芳族氟甲苯）或PCO（多环烯烃）中的至少一种。缓冲层由含硅的氮化物、含硅的氧化物或含硅的氮氧化物中的一种或两种及以上的堆栈结构组成。
步骤B02：在衬底101上形成第一栅极102a，请继续参阅图8。
具体的，首先在衬底101上沉积一层第一栅导电层1021。第一栅导电层1021可以采用钼(Mo)、铜(Cu)、铝(Al)、钛(Ti)和铬(Cr)中的单质或合金构成单一金属层或多层金属层。第一栅导电层1021也可以采用非反光材料，如导电金属氧化物(如ITO)或其他导电材料中的一种或多种组合。第一栅导电层1021的厚度根据需要可以是10nm～800nm，特别的可以是200nm。可以采用磁控溅射、反应溅射、热蒸镀、电子术蒸镀等技术将第一栅导电层1021形成在衬底101上。这里所说的反光，指的是透射率至少低于20％。然后，可以将第一栅导电层1021图形化形成第一栅极102a。具体的，在第一栅导电层1021上旋涂光刻胶，然后进行光刻、去胶、清洗处理等操作，最终得到图形化的第一栅极102a。
步骤B03：在衬底101上形成第一栅绝缘层103a，请参阅图9。
具体的，在衬底101和第一栅极102a上淀积一层第一栅绝缘层103a。第一栅绝缘层103a的材料可采用氧化硅、氮化硅、高介电常数介质材料(如氧化铝、氧化铪、氧化锆等)以及有机介质材料中的一种或者多种组合，并且第一栅绝缘层103a的厚度可以是500nm～1000nm，特别是600nm。可以采用等离子体化学气相淀积、磁控溅射或反应溅射、原子层淀积或旋涂技术等形成第一栅绝缘层103a。
步骤B04：在衬底101上形成有源层104，有源层104和第一栅极102a异层设置，有源层104至少包括层叠设置的第一子有源层104a、第二子有源层104b，第一子有源层104a中镓的原子数大于所述第二子有源层中镓的原子数，请参阅图10。
其中，在衬底101上形成有源层104的步骤包括：
在衬底101上形成铟镓锌氧化物，并对铟镓锌氧化物进行氮气掺杂，以形成第一子有源层104a。
具体的，采用磁控溅射、反应溅射、原子层淀积或旋涂等方法在第一栅绝缘层103a上形成第一氧化物材料层1041，并利用磁控溅射法对第一氧化物材料层1041进行氮气掺杂，第一氧化物材料层1041的厚度小于或等于15纳米。
接下来，在第一子有源层104a上形成铟镓锌氧化物，以形成第二子有源层104b。
具体的，采用磁控溅射、反应溅射、原子层淀积或旋涂等方法在第一氧化物材料层1041上形成第二氧化物材料层1042。第二氧化物材料层1042的厚度介于10纳米至90纳米。
可选的，步骤B04还可以包括：采用磁控溅射、反应溅射、原子层淀积或旋涂等方法在第二氧化物材料层1042上形成第三氧化物材料层1043，并利用磁控溅射法对第三氧化物材料层1043进行氮气掺杂，第三氧化物材料层1043的厚度小于或等于15纳米。
接下来，对第一氧化物材料层1041、第二氧化物材料层1042和第三氧化物材料层1043图形化以形成有源层104。具体的，可以在第三氧化物材料层1043上旋涂光刻胶，然后进行光刻、刻蚀，然后进行去胶、清洗处理，得到有源层104。有源层104包括掺杂区和沟道区，沟道区位于有源区的两侧。
在步骤B04之后，还可以包括以下步骤：
在有源层104上形成第二栅绝缘层103b，具体的，第二栅绝缘层103b的材料可采用氧化硅、氮化硅、高介电常数介质材料(如氧化铝、氧化铪、氧化锆等)以及有机介质材料中的一种或者多种组合，并且第一栅绝缘层103b的厚度可以是50nm～500nm，特别是300nm。可以采用等离子体化学气相淀积、磁控溅射或反应溅射、原子层淀积或旋涂技术等形成第二栅绝缘层103b，请参阅图11。
在有源层104上形成第二栅绝缘层103b的步骤之后，还可以包括：
在第二栅绝缘层103b上沉积一层第二栅导电层1022。第二栅导电层1022可以采用钼(Mo)、铜(Cu)、铝(Al)、钛(Ti)和铬(Cr)中的单质或合金构成单一金属层或多层金属层。第二栅导电层1022也可以采用非反光材料，如导电金属氧化物(如ITO)或其他导电材料中的一种或多种组合。第二栅导电层1022的厚度根据需要可以是100nm～800nm，特别的可以是200nm。可以采用磁控溅射、反应溅射、热蒸镀、电子术蒸镀等技术将第二栅导电层1022形成在衬底101上。这里所说的反光，指的是透射率至少低于20％。然后，可以将第二栅导电层1022图形化形成第二栅极102b。具体的，在第二栅导电层1022上旋涂光刻胶，然后进行光刻、去胶、清洗处理等操作，最终得到图形化的第二栅极102b，请参阅图11。
步骤B05：在衬底101上形成层间介质层105，请参考图12。
具体的，采用等离子体化学气相沉积方法在衬底101上沉积一层层间介质层105。层间介质层105的材料可采用氧化硅、氮化硅、高介电常数介质材料(如氧化铝、氧化铪、氧化锆等)以及有机介质材料中的一种或者多种组合，并且层间介质层105的厚度可以为100nm～1200nm，特别的可以是400nm。
步骤B06：在层间介质层105上形成第一过孔h1和第二过孔h2，请参阅图12。
步骤B06还包括形成第三过孔h3和第四过孔h4。具体的，通过一道黄光制程形成第一过孔h1、第二过孔h2、第三过孔h3和第四过孔h4。其中，第一过孔h1、第二过孔h2和第三过孔h3贯穿层间介质层105，第四过孔h4贯穿层间介质层105以及第一栅绝缘层103a。具体的，第一过孔h1可以是源极接触孔，第二过孔h2可以是漏极接触孔，第三过孔h3和第四过孔h4可以作为连接电极接触孔。
步骤B07：在衬底101上形成源极106和漏极107，其中，源极106通过第一过孔h1与有源层104电性连接，漏极107通过第二过孔h2与有源层104电性连接，请参阅图13。
在一实施例中，步骤B07还包括：形成连接电极109。其中，连接电极109、源极106以及漏极107可以通过同一道黄光制程制作形成。具体的，采用磁控溅射、反应溅射、热蒸镀、电子术蒸镀等在层间介质层105上以及第一过孔h1、第二过孔h2、第三过孔h3和第四过孔h4上沉积电极导电层，电极导电层的材料可采用金属(如钼、铜、铝、钛、铬等)、导电金属氧化物(如ITO)或其他导电材料中的一种或多种组合。然后，通过刻蚀形成源极106、漏极107和连接电极109。
在步骤B07之后，还包括：在衬底101上形成钝化层108，请参阅图3。
具体的，采用等离子体化学气相沉积方法在衬底101上沉积一层钝化层108。钝化层108的材料可采用氧化硅、氮化硅、高介电常数介质材料(如氧化铝、氧化铪、氧化锆等)以及有机介质材料中的一种或者多种组合，并且钝化层108的厚度可以为50nm～800nm，特别的可以是400nm。
本申请实施例提供一种显示面板及其制作方法。在本申请实施例提供的显示面板中，将有源层设置为三层，即第一子有源层、第二子有源层和第三子有源层，其中，第一子有源层和第三子有源层中镓的原子数大于第二子有源层中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制深能级缺陷的产生，从而提高器件的稳定性，从而改善了显示面板的可靠度。而第二子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1，保证了显示面板的导电性和迁移率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底；
    第一栅极，所述第一栅极设置在所述衬底上；
    第一栅绝缘层，所述第一栅绝缘层设置在所述衬底上；
    有源层，所述有源层设置在所述衬底上，所述有源层和所述第一栅极异层设置，所述有源层至少包括层叠设置的第一子有源层、第二子有源层，所述第一子有源层设置在所述衬底上，所述第二子有源层设置在所述第一子有源层远离所述衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数；
    层间介质层，所述层间介质层设置在所述衬底上；
    第一过孔，所述第一过孔至少贯穿所述层间介质层；
    第二过孔，所述第二过孔至少贯穿所述层间介质层；
    源极，所述源极设置在所述层间质层上，并通过所述第一过孔与所述有源层电性连接；
    漏极，所述漏极设置在所述层间介质层上，并通过所述第二过孔与所述有源层电性连接。
  2. 根据权利要求1所述的显示面板，其中，所述有源层还包括：
    第三子有源层，所述第三子有源层设置在所述第二子有源层上，所述第三子有源层中镓的原子数大于所述第二子有源层中镓的原子数。
  3. 根据权利要求2所述的显示面板，其中，所述第一子有源层的材料包括铟镓锌氧化物，其中，所述第一子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=M:1:N，其中，0＜M＜1，0＜N＜1，所述第三子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=X:1:Y，0＜X＜1，0＜Y＜1。
  4. 根据权利要求3所述的显示面板，其中，所述第一子有源层包括氮元素掺杂的铟镓锌氧化物有源层，所述第三子有源层包括氮元素掺杂的铟镓锌氧化物有源层。
  5. 根据权利要求1所述的显示面板，其中，所述第二子有源层的材料包括铟镓锌氧化物，其中，所述第二子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1。
  6. 根据权利要求1所述的显示面板，其中，所述第一栅极设置在所述衬底上，所述第一栅绝缘层覆盖所述第一栅极，所述有源层设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述有源层和所述第一栅绝缘层。
  7. 根据权利要求2所述的显示面板，其中，所述第一栅极设置在所述衬底上，所述第一栅绝缘层覆盖所述第一栅极，所述有源层设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述有源层和所述第一栅绝缘层。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板还包括：
    第二栅绝缘层，所述第二栅绝缘层设置在所述有源层远离所述第一栅绝缘层的一面；
    第二栅极，所述第二栅极设置在所述第二栅绝缘层远离所述有源层的一面；
    第三过孔，所述第三过孔贯穿所述层间介质层；
    第四过孔，所述第四过孔贯穿所述层间介质层和所述第一栅绝缘层；
    连接电极，所述连接电极设置在所述第三过孔和所述第四过孔内，用于连接所述第一栅极和所述第二栅极。
  9. 根据权利要求1所述的显示面板，其中，所述有源层设置在所述衬底上，所述第一栅绝缘层覆盖所述衬底和所述有源层，所述第一栅极设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述第一栅极和所述第一栅绝缘层。
  10. 根据权利要求2所述的显示面板，其中，所述有源层设置在所述衬底上，所述第一栅绝缘层覆盖所述衬底和所述有源层，所述第一栅极设置在所述第一栅绝缘层远离所述衬底的一面，所述层间介质层覆盖所述第一栅极和所述第一栅绝缘层。
  11. 根据权利要求2所述的显示面板，其中，所述第一子有源层的厚度和所述第三子有源层的厚度小于或等于15纳米，所述第二子有源层的厚度介于10纳米至90纳米。
  12. 根据权利要求2所述的显示面板，其中，所述第三子有源层中镓的原子数等于所述第一子有源层中镓的原子数。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    钝化层，所述钝化层设置在所述层间介质层上；
    接触电极，所述接触电极设置在所述钝化层上，所接触电极的一端连接所述漏极；
    平坦化层，所述平坦化层设置在所述钝化层上；
    阳极，设置在所述平坦化层上，所述接触电极的另一端连接所述阳极；
    像素定义层，所述像素定义层设置在所述平坦化层上，并覆盖所述阳极；
    发光层，所述发光层设置在所述像素定义层的开口内；
    阴极，所述阴极设置在所述发光层上。
  14. 一种显示面板的制作方法，其中，所述显示面板的制作方法包括以下步骤：
    提供一衬底；
    在所述衬底上形成第一栅极；
    在所述衬底上形成第一栅绝缘层；
    在所述衬底上形成有源层，所述有源层和所述第一栅极异层设置，所述有源层至少包括层叠设置的第一子有源层、第二子有源层，所述第二子有源层设置在所述第一子有源层远离所述衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数；
    在所述衬底上形成层间介质层；
    在所述层间介质层上形成第一过孔和第二过孔；
    在所述衬底上形成源极和漏极，其中，所述源极通过所述第一过孔与所述有源层电性连接，所述漏极通过所述第二过孔与所述有源层电性连接；其中，
    所述在所述衬底上形成有源层的步骤包括：
    在所述衬底上形成铟镓锌氧化物，并对铟镓锌氧化物进行氮气掺杂，以形成所述第一子有源层；
    在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层。
  15. 根据权利要求14所述的显示面板的制作方法，其中，所述在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层的步骤之后，还包括：
    在所述第二子有源层上形成氧化物材料，并对氧化物材料进行氮气掺杂，以形成所述第三子有源层。
  16. 根据权利要求15所述的显示面板的制作方法，其中，所述在所述衬底上形成有源层的步骤之后，还包括：
    在所述有源层上形成第二栅绝缘层；
    在所述第二栅绝缘层上形成第二栅极。
  17. 根据权利要求16所述的显示面板的制作方法，其中，所述在所述层间介质层上形成第一过孔和第二过孔的步骤还包括：
    在所述层间介质层上形成第三过孔和第四过孔。
  18. 根据权利要求17所述的显示面板的制作方法，其中，所述在所述衬底上形成源极和漏极的步骤还包括：在所述衬底上形成连接电极，所述连接电极设置在所述第三过孔和所述第四过孔内，用于连接所述第一栅极和所述第二栅极。
  19. 一种显示面板的制作方法，其中，所述显示面板的制作方法包括以下步骤：
    提供一衬底；
    在所述衬底上形成有源层，所述有源层和所述第一栅极异层设置，所述有源层至少包括层叠设置的第一子有源层、第二子有源层，所述第二子有源层设置在所述第一子有源层远离所述衬底的一面，所述第一子有源层中镓的原子数大于所述第二子有源层中镓的原子数；
    在所述有源层上形成第一栅绝缘层；
    在所述第一栅绝缘层上形成第一栅极；
    在所述第一栅极上形成层间介质层；
    在所述层间介质层上形成第一过孔和第二过孔；
    在所述衬底上形成源极和漏极，其中，所述源极通过所述第一过孔与所述有源层电性连接，所述漏极通过所述第二过孔与所述有源层电性连接；其中，
    所述在所述衬底上形成有源层的步骤包括：
    在所述衬底上形成铟镓锌氧化物，并对铟镓锌氧化物进行氮气掺杂，以形成所述第一子有源层；
    在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层。
  20. 根据权利要求19所述的显示面板的制作方法，其中，所述在所述第一子有源层上形成铟镓锌氧化物，以形成所述第二子有源层的步骤之后，还包括：
    在所述第二子有源层上形成氧化物材料，并对氧化物材料进行氮气掺杂，以形成所述第三子有源层。
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