WO2023084557A1 - Analog signal input device - Google Patents

Analog signal input device Download PDF

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Publication number
WO2023084557A1
WO2023084557A1 PCT/JP2021/041061 JP2021041061W WO2023084557A1 WO 2023084557 A1 WO2023084557 A1 WO 2023084557A1 JP 2021041061 W JP2021041061 W JP 2021041061W WO 2023084557 A1 WO2023084557 A1 WO 2023084557A1
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WIPO (PCT)
Prior art keywords
analog signal
pulse transformer
switch element
reset
signal
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PCT/JP2021/041061
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French (fr)
Japanese (ja)
Inventor
潤 西嶋
慶洋 明星
崇 桑原
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to KR1020247013827A priority Critical patent/KR102700289B1/en
Priority to PCT/JP2021/041061 priority patent/WO2023084557A1/en
Priority to JP2022535071A priority patent/JP7237246B1/en
Priority to GB2404995.9A priority patent/GB2626100A/en
Publication of WO2023084557A1 publication Critical patent/WO2023084557A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
    • H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Definitions

  • the present disclosure relates to an analog signal input device.
  • Analog signal input devices are often used in industrial control and monitoring equipment. This analog signal input device receives, with high accuracy, an analog signal output from a device such as a temperature sensor into an AD converter. At this time, insulation is required in order to AD-convert the analog signal. Assuming that analog signal input devices are generally used in harsh installation environments, insulation is provided between the input section and the internal circuits to avoid failures caused by ground loops via the earth (earth), etc. measures have been taken.
  • Patent Document 1 discloses an analog signal input device that employs an insulation method.
  • the analog signal input device disclosed in Patent Document 1 has a waveform shaping circuit on the secondary side of the pulse transformer.
  • This waveform shaping circuit demagnetizes the magnetic core of the pulse transformer.
  • the waveform shaping circuit is always electrically connected when outputting the analog signal to the AD converter, the waveform of the analog signal output from the waveform shaping circuit is distorted. becomes more likely to occur.
  • the accuracy of sensing the analog signal by the AD converter may deteriorate.
  • the present disclosure has been made to solve the above problems, and aims to provide an analog signal input device capable of suppressing distortion of analog signals.
  • An analog signal input device includes a pulse transformer that isolates an analog signal input from the outside, a first switch element connected to the primary side of the pulse transformer, and the pulse transformer on the secondary side of the pulse transformer. and a reset circuit having a resistance element and a second switch element connected in series with each other, and a drive signal for on-off controlling the first switch element to the first switch element, a control circuit for outputting a reset signal for on/off controlling the second switch element to the second switch element, wherein the control circuit turns off the second switch element when turning off the first switch element; ON.
  • the analog signal input device can sense analog signals with high accuracy.
  • FIG. 1 is a circuit configuration diagram showing the configuration of an analog signal input device according to Embodiment 1;
  • FIG. 4 is a timing chart showing operation waveforms of each part in the analog signal input device according to the first embodiment;
  • FIG. 3A is a circuit configuration diagram showing the driving state of the first pulse transformer.
  • FIG. 3B is a timing chart showing operation waveforms of each part in the driving state of the first pulse transformer.
  • FIG. 4A is a circuit configuration diagram showing a reset state of the first pulse transformer.
  • FIG. 4B is a timing chart showing operation waveforms of respective parts in the reset state of the first pulse transformer.
  • 2 is a circuit configuration diagram showing the configuration of an analog signal input device according to a second embodiment;
  • FIG. 1 is a circuit configuration diagram showing a conventional analog signal input device;
  • FIG. 1 is a circuit configuration diagram showing a conventional reset circuit;
  • Embodiment 1 An analog signal input device 1 according to Embodiment 1 will be described with reference to FIGS. 1 to 4, 6 and 7.
  • FIG. 1 An analog signal input device 1 according to Embodiment 1 will be described with reference to FIGS. 1 to 4, 6 and 7.
  • the analog signal output from the sensor element is finally transmitted to the AD converter via the switch element and pulse transformer.
  • a sensor element is assumed to be, for example, a temperature sensor.
  • the analog signal output from the sensor element is a very low frequency signal (substantially a DC signal)
  • isolated transmission via the transformer cannot be performed if the analog signal is a low frequency signal, or It is necessary to make the pulse transformer extremely large. Therefore, in the technique disclosed in Patent Document 1, by shaping (modulating) an analog signal into a transient pulse waveform, isolated transmission of the analog signal is performed using a small pulse transformer.
  • FIG. 1 is a circuit configuration diagram showing the configuration of an analog signal input device 1 according to Embodiment 1.
  • FIG. This analog signal input device 1 has input terminals 1a and 1b.
  • One or more sensor elements 2 are connected to the input terminals 1a and 1b via cables or the like.
  • the analog signal input device 1 includes a first pulse transformer 3, a second pulse transformer 4, a first switch element 5, a reset circuit 6, an amplifier element 7, a multiplexer 8, buffer elements 9a and 9b, an AD converter 10, and a control circuit.
  • a circuit 11 is provided.
  • This analog signal input device 1 employs a transformer insulation method.
  • Such an analog signal input device 1 is a device that accurately captures the analog signal (sensor element signal) W1 output from the sensor element 2 into the AD converter 10 via insulation. Also, the analog signal input device 1 has the number of circuits corresponding to the number of input channels (the number of analog channels).
  • FIG. 1 shows an example of eight input channels (Ch1-Ch8).
  • the first pulse transformer 3 insulates the analog signal W1 input from the sensor element 2.
  • the first pulse transformer 3 constitutes a pulse transformer.
  • the second pulse transformer 4 controls the first switch element 5, which will be described later.
  • the first switch element 5 is connected to the primary side (insulation side) of the first pulse transformer 3 .
  • the first switch element 5 applies the analog signal W1 to the first pulse transformer 3.
  • a drive signal W2 can be input from the second pulse transformer 4 to the first switch element 5 .
  • the drive signal W2 is a signal for controlling the on/off (opening/closing) of the first switch element 5 .
  • the reset circuit 6 is connected in parallel with the first pulse transformer 3 on the secondary side (internal circuit side) of the first pulse transformer 3 .
  • This reset circuit 6 demagnetizes the magnetic core that constitutes the first pulse transformer 3 .
  • the reset circuit 6 resets the excitation current W6 (see FIG. 3) flowing through the first pulse transformer 3.
  • the reset circuit 6 also has a resistance element 61 and a second switch element 62 that are connected in series with each other. Specifically, the resistance element 61 and the second switch element 62 are connected in series with the signal line from the first pulse transformer 3 .
  • a reset signal W4 can be input to the second switch element 62 .
  • the reset signal W4 is a signal for controlling on/off (open/close) of the second switch element 62 .
  • the amplifier element 7 is connected after the reset circuit 6 .
  • the amplifier element 7 amplifies the analog signal W1 output from the first pulse transformer 3.
  • the multiplexer 8 selects any one of a plurality of input channels. This multiplexer 8 is controlled by a control circuit 11 which will be described later.
  • the AD converter 10 is connected after the multiplexer 8 .
  • This AD converter 10 converts the analog signal W1 output from the multiplexer 8 into a digital signal. Also, the AD converter 10 outputs the converted digital signal to the control circuit 11 . Note that in FIG. 1, the analog signal W1 output from the multiplexer 8 is shown as an AD conversion input signal W3.
  • the control circuit 11 has a processing section 111 , a timing control section 112 and a Ch selection section 113 .
  • the processing unit 111 processes the digital signal output from the AD converter 10 .
  • the processing unit 111 also outputs the processing result to the timing control unit 112 and the Ch selection unit 113 .
  • the timing control section 112 outputs the sample signal W8, the drive signal W2, and the reset signal W4 based on the digital signal processed by the processing section 111.
  • the sample signal W8 is a signal for the AD converter 10 to sample the AD converted input signal W3. This sample signal W8 is output to the AD converter 10 by the timing control section 112 .
  • the drive signal W2 is output to the first pulse transformer 3 by the timing control section 112 via the buffer element 9a, the multiplexer 8, and the second pulse transformer 4.
  • the reset signal W4 is output to the reset circuit 6 by the timing control section 112 via the buffer element 9b and the multiplexer 8.
  • the analog signal input device 1 has a second pulse transformer 4 .
  • the primary sides of the first pulse transformer 3 and the second pulse transformer 4 in the analog signal input device 1 are composed only of a first switch element 5 using a transistor.
  • FIG. 6 is a circuit configuration diagram showing a conventional analog signal input device 1B.
  • the conventional analog signal input device 1B shown in FIG. 6 employs a photocoupler insulation system.
  • a conventional analog signal input device 1B includes an amplifier element 7, a multiplexer 8, buffer elements 9a and 9b, an AD converter 10, a control circuit 11, a photocoupler 12, and an isolated power supply circuit 13.
  • An AD converter 10 and an isolated power supply circuit 13 are arranged on the primary side of the analog signal input device 1B.
  • the analog signal input device 1 is advantageous in terms of the number of parts and manufacturing cost compared to the analog signal input device 1B.
  • control circuit 11 controls the reset circuit 6 so that the reset circuit 6 functions only immediately after the first pulse transformer 3 is driven and at the timing when the magnetic core of the first pulse transformer 3 needs to be demagnetized. 2 switch element 62 is controlled.
  • FIG. 2 is a timing chart showing operation waveforms in each part of the analog signal input device 1 according to the first embodiment.
  • the vertical axis in FIG. 2 represents the analog signal W1 input to the input terminals 1a and 1b, the drive signal W2 output from the timing control unit 112, the AD conversion input signal W3 input to the AD converter 10, and the timing control.
  • a reset signal W4 output from the unit 112 is shown.
  • the horizontal axis of FIG. 2 indicates the passage of time.
  • the analog signal W1 is an output signal from the sensor element 2, and gradually changes with the passage of time.
  • the drive signal W2 turns on or off the first switch element 5 via the buffer element 9a, the multiplexer 8, and the second pulse transformer 4. That is, the period during which the drive signal W2 is at a high potential is the period during which the first pulse transformer 3 is driven. During that period, a voltage corresponding to the amplitude of the analog signal W1 is transmitted to the secondary side of the first pulse transformer 3.
  • FIG. The period during which the drive signal W2 is at a low potential is the period during which the first pulse transformer 3 is reset.
  • the waveform of the AD conversion input signal W3 is observed on the secondary side of the first pulse transformer 3.
  • the AD conversion input signal W3 has a value corresponding to the amplitude of the analog signal W1 while the drive signal W2 is at high potential.
  • the amplitude of the AD conversion input signal W3 is sampled by the AD converter 10 .
  • backswing occurs in the AD conversion input signal W3 at the time when the reset signal W4 becomes high potential. This backswing is caused by a reset current W7 (see FIG. 4) generated as a residual excitation current W6 (see FIG. 3) of the first pulse transformer 3.
  • FIG. A reset circuit 6 is provided to suppress excessive amplitude and long-term vibration of the backswing.
  • the reset signal W4 turns on or off the second switch element 62 of the reset circuit 6 via the buffer element 9b and the multiplexer 8. That is, the period during which the reset signal W4 is at a high potential is the period during which the magnetic core of the first pulse transformer 3 is demagnetized (reset).
  • the backswing quickly attenuates and contracts due to power consumption by the resistance element 61 of the reset circuit 6 during the period in which the magnetic core of the first pulse transformer 3 is demagnetized.
  • FIG. 3A is a circuit configuration diagram showing the driving state of the first pulse transformer 3.
  • FIG. 3B is a timing chart showing operation waveforms of respective parts in the driving state (driving period) of the first pulse transformer 3. As shown in FIG. The vertical axis of FIG. 3B indicates the analog signal W1, the drive signal W2, the AD conversion input signal W3, the sample signal W8, and the excitation current W6. The horizontal axis of FIG. 3B indicates the passage of time.
  • the analog signal W1 is input to the first pulse transformer 3 with a constant value.
  • the first switch element 5 is in the ON state to conduct the drive signal W2.
  • the second switch element 62 is in the OFF state to cut off the reset signal W4.
  • an AD conversion input signal W3 corresponding to the analog signal W1 is generated on the secondary side of the first pulse transformer 3.
  • the potential of this AD conversion input signal W3 is constant at Vin.
  • the sample period of the sample signal W8 is within the conduction period of the AD conversion input signal W3.
  • FIG. 4A is a circuit configuration diagram showing the reset state of the first pulse transformer 3.
  • FIG. 4B is a timing chart showing operation waveforms of respective parts in the reset state (reset period) of the first pulse transformer 3.
  • FIG. The vertical axis of FIG. 4B indicates the analog signal W1, the reset signal W4, the AD conversion input signal W3, and the reset current W7.
  • the horizontal axis of FIG. 4B indicates the passage of time.
  • the analog signal W1 is input to the first pulse transformer 3 with a constant value. Further, during the reset period of the first pulse transformer 3, the first switch element 5 is in the OFF state to cut off the drive signal W2. On the other hand, the second switch element 62 is in the ON state to conduct the reset signal W4.
  • the reset circuit 6 has a resistance element 61 and a second switch element 62, and the reset current W7 flows through the resistance element 61 only during the reset period. Therefore, the first pulse transformer 3 is not affected by power consumption by the resistance element 61 during the driving period of the first pulse transformer 3 .
  • the AD converter 10 samples the AD converted input signal W3, the AD converter 10 can suppress distortion in the waveform of the AD converted input signal W3. can be sensed with high accuracy.
  • the reset circuit 6 is arranged on the secondary side of the first pulse transformer 3, an insulating element is provided for the reset circuit 6 that controls the second switch element 62. No need.
  • FIG. 7 is a circuit configuration diagram showing a conventional reset circuit 6B.
  • a resistance element 61 and a rectifying element 64 such as a diode are connected in series to the signal line from the first switch element 5.
  • the reset circuit 6 does not have the rectifying element 64 that the conventional reset circuit 6B has. can also exhibit the reset function.
  • the analog signal input device 1 includes the first pulse transformer 3 that insulates the analog signal W1 input from the outside, and the first switch element connected to the primary side of the first pulse transformer 3. 5, a reset circuit 6 connected in parallel with the first pulse transformer 3 on the secondary side of the first pulse transformer 3 and having a resistance element 61 and a second switch element 62 connected in series with each other; A drive signal W2 for on/off controlling the first switching element 5 is output to the element 5, and a reset signal W4 for on/off controlling the second switching element 62 is output to the second switching element 62. and a control circuit 11 for outputting, the control circuit 11 turns on the second switch element 62 when turning off the first switch element 5 . Therefore, the analog signal input device 1 can suppress distortion of the analog signal W1 (AD conversion input signal W3). As a result, the analog signal input device 1 can sense the analog signal W1 with high precision.
  • FIG. 5 is a circuit configuration diagram showing the configuration of an analog signal input device 1B according to the second embodiment. It should be noted that configurations having functions similar to those of the configurations described in the above-described embodiments are denoted by the same reference numerals, and description thereof will be omitted.
  • An analog signal input device 1A according to the second embodiment includes a reset circuit 6A instead of the reset circuit 6 of the analog signal input device 1 according to the first embodiment.
  • the reset circuit 6A is arranged on the secondary side of the first pulse transformer 3. This reset circuit 6A demagnetizes the magnetic core that constitutes the first pulse transformer 3. As shown in FIG.
  • the reset circuit 6 also has a resistance element 61 , a second switch element 62 and an inverting buffer element 63 .
  • the resistance element 61 , the second switch element 62 and the inverting buffer element 63 are connected in series with the signal line from the first pulse transformer 3 .
  • the drive signal W2 output from the timing control section 112 of the control circuit 11 is input to the first switch element 5 via the buffer element 9a, the multiplexer 8, and the second pulse transformer 4.
  • the drive signal W2 is also input to the second switch element 62 via the buffer element 9a, the multiplexer 8, and the inverting buffer element 63.
  • the reset signal W4 for on/off controlling the second switch element 62 is generated by using the inverting buffer element 63 to invert the polarity of the drive signal W2. Therefore, the timing control section 112 does not need to include a circuit for generating the reset signal W4 and a circuit for adjusting the output timing of the reset signal W4. As a result, the circuit configuration of the control circuit 11 can be simplified in the analog signal input device 1A.
  • the reset circuit 6A has the inversion buffer element 63 that inverts the polarity of the drive signal W2 to generate the reset signal W4. Therefore, in the analog signal input device 1A, the circuit configuration of the control circuit 11 can be simplified.
  • the present disclosure can freely combine each embodiment, modify any component of each embodiment, or omit any component in each embodiment. .
  • the analog signal input device suppresses distortion of the analog signal by turning on the second switch element to which the reset signal is input when turning off the first switch element to which the drive signal is input. and is suitable for use in analog signal input devices and the like.
  • 1, 1A, 1B analog signal input device 1a, 1b input terminal, 2 sensor element, 3 first pulse transformer, 4 second pulse transformer, 5 first switch element, 6, 6A, 6B reset circuit, 61 resistance element, 62 second switch element, 63 inverting buffer element, 64 rectifying element, 7 amplifier element, 8 multiplexer, 9a, 9b buffer element, 10 AD converter, 11 control circuit, 111 processing unit, 112 timing control unit, 113 Ch selection unit , 12 Photocoupler, 13 Isolated power supply circuit, W1 Analog signal, W2 Drive signal, W3 AD conversion input signal, W4 Reset signal, W6 Excitation current, W7 Reset current, W8 Sample signal.

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Abstract

This analog signal input device (1) comprises: a first pulse transformer (3) which insulates an analog signal (W1) input from the outside; a first switch element (5) which is connected to a primary side of the first pulse transformer (3); a reset circuit (6) which is connected in parallel to the first pulse transformer (3) on a secondary side of the first pulse transformer (3), and has a resistance element (61) and a second switch element (62) connected in series to each other; and a control circuit (11) which outputs, to the first switch element (5), a drive signal (W2) for controlling on-off of the first switch element (5), and outputs, to the second switch element (62), a reset signal (W4) for controlling on-off of the second switch element (62), wherein the control circuit (11) turns ON the second switch element (62) when turning OFF the first switch element (5).

Description

アナログ信号入力装置Analog signal input device
　本開示は、アナログ信号入力装置に関する。 The present disclosure relates to an analog signal input device.
　アナログ信号入力装置は、産業用途の制御監視機器等で使用されることが多い。このアナログ信号入力装置は、例えば、温度センサ等の機器から出力されたアナログ信号を、高い精度でＡＤ変換器に取り込む。このとき、アナログ信号をＡＤ変換するためには、絶縁が必要となる。アナログ信号入力装置においては、一般に厳しい設置環境で使用されることを想定し、大地（アース）等を介したグランドループに起因する障害を避けるために、入力部と内部回路との間に、絶縁の措置がなされている。 Analog signal input devices are often used in industrial control and monitoring equipment. This analog signal input device receives, with high accuracy, an analog signal output from a device such as a temperature sensor into an AD converter. At this time, insulation is required in order to AD-convert the analog signal. Assuming that analog signal input devices are generally used in harsh installation environments, insulation is provided between the input section and the internal circuits to avoid failures caused by ground loops via the earth (earth), etc. measures have been taken.
　そこで、アナログ信号を受信するにあたり、トランス素子を絶縁手段として用いた絶縁方式を、アナログ信号入力装置に採用することが、提案されている。特許文献１には、絶縁方式を採用したアナログ信号入力装置が開示されている。 Therefore, in receiving analog signals, it has been proposed to adopt an insulation method using a transformer element as an insulation means in an analog signal input device. Patent Document 1 discloses an analog signal input device that employs an insulation method.
特開２０１３－１４５５０９号公報JP 2013-145509 A
　特許文献１に開示されたアナログ信号入力装置は、パルストランスの２次側に、波形整形回路を備えている。この波形整形回路は、パルストランスの磁性コアを消磁させるものである。しかしながら、その波形整形回路は、アナログ信号をＡＤ変換器に出力する際に、常時電気的に接続された状態となっているため、その波形整形回路から出力されたアナログ信号の波形には、歪みが生じ易くなる。このように、アナログ信号の波形に歪みが発生すると、ＡＤ変換器よるアナログ信号のセンシング精度が低下するおそれがある。 The analog signal input device disclosed in Patent Document 1 has a waveform shaping circuit on the secondary side of the pulse transformer. This waveform shaping circuit demagnetizes the magnetic core of the pulse transformer. However, since the waveform shaping circuit is always electrically connected when outputting the analog signal to the AD converter, the waveform of the analog signal output from the waveform shaping circuit is distorted. becomes more likely to occur. When the waveform of the analog signal is distorted in this manner, the accuracy of sensing the analog signal by the AD converter may deteriorate.
　本開示は、上記のような課題を解決するためになされたもので、アナログ信号の歪みを抑えることができるアナログ信号入力装置を提供することを目的としている。 The present disclosure has been made to solve the above problems, and aims to provide an analog signal input device capable of suppressing distortion of analog signals.
　本開示に係るアナログ信号入力装置は、外部から入力されたアナログ信号を絶縁するパルストランスと、パルストランスの１次側に接続される第１スイッチ素子と、パルストランスの２次側において当該パルストランスと並列に接続され、互いに直列に接続された抵抗素子及び第２スイッチ素子を有するリセット回路と、第１スイッチ素子に対して、当該第１スイッチ素子をオンオフ制御するためのドライブ信号を出力し、第２スイッチ素子に対して、当該第２スイッチ素子をオンオフ制御するためのリセット信号を出力する制御回路とを備え、制御回路は、第１スイッチ素子をＯＦＦにするときに、第２スイッチ素子をＯＮにするものである。 An analog signal input device according to the present disclosure includes a pulse transformer that isolates an analog signal input from the outside, a first switch element connected to the primary side of the pulse transformer, and the pulse transformer on the secondary side of the pulse transformer. and a reset circuit having a resistance element and a second switch element connected in series with each other, and a drive signal for on-off controlling the first switch element to the first switch element, a control circuit for outputting a reset signal for on/off controlling the second switch element to the second switch element, wherein the control circuit turns off the second switch element when turning off the first switch element; ON.
　本開示によれば、アナログ信号の歪みを抑えることができる。この結果、本開示に係るアナログ信号入力装置は、アナログ信号を高精度でセンシングすることができる。 According to the present disclosure, distortion of analog signals can be suppressed. As a result, the analog signal input device according to the present disclosure can sense analog signals with high accuracy.
実施の形態１に係るアナログ信号入力装置の構成を示す回路構成図である。1 is a circuit configuration diagram showing the configuration of an analog signal input device according to Embodiment 1; FIG. 実施の形態１に係るアナログ信号入力装置における各部の動作波形を示すタイミングチャートである。4 is a timing chart showing operation waveforms of each part in the analog signal input device according to the first embodiment; 図３Ａは、第１パルストランスの駆動状態を示す回路構成図である。図３Ｂは、第１パルストランスの駆動状態における各部の動作波形を示すタイミングチャートである。FIG. 3A is a circuit configuration diagram showing the driving state of the first pulse transformer. FIG. 3B is a timing chart showing operation waveforms of each part in the driving state of the first pulse transformer. 図４Ａは、第１パルストランスのリセット状態を示す回路構成図である。図４Ｂは、第１パルストランスのリセット状態における各部の動作波形を示すタイミングチャートである。FIG. 4A is a circuit configuration diagram showing a reset state of the first pulse transformer. FIG. 4B is a timing chart showing operation waveforms of respective parts in the reset state of the first pulse transformer. 実施の形態２に係るアナログ信号入力装置の構成を示す回路構成図である。2 is a circuit configuration diagram showing the configuration of an analog signal input device according to a second embodiment; FIG. 従来のアナログ信号入力装置を示す回路構成図である。1 is a circuit configuration diagram showing a conventional analog signal input device; FIG. 従来のリセット回路を示す回路構成図である。1 is a circuit configuration diagram showing a conventional reset circuit; FIG.
　以下、本開示をより詳細に説明するために、本開示を実施するための形態について、添付の図面に従って説明する。 Hereinafter, in order to describe the present disclosure in more detail, embodiments for carrying out the present disclosure will be described according to the attached drawings.
実施の形態１．
　実施の形態１に係るアナログ信号入力装置１について、図１から図４、図６、図７を用いて説明する。 Embodiment 1.
An analog signal input device 1 according to Embodiment 1 will be described with reference to FIGS. 1 to 4, 6 and 7. FIG.
　先ず始めに、トランス絶縁方式を用いたアナログ信号入力装置の動作概要について、特許文献１に開示された技術を例に挙げて説明する。 First, an overview of the operation of an analog signal input device using a transformer isolation method will be described by taking the technology disclosed in Patent Document 1 as an example.
　センサ素子から出力されたアナログ信号は、スイッチ素子及びパルストランスを介して、最終的にＡＤ変換器に伝達される。センサ素子は、例えば、温度センサを想定している。このとき、センサ素子から出力されるアナログ信号が非常に低周波数信号（実質的に直流信号）である場合、当該アナログ信号が低周波数信号のままでは、トランスを介した絶縁伝送ができない、又は、パルストランスを極端に大きくする必要がある。そこで、特許文献１に開示された技術においては、アナログ信号を過渡パルス波形の形状にする（変調する）ことで、小型のパルストランスを用いて、アナログ信号の絶縁伝送を行っている。 The analog signal output from the sensor element is finally transmitted to the AD converter via the switch element and pulse transformer. A sensor element is assumed to be, for example, a temperature sensor. At this time, if the analog signal output from the sensor element is a very low frequency signal (substantially a DC signal), isolated transmission via the transformer cannot be performed if the analog signal is a low frequency signal, or It is necessary to make the pulse transformer extremely large. Therefore, in the technique disclosed in Patent Document 1, by shaping (modulating) an analog signal into a transient pulse waveform, isolated transmission of the analog signal is performed using a small pulse transformer.
　図１は、実施の形態１に係るアナログ信号入力装置１の構成を示す回路構成図である。このアナログ信号入力装置１は、入力端子１ａ，１ｂを有している。この入力端子１ａ，１ｂには、１つ以上のセンサ素子２がケーブル等を介して接続されている。 FIG. 1 is a circuit configuration diagram showing the configuration of an analog signal input device 1 according to Embodiment 1. FIG. This analog signal input device 1 has input terminals 1a and 1b. One or more sensor elements 2 are connected to the input terminals 1a and 1b via cables or the like.
　アナログ信号入力装置１は、第１パルストランス３、第２パルストランス４、第１スイッチ素子５、リセット回路６、アンプ素子７、マルチプレクサ８、バッファ素子９ａ，９ｂ、ＡＤ変換器１０、及び、制御回路１１を備えている。このアナログ信号入力装置１は、トランス絶縁方式を採用したものである。 The analog signal input device 1 includes a first pulse transformer 3, a second pulse transformer 4, a first switch element 5, a reset circuit 6, an amplifier element 7, a multiplexer 8, buffer elements 9a and 9b, an AD converter 10, and a control circuit. A circuit 11 is provided. This analog signal input device 1 employs a transformer insulation method.
　このような、アナログ信号入力装置１は、センサ素子２から出力されたアナログ信号（センサ素子信号）Ｗ１を、絶縁を介して、ＡＤ変換器１０に精度良く取り込む装置である。また、アナログ信号入力装置１は、入力チャンネル数（アナログチャンネル数）に応じた回路数を有している。図１は、入力チャンネル数が８つの（Ｃｈ１－Ｃｈ８）例を示している。 Such an analog signal input device 1 is a device that accurately captures the analog signal (sensor element signal) W1 output from the sensor element 2 into the AD converter 10 via insulation. Also, the analog signal input device 1 has the number of circuits corresponding to the number of input channels (the number of analog channels). FIG. 1 shows an example of eight input channels (Ch1-Ch8).
　第１パルストランス３は、センサ素子２から入力されたアナログ信号Ｗ１を絶縁するものである。なお、第１パルストランス３は、パルストランスを構成するものである。 The first pulse transformer 3 insulates the analog signal W1 input from the sensor element 2. The first pulse transformer 3 constitutes a pulse transformer.
　第２パルストランス４は、後述する第１スイッチ素子５を制御するものである。 The second pulse transformer 4 controls the first switch element 5, which will be described later.
　第１スイッチ素子５は、第１パルストランス３の１次側（絶縁側）に接続されている。この第１スイッチ素子５は、アナログ信号Ｗ１を第１パルストランス３に印加するものである。また、第１スイッチ素子５には、第２パルストランス４からドライブ信号Ｗ２が入力可能となっている。ドライブ信号Ｗ２は、第１スイッチ素子５をオンオフ（開閉）制御するための信号である。 The first switch element 5 is connected to the primary side (insulation side) of the first pulse transformer 3 . The first switch element 5 applies the analog signal W1 to the first pulse transformer 3. As shown in FIG. Further, a drive signal W2 can be input from the second pulse transformer 4 to the first switch element 5 . The drive signal W2 is a signal for controlling the on/off (opening/closing) of the first switch element 5 .
　リセット回路６は、第１パルストランス３の２次側（内部回路側）において、当該第１パルストランス３と並列に接続されている。このリセット回路６は、第１パルストランス３を構成する磁性コアを消磁するものである。言い換えれば、リセット回路６は、第１パルストランス３に流れる励磁電流Ｗ６（図３参照）をリセットするものである。 The reset circuit 6 is connected in parallel with the first pulse transformer 3 on the secondary side (internal circuit side) of the first pulse transformer 3 . This reset circuit 6 demagnetizes the magnetic core that constitutes the first pulse transformer 3 . In other words, the reset circuit 6 resets the excitation current W6 (see FIG. 3) flowing through the first pulse transformer 3. FIG.
　また、リセット回路６は、互いに直列に接続された抵抗素子６１及び第２スイッチ素子６２を有している。具体的には、抵抗素子６１と第２スイッチ素子６２とは、第１パルストランス３からの信号ラインに対して、直列で接続されている。そして、第２スイッチ素子６２には、リセット信号Ｗ４が入力可能となっている。リセット信号Ｗ４は、第２スイッチ素子６２をオンオフ（開閉）制御するための信号である。 The reset circuit 6 also has a resistance element 61 and a second switch element 62 that are connected in series with each other. Specifically, the resistance element 61 and the second switch element 62 are connected in series with the signal line from the first pulse transformer 3 . A reset signal W4 can be input to the second switch element 62 . The reset signal W4 is a signal for controlling on/off (open/close) of the second switch element 62 .
　アンプ素子７は、リセット回路６の後段に接続されている。このアンプ素子７は、第１パルストランス３から出力されたアナログ信号Ｗ１を増幅させるものである。 The amplifier element 7 is connected after the reset circuit 6 . The amplifier element 7 amplifies the analog signal W1 output from the first pulse transformer 3. FIG.
　マルチプレクサ８は、複数の入力チャンネルのうち、いずれか１つのチャンネルを選択するものである。このマルチプレクサ８は、後述する制御回路１１によって制御される。 The multiplexer 8 selects any one of a plurality of input channels. This multiplexer 8 is controlled by a control circuit 11 which will be described later.
　ＡＤ変換器１０は、マルチプレクサ８の後段に接続されている。このＡＤ変換器１０は、マルチプレクサ８から出力されたアナログ信号Ｗ１を、デジタル信号に変換する。また、ＡＤ変換器１０は、変換したデジタル信号を制御回路１１に出力する。なお、図１においては、マルチプレクサ８から出力されるアナログ信号Ｗ１を、ＡＤ変換入力信号Ｗ３と示している。 The AD converter 10 is connected after the multiplexer 8 . This AD converter 10 converts the analog signal W1 output from the multiplexer 8 into a digital signal. Also, the AD converter 10 outputs the converted digital signal to the control circuit 11 . Note that in FIG. 1, the analog signal W1 output from the multiplexer 8 is shown as an AD conversion input signal W3.
　制御回路１１は、処理部１１１、タイミング制御部１１２、及び、Ｃｈ選択部１１３を有している。 The control circuit 11 has a processing section 111 , a timing control section 112 and a Ch selection section 113 .
　処理部１１１は、ＡＤ変換器１０から出力されたデジタル信号を処理するものである。また、処理部１１１は、処理結果をタイミング制御部１１２及びＣｈ選択部１１３に出力する。 The processing unit 111 processes the digital signal output from the AD converter 10 . The processing unit 111 also outputs the processing result to the timing control unit 112 and the Ch selection unit 113 .
　タイミング制御部１１２は、処理部１１１によって処理されたデジタル信号に基づいて、サンプル信号Ｗ８、ドライブ信号Ｗ２、及び、リセット信号Ｗ４を出力するものである。 The timing control section 112 outputs the sample signal W8, the drive signal W2, and the reset signal W4 based on the digital signal processed by the processing section 111.
　サンプル信号Ｗ８は、ＡＤ変換器１０がＡＤ変換入力信号Ｗ３をサンプリングするための信号である。このサンプル信号Ｗ８は、タイミング制御部１１２によって、ＡＤ変換器１０に出力される。ドライブ信号Ｗ２は、タイミング制御部１１２によって、バッファ素子９ａ、マルチプレクサ８、及び、第２パルストランス４を介して、第１パルストランス３に出力される。リセット信号Ｗ４は、タイミング制御部１１２によって、バッファ素子９ｂ及びマルチプレクサ８を介して、リセット回路６に出力される。 The sample signal W8 is a signal for the AD converter 10 to sample the AD converted input signal W3. This sample signal W8 is output to the AD converter 10 by the timing control section 112 . The drive signal W2 is output to the first pulse transformer 3 by the timing control section 112 via the buffer element 9a, the multiplexer 8, and the second pulse transformer 4. FIG. The reset signal W4 is output to the reset circuit 6 by the timing control section 112 via the buffer element 9b and the multiplexer 8. FIG.
　ここで、制御回路１１が、第１スイッチ素子５をオンオフ制御するためには、ドライブ信号Ｗ２を絶縁する必要がある。このため、アナログ信号入力装置１は、第２パルストランス４を備えている。図１に示すように、アナログ信号入力装置１における第１パルストランス３及び第２パルストランス４の１次側は、トランジスタを用いた第１スイッチ素子５のみで構成されている。 Here, in order for the control circuit 11 to turn on/off the first switch element 5, it is necessary to insulate the drive signal W2. For this reason, the analog signal input device 1 has a second pulse transformer 4 . As shown in FIG. 1, the primary sides of the first pulse transformer 3 and the second pulse transformer 4 in the analog signal input device 1 are composed only of a first switch element 5 using a transistor.
　これに対して、図６は、従来のアナログ信号入力装置１Ｂを示す回路構成図である。この図６に示す従来のアナログ信号入力装置１Ｂは、フォトカプラ絶縁方式を採用するものである。従来のアナログ信号入力装置１Ｂは、アンプ素子７、マルチプレクサ８、バッファ素子９ａ，９ｂ、ＡＤ変換器１０、制御回路１１、フォトカプラ１２、及び、絶縁電源回路１３を備えている。アナログ信号入力装置１Ｂにおける１次側には、ＡＤ変換器１０及び絶縁電源回路１３が配置されている。 On the other hand, FIG. 6 is a circuit configuration diagram showing a conventional analog signal input device 1B. The conventional analog signal input device 1B shown in FIG. 6 employs a photocoupler insulation system. A conventional analog signal input device 1B includes an amplifier element 7, a multiplexer 8, buffer elements 9a and 9b, an AD converter 10, a control circuit 11, a photocoupler 12, and an isolated power supply circuit 13. An AD converter 10 and an isolated power supply circuit 13 are arranged on the primary side of the analog signal input device 1B.
　従って、図１及び図６に示すように、トランス絶縁方式のアナログ信号入力装置１の回路構成と、フォトカプラ絶縁方式のアナログ信号入力装置１Ｂの回路構成とを、対比すると、アナログ信号入力装置１は、アナログ信号入力装置１Ｂと比べて、部品点数及び製造コストの面で有利である。 Therefore, as shown in FIGS. 1 and 6, when the circuit configuration of the transformer insulation type analog signal input device 1 and the circuit configuration of the photocoupler insulation type analog signal input device 1B are compared, the analog signal input device 1 is advantageous in terms of the number of parts and manufacturing cost compared to the analog signal input device 1B.
　また、制御回路１１は、第１パルストランス３を駆動させた直後で、且つ、当該第１パルストランス３の磁性コアの消磁が必要となるタイミングでのみ、リセット回路６が機能するように、第２スイッチ素子６２を制御する。 Further, the control circuit 11 controls the reset circuit 6 so that the reset circuit 6 functions only immediately after the first pulse transformer 3 is driven and at the timing when the magnetic core of the first pulse transformer 3 needs to be demagnetized. 2 switch element 62 is controlled.
　次に、アナログ信号入力装置１の動作について、図２を用いて説明する。 Next, the operation of the analog signal input device 1 will be explained using FIG.
　図２は、実施の形態１に係るアナログ信号入力装置１の各部における動作波形を示すタイミングチャートである。図２の縦軸は、入力端子１ａ，１ｂに入力されたアナログ信号Ｗ１、タイミング制御部１１２から出力されたドライブ信号Ｗ２、ＡＤ変換器１０に入力されるＡＤ変換入力信号Ｗ３、及び、タイミング制御部１１２から出力されたリセット信号Ｗ４を示している。また、図２の横軸は、時間経過を示している。 FIG. 2 is a timing chart showing operation waveforms in each part of the analog signal input device 1 according to the first embodiment. The vertical axis in FIG. 2 represents the analog signal W1 input to the input terminals 1a and 1b, the drive signal W2 output from the timing control unit 112, the AD conversion input signal W3 input to the AD converter 10, and the timing control. A reset signal W4 output from the unit 112 is shown. Moreover, the horizontal axis of FIG. 2 indicates the passage of time.
　アナログ信号Ｗ１は、センサ素子２からの出力信号であり、時間の経過と共に、緩やかに変化している。 The analog signal W1 is an output signal from the sensor element 2, and gradually changes with the passage of time.
　ドライブ信号Ｗ２は、バッファ素子９ａ、マルチプレクサ８、及び、第２パルストランス４を介して、第１スイッチ素子５をオン又はオフにする。即ち、ドライブ信号Ｗ２が高電位となる期間は、第１パルストランス３が駆動する期間となる。その期間においては、アナログ信号Ｗ１の振幅に対応した電圧が、第１パルストランス３の２次側に伝達される。また、ドライブ信号Ｗ２が低電位となる期間は、第１パルストランス３がリセットされる期間となる。 The drive signal W2 turns on or off the first switch element 5 via the buffer element 9a, the multiplexer 8, and the second pulse transformer 4. That is, the period during which the drive signal W2 is at a high potential is the period during which the first pulse transformer 3 is driven. During that period, a voltage corresponding to the amplitude of the analog signal W1 is transmitted to the secondary side of the first pulse transformer 3. FIG. The period during which the drive signal W2 is at a low potential is the period during which the first pulse transformer 3 is reset.
　ＡＤ変換入力信号Ｗ３の波形は、第１パルストランス３の２次側で観測される。ＡＤ変換入力信号Ｗ３は、ドライブ信号Ｗ２が高電位となる期間において、アナログ信号Ｗ１の振幅に対応した値となる。このとき、ＡＤ変換入力信号Ｗ３の振幅は、ＡＤ変換器１０によってサンプリングされる。また、ＡＤ変換入力信号Ｗ３には、リセット信号Ｗ４が高電位となる時刻において、バックスイングが生じる。このバックスイングは、第１パルストランス３の励磁電流Ｗ６（図３参照）の残留として生じるリセット電流Ｗ７（図４参照）に起因するものである。リセット回路６は、そのバックスイングの過大振幅及び長期振動を抑制するために設けられている。 The waveform of the AD conversion input signal W3 is observed on the secondary side of the first pulse transformer 3. The AD conversion input signal W3 has a value corresponding to the amplitude of the analog signal W1 while the drive signal W2 is at high potential. At this time, the amplitude of the AD conversion input signal W3 is sampled by the AD converter 10 . Further, backswing occurs in the AD conversion input signal W3 at the time when the reset signal W4 becomes high potential. This backswing is caused by a reset current W7 (see FIG. 4) generated as a residual excitation current W6 (see FIG. 3) of the first pulse transformer 3. FIG. A reset circuit 6 is provided to suppress excessive amplitude and long-term vibration of the backswing.
　リセット信号Ｗ４は、バッファ素子９ｂ及びマルチプレクサ８を介して、リセット回路６の第２スイッチ素子６２をオン又はオフにする。即ち、リセット信号Ｗ４が高電位となる期間は、第１パルストランス３の磁性コアが消磁（リセット）される期間となる。バックスイングは、その第１パルストランス３の磁性コアが消磁される期間において、リセット回路６の抵抗素子６１による電力消費によって、速やかに減衰収縮する。 The reset signal W4 turns on or off the second switch element 62 of the reset circuit 6 via the buffer element 9b and the multiplexer 8. That is, the period during which the reset signal W4 is at a high potential is the period during which the magnetic core of the first pulse transformer 3 is demagnetized (reset). The backswing quickly attenuates and contracts due to power consumption by the resistance element 61 of the reset circuit 6 during the period in which the magnetic core of the first pulse transformer 3 is demagnetized.
　次に、第１パルストランス３の動作について、図３及び図４を用いて詳細に説明する。 Next, the operation of the first pulse transformer 3 will be described in detail using FIGS. 3 and 4. FIG.
　図３Ａは、第１パルストランス３の駆動状態を示す回路構成図である。図３Ｂは、第１パルストランス３の駆動状態（駆動期間）における各部の動作波形を示すタイミングチャートである。図３Ｂの縦軸は、アナログ信号Ｗ１、ドライブ信号Ｗ２、ＡＤ変換入力信号Ｗ３、及び、サンプル信号Ｗ８、及び、励磁電流Ｗ６を示している。図３Ｂの横軸は、時間の経過を示している。 3A is a circuit configuration diagram showing the driving state of the first pulse transformer 3. FIG. FIG. 3B is a timing chart showing operation waveforms of respective parts in the driving state (driving period) of the first pulse transformer 3. As shown in FIG. The vertical axis of FIG. 3B indicates the analog signal W1, the drive signal W2, the AD conversion input signal W3, the sample signal W8, and the excitation current W6. The horizontal axis of FIG. 3B indicates the passage of time.
　図３に示すように、第１パルストランス３には、アナログ信号Ｗ１が一定の値で入力されている。また、第１パルストランス３の駆動期間においては、第１スイッチ素子５は、ドライブ信号Ｗ２を導通させるＯＮ状態となっている。一方、第２スイッチ素子６２は、リセット信号Ｗ４を遮断するＯＦＦ状態となっている。 As shown in FIG. 3, the analog signal W1 is input to the first pulse transformer 3 with a constant value. During the drive period of the first pulse transformer 3, the first switch element 5 is in the ON state to conduct the drive signal W2. On the other hand, the second switch element 62 is in the OFF state to cut off the reset signal W4.
　第１スイッチ素子５に対してドライブ信号Ｗ２が導通すると、第１パルストランス３の１次側には、励磁電流Ｗ６が流れる。第１パルストランス３の駆動期間（第１スイッチ素子５の導通期間）においては、励磁電流Ｗ６は、ファラデー（電磁誘導）の法則に従って線形的に増加し、当該励磁電流Ｗ６の総和は、Ｉｄｒとなる。 When the drive signal W2 is conducted to the first switch element 5, an exciting current W6 flows through the primary side of the first pulse transformer 3. During the driving period of the first pulse transformer 3 (the conduction period of the first switch element 5), the excitation current W6 linearly increases according to the Faraday (electromagnetic induction) law, and the total excitation current W6 is Idr Become.
　また、第１パルストランス３の駆動期間においては、当該第１パルストランス３の二次側には、アナログ信号Ｗ１に対応したＡＤ変換入力信号Ｗ３が発生する。このＡＤ変換入力信号Ｗ３の電位は、Ｖｉｎで一定となる。更に、サンプル信号Ｗ８によるサンプル期間は、ＡＤ変換入力信号Ｗ３の導通期間以内となっている。 Also, during the driving period of the first pulse transformer 3, an AD conversion input signal W3 corresponding to the analog signal W1 is generated on the secondary side of the first pulse transformer 3. The potential of this AD conversion input signal W3 is constant at Vin. Furthermore, the sample period of the sample signal W8 is within the conduction period of the AD conversion input signal W3.
　図４Ａは、第１パルストランス３のリセット状態を示す回路構成図である。図４Ｂは、第１パルストランス３のリセット状態（リセット期間）における各部の動作波形を示すタイミングチャートである。図４Ｂの縦軸は、アナログ信号Ｗ１、リセット信号Ｗ４、ＡＤ変換入力信号Ｗ３、及び、リセット電流Ｗ７を示している。図４Ｂの横軸は、時間の経過を示している。 4A is a circuit configuration diagram showing the reset state of the first pulse transformer 3. FIG. FIG. 4B is a timing chart showing operation waveforms of respective parts in the reset state (reset period) of the first pulse transformer 3. FIG. The vertical axis of FIG. 4B indicates the analog signal W1, the reset signal W4, the AD conversion input signal W3, and the reset current W7. The horizontal axis of FIG. 4B indicates the passage of time.
　第１パルストランス３を構成する磁性コアの飽和又は偏磁を防止するためには、リセット信号Ｗ４によるリセット期間において、磁性コアを消磁させる必要がある。 In order to prevent saturation or biased magnetization of the magnetic core that constitutes the first pulse transformer 3, it is necessary to demagnetize the magnetic core during the reset period by the reset signal W4.
　図４に示すように、第１パルストランス３には、アナログ信号Ｗ１が一定の値で入力されている。また、第１パルストランス３のリセット期間においては、第１スイッチ素子５は、ドライブ信号Ｗ２を遮断するＯＦＦ状態となっている。一方、第２スイッチ素子６２は、リセット信号Ｗ４を導通させるＯＮ状態となっている。 As shown in FIG. 4, the analog signal W1 is input to the first pulse transformer 3 with a constant value. Further, during the reset period of the first pulse transformer 3, the first switch element 5 is in the OFF state to cut off the drive signal W2. On the other hand, the second switch element 62 is in the ON state to conduct the reset signal W4.
　第２スイッチ素子６２に対してリセット信号Ｗ４が導通すると、第１パルストランス３の２次側には、リセット電流Ｗ７が流れる。第１パルストランス３のリセット期間における第２スイッチ素子６２の導通期間においては、リセット電流Ｗ７の総和は、Ｉｒｓｔとなる。このとき、リセット電流Ｗ７がリセット回路６の抵抗素子６１を流れることで、当該リセット電流Ｗ７には、電力消費が発生する。このため、ＡＤ変換入力信号Ｗ３のバックスイングは、速やかに収束される。 When the reset signal W4 is conducted to the second switch element 62, a reset current W7 flows through the secondary side of the first pulse transformer 3. During the conduction period of the second switch element 62 during the reset period of the first pulse transformer 3, the total sum of the reset current W7 is Irst. At this time, as the reset current W7 flows through the resistance element 61 of the reset circuit 6, power consumption occurs in the reset current W7. Therefore, the backswing of the AD conversion input signal W3 quickly converges.
　即ち、リセット回路６は、抵抗素子６１及び第２スイッチ素子６２を有しており、リセット期間でのみ、抵抗素子６１にリセット電流Ｗ７が流れる。このため、第１パルストランス３は、当該第１パルストランス３の駆動期間において、抵抗素子６１による電力消費の影響を受けることがない。この結果、ＡＤ変換器１０がＡＤ変換入力信号Ｗ３に対してサンプリングする場合、当該ＡＤ変換器１０は、ＡＤ変換入力信号Ｗ３の波形に対して、歪みを抑えることができ、ＡＤ変換入力信号Ｗ３を高精度でセンシングすることができる。 That is, the reset circuit 6 has a resistance element 61 and a second switch element 62, and the reset current W7 flows through the resistance element 61 only during the reset period. Therefore, the first pulse transformer 3 is not affected by power consumption by the resistance element 61 during the driving period of the first pulse transformer 3 . As a result, when the AD converter 10 samples the AD converted input signal W3, the AD converter 10 can suppress distortion in the waveform of the AD converted input signal W3. can be sensed with high accuracy.
　なお、アナログ信号入力装置１においては、第１パルストランス３の２次側に、リセット回路６を配置させているため、第２スイッチ素子６２を制御するリセット回路６に対して、絶縁素子を設ける必要は無い。 In the analog signal input device 1, since the reset circuit 6 is arranged on the secondary side of the first pulse transformer 3, an insulating element is provided for the reset circuit 6 that controls the second switch element 62. No need.
　ここで、図７は、従来のリセット回路６Ｂを示す回路構成図である。この従来のリセット回路６Ｂは、第１スイッチ素子５からの信号ラインに対して、抵抗素子６１、及び、ダイオード等の整流素子６４を直列で接続するものである。これに対して、リセット回路６は、従来のリセット回路６Ｂが備えるような、整流素子６４を有していないため、仮に、アナログ信号Ｗ１がダイオードの順方向降下電圧よりも微小振幅であったとしても、上記リセット機能を発揮することができる。 Here, FIG. 7 is a circuit configuration diagram showing a conventional reset circuit 6B. In this conventional reset circuit 6B, a resistance element 61 and a rectifying element 64 such as a diode are connected in series to the signal line from the first switch element 5. FIG. On the other hand, the reset circuit 6 does not have the rectifying element 64 that the conventional reset circuit 6B has. can also exhibit the reset function.
　以上、実施の形態１に係るアナログ信号入力装置１は、外部から入力されたアナログ信号Ｗ１を絶縁する第１パルストランス３と、第１パルストランス３の１次側に接続される第１スイッチ素子５と、第１パルストランス３の２次側において当該第１パルストランス３と並列に接続され、互いに直列に接続された抵抗素子６１及び第２スイッチ素子６２を有するリセット回路６と、第１スイッチ素子５に対して、当該第１スイッチ素子５をオンオフ制御するためのドライブ信号Ｗ２を出力し、第２スイッチ素子６２に対して、当該第２スイッチ素子６２をオンオフ制御するためのリセット信号Ｗ４を出力する制御回路１１とを備え、制御回路１１は、第１スイッチ素子５をＯＦＦにするときに、第２スイッチ素子６２をＯＮにする。このため、アナログ信号入力装置１は、アナログ信号Ｗ１（ＡＤ変換入力信号Ｗ３）の歪みを抑えることができる。この結果、アナログ信号入力装置１は、アナログ信号Ｗ１を高精度でセンシングすることができる。 As described above, the analog signal input device 1 according to the first embodiment includes the first pulse transformer 3 that insulates the analog signal W1 input from the outside, and the first switch element connected to the primary side of the first pulse transformer 3. 5, a reset circuit 6 connected in parallel with the first pulse transformer 3 on the secondary side of the first pulse transformer 3 and having a resistance element 61 and a second switch element 62 connected in series with each other; A drive signal W2 for on/off controlling the first switching element 5 is output to the element 5, and a reset signal W4 for on/off controlling the second switching element 62 is output to the second switching element 62. and a control circuit 11 for outputting, the control circuit 11 turns on the second switch element 62 when turning off the first switch element 5 . Therefore, the analog signal input device 1 can suppress distortion of the analog signal W1 (AD conversion input signal W3). As a result, the analog signal input device 1 can sense the analog signal W1 with high precision.
実施の形態２．
　実施の形態２に係るアナログ信号入力装置１Ｂについて、図５を用いて説明する。図５は、実施の形態２に係るアナログ信号入力装置１Ｂの構成を示す回路構成図である。なお、上述した実施の形態で説明した構成と同様の機能を有する構成については、同一の符号を付し、その説明を省略する。 Embodiment 2.
An analog signal input device 1B according to Embodiment 2 will be described with reference to FIG. FIG. 5 is a circuit configuration diagram showing the configuration of an analog signal input device 1B according to the second embodiment. It should be noted that configurations having functions similar to those of the configurations described in the above-described embodiments are denoted by the same reference numerals, and description thereof will be omitted.
　実施の形態２に係るアナログ信号入力装置１Ａは、実施の形態１に係るアナログ信号入力装置１のリセット回路６に替えて、リセット回路６Ａを備えている。 An analog signal input device 1A according to the second embodiment includes a reset circuit 6A instead of the reset circuit 6 of the analog signal input device 1 according to the first embodiment.
　リセット回路６Ａは、第１パルストランス３の２次側に配置されている。このリセット回路６Ａは、第１パルストランス３を構成する磁性コアを消磁するものである。また、リセット回路６は、抵抗素子６１、第２スイッチ素子６２、及び、反転バッファ素子６３を有している。抵抗素子６１、第２スイッチ素子６２、及び、反転バッファ素子６３は、第１パルストランス３からの信号ラインに対して、直列で接続されている。 The reset circuit 6A is arranged on the secondary side of the first pulse transformer 3. This reset circuit 6A demagnetizes the magnetic core that constitutes the first pulse transformer 3. As shown in FIG. The reset circuit 6 also has a resistance element 61 , a second switch element 62 and an inverting buffer element 63 . The resistance element 61 , the second switch element 62 and the inverting buffer element 63 are connected in series with the signal line from the first pulse transformer 3 .
　制御回路１１のタイミング制御部１１２から出力されたドライブ信号Ｗ２は、バッファ素子９ａ、マルチプレクサ８、及び、第２パルストランス４を介して、第１スイッチ素子５に入力される。また、そのドライブ信号Ｗ２は、バッファ素子９ａ、マルチプレクサ８、及び、反転バッファ素子６３を介して、第２スイッチ素子６２に入力される。 The drive signal W2 output from the timing control section 112 of the control circuit 11 is input to the first switch element 5 via the buffer element 9a, the multiplexer 8, and the second pulse transformer 4. The drive signal W2 is also input to the second switch element 62 via the buffer element 9a, the multiplexer 8, and the inverting buffer element 63. FIG.
　即ち、第２スイッチ素子６２をオンオフ制御するリセット信号Ｗ４は、反転バッファ素子６３を用いて、ドライブ信号Ｗ２の極性を反転させることによって生成される。このため、タイミング制御部１１２は、リセット信号Ｗ４を生成するための回路、及び、そのリセット信号Ｗ４の出力タイミングを調整するための回路を、備える必要が無い。この結果、アナログ信号入力装置１Ａは、制御回路１１の回路構成を簡素にすることができる。 That is, the reset signal W4 for on/off controlling the second switch element 62 is generated by using the inverting buffer element 63 to invert the polarity of the drive signal W2. Therefore, the timing control section 112 does not need to include a circuit for generating the reset signal W4 and a circuit for adjusting the output timing of the reset signal W4. As a result, the circuit configuration of the control circuit 11 can be simplified in the analog signal input device 1A.
　以上、実施の形態２に係るアナログ信号入力装置１Ａにおいては、リセット回路６Ａは、ドライブ信号Ｗ２の極性を反転させることで、リセット信号Ｗ４を生成する反転バッファ素子６３を有する。このため、アナログ信号入力装置１Ａは、制御回路１１の回路構成を簡素にすることができる。 As described above, in the analog signal input device 1A according to the second embodiment, the reset circuit 6A has the inversion buffer element 63 that inverts the polarity of the drive signal W2 to generate the reset signal W4. Therefore, in the analog signal input device 1A, the circuit configuration of the control circuit 11 can be simplified.
　なお、本開示はその開示の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In addition, within the scope of the disclosure, the present disclosure can freely combine each embodiment, modify any component of each embodiment, or omit any component in each embodiment. .
　本開示に係るアナログ信号入力装置は、ドライブ信号が入力される第１スイッチ素子をＯＦＦにするときに、リセット信号が入力される第２スイッチ素子をＯＮにすることで、アナログ信号の歪みを抑えることができ、アナログ信号入力装置等に用いるのに適している。 The analog signal input device according to the present disclosure suppresses distortion of the analog signal by turning on the second switch element to which the reset signal is input when turning off the first switch element to which the drive signal is input. and is suitable for use in analog signal input devices and the like.
　１，１Ａ，１Ｂ　アナログ信号入力装置、１ａ，１ｂ　入力端子、２　センサ素子、３　第１パルストランス、４　第２パルストランス、５　第１スイッチ素子、６，６Ａ，６Ｂ　リセット回路、６１　抵抗素子、６２　第２スイッチ素子、６３　反転バッファ素子、６４　整流素子、７　アンプ素子、８　マルチプレクサ、９ａ，９ｂ　バッファ素子、１０　ＡＤ変換器、１１　制御回路、１１１　処理部、１１２　タイミング制御部、１１３　Ｃｈ選択部、１２　フォトカプラ、１３　絶縁電源回路、Ｗ１　アナログ信号、Ｗ２　ドライブ信号、Ｗ３　ＡＤ変換入力信号、Ｗ４　リセット信号、Ｗ６　励磁電流、Ｗ７　リセット電流、Ｗ８　サンプル信号。 1, 1A, 1B analog signal input device, 1a, 1b input terminal, 2 sensor element, 3 first pulse transformer, 4 second pulse transformer, 5 first switch element, 6, 6A, 6B reset circuit, 61 resistance element, 62 second switch element, 63 inverting buffer element, 64 rectifying element, 7 amplifier element, 8 multiplexer, 9a, 9b buffer element, 10 AD converter, 11 control circuit, 111 processing unit, 112 timing control unit, 113 Ch selection unit , 12 Photocoupler, 13 Isolated power supply circuit, W1 Analog signal, W2 Drive signal, W3 AD conversion input signal, W4 Reset signal, W6 Excitation current, W7 Reset current, W8 Sample signal.

Claims (2)

  1. 　外部から入力されたアナログ信号を絶縁するパルストランスと、
    　前記パルストランスの１次側に接続される第１スイッチ素子と、
    　前記パルストランスの２次側において当該パルストランスと並列に接続され、互いに直列に接続された抵抗素子及び第２スイッチ素子を有するリセット回路と、
    　前記第１スイッチ素子に対して、当該第１スイッチ素子をオンオフ制御するためのドライブ信号を出力し、前記第２スイッチ素子に対して、当該第２スイッチ素子をオンオフ制御するためのリセット信号を出力する制御回路とを備え、
    　前記制御回路は、前記第１スイッチ素子をＯＦＦにするときに、前記第２スイッチ素子をＯＮにする
    　ことを特徴とするアナログ信号入力装置。     A pulse transformer that isolates an analog signal input from the outside,
    a first switch element connected to the primary side of the pulse transformer;
    a reset circuit connected in parallel with the pulse transformer on the secondary side of the pulse transformer and having a resistive element and a second switch element connected in series with each other;
    Outputting a drive signal for on/off controlling the first switching element to the first switching element, and outputting a reset signal for on/off controlling the second switching element to the second switching element and a control circuit for
    The analog signal input device, wherein the control circuit turns on the second switch element when turning off the first switch element.
  2. 　前記リセット回路は、
    　前記ドライブ信号の極性を反転させることで、前記リセット信号を生成する反転バッファ素子を有する
    　ことを特徴とする請求項１記載のアナログ信号入力装置。     The reset circuit is
    2. The analog signal input device according to claim 1, further comprising an inverting buffer element that generates the reset signal by inverting the polarity of the drive signal.
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