WO2023077787A1 - 一种perc电池的se激光掺杂图形和perc电池制备方法 - Google Patents

一种perc电池的se激光掺杂图形和perc电池制备方法 Download PDF

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WO2023077787A1
WO2023077787A1 PCT/CN2022/096068 CN2022096068W WO2023077787A1 WO 2023077787 A1 WO2023077787 A1 WO 2023077787A1 CN 2022096068 W CN2022096068 W CN 2022096068W WO 2023077787 A1 WO2023077787 A1 WO 2023077787A1
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laser
silicon wafer
pattern
perc battery
resistance
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PCT/CN2022/096068
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French (fr)
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眭山
郑清吉
王玉浩
高柳
戴睿哲
芮亚豪
吴星
刘小瑞
侯东京
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通威太阳能（成都）有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application belongs to the field of solar cell preparation, and more specifically, relates to an SE laser doping pattern of a PERC cell and a method for preparing the PERC cell.
  • the publication date of the application is May 19, 2020, the application publication number is CN111180530A, and the Chinese patent titled a preparation method for a selective emitter battery discloses a technical solution, including dopant source diffusion to form a PN junction and laser
  • the step of doping to make a selective emitter is characterized in that in the step of laser doping to make a selective emitter, the energy and spot size of the laser irradiating the area to be metallized on the silicon wafer are changed, so that all The doped element is enriched to form a selective emitter.
  • the invention reduces the damage area of the cell sheet caused by the laser, realizes different doping regions in the contact area and non-contact area of the grid line, and improves the cell efficiency at the same time.
  • the authorized announcement date is July 27, 2021
  • the authorized announcement number is CN213798653U
  • the Chinese patent titled a DUP sub-gate alignment structure on the front of PERC battery discloses a technical solution, including the SE laser set on the front of the battery MARK points and three printing patterns, the three printing patterns include three main grids and alignment holes, and the SE laser MARK points do not coincide with the three printing patterns.
  • the SE laser MARK point is located outside the three printing patterns.
  • the three printing patterns are three busbars, that is, the alignment holes are blocked and will not be printed on the battery after the positions are confirmed by the three printing screens.
  • the three printing patterns of the utility model include three main grids and alignment holes, and the SE laser MARK points do not coincide with the three printing patterns, that is, the SE laser MARK points are not blocked by the three main grids and the alignment holes.
  • the three main grids and the four sub grids all capture the SE laser MARK points, so as to prevent the three printings from interfering with the four sub grids, make the sub grid printing accurate alignment, and thus solve the problem of EL foggy blackening.
  • anti-broken grid and resistance-reducing graphics are used in the design of the front fine grid screen, but the laser SE graphic only has a horizontal fine grid design, and laser SE is not used in the anti-broken grid line and harpoon area, but here There is front-side silver paste printed on the screen, the main resistance of the contact is high, and the low surface concentration fails to form a good ohmic contact, and the contact resistance is large, which affects the further improvement of battery efficiency.
  • this application provides a SE laser doping pattern of PERC battery and preparation method of PERC battery.
  • a PERC cell SE laser doping pattern may include several anti-broken grids, and the anti-broken grids are evenly arranged on the horizontal laser SE line and connected to the horizontal laser SE line.
  • the SE line forms an included angle ⁇ , wherein, 10° ⁇ 90°, and several resistance-reducing patterns are arranged on the top and/or bottom of the SE laser-doped pattern of the PERC cell, one of the resistance-reducing patterns
  • the angle between the side and the horizontal direction is ⁇ , where 10° ⁇ 90°.
  • This technical solution is provided with an anti-broken grid and a resistance-reducing pattern, and there is an included angle between the anti-broken grid and the horizontal laser SE line in the horizontal direction, and an included angle is formed between one side of the resistance-reduced graphic and the horizontal direction, which is convenient for screen printing and can be more It can well solve the problem that the printing is easy to break the grid and print falsely, which will lead to defective products.
  • the anti-breakage grids may be arranged at intervals in the vertical direction.
  • the anti-breakage barriers may be arranged in a row in the horizontal direction, and a blank row is provided between two adjacent rows of anti-breakage barriers.
  • the length of the resistance reducing pattern in the vertical direction may be 0.5 mm to 20 mm.
  • the included angle ⁇ between the anti-breaking grid and the horizontal laser line may be 30° ⁇ 60°, and the included angle ⁇ between one side of the resistance-reducing pattern and the horizontal direction may be 30° ⁇ 60° °.
  • the resistance-reducing patterns may be arranged at intervals in the horizontal direction.
  • the resistance-reducing figure can be set as various figures, and the figure includes a rectangle, a harpoon or trapezoid, a parallelogram, a triangle, or a square.
  • the present application also includes a method for preparing a PERC battery, which may include the following steps:
  • step S3 is specifically: setting an anti-breakage grid in the laser pattern, and the anti-breakage grid is evenly arranged on the horizontal laser SE line and forms an angle ⁇ with the horizontal laser SE line, wherein, 10° ⁇ 90° °.
  • resistance-reducing figures are also arranged on the top and/or bottom of the laser pattern in the step S3, and the resistance-reducing figures are arranged at intervals in the horizontal direction, and one side of the said resistance-reducing figure is in line with the horizontal direction.
  • the included angle is ⁇ , where 10° ⁇ 90°.
  • the laser spot in the step S3 is a square spot
  • the spot width is 40um to 150um
  • the laser frequency is 10KHz to 5000KHz
  • the pulse energy is 10J/pulse to 120uJ/pulse
  • the power per unit area is 2J/ cm2 to 80J /cm 2 .
  • the step S1 may include: cleaning the surface of the silicon wafer to form a triangular texture on the surface of the silicon wafer.
  • the step S2 may include: depositing a dopant source on the surface of the silicon wafer processed in the step S1 and performing thermal diffusion to prepare a P-N junction; the dopant source is phosphorus oxychloride and oxygen.
  • step S4 may include:
  • the step S41 may include: cleaning and back-polishing the laser-doped silicon wafer, and polishing the back of the silicon wafer with a mixed solution of HF, HNO 3 and H 2 SO 4 and a KOH/NaOH solution in a subsequent alkaline tank.
  • the N-type layer is etched and removed, and the front phosphosilicate glass is removed, and the back PN junction, peripheral PN junction and phosphosilicate glass layer are removed; and the back surface of the silicon wafer is polished to 3um to 8um.
  • the step S44 may include: completing the oxidation annealing according to the PERC process flow, preparing a 3nm to 20nm Al 2 O 3 rear passivation layer and a 100nm to 150nm rear silicon nitride anti-reflection passivation protective film layer by improving the formula on the back side , turn over the front side of the cell and deposit a silicon nitride anti-reflection passivation protective film layer with a film thickness of 74nm to 84nm by PECVD.
  • the beneficial effects of the present application at least include:
  • This application is based on the conventional high-efficiency PERC+SE battery structure.
  • the laser SE at the anti-break gate and the resistance-reducing laser SE at the top and bottom are added.
  • the laser parameters are consistent with the original ones, which can improve the battery performance. Fill and reduce series resistance, thereby improving battery efficiency;
  • Fig. 1 is the process flow diagram of the present application
  • Fig. 2 is a schematic diagram of SE laser doping pattern in the related art
  • Fig. 3 is one of the schematic diagrams of the SE laser doping pattern of the present application.
  • Figure 4 is the second schematic diagram of the SE laser doping pattern of the present application.
  • Figure 5 is the third schematic diagram of the SE laser doping pattern of the present application.
  • Figure 6 is the fourth schematic diagram of the SE laser doping pattern of the present application.
  • FIG. 7 is a cross-sectional view of a battery in the present application.
  • 1 Front side of silicon wafer; 2: Laser SE frame line; 3: Horizontal laser SE line; 4: Anti-broken grid; 5: Resistance reduction pattern; 11: Aluminum back field; 12: Silicon nitride layer; 13: Aluminum oxide layer; 14: P-type silicon substrate; 15: N-type phosphorus diffusion layer; 16: silicon oxide layer; 17: silicon nitride antireflection stack; 18: positive electrode; 19: back electrode; 20: laser SE doped Miscellaneous.
  • the application may include the following steps:
  • Step 1 Pretreatment of the silicon wafer: use strong acid or strong alkali to corrosively clean the surface of the silicon wafer to remove damage and make texture on both sides to form a triangular texture on the surface of the silicon wafer. Specifically: use HF, HNO 3 , H 2 SO 4 , KOH, NaOH, Na 2 SiO 3 , etc. and DI-water to make a chemical corrosion solution, and in order to optimize the process, add additives to the alkaline solution, such as isopropanol, (NH 4 ) 2 S 2 O 4 , N 2 H 4 ⁇ H 2 O, etc., for pre-cleaning and surface texturing of silicon wafers;
  • Step 2 Preparation of PN junction: high-temperature diffusion of phosphorus oxychloride on silicon wafers with high square resistance, specifically: depositing a doping source on the surface of the processed silicon substrate and performing thermal diffusion to prepare a PN junction; the doping source For phosphorus oxychloride and oxygen, under high-temperature diffusion conditions, the heating time is 30 minutes to 60 minutes to form a PN junction; during the diffusion process, POCl 3 is carried by nitrogen gas, and the nitrogen flow rate is 700sccm to 1000sccm, time: 20 minutes to 35 minutes, carrying capacity: POCl 3 15g to 25g, oxygen flow rate: 500sccm to 700sccm, time: 30 minutes to 45 minutes, temperature: 830°C to 870°C, to produce a PSG layer with low surface concentration, so that the diffusion thin layer
  • the square resistance is increased from 120 ⁇ /sq to 180 ⁇ /sq, and the standard deviation of the square resistance is within 5%;
  • Step 3 SE laser doping: make SE laser doping patterns, specifically: use laser irradiation with a wavelength of 532nm, and design SE laser doping patterns according to the front electrode pattern of the battery.
  • the SE laser doping patterns in related technologies are shown in the figure 2, in Fig. 2, a laser pattern is provided on the back of the silicon chip opposite to the front side 1 of the silicon chip, the laser SE frame line 2 and the horizontal laser SE line 3, compared with the related art, the present application adds a laser pattern to the laser pattern
  • the anti-broken grid 4 and the resistance-reducing pattern 5 shown in FIG. 3 are used to prevent the effects of broken grid and virtual printing, thereby improving the filling of the battery and reducing the series resistance.
  • the anti-broken grid 4 is evenly arranged on the horizontal laser line 3 and forms an angle ⁇ with the horizontal laser line 3, wherein, 10° ⁇ 90°, the anti-broken grid 4 can be continuous in the vertical direction It can also be arranged at intervals.
  • the so-called interval arrangement means that in the horizontal direction, the anti-broken grids 4 are arranged in a row, and a blank row is arranged between two adjacent rows of anti-broken grids 4 .
  • Several resistance-reducing patterns 5 are also arranged on the top and bottom of the SE laser-doped pattern of the PERC cell. Of course, several resistance-reducing patterns 5 can also be arranged only on the top or bottom of the SE laser-doped pattern.
  • Graphics 5 can be arranged continuously in the horizontal direction, and can also be arranged at intervals.
  • the so-called resistance-reducing graphics 5 are set at intervals in the horizontal direction.
  • the role of the resistance-reducing pattern 5 is to reduce the high square resistance to a low square resistance.
  • it is the resistance-reducing pattern 5 in this application. If it is in the screen version, it can be called In order to prevent hidden crack graphics, its function is to prevent cell cracks during and after screen printing.
  • the anti-breakage grid 4 can be set as an inclined line as shown in Figure 4.
  • the resistance-reducing figure 5 can be provided with multiple figures, including a rectangle as shown in Figure 3 and Figure 4, a harpoon or trapezoid as shown in Figure 5, a parallelogram as shown in Figure 6, or a triangle, a square (not shown in the figure). shown) and so on.
  • the included angle between one of the sides of the resistance-reducing graph 5 and the horizontal direction is ⁇ , wherein, when 10° ⁇ 90°, it has a better effect of preventing broken grids and false prints. In specific implementation, when 30° ⁇ ⁇ 60°, the effect is better, and when ⁇ is 45°, the effect is the best.
  • the angles of the anti-broken grid 4 and the resistance-reducing pattern 5 are variable, which is convenient for screen printing and solves the problems of easy grid-break and virtual printing, which lead to defective products.
  • This application adds anti-broken grid 4 and resistance-reducing pattern 5 in the new design of SE laser pattern to carry out SE to perform localized laser ablation. After the laser pattern is changed, the speed, power and virtual-to-real ratio of the laser are adjusted accordingly.
  • the irradiated area of the silicon wafer is doped with low concentration of phosphorus to form an N-type emitter, and a preliminary selective emitter junction structure is prepared.
  • this application introduces laser technology in diffusion.
  • the laser uses Nd:YAG laser with a wavelength of 532nm. /s, spot width 40um to 150um, laser frequency 10KHz to 5000KHz, pulse energy 10uJ/pulse to 120uJ/pulse, power per unit area 2J/cm2 to 80J/cm 2 .
  • Carry out reprocessing to silicon wafer specifically comprise step 4, step 5, step 6 and step 7, wherein,
  • Step 4 Polish, etch and remove glass impurities on the back of the silicon wafer; specifically: clean and polish the laser-doped silicon wafer, pass HF, HNO 3 and H 2 SO 4 mixed solution and subsequent alkali KOH/NaOH solution in the tank etches and removes the N-type layer on the back of the silicon wafer, removes the phosphosilicate glass on the front, removes the PN junction on the back, the peripheral PN junction and the phosphosilicate glass layer; and polishes the back surface of the silicon wafer to 3um to 8um deal with;
  • Step 5 forming a silicon nitride film on the front side of the silicon wafer by plasma chemical vapor deposition
  • Step 6 ALD (Atomic Layer Deposition, atomic layer deposition technology) or PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) deposition to form an aluminum oxide film on the back of the silicon wafer;
  • ALD Atomic Layer Deposition, atomic layer deposition technology
  • PECVD Plasma enhanced chemical vapor deposition method
  • Step 7 Form a silicon nitride film on the back of the silicon wafer by plasma chemical vapor deposition; specifically: complete the oxidation annealing according to the PERC process flow, and prepare a 3nm to 20nm Al 2 O 3 back passivation layer and a 100nm to 150nm Silicon nitride anti-reflection passivation protective film layer on the back, PECVD deposited silicon nitride anti-reflection passivation film layer with a film thickness of 74nm to 84nm on the front side of the cell;
  • Step 8 Groove the laser pattern on the back; specifically: on the silicon nitride coating layer on the back, design the laser groove pattern on the back of the high-resistance dense grid battery according to the screen-printed back electrode pattern, and make laser grooves;
  • Step 9 Screen printing and sintering; specifically: screen printing for the third and fourth passes using battery-specific screens, adding an alignment camera and upgrading the alignment software for the second, third, and fourth stages of screen printing to ensure front and rear grid lines Accurately printed on the SE area and the laser grooved area on the back, and matched with SE+PREC single crystal positive electrode paste, low-temperature rapid sintering and annealing to form a low-resistance battery;
  • Step 10 Testing and sorting, specifically: online testing of battery cell performance and EL, and completing efficiency classification and appearance inspection to meet customer requirements. For battery reliability verification, test positive electrode pulling force, PID, LID and other reliability tests.
  • FIG. 7 The cross-sectional view of the cell after preparation is shown in Figure 7, including an aluminum back field 11, a silicon nitride layer 12, an aluminum oxide layer 13, a P-type silicon substrate 14, an N-type phosphorus diffusion layer 15, a silicon oxide layer 16, a nitrogen Silicone anti-reflection stack 17, positive electrode 18, back electrode 19, laser SE doped layer 20, wherein an N-type phosphorus diffusion layer 15 is arranged on the top of the P-type silicon substrate 14, and an N-type phosphorus diffusion layer 15 is arranged on the top of the N-type phosphorus diffusion layer 15.
  • a silicon oxide layer 16, a silicon nitride anti-reflection layer 17 is arranged above the silicon oxide layer 16, a positive electrode 18 is arranged on the N-type phosphorus diffusion layer 15, an aluminum oxide layer 13 is arranged under the P-type silicon substrate 14, and the oxide An aluminum oxide layer 13 is arranged under the aluminum layer 13, a silicon nitride layer 12 is arranged under the aluminum oxide layer 13, an aluminum back field 11 is arranged under the silicon nitride layer 12, and a back electrode 19 is arranged on a P-type silicon substrate 14 , the laser SE doped layer 20 is disposed on the N-type phosphorus diffusion layer 15 .
  • the present application provides a SE laser doping pattern of a PERC cell, including several anti-broken grids, the anti-broken grids are evenly arranged on the horizontal laser SE line and form an angle ⁇ with the horizontal laser SE line, wherein, 10 ° ⁇ 90°.
  • the present application also provides a preparation method of the PERC battery.
  • an anti-broken grid is provided, and the anti-broken grid has an included angle with the horizontal laser SE line in the horizontal direction, which is convenient for screen printing, and solves the problem of easy broken grid and false printing in printing, which leads to defective products.
  • the SE laser doping pattern of the PERC cell and the PERC cell fabrication method of the present application are reproducible and can be used in various industrial applications.
  • the SE laser doping pattern of the PERC cell and the PERC cell preparation method of the present application can be used in the field of solar cell preparation.

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Abstract

本申请公开了一种PERC电池的SE激光掺杂图形，包括若干防断栅，所述防断栅在水平激光SE线上均匀排布且与水平激光SE线呈一夹角α，其中，10°≤α≤90°。本申请同时还提供一种PERC电池的制备方法。本申请通过设置防断栅，并且防断栅与水平激光SE线在水平方向有一夹角，便于丝网印刷，以解决印刷容易断栅和虚印，进而导致产品不良的问题。

Description

一种PERC电池的SE激光掺杂图形和PERC电池制备方法
相关申请的交叉引用
本申请要求于2021年11月05日提交中国国家知识产权局的申请号为202111305590.5、名称为“一种PERC电池的SE激光掺杂图形和PERC电池制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于太阳能电池制备领域，更具体地说，涉及一种PERC电池的SE激光掺杂图形和PERC电池制备方法。
背景技术
晶体硅太阳能电池在制造过程中，特别是高效PERC(Passivated Emitter and Rear Cell，发射极和背面钝化电池)+SE(选择极发射SelectiveEmitter)电池制作过程中，使用了激光SE技术，此技术的应用是在硅片扩散为高方阻，表面有一层厚的磷硅玻璃，激光打在硅片扩散面磷硅玻璃上，由于短暂的热作用使表面的磷硅玻璃磷扩散进入硅表面，形成磷重掺杂，即P++，印刷过程中P++处与金属接触形成欧姆接触，减少接触电阻，提高电池效率；未经过激光区域为轻掺杂，方阻较高，未有相匹配的浆料，接触性差，印刷浆料接触电阻较大，效率会偏低。
申请公布日为2020年5月19日，申请公布号为CN111180530A，专利名称为一种选择性发射极电池的制备方法的中国专利公开了一种技术方案，包括掺杂源扩散形成PN结和激光掺杂制作选择性发射极的步骤，其特征在于，所述激光掺杂制作选择性发射极的步骤中通过改变照射在硅片上欲金属化的区域激光的能量和光斑大小，使区域内所掺杂的元素富集，形成选择性发射极。该发明通过调整激光的能量和光斑大小，减小激光对电池片的损伤面积，实现SE在栅线接触区域和非接触区域实现不同的掺杂区，同时提升电池效率。
授权公告日为2021年7月27日，授权公告号为CN213798653U，专利名称为一种PERC电池正面DUP副栅对位结构的中国专利公开了一种技术方案，包括设置在电池正面上的SE激光MARK点和三道印刷图形，三道印刷图形包括三道主栅和对位孔，SE激光MARK点与所述三道印刷图形不重合。所述SE激光MARK点位于所述三道印刷图形之外。所述三道印刷图形是三道主栅，即对位孔在三道印刷网版确认位置后被遮挡而不会印刷在电池上。该实用新型的三道印刷图形包括三道主栅和对位孔，SE激光MARK点与三道印刷图形不重合，即为SE激光MARK点不被三道主栅和对位孔遮挡，印刷时，三道主栅和四道副栅均抓取SE激光MARK点，从而防止三道印刷对四道副栅印刷造成干扰，使得副栅印 刷精准对位，从而解决EL雾状发黑问题。
此外，相关技术中在正面细栅网版设计采用防断栅和降阻图形设计，但激光SE图形只有水平细栅设计，未有在防断栅线和鱼叉区域打激光SE，但此处丝网印刷有正银浆料，接触处是高主阻，表面浓度低未能形成良好的欧姆接触，接触电阻大，进而影响电池效率的进一步提升。
发明内容
1.要解决的问题
针对相关技术中生产线在激光SE设计的图形的某些区域存在的接触电阻大，复合相对较高，导致电池填充较低，串阻增加，进而影响效率的进一步提升的问题，本申请提供一种PERC电池的SE激光掺杂图形和PERC电池的制备方法。
2.技术方案
为了解决上述问题，本申请所采用的技术方案如下：一种PERC电池的SE激光掺杂图形，可以包括若干防断栅，所述防断栅在水平激光SE线上均匀排布且与水平激光SE线呈一夹角α，其中，10°≤α≤90°，在所述PERC电池的SE激光掺杂图形的顶部和/或底部还设置有若干降阻图形，所述降阻图形的一条边与水平方向的夹角为β，其中，10°≤β≤90°。本技术方案通过设置防断栅和降阻图形，并且防断栅与水平激光SE线在水平方向有一夹角，降阻图形的一条边与水平方向呈一夹角，便于丝网印刷，能够更好地解决印刷容易断栅和虚印，进而导致产品不良的问题。
可选地，所述防断栅可以在竖直方向上间隔设置。
可选地，所述防断栅可以在水平方向上排成一行，相邻两行防断栅之间设置有一空行。
可选地，所述降阻图形可以在竖直方向上的长度为0.5mm至20mm。
可选地，所述防断栅与水平激光线的夹角α可以为30°≤α≤60°，所述降阻图形的一条边与水平方向的夹角β可以为30°≤β≤60°。
可选地，所述降阻图形可以在水平方向上间隔设置。
可选地，所述降阻图形可以设置为多种图形，所述图形包括长方形、鱼叉形或梯形、平行四边形、三角形、或正方形。
本申请还包括一种PERC电池制备方法，可以包括以下步骤：
S1：对硅片进行预处理；
S2：制备P-N结；
S3：SE激光掺杂；
S4：对硅片进行再处理；
S5：激光开槽；
S6：对硅片背面进行背电极和背电场的印刷；
S7：烧结测试；
其中，步骤S3具体为：在激光图形中设置防断栅，所述防断栅在水平激光SE线上均匀排布且与水平激光SE线呈一夹角α，其中，10°≤α≤90°。
可选地，在所述步骤S3中的激光图形的顶部和/或底部还设置有若干降阻图形，所述降阻图形在水平方向上间隔设置，所述降阻图形的一条边与水平方向的夹角为β，其中，10°≤β≤90°。
可选地，所述步骤S3中的激光器的光斑为方形光斑，光斑宽度40um至150um，激光频率10KHz至5000KHz，脉冲能量为10J/脉冲至120uJ/脉冲，单位面积功率为2J/cm 2至80J/cm 2。
可选地，所述步骤S1可以包括：对硅片表面进行清洗，使硅片表面形成三角形绒面。
可选地，所述步骤S2可以包括：将经过步骤S1加工得到的硅片表面进行淀积掺杂源并进行热扩散制备P-N结；所述掺杂源为三氯氧磷和氧气。
可选地，所述步骤S4可以包括：
S41、对硅片背面进行抛光、刻蚀和去除杂质处理；
S42、通过等离子体化学气相沉积使硅片正面形成氮化硅薄膜；
S43、通过原子层沉积技术或等离子体增强化学的气相沉积法沉积使硅片背面形成氧化铝薄膜；
S44、通过等离子体化学气相沉积使硅片背面形成氮化硅薄膜。
可选地，所述步骤S41可以包括：对激光掺杂后的硅片进行清洗和背面抛光，通过HF、HNO 3及H 2SO 4混合溶液和后续碱槽中KOH/NaOH溶液将硅片背面N型层腐蚀去除，并将正面的磷硅玻璃去除，去除背面PN结、周边PN结和磷硅玻璃层；并对硅片背表面进行3um至8um抛光处理。
可选地，所述步骤S44可以包括：按PERC工艺流程完成氧化退火，背面改进配方制备3nm至20nm的Al 2O 3背钝化层及100nm至150nm背面氮化硅减反射钝化保护膜层，翻转电池片正面PECVD沉积膜厚74nm至84nm的氮化硅减反射钝化保护膜层。
3.有益效果
相比于相关技术，本申请的有益效果至少包括：
(1)本申请基于常规高效PERC+SE电池结构，在SE激光掺杂图形上，增加防断栅处激光SE、顶部和底部的降阻激光SE，激光参数与原保持一致，能提升电池的填充和降低串阻，进而提升电池效率；
(2)本申请结构简单，设计合理，易于制造。
附图说明
图1为本申请的工艺流程图；
图2为相关技术中SE激光掺杂图形示意图；
图3为本申请的SE激光掺杂图形示意图之一；
图4为本申请的SE激光掺杂图形示意图之二；
图5为本申请的SE激光掺杂图形示意图之三；
图6为本申请的SE激光掺杂图形示意图之四；
图7为本申请中的电池截面图。
图中：1：硅片正面；2；激光SE边框线；3：水平激光SE线；4：防断栅；5：降阻图形；11：铝背场；12：氮化硅层；13：氧化铝层；14：P型硅衬底；15：N型磷扩散层；16：氧化硅层；17：氮化硅减反层叠；18：正电极；19：背电极；20：激光SE掺杂层。
具体实施方式
下面结合具体实施例对本申请进一步进行描述。
如图1所示，本申请可以包括以下步骤：
步骤1：对硅片进行预处理：利用强酸或强碱对硅片表面进行腐蚀性清洗去损伤和双面制绒，使硅片表面形成三角形绒面，具体为：使用HF、HNO 3、H 2SO 4、KOH、NaOH、Na 2SiO 3等和DI-water制成化学腐蚀溶液，同时为了优化工艺在碱溶液中加入添加剂，如异丙醇、(NH 4) 2S 2O 4、N 2H 4·H 2O等，对硅片进行前清洗和表面制绒；
步骤2：制备P-N结：对硅片三氯氧磷高温扩散高方阻，具体为：将加工得到的硅衬底表面进行淀积掺杂源并进行热扩散制备P-N结；所述掺杂源为三氯氧磷和氧气，在高温扩散条件下时，加热时间30分钟至60分钟，形成P-N结；在扩散过程中，POCl 3采用氮气携带，流量携带氮气流量：700sccm至1000sccm，时间：20分钟至35分钟，携带量：POCl 315g至25g，氧气流量：500sccm至700sccm，时间：30分钟至45分钟，温度：830℃至870℃，制作出低表面浓度的PSG层，使扩散薄层方块电阻达到120Ω/sq提高到180Ω/sq，方块电阻标准差在5％以内；
步骤3：SE激光掺杂：制作SE激光掺杂图形，具体为：使用波长为532nm的激光辐 照，根据电池正面电极图形设计SE激光掺杂图形，相关技术中的SE激光掺杂图形如图2所示，图2中，在和硅片正面1相对的硅片背面设置有激光图形，激光SE边框线2和水平激光SE线3，和相关技术相比，本申请在激光图形中增加了如图3所示的防断栅4和降阻图形5，以防止断栅和虚印的效果，进而提升电池的填充和降低串阻。
具体实施时，防断栅4在水平激光线3上均匀排布且与水平激光线3呈一夹角α，其中，10°≤α≤90°，防断栅4在竖直方向上可连续设置，也可间隔设置，所谓的间隔设置指的是在水平方向上，防断栅4排成一行，相邻两行防断栅4之间设置有一空行。在所述PERC电池的SE激光掺杂图形的顶部和底部还设置有若干降阻图形5，当然，也可以只在SE激光掺杂图形的顶部或底部设置若干降阻图形5，所述降阻图形5在水平方向上可连续设置，也可间隔设置，所谓的降阻图形5在水平方向行间隔设置指的是在相邻的两个降阻图形5不接触，当降阻图形5在竖直方向上的长度为0.5mm至20mm时，具有更好的效果。在本申请中，降阻图形5的作用系将高方阻降为低方阻，本领域技术人员应当理解，在本申请中其为降阻图形5，如果在丝网网版中，可以称为防隐裂图形，其作用是在丝网印刷过程中和印刷后防止电池片隐裂。
具体实施时，可将防断栅4设置成如图4所示的倾斜线，一般来说，当防断栅4与水平激光线3的夹角α为10°≤α≤90°时，有较好的防止断栅和虚印的效果，可选地，当防断栅4与水平激光线3的夹角α为30°≤α≤60°时，效果更好，而当α为45°时，效果最好。降阻图形5可设置多种图形，包括图3和图4所示的长方形、如图5所示的鱼叉形或梯形、如图6所示的平行四边形，或者三角形、正方形(图中未示出)等等。降阻图形5的其中一条边与水平方向的夹角为β，其中，10°≤β≤90°时，有较好的防止断栅和虚印的效果，具体实施时，当30°≤β≤60°时，效果更好，而当β为45°时，效果最好。在本申请中，防断栅4和降阻图形5的角度可变，便于丝网印刷，以解决印刷容易断栅和虚印，进而导致产品不良的问题。
本申请在SE激光图形新设计增加防断栅4和降阻图形5处进行SE，进行激光局域烧蚀，激光图形改变后，对激光的速率、功率和虚实比做相应调整，在所述硅片的辐照区实现磷的低浓度掺杂而形成N-type发射极，制备得到初步的选择性发射结结构。具体实施时，本申请在扩散引入激光工艺，激光器选用Nd：YAG激光器，波长532nm，激光器安装整形镜，光斑为方形光斑，有利于减少激光对硅片的损伤，扫描速度为10mm/s至100000mm/s，光斑宽度40um至150um，激光频率10KHz至5000KHz，脉冲能量为10uJ/脉冲至120uJ/脉冲，单位面积功率为2J/cm2至80J/cm 2。
对硅片进行再处理：具体包括步骤4、步骤5、步骤6和步骤7，其中，
步骤4：对硅片背面进行抛光、刻蚀和去除玻璃杂质处理；具体为：对激光掺杂后的硅片进行清洗和背面抛光，通过HF、HNO 3及H 2SO 4混合溶液和后续碱槽中KOH/NaOH溶液将硅片背面N型层腐蚀去除，并将正面的磷硅玻璃去除，去除背面PN结、周边PN结和磷硅玻璃层；并对硅片背表面进行3um至8um抛光处理；
步骤5：通过等离子体化学气相沉积使硅片正面形成氮化硅薄膜；
步骤6：通过ALD(Atomic Layer Deposition，原子层沉积技术)或者PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积法)沉积使硅片背面形成氧化铝薄膜；
步骤7：通过等离子体化学气相沉积使硅片背面形成氮化硅薄膜；具体为：按PERC工艺流程完成氧化退火，背面改进配方制备3nm至20nm的Al 2O 3背钝化层及100nm至150nm背面氮化硅减反射钝化保护膜层，翻转电池片正面PECVD沉积膜厚74nm至84nm的氮化硅减反射钝化保护膜层；
步骤8：背面激光图形开槽；具体为：在背面氮化硅镀膜层上，根据丝网印刷背面电极图形设计高阻密栅电池背面激光开槽图形，并做激光刻槽；
步骤9：丝网印刷并烧结；具体为：丝网印刷三、四道使用电池专用网版，在网印二、三、四道增加对位相机、升级对位软件，确保正、背面栅线精确印刷到SE区、背面激光开槽区，同时匹配SE+PREC单晶正电极专用浆料，低温快速烧结退火形成低电阻电池；
步骤10：测试并分选，具体为：在线测试电池的电池片电性能和EL，完成效率分档及外观检验，满足客户要求。对电池可靠性验证，测试正电极拉力、PID、LID等可靠性测试。
表1
项目 计数 Eta Voc Isc FF Rsh Rse IRev2
BL 4880 23.253 0.6862 11.401 81.54 263.3 0.00145 0.1433
实验组 7614 23.281 0.6858 11.398 81.68 314.8 0.00142 0.1302
通过上述结构进行实验得到结果如表1所示，本申请可以有效提升电池填充因子和降低串阻，最终实现提升电池光电转换效率，增加PERC电池在未来光伏市场中竞争力，降低PERC电池的度电成本。
制备完成后的电池截面图如图7所示，包括铝背场11、氮化硅层12、氧化铝层13、P型硅衬底14、N型磷扩散层15、氧化硅层16、氮化硅减反层叠17、正电极18、背电极19、激光SE掺杂层20，其中P型硅衬底14的上方设置有N型磷扩散层15，N型磷扩散层15的上方设置有氧化硅层16，氧化硅层16的上方设置有氮化硅减反层叠17，正电极18设置 在N型磷扩散层15上，氧化铝层13设置在P型硅衬底14的下方，氧化铝层13的下方设置有氧化铝层13，氧化铝层13的下方设置有氮化硅层12，氮化硅层12的下方设置有铝背场11，背电极19设置在P型硅衬底14上，激光SE掺杂层20设置在N型磷扩散层15上。
工业实用性
本申请提供了一种PERC电池的SE激光掺杂图形，包括若干防断栅，所述防断栅在水平激光SE线上均匀排布且与水平激光SE线呈一夹角α，其中，10°≤α≤90°。本申请同时还提供一种PERC电池的制备方法。本申请通过设置防断栅，并且防断栅与水平激光SE线在水平方向有一夹角，便于丝网印刷，以解决印刷容易断栅和虚印，进而导致产品不良的问题。
此外，可以理解的是，本申请的PERC电池的SE激光掺杂图形和PERC电池制备方法是可以重现的，并且可以用在多种工业应用中。例如，本申请的PERC电池的SE激光掺杂图形和PERC电池制备方法可以用于太阳能电池制备领域。

Claims (15)

  1. 一种PERC电池的SE激光掺杂图形，其特征在于：包括若干防断栅，所述防断栅在水平激光SE线上均匀排布且与水平激光SE线呈一夹角α，其中，10°≤α≤90°，在所述PERC电池的SE激光掺杂图形的顶部和/或底部还设置有若干降阻图形，所述降阻图形的一条边与水平方向的夹角为β，其中，10°≤β≤90°。
  2. 根据权利要求1所述的PERC电池的SE激光掺杂图形，其特征在于：所述防断栅在竖直方向上间隔设置。
  3. 根据权利要求1所述的PERC电池的SE激光掺杂图形，其特征在于：所述防断栅在水平方向上排成一行，相邻两行防断栅之间设置有一空行。
  4. 根据权利要求1至3中任一项所述的PERC电池的SE激光掺杂图形，其特征在于：所述降阻图形在竖直方向上的长度为0.5mm-20mm。
  5. 根据权利要求1至3中任一项所述的PERC电池的SE激光掺杂图形，其特征在于：所述防断栅与水平激光线的夹角α为30°≤α≤60°，所述降阻图形的一条边与水平方向的夹角β为30°≤β≤60°。
  6. 根据权利要求1至5中任一项所述的PERC电池的SE激光掺杂图形，其特征在于：所述降阻图形在水平方向上间隔设置。
  7. 根据权利要求1至6中任一项所述的PERC电池的SE激光掺杂图形，其特征在于：所述降阻图形设置为多种图形，所述图形包括长方形、鱼叉形或梯形、平行四边形、三角形、或正方形。
  8. 一种PERC电池制备方法，其特征在于：包括以下步骤：
    S1：对硅片进行预处理；
    S2：制备P-N结；
    S3：SE激光掺杂；
    S4：对硅片进行再处理；
    S5：激光开槽；
    S6：对硅片背面进行背电极和背电场的印刷；
    S7：烧结测试；
    其中，步骤S3具体为：在激光图形中设置防断栅，所述防断栅在水平激光SE线上均匀排布且与水平激光SE线呈一夹角α，其中，10°≤α≤90°。
  9. 根据权利要求8所述的PERC电池制备方法，其特征在于：在所述步骤S3中的激 光图形的顶部和/或底部还设置有若干降阻图形，所述降阻图形在水平方向上间隔设置，所述降阻图形的一条边与水平方向的夹角为β，其中，10°≤β≤90°。
  10. 根据权利要求8或9所述的PERC电池制备方法，其特征在于：所述步骤S3中的激光器的光斑为方形光斑，光斑宽度40um至150um，激光频率10KHz至5000KHz，脉冲能量为10uJ/脉冲至120uJ/脉冲，单位面积功率为2J/cm2至80J/cm 2。
  11. 根据权利要求8至10中任一项所述的PERC电池制备方法，其特征在于：所述步骤S1包括：对硅片表面进行清洗，使硅片表面形成三角形绒面。
  12. 根据权利要求11所述的PERC电池制备方法，其特征在于：所述步骤S2包括：将经过步骤S1加工得到的硅片表面进行淀积掺杂源并进行热扩散制备P-N结；所述掺杂源为三氯氧磷和氧气。
  13. 根据权利要求12所述的PERC电池制备方法，其特征在于：所述步骤S4包括：
    S41、对硅片背面进行抛光、刻蚀和去除杂质处理；
    S42、通过等离子体化学气相沉积使硅片正面形成氮化硅薄膜；
    S43、通过原子层沉积技术或等离子体增强化学的气相沉积法沉积使硅片背面形成氧化铝薄膜；
    S44、通过等离子体化学气相沉积使硅片背面形成氮化硅薄膜。
  14. 根据权利要求13所述的PERC电池制备方法，其特征在于：所述步骤S41包括：对激光掺杂后的硅片进行清洗和背面抛光，通过HF、HNO 3及H 2SO 4混合溶液和后续碱槽中KOH/NaOH溶液将硅片背面N型层腐蚀去除，并将正面的磷硅玻璃去除，去除背面PN结、周边PN结和磷硅玻璃层；并对硅片背表面进行3um至8um抛光处理。
  15. 根据权利要求13或14所述的PERC电池制备方法，其特征在于：所述步骤S44包括：按PERC工艺流程完成氧化退火，背面改进配方制备3nm至20nm的Al 2O 3背钝化层及100nm至150nm背面氮化硅减反射钝化保护膜层，翻转电池片正面PECVD沉积膜厚74nm至84nm的氮化硅减反射钝化保护膜层。
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