WO2015027269A1

WO2015027269A1 - Photovoltaic device with selective emitter structure and method of producing same

Info

Publication number: WO2015027269A1
Application number: PCT/AU2013/000990
Authority: WO
Inventors: Andres CUEVAS; Daniel Harold MACDONALD; Kylie Rose CATCHPOLE
Original assignee: The Australian National University; Changzhou Trina Solar Energy Co.
Priority date: 2013-09-02
Filing date: 2013-09-02
Publication date: 2015-03-05

Abstract

A method of producing a photovoltaic device from a semiconductor substrate, the method including: forming a doped emitter layer by introducing a dopant species into a surface of the semiconductor substrate; etching selected regions of the doped emitter layer to remove at least a portion of the doped emitter layer in each selected region; forming on first unetched regions of the doped emitter layer a plurality of parallel elongate finger electrodes to collect charge carriers from the doped emitter layer, each pair of adjacent ones of said electrodes defining a corresponding photon collecting region therebetween; wherein the photon collecting regions include the etched regions and second unetched regions of the doped emitter layer, the etched regions having a lower charge carrier recombination rate than the unetched regions and constituting a majority of each photon collecting region, and (i) the second unetched regions being arranged between the etched regions to define conducting paths to the finger electrodes and/or (ii) the etched regions being configured to define a non-planar optically active structure that acts as an anti-reflection structure and/or traps light within the device.

Description

PHOTOVOLTAIC DEVICE WITH

SELECTIVE EMITTER STRUCTURE AND METHOD OF PRODUCING SAME

TECHNICAL FIELD

The present invention relates to photovoltaic devices such as solar cells, and in particular to selective emitter photovoltaic devices and methods for producing same.

BACKGROUND

Commercial photovoltaic devices or solar cells are fabricated by introducing electrically active impurity or 'dopant* atoms into the surface of a semiconductor wafer to form a 'doped' surface layer of opposite polarity type to the polarity of the wafer itself. Typically, the starting wafer is a p-type silicon wafer, and the dopant is an n-type dopant such as phosphorus, thereby forming a large area pn junction between the n-type surface layer and the p-type substrate.

Some of the photons incident upon the surface of the solar cell generate electron-hole pairs that form an electric current that can be conducted from the solar cell via electrical contacts formed on its front and rear surfaces. However, there is a trade-off between the need to efficiently conduct electrical current from the largest possible area of the wafer surface and the need to reduce shadowing of the wafer surface from the incident photons that generate that current.

To balance these competing requirements, the electrical contacts to the doped surface layer of the wafer 100 are generally in the form a rectangular grid or mesh of mutually parallel, elongate, fine and high aspect ratio 'finger' electrodes 102 interconnected by one or more (typically two or three per wafer) larger elongate bus bar electrodes 104 orthogonal to the 'finger' electrodes 102, as shown schematically in Figures 1 and 2. The rectangular regions 106 bounded on two opposite sides by 'finger' electrodes 102 and on at least one of the other two sides by a corresponding busbar 104 can be considered to constitute the 'active' or 'photon collecting' regions of the device. In order to efficiently conduct electrical current to the electrodes and to form good Ohmic contacts to these electrodes, it is generally desirable for the doped surface layer to have a high concentration of the dopant species near the wafer surface and a low sheet resistance. However, high concentrations of dopant species also have the undesirable effect of increasing the recombination of the photon-generated electron-hole pairs, thereby degrading the efficiency of the device.

Consequently, it is generally desirable to minimise recombination in the photon collecting regions between the electrodes by configuring the doped surface layer in those regions to have a relatively high sheet resistance (but only up to about 200 Ω/D to avoid excessive resistive losses) and also to coat these regions with a passivating surface layer such as silicon nitride (SiN) to reduce recombination at the wafer surface. Conversely, to reduce recombination in the regions under the electrodes while still forming good contacts, it is desirable to form a relatively deep and high concentration doped layer having a low sheet resistance.

However, to reduce manufacturing costs, most commercially available silicon solar cells have a doped surface layer formed by a single thermal diffusion step, typically a phosphorus diffusion into a p-type silicon wafer, producing a relatively high dopant concentration at the wafer surface so that device metallisation can be performed by low cost screen printing of silver paste. However, such a high dopant concentration results in significant recombination loss and an inability to perform good surface passivation, thus limiting the voltage and current produced by the device. In the case of a phosphorus diffusion, the most heavily doped part of the diffused region, typically a few tens of nanometers deep, is commonly referred to as the "dead layer" due to the high recombination losses that occur therein.

To address the competing doping requirements of the contacted and uncontacted regions, photovoltaic devices have been developed in which the doping concentration in the surface layer is relatively high underneath the electrodes and relatively low elsewhere over the majority of the device surface, a structure referred to in the art as a 'double emitter' or 'selective emitter' structure. With some dopant species, including phosphorus, this hybrid doping configuration also provides the additional benefit of the highly doped regions gettering unwanted metallic impurities from the photon collecting regions, thereby decreasing recombination in those regions and thus further improving device performance.

Some of the technologies that are being pursued use lasers to selectively create highly doped regions underneath the metal fingers, while the rest of the surface has a lightly to moderately doped diffusion. In some cases, laser doping has been used to create so called "semiconductor fingers" that run perpendicular to the finger electrodes. However, such technologies are generally inconvenient, expensive, and non-standard.

It is desired, therefore, to provide a photovoltaic device and a method of producing a photovoltaic device from a semiconductor substrate that alleviate one or more difficulties of the prior art, or that at least provide a useful alternative.

SUMMARY

Some embodiments of the present invention provide a method of producing a photovoltaic device from a semiconductor substrate, the method including:

forming a doped emitter layer by introducing a dopant species into a surface of the semiconductor substrate;

etching selected regions of the doped emitter layer to remove at least a portion of the doped emitter layer in each selected region;

forming on first unetched regions of the doped emitter layer a plurality of parallel elongate finger electrodes to collect charge carriers from the doped emitter layer, each pair of adjacent ones of said electrodes defining a corresponding photon collecting region therebetween;

wherein the photon collecting regions include the etched regions and second unetched regions of the doped emitter layer, the etched regions having a lower charge carrier recombination rate than the unetched regions and constituting a majority of each photon collecting region, and the second unetched regions being arranged between the etched regions to define conducting paths to the finger electrodes.

wherein the photon collecting regions include the etched regions and second unetched regions of the doped emitter layer, the etched regions having a lower charge carrier recombination rate than the unetched regions and constituting a majority of each photon collecting region, and at least one of:

(i) the second unetched regions are arranged between the etched regions to define conducting paths to the finger electrodes; and

(ii) the etched regions of the doped emitter layer are configured to define a non- planar optically active structure that acts as an anti-reflection structure and/or traps light within the device.

In some embodiments, the second unetched regions are arranged between the etched regions to define conducting paths to the finger electrodes.

In some embodiments, the etched regions of the doped emitter layer define a non-planar optically active structure that acts as an anti-reflection structure and/or traps light within the device. In some embodiments, the method includes forming at least one busbar interconnecting said finger electrodes.

In some embodiments, the dopant species is introduced into the surface of the semiconductor substrate by thermal diffusion.

In some embodiments, the method includes forming an etch mask on the doped emitter layer so that only the selected regions of the doped emitter layer are exposed through the etch mask.

In some embodiments, each of the unetched regions between the etched regions defines a continuous conducting path to both of the corresponding finger electrodes.

In some embodiments, said etching removes substantially all of the doped emitter layer in each selected region.

wherein the etched and unetched regions define a selective emitter structure of the photovoltaic device, the unetched regions including a plurality of parallel elongate unetched contact regions for forming elongate finger electrodes thereon and defining photon collecting regions therebetween, the photon collecting regions including the etched regions and other unetched regions of the doped emitter layer to conduct charge carriers from the etched regions to the elongate unetched contact regions.

In some embodiments, the etched regions are in the form of mutually spaced and mutually parallel elongate troughs. In some embodiments, the elongate troughs define corresponding unetched elongate regions of the doped emitter layer therebetween, each of the unetched elongate regions of the doped emitter layer providing a conducting path to at least one of the corresponding pair of finger electrodes.

In some embodiments, each of the unetched elongate regions of the doped emitter layer provides a conducting path to the corresponding pair of finger electrodes. In some embodiments, the etched and unetched elongate regions are parallel to one or more bus bars of the photovoltaic device and orthogonal to the finger electrodes.

Some embodiments of the present invention provide a photovoltaic device, including: a semiconductor substrate having a doped emitter layer; and

a plurality of parallel elongate finger electrodes disposed on the doped emitter layer, each pair of adjacent ones of said electrodes defining a corresponding photon collecting region therebetween, the finger electrodes being arranged to collect charge carriers generated in the photon collecting regions by photons incident thereupon;

wherein at least a portion of the doped emitter layer in each of a plurality of regions in each photon collecting region has been removed to reduce the recombination of charge carriers therein, the remaining regions of the doped emitter layer in each photon collecting region being configured to provide conducting paths to at least one of the corresponding pair of finger electrodes. Some embodiments of the present invention provide a photovoltaic device, including: a semiconductor substrate having a doped emitter layer; and

a plurality of parallel elongate finger electrodes disposed on the doped emitter layer, each pair of adjacent ones of said electrodes defining a corresponding photon collecting region therebetween, the finger electrodes being arranged to collect charge carriers generated in the photon collecting regions by photons incident thereupon; wherein at least a portion of the doped emitter layer in each of a plurality of regions in each photon collecting region has been removed to reduce the recombination of charge carriers therein, and at least one of:

(i) the remaining regions of the doped emitter layer in each photon collecting region being are configured to provide conducting paths to at least one of the corresponding pair of finger electrodes; and

(ii) the etched and unetched regions are configured to define a non-planar optically active structure that acts as an anti-reflection structure and/or traps light within the device.

In some embodiments, the remaining regions of the doped emitter layer in each photon collecting region are configured to provide conducting paths the corresponding pair of finger electrodes. In some embodiments, the remaining regions of the doped emitter layer in each photon collecting region are in the form of mutually spaced and mutually parallel elongate ridges.

In some embodiments, the elongate, ridges are interleaved with corresponding elongate troughs therebetween.

In some embodiments, the elongate ridges and troughs are parallel to one or more bus bars of the photovoltaic device and orthogonal to the finger electrodes.

wherein the photon collecting regions include the etched regions of the doped emitter layer, the etched regions having a lower charge carrier recombination rate than the unetched regions, and defining a non-planar optically active structure that acts as an anti- reflection structure and/or traps light within the device.

In some embodiments, the photon collecting regions include the etched regions and second unetched regions of the doped emitter layer, the etched regions having a lower charge carrier recombination rate than the second unetched regions, and constituting a majority of each photon collecting region, and the second unetched regions being arranged between the etched regions to define conducting paths to the finger electrodes.

In some embodiments, the method includes forming at least one busbar interconnecting said finger electrodes.

In some embodiments, the dopant species is introduced into the surface of the semiconductor substrate by thermal diffusion. In some embodiments, the method includes forming an etch mask on the doped emitter layer so that only the selected regions of the doped emitter layer are exposed through the etch mask.

In some embodiments, the method includes said etching removes substantially all of the doped emitter layer in each selected region. Some embodiments of the present invention provide a method of producing a photovoltaic device from a semiconductor substrate, the method including: forming a doped emitter layer by introducing a dopant species into a surface of the semiconductor substrate;

wherein the etched and unetched regions define a selective emitter structure of the photovoltaic device, the unetched regions including a plurality of parallel elongate unetched contact regions for forming elongate finger electrodes thereon and defining photon collecting regions therebetween, the photon collecting regions including the etched regions and having a non-planar optically active surface that acts as an anti-reflection structure and/or traps light within the device.

In some embodiments, the unetched regions include other unetched regions of the doped emitter layer to conduct charge carriers from the etched regions to the elongate unetched contact regions.

In some embodiments, the etched regions are in the form of an array of mutually spaced tubs. In some embodiments, the tubs define corresponding unetched regions of the doped emitter layer therebetween, the unetched elongate regions of the doped emitter layer providing conducting paths to at least one of the corresponding pair of finger electrodes. In some embodiments, the unetched regions of the doped emitter layer provide conducting paths to the corresponding pair of finger electrodes.

In some embodiments, the etched regions are substantially circular in plan view. In some embodiments, the etched regions have microscale or nanoscale dimensions in plan view.

wherein at least a portion of the doped emitter layer in each of a plurality of mutually spaced etched regions in each photon collecting region has been removed to reduce the recombination of charge carriers therein relative to unetched regions disposed between the etched regions, and the etched and unetched regions define a non-planar optically active structure that acts as an anti-reflection structure and/or traps light within the device. In some embodiments, the unetched are configured to provide conducting paths to the corresponding pair of finger electrodes.

Described herein are methods of producing a photovoltaic device from a semiconductor substrate, involving deposition of an etch mask layer with microscale and/or nanoscale features, deposited after the formation of a doped emitter layer on the substrate. A shallow etch of the semiconductor then selectively removes at least the upper, most heavily doped portion of the emitter layer in the exposed regions of the semiconductor substrate, while keeping a deep, heavy diffusion underneath the areas where metal contacts are to be formed.

The etching can be performed so that unetched regions remain in the photon collecting regions of the device to highly conducting pathways or channels to facilitate the conduction of electrical current to electrodes of the device. By removing some of the highly doped surface layer in the etched regions, surface passivation can be made more effective, and global recombination losses can be reduced. At the same time, the microscale and/or nanoscale topographical surface features produced by etching constitute an optically active structure that, when combined with the deposition of an anti-reflection coating such as SiN, reduces light reflection and enhances light absorption. The process can also be beneficial when applied to the rear of a photovoltaic device or solar cell to assist with current transport and reduce recombination while also incorporating light trapping.

These are very important functions in the development of advanced, high performance solar cells, particularly of silicon solar cells. For example, nanoimprinting is an emerging technology used to create patterns that, together with subsequent etching of the silicon, can create features with sizes in the range of a few hundreds of nanometers ( l OOnm- l OOOnm). The methods described herein extend the use of nano-structuring to accomplish not just optical functions but also electronic functions in a photovoltaic or solar cell device.

Furthermore, the etch mask is configured so that no etching occurs in the regions where the metal contact grid of the solar cell is to be deposited. This retains the deep, heavy doping or diffusion underneath the metal contacts, thus minimising recombination in those areas of the device surface and facilitating the formation of a good electrical contact between the metal and the semiconductor.

The dopant diffusion, typically phosphorus in the case of a p-type silicon substrate, is used to create the pn junction in a solar cell and also provides a "gettering" function to reduce the adverse effects of any metallic impurities that may be present in the silicon wafer, particularly in the case of multicrystalline silicon. This gettering function is best accomplished by using relatively heavy diffusions. With the methods described herein, more effective removal of bulk impurities by gettering can be accomplished since the described methods allow the use of heavier initial diffusions than would otherwise be practical.

In addition to the front side of a photovoltaic device or solar cell, the same methods can be applied to the rear side of such devices to further optimise light trapping in these devices and their electronic performance. The methods are generally applicable to both n-type and p-type substrates. BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of the present invention are hereinafter described, by way of example only, with reference to the accompanying drawings, wherein:

Figure 1 is a schematic plan view of a generic solar cell, illustrating the general arrangement of busbars and elongate finger electrodes extending therefrom;

Figure 2 is an enlarged view of a portion of the generic solar cell of Figure 1 , showing a single vertical bus bar and horizontal elongate finger electrodes extending therefrom;

Figure 3 is a flow diagram of a method of producing a photovoltaic device from a semiconductor substrate in accordance with an aspect of the present invention;

Figures 4 to 10 are schematic side views of a semiconductor substrate being processed to form a photovoltaic device using a first method as shown in Figure 3;

Figure 1 1 is a graph showing the concentration of phosphorus dopant as a function of depth into a silicon substrate for thermally-assisted diffusions at temperatures of 850°C, 900°C, and 950°C for 30 minutes;

Figures 12 is a schematic plan view of a photovoltaic device produced by the method of Figure 3 (compare with Figure 2), illustrating one possible arrangement of etched regions, in this instance being a series of parallel elongate regions oriented parallel to the bus bar and orthogonally to the elongate finger electrodes;

Figure 13 is a perspective view of a portion of the photovoltaic device of Figure 12, showing the etched regions as concave troughs with unetched ridges therebetween;

Figure 14 is a perspective cross-sectional view of a portion of a photovoltaic device similar to that of Figure 13, in which the elongate concave troughs extended only part way through the doped emitter layer;

Figure 15 is a perspective cross-sectional view of a portion of a photovoltaic device similar to that of Figure 13, in which the doped emitter layer has been completely removed in the deeper part of the elongate concave troughs;

Figures 16 to 18 are schematic side views of a semiconductor substrate being processed to form a photovoltaic device using an alternative method as shown in Figure 3; Figures 19 is a schematic plan view of a photovoltaic device produced by the alternative method (compare with Figure 2), illustrating one possible arrangement of etched regions, in this view being in the form of an array of circular regions distributed uniformly throughout the photon receiving regions bounded by the bus bar(s) and elongate finger electrodes of the device;

Figures 20 and 21 are scanning electron microscope images of respective portions of an emitter region of a photovoltaic device formed by the alternative method, showing a regular arrangement of etched regions; and

Figure 22 is a graph illustrating the relationship between sheet resistance of the emitter region of a photovoltaic device formed by the alternative method and the duration of the etch step used to form the circular regions.

DETAILED DESCRIPTION

As shown in the flow diagram of Figure 3, a method of producing a photovoltaic device begins with a semiconductor substrate 400, as shown in Figure 4, which may or may not be in wafer form. The semiconductor substrate 400 may be composed of an elemental or a compound semiconductor, but is typically a standard silicon wafer.

At step 302, a dopant species is introduced into a surface 402 of the semiconductor substrate 400 to form a doped emitter layer 502, as shown in Figure 5. The dopant species can be introduced into the semiconductor substrate 400 using any suitable method, including standard methods known to those skilled in the art such as ion implantation, alloying, and thermally assisted diffusion, for example. Where a low cost device is desired, thermal diffusion will typically be chosen.

Next, selected regions of the doped emitter layer are etched to remove at least a portion of the doped emitter layer in each selected region at step 304. Typically, the etching step will use a masked isotropic wet etching method, but other methods can be used if desired, including dry etching methods such as plasma etching or laser or ion ablation methods. Where an undirected etching method such as wet or plasma etching is used, the selected areas will typically be defined by an etch mask, although this may not be necessary if a maskless or directed beam method or self-masking method is used.

An etch mask can be formed using standard lithography techniques known to those skilled in the art, for example by depositing a layer of photoresist 602, as shown in Figure 6, and then exposing selected regions of the photoresist 602 using a shadow mask, for example, and then developing the photoresist 602 to selectively remove the exposed (or, conversely, the unexposed) regions to form a mask such as that shown in Figure 7. The exposed regions 702 of the doped emitted layer 502 can then be etched to form etched regions 802, as shown in Figure 8. The photoresist 602 can then be stripped to produce the structure shown in Figure 9, with unetched regions 902, 904 remaining between the etched regions 802. Alternatively, the etch mask may be created using nano-imprinting techniques, laser patterning, inkjet patterning, sub-wavelength interferometric lithography, and other patterning methods known to those skilled in the art.

Due to the removal of at least part of the doped emitter layer 502, the etched regions 802 will have a higher sheet resistance than the unetched regions 902, 904. In particular, where the depth profile of the introduced dopant species has a peak close to the semiconductor surface 402 and a long tail into the semiconductor substrate 400, the etching can be performed to remove the peak from the etched regions 802, leaving only the relatively low concentration tail of the dopant distribution. This produces a substantial difference in sheet resistance between the etched regions 802 and the unetched regions 902, 904 from a single doping step followed by relatively simple and low cost etch step. For example, Figure 1 1 is a graph showing the concentration of phosphorus dopant as a function of depth into a silicon substrate for a thermally assisted diffusion step performed at a temperature of 850°C (diamond symbols 1 102), 900°C (triangle symbols 1 104), and 950°C (square symbols 1 106) for 30 minutes. The respective sheet resistances are 83 Ω/θ, 35 Ω/α, and 15 Ω/α. Note that the junction depth, defined in this instance by the depth at which the dopant density is ~10¹⁶ cm^'3, is about 0.43 microns, 0.7 microns and 1 .15 microns, respectively. Taking the middle 900°C case where the junction depth is about 0.7 microns, selected regions of this doped emitter layer can be etched to a depth of about 0.2 microns (200nm), leaving a relatively lightly doped portion of the doped emitter layer (having a peak concentration nearly two orders of magnitude lower than the unetched portions).

It will be apparent from the above that the described processes allow the production of a photovoltaic device having doped surface regions of essentially any desired shape (in plan view) and with a selected one of a low or a high sheet resistance value, while requiring only a single doping step (typically, but not necessarily, a thermal diffusion step).

At step 306, a passivation layer (not shown) is formed on the etched and unetched surface regions of at least the photon collecting regions of the wafer to reduce surface recombination of charge carriers. The composition of the passivation layer can be any suitable dielectric material known to those skilled in the art. For example, where the substrate is p-\ypc silicon, a silicon nitride layer can be used, as discussed further below.

At step 308, a plurality of parallel elongate finger electrodes 102 is formed on some of the low sheet resistance unetched regions of the doped emitter layer 502. As described above, these finger electrodes are used to collect charge carriers from the doped emitter layer. One or more bus bar electrodes 104, as shown in Figure 10, may be formed on corresponding low sheet resistance unetched regions 904, either at the same time or in an independent step. The finger electrodes 102 and bus bar electrodes 104 can be formed using any standard method known to those skilled in the art, including screen printing with conducting silver paste. In any case, the regions between adjacent parallel finger electrodes constitute the photon collecting regions of the device, because the regions underneath the finger electrodes 102 and busbar electrodes 104 are shadowed by those electrodes 102, 104.

As will be appreciated by those skilled in the art, step 308 will typically include a thermal firing step that causes the deposited electrode structures to punch through the underlying passivation layer. However, in some embodiments where very high efficiency devices are desired, the process can optionally include a patterned etch step 307 to selectively remove the passivation layer from the regions on which the conductive electrodes are formed at step 308. Each of these photon collecting regions includes both etched regions 802 and unetched regions 902 of the doped emitter layer 502. For the reasons described above, the etched regions 802, when passivated by a suitable dielectric coating, for example silicon nitride, have a lower charge carrier recombination rate than the unetched regions 902 due to the reduction in dopant concentration in the etched regions 802, and are therefore arranged to constitute a majority of each photon collecting region. However, to improve the conduction of charge carriers to the finger electrodes 102, the unetched regions 902 in each photon collecting region are arranged between the etched regions 802 to define conducting paths to the finger electrodes 102. The provision in each photon collecting region of highly doped conducting pathways of doped semiconductor through the etched regions 802 of relatively low carrier recombination allows the competing requirements for low resistance pathways and low recombination to be balanced or even optimised; for example, by trial and error and/or simulation.

As described above, the unetched regions 902 of the doped surface layer 502 extend from finger electrodes 102 to define conducting paths from the etched regions 802 to the finger electrodes 102, thereby reducing the average distance that charge carriers are required to travel through the etched regions 802 to reach the finger electrodes 102.

In some embodiments, the unetched regions 902 in each photon collecting region are in the form of a series of parallel fine lines or elongate regions (in plan view) of the unetched emitter layer that each defines a continuous path of relatively high conductivity to at least one of the two finger electrodes bounding the corresponding photon collecting region. In some embodiments, the elongate regions alternately contact the two bounding finger electrodes. In some embodiments, these unetched regions define a continuous path to both of the finger electrodes bounding the corresponding photon collecting region. In some embodiments, the etched and unetched regions are interleaved and each etched region is bounded by unetched regions of the doped emitter layer. In some embodiments, the unetched regions are in the form of a two dimensional grid or mesh forming an interconnected network of continuous pathways. However, it will be apparent that the etched and unetched regions can be configured in many different ways.

Figure 12 is a schematic plan view of a photovoltaic device in which the etched regions in each photon receiving region 106 are in the form of an array, series, or grid of elongate concave troughs 1202 extending between and orthogonal to the corresponding pair of finger electrodes 102 bounding the photon receiving region 106. The corresponding unetched regions 1204 of the doped emitter layer defined by the etched regions 1202 are thus interleaved with the elongate troughs 1202 and form continuous pathways of relatively high conductivity and low sheet resistance to both of the finger electrodes 102.

The shape of the etched troughs 1202 is shown more clearly in the enlarged perspective view of Figure 13. In this embodiment, the elongate ridge-shaped unetched regions 1204 are very thin or narrow compared with the relatively wide etched troughs 1202, as it is generally desirable for the etched, high sheet resistance regions to occupy a majority of the photo receiving regions 106, with only a relative small amount of the plan view area devoted to the transport-assisting low resistivity unetched regions 1204. However, the relative proportions (in plan view) of the photo receiving regions 106 occupied by the etched and unetched regions, and their spatial configurations (in plan view and/or in three- dimensional shape) can be varied as desired, allowing the performance of a photovoltaic device to optimised with respect to these variables.

In some embodiments, the etched regions 802 are etched to remove only a portion of the doped emitter layer 502 from each etched region 802. For example, Figure 14 is. an enlarged view of a portion of a device (not to scale), showing part of one of the photon receiving regions 106 bounded on one side by a corresponding finger electrode 102 and a corresponding bus bar 104. In this instance, the etched regions 1202 still retain a portion of the doped emitter layer 502, the amount remaining varying with lateral position across the etched trench due to the isotropic etching process used. Where the doped emitter layer is formed by thermally-assisted diffusion of phosphorus into a silicon substrate, the depth of the emitter layer is typically about 300-1000 nm.

In other embodiments, the entirety of the doped emitter layer 502 is removed in at least a part of each etched region, as shown in Figure 15. In this Figure, the entirety of the doped emitter layer 502 has been removed in all but the very edges of each etched trench 802. In such embodiments, the so-called emitter region is constituted by the set of interconnected, ridge-like remaining portions of the doped emitter layer 1202 with spaces therebetween where the underlying base region or substrate 400 is exposed in the deeper portion of each trench 1202. In this embodiment, the trenches 1202 are spaced further apart, so that the corresponding unetched fingers 1204 of the emitter layer remaining between the etched trenches 1202 have flat top surfaces of the original, wafer surface 402 that are typically about 0.1 microns wide. The trenches themselves are typically about 0.5-1.0 microns wide. For comparison, each finger electrode is typically about 50 -100 microns wide. However, it should be understood that these dimensions are only typical values for the embodiments illustrated, and that even in such embodiments, very different values for any or all of these dimensions can be used if desired.

In embodiments where the substrate is a p-type silicon wafer and the emitter layer is n- type, a dielectric coating such as a thin film of silicon nitride (SiN) is added at step 306 to provide surface passivation to both the diffused ridges and the exposed base areas. Furthermore, positive charge in the SiN film can induce an n-type inversion layer on the exposed p-type base, thereby forming a continuous n-type layer with the n-type doped ridges and thus re-establishing a pn junction over the whole surface of each photon receiving region 106.

The dimensions and number of the highly conductive ridges of the unetched gridded emitter layer can be selected to achieve a desired effective sheet resistance, for example of the order of 100 Ω/D, while having most of the surface either as lightly doped (the slopes of the ridges) or as p-type exposed based region, passivated by the addition of a dielectric anti-reflection coating.

As long as the spacing between adjacent ridges is sufficiently small, which in silicon can still represent tens or hundreds of micrometers, charge carriers generated in the base, including the exposed base region (where applicable), can diffuse laterally through the base to the pn junction. Therefore, the etch mask used to form the etched regions can be formed using relatively coarse patterning techniques, such as ink-jet or screen printing, for example.

Appropriate etch solutions can be selected to achieve a desired result. For example, where the substrate is silicon, these can be acidic, such as mixes of HF and nitric acids, or basic, such as TMAH, OH, etc. When using a basic etchant on single crystalline silicon with an appropriate crystal lographic orientation (typically 100), anisotropic etching can be used to reduce reflection and enhance trapping of light within the device by creating shapes such as inverted pyramids or V-shaped grooves in the silicon wafer, either fully formed or partially (truncated pyramids).

When performing the patterning and etching of the wafer, it is possible to also etch completely through the diffused region at the edges of the semiconductor substrate, thus · performing another necessary fabrication step, usually referred to as edge isolation. In addition, any parasitic diffusion on the rear side of the wafer can also be removed in the same step, thus facilitating the fabrication of devices with a rear dielectric passivation or a second dopant diffusion.

In yet further embodiments of the present invention, the photon collecting regions include etched regions that are configured to define a non-planar optically active structure that acts as an anti-reflection structure and/or traps light within the device. In these further embodiments, the photon collecting regions may or may not include unetched regions of the doped emitter layer. Where unetched regions are included, in some embodiments they define conducting paths from the etched regions to the finger electrodes 102 as described above.

Such photovoltaic devices can be produced by a modified version of the method described above in which the masking and/or etching steps are modified.

In these embodiments, the doped emitter layer 502 is formed as described above at step 302 to form the structure shown in Figure 5. In some embodiments, an etch mask is then formed over the doped emitter layer 502. In some embodiments, the etch mask is formed by patterning a photoresist layer as described above, using lithography or a shadow mask, for example, or any of the other techniques described above.

Alternatively, the etch mask may be created using imprinting techniques, laser patterning, inkjet patterning, sub- wavelength interferometric lithography, and other patterning methods known to those skilled in the art. For example, the patterned masking layer 602 shown in Figure 7 can be formed directly by contacting a correspondingly patterned and pre-coated stamp against the doped surface of the semiconductor substrate 400 and then removing the stamp to leave the patterned masking layer 602. Stamps with patterned features having lateral dimensions down to the nanoscale can be formed using methods known to those skilled in the art, including the method described in M. Verschuuren and H. van Sprang, 3D Photonic Structures by Sol-Gel Imprint Lithography, Mat. Res. Soc. Symp. Proc. 1002, for example. In the described embodiments, the etch mask is a patterned sol-gel oxide or polymer layer deposited by stamping. However, other materials and methods may be used in other embodiments, as will be apparent to those skilled in the art.

Irrespective of the method used to form the etch mask, the exposed regions 702 of the doped emitted layer 502 can then be selectively etched to form etched regions 1602, as shown in Figure 16. In these embodiments, the etched regions/features 1602 can extend deeply into the doped emitter layer 502, as shown in the left-hand side of Figure 16, and in some embodiments extend completely through it, as shown in the right-hand side of Figure 16. The photoresist or other masking layer 602 can then be stripped to produce a structure such as that shown in Figure 17. Depending on the lateral dimensions of the openings in the etch mask and the extent of etching, in some embodiments unetched regions 1702 remain between the etched regions 1602. In other embodiments, the etched regions 1602 partially merge together, but nevertheless the etching forms a non-planar surface having microscale or nanoscale topographical features, as described further below. In all of these embodiments, larger unetched regions 1704 remain where the elongate finger electrodes 102 and bus bar electrodes 104 (as shown in Figure 18) are formed in a subsequent step, as described above. As with the embodiments described above, the etched regions 1602 have a higher sheet resistance than any unetched regions 1702, 1 704. In particular, where the depth profile of the introduced dopant species has a peak close to the surface of the semiconductor substrate 402 and a long tail into the semiconductor substrate 400, as shown in Figure 1 1 , the etching can be performed to remove the peak from the etched regions 1602, leaving only the relatively low concentration tail of the dopant distribution. This produces a substantial difference in sheet resistance between the etched regions 1602 and the unetched regions 1702, 1704 from a single doping step followed by relatively simple and low cost etch step. It will be apparent from the above that the described processes allow the production of a photovoltaic device having doped surface regions of essentially any desired shape (in plan view) and with a selected one of a low or a high sheet resistance value, while requiring only a single doping step (typically, but not necessarily, a thermal diffusion step). At step 306, a passivation layer (not shown) is formed on the etched and unetched regions of the photon collecting regions of the wafer as described above, and at step 308, a plurality of parallel elongate finger electrodes 102 is formed on some of the low sheet resistance unetched regions of the doped emitter layer 502, again as described above. Similar to the embodiments described above, in these embodiments the unetched regions 902 of the doped surface layer 502 extend from the finger electrodes 102 to define conducting paths from the etched regions 802 to the finger electrodes 102, thereby reducing the average distance that charge carriers are required to travel through the etched regions 802 to reach the finger electrodes 102. In some embodiments, the etched regions are in the form of mutually spaced arrays of openings in the respective photon collecting regions of the wafer. The openings in each photon collecting region may be substantially uniformly distributed in that region. In some embodiments, the openings are in the form of 'tubs' that are circular in plan view. The diameter of each circular opening is of micron or nanometre dimensions. The array of openings is configured to act as an optically active component of the photovoltaic device so that it constitutes an anti-reflection structure and traps light within the device, especially after encapsulation, thereby improving the conversion efficiency of the device.

For example, Figure 19 is a schematic plan view of a photovoltaic device in which the etched regions in each photon receiving region 106 are in the form of an array of circular (in plan view) concave tubs 1902 distributed uniformly over the photon receiving region 106 partially bounded by the corresponding pair of finger electrodes 102 and bus bar 104. The corresponding unetched regions 1904 of the doped emitter layer defined by the etched regions 1902 are thus correspondingly arranged and form continuous pathways or channels of relatively high conductivity and low sheet resistance to both of the finger electrodes 102 and to the bus bar 104.

Figures 20 and 21 are scanning electron microscope images of portions of structured emitter regions of respective devices formed as described above for different etching conditions. Each image shows a regular arrangement of etched openings or 'tubs' in the emitter layer 502 between residual peak and mesa-like structures, respectively, corresponding to the masked regions. These nanoscale openings were formed by depositing a solgel masking layer over an n-type emitter layer 502 on a silicon wafer, and then using an imprint stamp with nanoscale features to form openings in the solgel layer. The openings have a diameter of about 400nm, and are mutually spaced by about 513 nm. A silicon etch solution including hydrofluoric acid and nitric acid was then used to isotropically etch the regions of the emitter layer 502 exposed through the openings in the soigel mask for etch times between 4 and 8 minutes to form the etched tubs shown in the images. Before etching, the emitter layer 502 (formed by phosphorus diffusion) had a sheet resistance of about 20.8 Ω/ο. As described above, the sheet resistance of the nanostructured emitter layer after etching depends on the extent of etching. For example, Figure 22 is a graph illustrating the relationship between the measured sheet resistance of the nanostructured emitter region and the duration of the etch step used to form the circular tubs. The graph demonstrates that it is possible to control the sheet resistance of the nanostructured emitter layer by selecting the etching time (for a given emitter layer, etch mask, and etch solution) and hence the depth and lateral extent of the "nanotubs" etched in the silicon. In this case, the relationship between sheet resistance R_s and etching time / is well represented by the function R_s = 22.3 exp(0.345* t), which is shown as the solid line in Figure 22. The use of different etch mask patterns can also be used as an additional way to control the sheet resistance.

As described above, in some embodiments the openings etched into the emitter layer 502 are made to coalesce (e.g. , by prolonged etching), thereby removing all or most of the heavily doped "dead layer" (i.e., the most heavily doped surface portion of the emitter layer 502), while keeping a sufficient thickness of the diffused region to form a lightly doped emitter region. For example, in some embodiments, an initial heavy thermal diffusion forms an emitter layer 502 having a sheet resistance in the range of 10-50 Ω/θ. After etching to remove a relatively heavily doped portion of the emitter layer 502, the remaining relatively lightly doped portion of the emitter layer 502 has a sheet resistance in the range of 70-200 Ω/D. At the same time, the non-planar etched surface of the remaining portion of the emitter layer 502 acts to reduce reflection and also to trap light inside the active layer of the device. In order to achieve this, the dimensions of the textured features are typically in the range from 50 run to some tens of microns. These features are typically rounded and symmetrical in plan view when using an isotropic etch, e.g., substantially hemispherical tubs in a hexagonally close packed arrangement. However, if formed using an alkaline etch on monocrystalline silicon, the features may be square-based upright pyramids or inverted pyramids. If using directional plasma etching, they may be inverted conical shapes, for example. Many other suitable shapes and configurations will be apparent to those skilled in the art.

In other embodiments, the etch mask and etch step are configured so that heavily doped, unetched regions 902 of the emitter layer 502 remain between the etched regions 802, so that they can act as current-conducting channels towards the metal finger electrodes 102. These highly conductive regions can be configured as lines or a mesh of ridge-like structures, with etched "tubs" in-between.

In some embodiments, the openings are configured as "tubs" as described above, and the diameter of these tubs in plan view is similar to the thickness of the emitter layer 502, which is typically in the range of about 300 - 1000 nm. In other embodiments, the tubs are deeper than the thickness of the emitter layer 502, but the etch mask and etch step are configured so that unetched regions 902 of the emitter layer 502 remain between the etched regions 802 to act as current-conducting channels towards the metal finger electrodes 102. In such embodiments, the so called emitter region is formed by a mesh of interconnected, ridge-like, diffused regions with spaces in between where the underlying base region, or substrate of the device is exposed.

In the case of a photovoltaic device or solar cell made on a p-type silicon wafer, where the diffused region is n-type (e.g. , phosphorus doped), the dielectric coating (e.g. , silicon nitride) provides surface passivation to both the diffused ridges and the exposed base areas. Furthermore, the positive charge in the silicon nitride film can create an induced n-type surface layer on the exposed p-type base by inversion that joins up with the n-type doped ridges and thus forms a pn junction over the whole area of the device. Similarly, in embodiments where the device is formed on an n-type silicon wafer or the so called BSF on a p-type cell so that the doped surface region is p-type (e.g. , doped with boron, aluminium or gallium), the application at step 306 of a dielectric coating possessing negative charge (e.g. , aluminium oxide) provides surface passivation to both the p-type doped ridges and the exposed n-type base regions, as well as creating an induced p-type region on the exposed n-type (or p-type in the case of a BSF layer) base, thus forming a pn junction (or a BSF layer) over the whole area of the device.

As will be apparent to those skilled in the art, appropriate silicon etch solutions can be selected to achieve the desired result. These can be acidic (e.g., mixes of HF and nitric acids) or basic (e.g. , TMAH, OH, NaOH or ammonia). When using a basic etchant on single crystalline silicon with an appropriate crystallographic orientation (100), it is possible to apply the above techniques to create inverted pyramids, V-shaped grooves in the silicon wafer, either fully formed or partially (truncated pyramids). In some embodiments, truncated or complete inverted pyramids are arranged to form an emitter region having a surface like that of a waffle, with well defined current conducting channels provided by the ridges between the inverted pyramids.

In some embodiments, the etched regions 802 are etched to remove only a portion of the doped emitter layer 502 from each etched region 802, as shown in the left-hand part of Figure 16, for example. In such embodiments, the etched regions 802 still retain a (relatively lightly doped) portion of the doped emitter layer 502, the amount remaining varying with lateral position across the etched features due to the isotropic etching process used. Where the doped emitter layer is formed by thermally-assisted diffusion of phosphorus into a silicon substrate, the depth of the emitter layer is typically about 300- 1000 nm.

In other embodiments, the entirety of the doped emitter layer 502 is removed in at least a part of each etched region, as shown in the right-hand part of Figure 16, for example. In such embodiments, the entirety of the doped emitter layer 502 has been removed in all but the very edges of each etched feature 1602. In such embodiments, the so-called emitter region is constituted by the set of interconnected, ridge-like remaining portions of the doped emitter layer 502 with spaces therebetween where the underlying base region or substrate 400 is exposed in the deeper portion of each etched feature 1602. In this embodiment, the etched features 1602 are spaced further apart, so that the corresponding unetched regions 1702 of the emitter layer remaining between the etched features 1602 have flat top surfaces that are typically about 0.1 microns wide. The features themselves 1702 are typically about 0.2-1.0 microns wide. For comparison, each finger electrode is typically about 50 -100 microns wide. However, it should be understood that these dimensions are only typical values for the embodiments illustrated, and that even in such embodiments, very different values for any or all of these dimensions can be used if desired.

Many modifications will be apparent to those skilled in the art without departing from the scope of the present invention.

Claims

CLAIMS:

1. A method of producing a photovoltaic device from a semiconductor substrate, the method including:

, forming a doped emitter layer by introducing a dopant species into a surface of the semiconductor substrate;

etching selected regions of the doped emitter layer to remove at least a

l

portion of the doped emitter layer in each selected region;

(ii) the etched regions of the doped emitter layer are configured to define a non-planar optically active structure that acts as an anti-reflection structure and/or traps light within the device.

2. The method of claim 1, wherein the second unetched regions are arranged between the etched regions to define conducting paths to the finger electrodes.

3. The method of claim 1 or 2, wherein the etched regions of the doped emitter layer are configured to define a non-planar optically active structure that acts as an anti- reflection structure and/or traps light within the device.

4. The method of any one of claims 1 to 3, including forming at least one busbar interconnecting said finger electrodes.

5. The method of any one of claims 1 to 4, wherein the dopant species is introduced into the surface of the semiconductor substrate by thermal diffusion.

6. The method of any one of claims 1 to 5, including:

forming an etch mask on the doped emitter layer so that only the selected regions of the doped emitter layer are exposed through the etch mask.

7. The method of any one of claims 1 to 6, wherein the unetched regions between the etched regions define continuous conducting paths to both of the corresponding finger electrodes.

8. The method of any one of claims 1 to 7, wherein said etching removes substantially all of the doped emitter layer in each selected region.

9. A method of producing a photovoltaic device from a semiconductor substrate, the method including:

10. A method of producing a photovoltaic device from a semiconductor substrate, the method including:

1 1. The method of any one of claims 1 to 10, wherein the etched regions are in the form of mutually spaced and mutually parallel elongate troughs.

12. The method of claim 1 1, wherein the elongate troughs define corresponding unetched elongate regions of the doped emitter layer therebetween, each of the unetched elongate regions of the doped emitter layer providing a conducting path to at least one of the corresponding pair of finger electrodes.

13. The method of claim 12, wherein each of the unetched elongate regions of the doped emitter layer provides a conducting path to the corresponding pair of finger electrodes.

14. The method of any one of claims l l to 13, wherein the etched and unetched elongate regions are parallel to one or more bus bars of the photovoltaic device and orthogonal to the finger electrodes.

15. The method of any one of claims 1 to 14, wherein the etched regions are in the form of mutually spaced tubs.

16. The method of any one of claims 1 to 15, wherein the etched regions have microscale or nanoscale dimensions in plan view.

17. A photovoltaic device, including:

a semiconductor substrate having a doped emitter layer; and

wherein at least a portion of the doped emitter layer in each of a plurality of regions in each photon collecting region has been removed to reduce the recombination of charge carriers therein, and at least one of:

(i) the remaining regions of the doped emitter layer in each photon collecting region are configured to provide conducting paths to at least one of the corresponding pair of finger electrodes; and

18. The photovoltaic device of claim 17, wherein the remaining regions of the doped emitter layer in each photon collecting region are configured to provide conducting paths to at least one of the corresponding pair of finger electrodes.

19. The photovoltaic device of claim 17 or 18, wherein the etched and unetched regions are configured to define a non-planar optically active structure that acts as an anti-reflection structure and or traps light within the device.

20. The photovoltaic device of any one of claims 17 to 19, wherein the remaining regions of the doped emitter layer in each photon collecting region are configured to provide conducting paths the corresponding pair of finger electrodes.

21. The photovoltaic device of any one of claims 17 to 20, wherein the remaining regions of the doped emitter layer in each photon collecting region are in the form of mutually spaced and mutually parallel elongate ridges.

22. The photovoltaic device of claim 21 , wherein the elongate ridges are interleaved with corresponding elongate troughs therebetween.

23. The photovoltaic device of any one of claims 17 to 22, wherein the elongate ridges and troughs are parallel to one or more bus bars of the photovoltaic device and orthogonal to the finger electrodes.

24. The photovoltaic device of any one of claims 17 to 19, wherein the etched regions are in the form of mutually spaced tubs.